Merge changes from topic "xlnx_fix_misra_common_fdt_split" into integration

* changes:
fix(libfdt): resolve misra 10.3 violations
feat(lib): use C/assembler for HI/LO macros
fix(libfdt): addin

Merge changes from topic "xlnx_fix_misra_common_fdt_split" into integration

* changes:
fix(libfdt): resolve misra 10.3 violations
feat(lib): use C/assembler for HI/LO macros
fix(libfdt): adding missing curly braces
fix(libfdt): fix misra 14.4 and 15.6 violations
fix(libfdt): typecast operands to match data type

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Merge changes I2485d583,I1374c482,I07e29dbb,I949e6486 into integration

* changes:
feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB
feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status

Merge changes I2485d583,I1374c482,I07e29dbb,I949e6486 into integration

* changes:
feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB
feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status
feat(cpufeat): advertise support for FEAT_RASv2
feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

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Merge changes I3a2243d0,Ifeb88c8f,I8ac77336 into integration

* changes:
feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION
docs(cpufeat): add analysis of 2024 features
fix(cpu

Merge changes I3a2243d0,Ifeb88c8f,I8ac77336 into integration

* changes:
feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION
docs(cpufeat): add analysis of 2024 features
fix(cpufeat): add FEAT_SPE to FEATURE_DETECTION

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fix(libfdt): resolve misra 10.3 violations

The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replace the hard‑co

fix(libfdt): resolve misra 10.3 violations

The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replace the hard‑coded low‑bits mask with the LO() macro to avoid
implicit type conversions and ensure compliance with MISRA 10.3.

Change-Id: I09696e90733b101c346f4e3e3c2baf63dc1b6607
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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feat(cpufeat): advertise support for FEAT_RASv2

From a PE architecture standpoint, FEAT_RASv2 only does three things:
* adds the SCR_EL3.TWERR trap bit (active high). That defaults to 0
unless RAS

feat(cpufeat): advertise support for FEAT_RASv2

From a PE architecture standpoint, FEAT_RASv2 only does three things:
* adds the SCR_EL3.TWERR trap bit (active high). That defaults to 0
unless RAS_TRAP_NS_ERR_REC_ACCESS overrides it but that's unused.
* adds the read only ERXGSR_EL1 register which cannot be saved/restored.
* changes the signalling of Uncontainable Instruction Aborts. When
FEAT_RASv2 is present Uncontainable EAs cannot happen and instead
SErrors will be signalled with more information.

So there isn't much to do and we can safely advertise FEAT_RASv2
support.

Change-Id: I07e29dbbd7fe824bed5a22ae22bd50eb16a0acd0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

FEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.
However, the ability to use it was removed with 970a4a8d8 by simply

feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

FEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.
However, the ability to use it was removed with 970a4a8d8 by simply
saying it impacts execution at EL3. That's true, but FEAT_STATE_CHECKED
can still be allowed by being a bit clever about it.

First, the remainder of common code can be converted to use the
is_feat_ras_supported() helper instead of the `#if FEATURE` pattern.
There are no corner cases to consider there. The feature is either
present (and appropriate action must be taken) or the feature is not (so
we can skip RAS code).

A conscious choice is taken to check the RAS code in synchronize_errors
despite it being in a hot path. Any fixed platform that seeks to be
performant should be setting features to 0 or 1. Then, the
SCTLR_EL3.IESB bit is always set if ENABLE_FEAT_RAS != 0 since we expect
FEAT_IESB to be present if FEAT_RAS is (despite the architecture not
guaranteeing it). If FEAT_RAS isn't present then we don't particularly
care about the status of FEAT_IESB.

Second, platforms that don't set ENABLE_FEAT_RAS must continue to work.
This is true out of the box with the is_feat_xyz_supported() helpers, as
they make sure to fully disable code within them.

Third, platforms that do set ENABLE_FEAT_RAS=1 must continue to work.
This is also true out of the box and no logical change is undertaken in
common code.

Finally, ENABLE_FEAT_RAS is set to 2 on FVP. Having RAS implies that the
whole handling machinery will be built-in and registered as appropriate.
However, when RAS is built-in but not present in hardware, these
registrations can still happen, they will only never be invoked at
runtime.

Change-Id: I949e648601dc0951ef9c2b217f34136b6ea4b3dc
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(libfdt): adding missing curly braces

This corrects MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.
Enclosed statement body

fix(libfdt): adding missing curly braces

This corrects MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I71a1ad2a6f85edbf5133a7860453db2937988e22
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(libfdt): fix misra 14.4 and 15.6 violations

Fixed below MISRA violations:

MISRA violation C2012-14.4:
The controlling expression of an if statement and the controlling
expression of an iteratio

fix(libfdt): fix misra 14.4 and 15.6 violations

Fixed below MISRA violations:

MISRA violation C2012-14.4:
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean
type.
Used boolean in control expressions for fixing this violation.

MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.Enclosed statement body within
the curly braces.

Change-Id: Ic6536e1b749a7aacdf265c632ceea8d344f2e7b5
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(libfdt): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a d

fix(libfdt): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The operand is explicitly typecasted to required type
to match the operand/return type.

Change-Id: I9d9a2e13225369281e2a1dc09d06bf6177d81f3a
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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Merge changes from topic "bk/simpler_panic" into integration

* changes:
refactor(aarch64): remove crash reporting's dependency on cpu_data
fix(el3-runtime): remove lower_el_panic()

feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION

Now that the 2024 features have been analysed, bump those that don't
need any specific EL3 support so that FEATURE_DETECTION doesn

feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION

Now that the 2024 features have been analysed, bump those that don't
need any specific EL3 support so that FEATURE_DETECTION doesn't complain
when it encounters them.

Change-Id: I3a2243d021a9a5385d14b3c1d569142e34145e51
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(cpufeat): add FEAT_SPE to FEATURE_DETECTION

Documentation in docs/architecture_features.rst suggests we're okay with
anything up to FEAT_SPEv1p3 but FEAT_DETECT is unaware of it. Add it to
the l

fix(cpufeat): add FEAT_SPE to FEATURE_DETECTION

Documentation in docs/architecture_features.rst suggests we're okay with
anything up to FEAT_SPEv1p3 but FEAT_DETECT is unaware of it. Add it to
the list.

Change-Id: I8ac773361fb8d18b850da1e45fdb6a54cfe65063
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(morello): add Morello capability enablement changes

This patch adds a build macro ENABLE_FEAT_MORELLO which when set will
compile BL31 firmware with changes required to boot capability
aware so

feat(morello): add Morello capability enablement changes

This patch adds a build macro ENABLE_FEAT_MORELLO which when set will
compile BL31 firmware with changes required to boot capability
aware software.

It also adds helper function in c and assmbly to check if morello
hardware is present and if morello capability is enabled or not.

CE field, bits [23:20] in ID_AA64PFR1_EL1 defines whether morello
architecture is present or not, 0b0000 indicates that it is absent
and 0b0001 indicates that it is present. While whether capabilities
are enabled or not is decided at runtime with ENABLE_FEAT_MORELLO build
option.

Reference: https://developer.arm.com/documentation/ddi0606/latest/

Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Varshit Pandya <varshit.pandya@arm.com>
Change-Id: Ib16877acbfcb72c4bd8c08e97e44edc0a3e46089

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fix(el3-runtime): remove lower_el_panic()

A panic at EL3 is bad news and should never happen. What caused it isn't
exactly relevant or possible to figure out without manual debugging
(surely there w

fix(el3-runtime): remove lower_el_panic()

A panic at EL3 is bad news and should never happen. What caused it isn't
exactly relevant or possible to figure out without manual debugging
(surely there wouldn't have been a panic if not). A misbehaving lower EL
should never be able to cause problems for a higher EL and since EL3 is
in control of all lower ELs a panic at EL3 means that there is a
problem with EL3.

This patch removes lower_el panic and replaces it with a simple panic
for simplicity. There is a slight loss of information when an AArch32
lower EL has one of its instructions trapped by EL3. An explicit error
message is added to preserve this information.

Change-Id: Iefd20eb43d69cbcf6d66ed5cc894c4e0255782e3
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(el3-runtime): actually check for the EA bit on exception entry" into integration

fix(el3-runtime): actually check for the EA bit on exception entry

The C conversion patch - 14320bce3 - had a typo in it that it would
bitwise or SCR_EL3 with the EA bit effectively making the check

fix(el3-runtime): actually check for the EA bit on exception entry

The C conversion patch - 14320bce3 - had a typo in it that it would
bitwise or SCR_EL3 with the EA bit effectively making the check always
true. Correct it to a bitwise and to actually check the bit.

Change-Id: I9897cd6d816f5d86024a05bd58585d5fb2ab2e1d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(build): use ARM_ARCH_FEATURE instead of -march directly" into integration

fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FE

fix(build): use ARM_ARCH_FEATURE instead of -march directly

The -march compiler flag is owned by make_helpers/march.mk and its
output is controlled by ARM_ARCH_MAJOR, ARM_ARCH_MINOR, and
ARM_ARCH_FEATURE. Setting -march directly can lead to unexpected results
when using the above flags and is generally not recommended within tfa.

This patch migrates all instances of -march=armv8-a+crc to
ARM_ARCH_FEATURE=crc. Arm platforms (via arm_common.mk) are checked and
those that support cores greater than arm8.1 do not get the flag as it
is automatically pulled in.

Change-Id: I846f97367eab9529524a2805d5b87d34cce2360f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(el3-runtime): translate EL3 handled exceptions to C and always call prepare_el3_entry

Exception handling in BL31 is tricky business and to satisfy the varying
requirements of the different code

feat(el3-runtime): translate EL3 handled exceptions to C and always call prepare_el3_entry

Exception handling in BL31 is tricky business and to satisfy the varying
requirements of the different code paths it has thus far largely been
written in assembly. However, assembly is extremely tedious to read and
modify. Similar to context management, it is desirable to have as much
as possible in C. C code is generally easier to follow and can enable
the compiler to do more optimisations on surrounding code.

Most exceptions that BL31 deals with are the synchronous exceptions and
those are processed within BL31. They already get prepared for EL3 entry
and after the initial dispatch end up in C. So the dispatch can also be
converted in C. Interrupt exceptions are very similar so are converted
too. Finally, asynchronous external aborts share some code with
synchronous external aborts and may end up being processed deeper in
BL31. So they can safely be prepared for EL3 entry too and converted to
C so that they can share code properly.

The IMP DEF exceptions are not part of this refactor as their speed may
be important. There is currently little that uses them, but they can be
converted to C too once their use expands and usage allows it.

This refactor allows to expand the responsibilities of
prepare_el3_entry(). Its role is already to prepare context for
executing within EL3 but with this patch EL3 execution is synonymous
with C runtime execution. So it's given the responsibility of saving
spsr and elr as well as putting the runtime stack in.

When a synchronous exception happens, the only possible paths are to
enter the C EL3 runtime, exiting via el3_exit(), or to panic. In the EL3
runtime case, we always need prepare_el3_entry() and the runtime stack,
whereas in the panic case, this doesn't matter as we will never return.
So hoist the prepare_el3_entry() call and the changing of the stacks as
early as possible and make the rest of the code agnostic of this.

This patch also gets rid of smc_prohibited. It is an optimisation by
skipping prepare_el3_entry() when a bad smc call happens. However, speed
doesn't matter in this case as this is an erroneous case.

Change-Id: I411af9d17ef4046a736b1f4f5f8fbc9c28e66106
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): factor out handler fetching code

handle_runtime_svc() is AArch32 only, but the part that fetches the
handler is not. Factor it out into its own function so it can be used
for

refactor(el3-runtime): factor out handler fetching code

handle_runtime_svc() is AArch32 only, but the part that fetches the
handler is not. Factor it out into its own function so it can be used
for AArch64.

Change-Id: I89813759814817390065540329af98168fd04a88
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED" into integration

feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've

feat(cpufeat): enable USE_SPINLOCK_CAS to FEAT_STATE_CHECKED

The FEAT_LSE enablement predates the FEAT_STATE framework and has never
been converted. Since the introduction of USE_SPINLOCK_CAS we've gained
lots of quality of life features that allow for better feature
enablement. This patch converts USE_SPINLOCK_CAS to tri-state and adds
it to FEATURE_DETECTION to align with all other features.

Instead of introducing the assembly checking for tri-state, this patch
translates all locking routines to C inline assembly and uses the
standard C helpers. The main benefit is that this gives greater
visibility to the compiler about what the functions are doing and lets
it optimise better. Namely, it is able to allocate registers itself and
inline the functions when LTO is enabled.

An unsuccessful attempt was made to use the instructions directly and
have even flow control in C. This, however, made code very complicated
and less efficient in the tight loops of the spinlock.

The last use of ARM_ARCH_AT_LEAST goes away with this change and so this
macro is removed. It has now been fully superseded by the FEAT_STATE
framework.

This change exposes a limitation - RME_GPT_BITLOCK_BLOCK requires
USE_SPINLOCK_CAS. This patch does not address this in any way but makes
the relationship explicit.

Change-Id: I580081549aceded2dca3e0f4564ee7510a7e56ae
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(measured-boot): enable dynamic hash provisioning

Introduce dynamic hash provisioning for Measured Boot by removing the
previous static hash-selection path and allowing platforms to supply
algor

feat(measured-boot): enable dynamic hash provisioning

Introduce dynamic hash provisioning for Measured Boot by removing the
previous static hash-selection path and allowing platforms to supply
algorithm metadata at runtime. Add mboot_find_event_log_metadata() as a
common helper for resolving image metadata. Update the Event Log build
logic to use MAX_DIGEST_SIZE and MAX_HASH_COUNT, deprecate legacy
MBOOT_EL_HASH_ALG, and warn when it is used. Adjust MbedTLS
configuration to enable hash algorithms automatically when Measured Boot
is enabled.

Change-Id: I704e1a5005f6caad3d51d868bacc53699b6dd64f
Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>

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feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return

feat(cpufeat): add support for FEAT_UINJ

FEAT_UINJ allows higher ELs to inject Undefined Instruction exceptions
into lower ELs by setting SPSR_ELx.UINJ, which updates PSTATE.UINJ on
exception return. When PSTATE.UINJ is set, instruction execution at the
lower EL raises an Undefined Instruction exception (EC=0b000000).

This patch introduces support for FEAT_UINJ by updating the
inject_undef64() to use hardware undef injection if supported.

Signed-off-by: Arvind Ram Prakash <arvind.ramprakash@arm.com>
Change-Id: I48ad56a58eaab7859d508cfa8dfe81130b873b6b

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Merge changes I6e44c7f1,Id4320cbf,Ibb05dd47,Icec70861 into integration

* changes:
fix(morello): don't define get_mem_client_mode() when it won't be used
fix(rdn2): don't use V1 as a label
fix(

Merge changes I6e44c7f1,Id4320cbf,Ibb05dd47,Icec70861 into integration

* changes:
fix(morello): don't define get_mem_client_mode() when it won't be used
fix(rdn2): don't use V1 as a label
fix(tspd): don't forward declare tsp_vectors_t
fix(cpufeat): drop feature_panic() as unused

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