Merge changes Ic8700325,I6a3a9f28,I91a28b5f,Ia69289bf,I81d9b73a, ... into integration

* changes:
feat(cpufeat): constrain RAS_TRAP_NS_ERR_REC_ACCESS on ENABLE_FEAT_RAS
fix(build): set defaults t

Merge changes Ic8700325,I6a3a9f28,I91a28b5f,Ia69289bf,I81d9b73a, ... into integration

* changes:
feat(cpufeat): constrain RAS_TRAP_NS_ERR_REC_ACCESS on ENABLE_FEAT_RAS
fix(build): set defaults to feature flags before platform.mk
refactor(cpufeat): unify FEAT_IDTE3's definitions with arch.h
refactor(el3-runtime): generalise sysreg trapping
refactor(el3-runtime): use contexted SCR_EL3 instead of the register
build: rename default_ones to set_ones

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fix(cpufeat): fix compiler warning in feature detection

The underlying types are unsigned but the placeholders are signed. This
sometimes produces warnings.

Change-Id: I8dccfc0cfc7a48ae0bd531065abf

fix(cpufeat): fix compiler warning in feature detection

The underlying types are unsigned but the placeholders are signed. This
sometimes produces warnings.

Change-Id: I8dccfc0cfc7a48ae0bd531065abf4b34a75cab06
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(el3-runtime): use contexted SCR_EL3 instead of the register

One of the first things EL3 does (via prepare_el3_entry()) is to update
its SCR_EL3. As a result, reading it later to make decisi

refactor(el3-runtime): use contexted SCR_EL3 instead of the register

One of the first things EL3 does (via prepare_el3_entry()) is to update
its SCR_EL3. As a result, reading it later to make decision about the
suspended world's runtime is no longer valid. Up until now, EL3 hasn't
changed any bits that would affect this decision making but this can
change at any time with any root context expansion. Use the contexted
copy to prevent this altogether.

Change-Id: I81d9b73afb0bde26136e9e35c2e540acc6bee677
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore(cpufeat): check FEAT_RAS's dependency on FEAT_IESB

Our enablement of FEAT_RAS hinges on the assumption that FEAT_IESB will
also be there. That is true for all cores implemented to date, howeve

chore(cpufeat): check FEAT_RAS's dependency on FEAT_IESB

Our enablement of FEAT_RAS hinges on the assumption that FEAT_IESB will
also be there. That is true for all cores implemented to date, however,
it is not architecturally required. Add a feat detect check to catch
if this assumption ever stops being true.

Change-Id: Ie76f11e1eb76044c68ce18c7ffc39ef9c587d6e0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option perfor

feat(rmmd): replace ENABLE_RME with ENABLE_RMM

RME architectural requirements are now handled under the feature
detection option ENABLE_FEAT_RME. However, the existing ENABLE_RME build
option performs RMM-specific tasks such as GPT setup, loading the RMM,
and enabling RMMD support.

Since ENABLE_RME now only controls RMM-related functionality, rename it
to ENABLE_RMM to better reflect its purpose and avoid confusion with
ENABLE_FEAT_RME.

For backward compatibility, setting the legacy ENABLE_RME=1 (until it is
deprecated) will automatically enable both ENABLE_FEAT_RME and
ENABLE_RMM.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: Iac945bdffe5002161bf1161b81a5aa7abec68192

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feat(rme): split off ENABLE_FEAT_RME

ENABLE_RME currently controls multiple, distinct aspects of RME support,
including forcing BL2 to EL3, ROOT world page table setup, GPT
initialization, and full

feat(rme): split off ENABLE_FEAT_RME

ENABLE_RME currently controls multiple, distinct aspects of RME support,
including forcing BL2 to EL3, ROOT world page table setup, GPT
initialization, and full RMM loading and handling.

While full CCA support requires all of these steps, some systems running
on FEAT_RME-capable cores do not need or want an RMM. However, such
systems still require TF-A page table entries to set the .NSE bit so
that TF-A accesses are correctly attributed to the ROOT world,
otherwise, enabling the MMU may cause the system to hang.

To address this, a new build option, ENABLE_FEAT_RME, is introduced. It
handles only the .NSE PTE setup and ignores the rest of the RME/RMM
initialization. ENABLE_FEAT_RME follows the ENABLE_FEAT_* convention and
supports values 0–2, with 2 enabling runtime detection.

Full RME functionality remains gated by ENABLE_RME, which now implicitly
enables ENABLE_FEAT_RME, allowing TF-A to run safely on FEAT_RME systems
without requiring an RMM.

Change-Id: I8391652842ff2e62a73b61829c6250c3805d4a4e
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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Merge "test(bl): add short-read negative test scenario" into integration

test(bl): add short-read negative test scenario

Add an opt-in negative test mode that simulates a short read
for a selected image_id during image loading. This exercises
the partial-read error handl

test(bl): add short-read negative test scenario

Add an opt-in negative test mode that simulates a short read
for a selected image_id during image loading. This exercises
the partial-read error handling path and is intended for CI
validation only.

Disabled by default via build options.

Change-Id: I219b75898e1778c0b263f99a9370425098d52f8f
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

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perf(el3-runtime): only check for EAs with FFH_SUPPORT

Without FFH_SUPPORT we won't set SCR_EL3.EA and as such we do not expect
External Aborts to end up in EL from lower ELs. So we can skip the che

perf(el3-runtime): only check for EAs with FFH_SUPPORT

Without FFH_SUPPORT we won't set SCR_EL3.EA and as such we do not expect
External Aborts to end up in EL from lower ELs. So we can skip the check
to gain a tiny bit of speed.

Change-Id: I5cdecf75f50ab6bbe50cd37580905f5a2904fb7f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): bump FEATURE_DETECTION features up to 9.5

FEAT_LSE has a new revision FEAT_LSE128 which requires no support but we
tolerate. FEAT_MTPMU has the 0b1111 variant that was never checked b

feat(cpufeat): bump FEATURE_DETECTION features up to 9.5

FEAT_LSE has a new revision FEAT_LSE128 which requires no support but we
tolerate. FEAT_MTPMU has the 0b1111 variant that was never checked but
is perfectly valid from the point of view of the flag - the MTPMU is
disabled even though the feature isn't implemented.

Change-Id: I0a89eb5ade96e42bfeeb50cc54fad84ab5d60415
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(el3-runtime): handle SVE/SMC traps instead of panicing

We generally expect hardware's and firmware's view of features to match.
However, either on purpose or by accident this may not be the case

fix(el3-runtime): handle SVE/SMC traps instead of panicing

We generally expect hardware's and firmware's view of features to match.
However, either on purpose or by accident this may not be the case. When
this happens we expect any instruction/register traps to result in an
UNDEF exception being injected into the lower EL and under no
circumstances panic at EL3. Well, SVE and SME have their own exception
syndromes that we didn't catch, resulting in a panic if misconfigured.

This patch make the UNDEF injection logic to be a fallback for anything
that wasn't otherwise handled. Exception syndromes that need special
actions are explicitly matched. This ensures that all of the various
instruction traps end up on an UNDEF rather than a panic.

There is a slight corner case in which a new and unlisted exception
syndrome is encountered. In that case, an incorrect UNDEF injection into
the lower EL will happen instead of the old panic at EL3. Neither option
is desired and both will likely result in an unusable system so the less
harmful one is chosen.

Change-Id: I36b4aee109ff6f87f3ef7c34b74346ca51d1f753
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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Merge "fix(bl): error out if image read size is too short" into integration

feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS wo

feat(cpufeat): add support for FEAT_HACDBS

The Hardware accelerator for cleaning Dirty state feature also has two
register just like FEAT_HDBSS. They are guarded by a SCR_EL3 bit which
set for NS world only and are not context switched as a result. There is
no use for this feature at EL3.

Change-Id: Ica7a312d891a1671df8e9f2adbfe464d96bbcd4d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for

feat(cpufeat): add support for FEAT_HDBSS

The Hardware Dirty state tracking structure feature has two registers to
enable tracking at lower ELs which are guarded by an SCR_EL3 bit. Set
that bit for NS only and do not context switch the registers. There is
no use of the feature at EL3.

Change-Id: I174a256d70a99abfafc65eed3a2fbdaea5ea946d
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a0

feat(cpufeat): add support for FEAT_STEP2

This feature only needs MDCR_EL3.EnSTEPOP to be written and mdstepop_el1
to be context switched when the next EL is EL1.

Change-Id: I70e2a488f4e50da4b181a00648c4f608e1da451c
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(bl): error out if image read size is too short

Change the return value of function to error value when image read is
shorter than expected file length.

Signed-off-by: Marek Vasut <marek.vasut+r

fix(bl): error out if image read size is too short

Change the return value of function to error value when image read is
shorter than expected file length.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: If16a23c9e212e48271589e6782761c12e63766d7

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Merge changes from topic "xlnx_fix_misra_common_fdt_split" into integration

* changes:
fix(libfdt): resolve misra 10.3 violations
feat(lib): use C/assembler for HI/LO macros
fix(libfdt): addin

Merge changes from topic "xlnx_fix_misra_common_fdt_split" into integration

* changes:
fix(libfdt): resolve misra 10.3 violations
feat(lib): use C/assembler for HI/LO macros
fix(libfdt): adding missing curly braces
fix(libfdt): fix misra 14.4 and 15.6 violations
fix(libfdt): typecast operands to match data type

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Merge changes I2485d583,I1374c482,I07e29dbb,I949e6486 into integration

* changes:
feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB
feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status

Merge changes I2485d583,I1374c482,I07e29dbb,I949e6486 into integration

* changes:
feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB
feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status
feat(cpufeat): advertise support for FEAT_RASv2
feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

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Merge changes I3a2243d0,Ifeb88c8f,I8ac77336 into integration

* changes:
feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION
docs(cpufeat): add analysis of 2024 features
fix(cpu

Merge changes I3a2243d0,Ifeb88c8f,I8ac77336 into integration

* changes:
feat(cpufeat): add the newly analyzed features to FEATURE_DETECTION
docs(cpufeat): add analysis of 2024 features
fix(cpufeat): add FEAT_SPE to FEATURE_DETECTION

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fix(libfdt): resolve misra 10.3 violations

The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replace the hard‑co

fix(libfdt): resolve misra 10.3 violations

The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
Replace the hard‑coded low‑bits mask with the LO() macro to avoid
implicit type conversions and ensure compliance with MISRA 10.3.

Change-Id: I09696e90733b101c346f4e3e3c2baf63dc1b6607
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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feat(cpufeat): advertise support for FEAT_RASv2

From a PE architecture standpoint, FEAT_RASv2 only does three things:
* adds the SCR_EL3.TWERR trap bit (active high). That defaults to 0
unless RAS

feat(cpufeat): advertise support for FEAT_RASv2

From a PE architecture standpoint, FEAT_RASv2 only does three things:
* adds the SCR_EL3.TWERR trap bit (active high). That defaults to 0
unless RAS_TRAP_NS_ERR_REC_ACCESS overrides it but that's unused.
* adds the read only ERXGSR_EL1 register which cannot be saved/restored.
* changes the signalling of Uncontainable Instruction Aborts. When
FEAT_RASv2 is present Uncontainable EAs cannot happen and instead
SErrors will be signalled with more information.

So there isn't much to do and we can safely advertise FEAT_RASv2
support.

Change-Id: I07e29dbbd7fe824bed5a22ae22bd50eb16a0acd0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

FEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.
However, the ability to use it was removed with 970a4a8d8 by simply

feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

FEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.
However, the ability to use it was removed with 970a4a8d8 by simply
saying it impacts execution at EL3. That's true, but FEAT_STATE_CHECKED
can still be allowed by being a bit clever about it.

First, the remainder of common code can be converted to use the
is_feat_ras_supported() helper instead of the `#if FEATURE` pattern.
There are no corner cases to consider there. The feature is either
present (and appropriate action must be taken) or the feature is not (so
we can skip RAS code).

A conscious choice is taken to check the RAS code in synchronize_errors
despite it being in a hot path. Any fixed platform that seeks to be
performant should be setting features to 0 or 1. Then, the
SCTLR_EL3.IESB bit is always set if ENABLE_FEAT_RAS != 0 since we expect
FEAT_IESB to be present if FEAT_RAS is (despite the architecture not
guaranteeing it). If FEAT_RAS isn't present then we don't particularly
care about the status of FEAT_IESB.

Second, platforms that don't set ENABLE_FEAT_RAS must continue to work.
This is true out of the box with the is_feat_xyz_supported() helpers, as
they make sure to fully disable code within them.

Third, platforms that do set ENABLE_FEAT_RAS=1 must continue to work.
This is also true out of the box and no logical change is undertaken in
common code.

Finally, ENABLE_FEAT_RAS is set to 2 on FVP. Having RAS implies that the
whole handling machinery will be built-in and registered as appropriate.
However, when RAS is built-in but not present in hardware, these
registrations can still happen, they will only never be invoked at
runtime.

Change-Id: I949e648601dc0951ef9c2b217f34136b6ea4b3dc
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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fix(libfdt): adding missing curly braces

This corrects MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.
Enclosed statement body

fix(libfdt): adding missing curly braces

This corrects MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I71a1ad2a6f85edbf5133a7860453db2937988e22
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(libfdt): fix misra 14.4 and 15.6 violations

Fixed below MISRA violations:

MISRA violation C2012-14.4:
The controlling expression of an if statement and the controlling
expression of an iteratio

fix(libfdt): fix misra 14.4 and 15.6 violations

Fixed below MISRA violations:

MISRA violation C2012-14.4:
The controlling expression of an if statement and the controlling
expression of an iteration-statement shall have essentially Boolean
type.
Used boolean in control expressions for fixing this violation.

MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement
shall be a compound-statement.Enclosed statement body within
the curly braces.

Change-Id: Ic6536e1b749a7aacdf265c632ceea8d344f2e7b5
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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fix(libfdt): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a d

fix(libfdt): typecast operands to match data type

This corrects the MISRA violation C2012-10.3:
The value of an expression shall not be assigned to an object with a
narrower essential type or of a different essential type category.
The operand is explicitly typecasted to required type
to match the operand/return type.

Change-Id: I9d9a2e13225369281e2a1dc09d06bf6177d81f3a
Signed-off-by: Suraj Kakade <suraj.hanumantkakade@amd.com>

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