1 /* 2 * Copyright (c) 2023-2026, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #include <drivers/st/stm32mp2_clk.h> 14 #include <drivers/st/stm32mp2_risaf.h> 15 #include <drivers/st/stm32mp_rifsc_regs.h> 16 #endif 17 #if STM32MP21 18 #include <drivers/st/stm32mp21_pwr.h> 19 #include <drivers/st/stm32mp21_rcc.h> 20 #else /* STM32MP21 */ 21 #include <drivers/st/stm32mp2_pwr.h> 22 #include <drivers/st/stm32mp25_rcc.h> 23 #endif /* STM32MP21 */ 24 #if STM32MP21 25 #include <dt-bindings/clock/st,stm32mp21-rcc.h> 26 #include <dt-bindings/clock/stm32mp21-clksrc.h> 27 #include <dt-bindings/reset/st,stm32mp21-rcc.h> 28 #endif /* STM32MP21 */ 29 #if STM32MP23 30 #include <dt-bindings/clock/stm32mp25-clks.h> 31 #include <dt-bindings/clock/stm32mp25-clksrc.h> 32 #include <dt-bindings/reset/stm32mp25-resets.h> 33 #endif /* STM32MP23 */ 34 #if STM32MP25 35 #include <dt-bindings/clock/stm32mp25-clks.h> 36 #include <dt-bindings/clock/stm32mp25-clksrc.h> 37 #include <dt-bindings/reset/stm32mp25-resets.h> 38 #endif /* STM32MP25 */ 39 #include <dt-bindings/gpio/stm32-gpio.h> 40 #include <dt-bindings/soc/rif.h> 41 #include <dt-bindings/soc/stm32mp25-rif.h> 42 43 #ifndef __ASSEMBLER__ 44 #include <boot_api.h> 45 #include <stm32mp2_private.h> 46 #include <stm32mp_common.h> 47 #include <stm32mp_dt.h> 48 #include <stm32mp_shared_resources.h> 49 #endif 50 51 /******************************************************************************* 52 * CHIP ID 53 ******************************************************************************/ 54 #define STM32MP2_CHIP_ID U(0x505) 55 56 #define STM32MP251A_PART_NB U(0x400B3E6D) 57 #define STM32MP251C_PART_NB U(0x000B306D) 58 #define STM32MP251D_PART_NB U(0xC00B3E6D) 59 #define STM32MP251F_PART_NB U(0x800B306D) 60 #define STM32MP253A_PART_NB U(0x400B3E0C) 61 #define STM32MP253C_PART_NB U(0x000B300C) 62 #define STM32MP253D_PART_NB U(0xC00B3E0C) 63 #define STM32MP253F_PART_NB U(0x800B300C) 64 #define STM32MP255A_PART_NB U(0x40082E00) 65 #define STM32MP255C_PART_NB U(0x00082000) 66 #define STM32MP255D_PART_NB U(0xC0082E00) 67 #define STM32MP255F_PART_NB U(0x80082000) 68 #define STM32MP257A_PART_NB U(0x40002E00) 69 #define STM32MP257C_PART_NB U(0x00002000) 70 #define STM32MP257D_PART_NB U(0xC0002E00) 71 #define STM32MP257F_PART_NB U(0x80002000) 72 73 #define STM32MP2_REV_A U(0x08) 74 #define STM32MP2_REV_B U(0x10) 75 #define STM32MP2_REV_X U(0x12) 76 #define STM32MP2_REV_Y U(0x11) 77 #define STM32MP2_REV_Z U(0x09) 78 79 /******************************************************************************* 80 * PACKAGE ID 81 ******************************************************************************/ 82 #define STM32MP25_PKG_CUSTOM U(0) 83 #define STM32MP25_PKG_AL_VFBGA361 U(1) 84 #define STM32MP25_PKG_AK_VFBGA424 U(3) 85 #define STM32MP25_PKG_AI_TFBGA436 U(5) 86 #define STM32MP25_PKG_UNKNOWN U(7) 87 88 /******************************************************************************* 89 * STM32MP2 memory map related constants 90 ******************************************************************************/ 91 #define STM32MP_SYSRAM_BASE U(0x0E000000) 92 #define STM32MP_SYSRAM_SIZE U(0x00040000) 93 #define SRAM1_BASE U(0x0E040000) 94 #define SRAM1_SIZE_FOR_TFA U(0x00010000) 95 #define RETRAM_BASE U(0x0E080000) 96 #define RETRAM_SIZE U(0x00020000) 97 98 #if defined(IMAGE_BL2) && STM32MP_USB_PROGRAMMER 99 #define STM32MP_USB_DWC3_SIZE PAGE_SIZE 100 #define STM32MP_USB_DWC3_BASE (STM32MP_SYSRAM_BASE + \ 101 STM32MP_SYSRAM_SIZE - \ 102 STM32MP_SYSRAM_DEVICE_SIZE) 103 104 #define STM32MP_SYSRAM_DEVICE_SIZE STM32MP_USB_DWC3_SIZE 105 #define STM32MP_SYSRAM_DEVICE_BASE STM32MP_USB_DWC3_BASE 106 107 #define STM32MP_SYSRAM_MEM_SIZE (STM32MP_SYSRAM_SIZE - \ 108 STM32MP_SYSRAM_DEVICE_SIZE) 109 #define STM32MP_SYSRAM_MEM_BASE STM32MP_SYSRAM_BASE 110 #endif /* IMAGE_BL2 && STM32MP_USB_PROGRAMMER */ 111 112 /* DDR configuration */ 113 #define STM32MP_DDR_BASE U(0x80000000) 114 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 115 116 /* DDR power initializations */ 117 #ifndef __ASSEMBLER__ 118 enum ddr_type { 119 STM32MP_DDR3, 120 STM32MP_DDR4, 121 STM32MP_LPDDR4 122 }; 123 #endif 124 125 /* Section used inside TF binaries */ 126 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 127 /* 512 Bytes reserved for header */ 128 #define STM32MP_HEADER_SIZE U(0x00000200) 129 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \ 130 STM32MP_PARAM_LOAD_SIZE) 131 132 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 133 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 134 135 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 136 STM32MP_PARAM_LOAD_SIZE + \ 137 STM32MP_HEADER_SIZE) 138 139 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 140 (STM32MP_PARAM_LOAD_SIZE + \ 141 STM32MP_HEADER_SIZE)) 142 143 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 144 #define STM32MP_BL2_RO_SIZE U(0x0001F000) /* 124 KB */ 145 #define STM32MP_BL2_SIZE U(0x00028000) /* 160 KB for BL2 */ 146 #else /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 147 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */ 148 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */ 149 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 150 151 /* Allocate remaining sysram to BL31 Binary only */ 152 #define STM32MP_BL31_SIZE (STM32MP_SYSRAM_SIZE - \ 153 STM32MP_BL2_SIZE) 154 155 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \ 156 STM32MP_SYSRAM_SIZE - \ 157 STM32MP_BL2_SIZE) 158 159 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 160 161 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 162 STM32MP_BL2_RO_SIZE) 163 164 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 165 STM32MP_SYSRAM_SIZE - \ 166 STM32MP_BL2_RW_BASE) 167 168 /* BL2 and BL32/sp_min require 4 tables */ 169 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 170 171 /* 172 * MAX_MMAP_REGIONS is usually: 173 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 174 */ 175 #if STM32MP_USB_PROGRAMMER || defined(IMAGE_BL31) 176 #define MAX_MMAP_REGIONS 7 177 #else 178 #define MAX_MMAP_REGIONS 6 179 #endif 180 181 /* DTB initialization value */ 182 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ 183 184 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 185 STM32MP_BL2_DTB_SIZE) 186 187 #if defined(IMAGE_BL2) 188 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 189 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 190 #endif 191 192 #if STM32MP_DDR_FIP_IO_STORAGE 193 #define STM32MP_DDR_FW_BASE SRAM1_BASE 194 #define STM32MP_DDR_FW_DMEM_OFFSET U(0x400) 195 #define STM32MP_DDR_FW_IMEM_OFFSET U(0x800) 196 #define STM32MP_DDR_FW_MAX_SIZE U(0x8800) 197 #endif 198 199 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE 200 #define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE 201 202 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 203 #define STM32MP_BL33_MAX_SIZE U(0x400000) 204 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 205 STM32MP_BL33_MAX_SIZE) 206 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) 207 #define STM32MP_SOC_FW_CONFIG_MAX_SIZE U(0x10000) /* 64kB for BL31 DT */ 208 209 /******************************************************************************* 210 * STM32MP2 device/io map related constants (used for MMU) 211 ******************************************************************************/ 212 #define STM32MP_DEVICE_BASE U(0x40000000) 213 #define STM32MP_DEVICE_SIZE U(0x40000000) 214 215 /******************************************************************************* 216 * STM32MP2 RCC 217 ******************************************************************************/ 218 #define RCC_BASE U(0x44200000) 219 220 /******************************************************************************* 221 * STM32MP2 PWR 222 ******************************************************************************/ 223 #define PWR_BASE U(0x44210000) 224 225 /******************************************************************************* 226 * STM32MP2 GPIO 227 ******************************************************************************/ 228 #define GPIOA_BASE U(0x44240000) 229 #define GPIOB_BASE U(0x44250000) 230 #define GPIOC_BASE U(0x44260000) 231 #define GPIOD_BASE U(0x44270000) 232 #define GPIOE_BASE U(0x44280000) 233 #define GPIOF_BASE U(0x44290000) 234 #define GPIOG_BASE U(0x442A0000) 235 #define GPIOH_BASE U(0x442B0000) 236 #define GPIOI_BASE U(0x442C0000) 237 #define GPIOJ_BASE U(0x442D0000) 238 #define GPIOK_BASE U(0x442E0000) 239 #define GPIOZ_BASE U(0x46200000) 240 #define GPIO_BANK_OFFSET U(0x10000) 241 242 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 243 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 244 245 /******************************************************************************* 246 * STM32MP2 UART 247 ******************************************************************************/ 248 #define USART1_BASE U(0x40330000) 249 #define USART2_BASE U(0x400E0000) 250 #define USART3_BASE U(0x400F0000) 251 #define UART4_BASE U(0x40100000) 252 #define UART5_BASE U(0x40110000) 253 #define USART6_BASE U(0x40220000) 254 #define UART7_BASE U(0x40370000) 255 #define UART8_BASE U(0x40380000) 256 #define UART9_BASE U(0x402C0000) 257 #define STM32MP_NB_OF_UART U(9) 258 259 /* For UART crash console */ 260 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 261 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 262 #ifdef ULTRA_FLY 263 #define STM32MP_DEBUG_USART_BASE USART1_BASE 264 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 265 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 266 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 267 #define DEBUG_UART_TX_GPIO_PORT 3 268 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 269 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 270 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 271 #define DEBUG_UART_TX_EN_REG RCC_USART1CFGR 272 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 273 #define DEBUG_UART_RST_REG RCC_USART1CFGR 274 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 275 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV19CFGR 276 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV19CFGR 277 #else 278 #define STM32MP_DEBUG_USART_BASE USART2_BASE 279 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 280 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 281 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 282 #define DEBUG_UART_TX_GPIO_PORT 4 283 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 284 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 285 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 286 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 287 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 288 #define DEBUG_UART_RST_REG RCC_USART2CFGR 289 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 290 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 291 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 292 #endif 293 294 /******************************************************************************* 295 * STM32MP2 SDMMC 296 ******************************************************************************/ 297 #define STM32MP_SDMMC1_BASE U(0x48220000) 298 #define STM32MP_SDMMC2_BASE U(0x48230000) 299 #define STM32MP_SDMMC3_BASE U(0x48240000) 300 301 /******************************************************************************* 302 * STM32MP2 OSPI 303 ******************************************************************************/ 304 /* OSPI 1 & 2 memory map area */ 305 #define STM32MP_OSPI_MM_BASE U(0x60000000) 306 #define STM32MP_OSPI_MM_SIZE U(0x10000000) 307 308 /******************************************************************************* 309 * STM32MP2 BSEC / OTP 310 ******************************************************************************/ 311 /* 312 * 367 available OTPs, the other are masked 313 * - ECIES key: 368 to 375 (only readable by bootrom) 314 * - HWKEY: 376 to 383 (never reloadable or readable) 315 */ 316 #define STM32MP2_OTP_MAX_ID U(0x16F) 317 #define STM32MP2_MID_OTP_START U(0x80) 318 #define STM32MP2_UPPER_OTP_START U(0x100) 319 320 /* OTP labels */ 321 #define PART_NUMBER_OTP "part-number-otp" 322 #define REVISION_OTP "rev_otp" 323 #define PACKAGE_OTP "package-otp" 324 #define HCONF1_OTP "otp124" 325 #define NAND_OTP "otp16" 326 #define NAND2_OTP "otp20" 327 #define BOARD_ID_OTP "board-id" 328 #define UID_OTP "uid-otp" 329 #define LIFECYCLE2_OTP "otp18" 330 #define PKH_OTP "otp144" 331 #define ENCKEY_OTP "otp260" 332 333 /* OTP mask */ 334 /* PACKAGE */ 335 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0) 336 #define PACKAGE_OTP_PKG_SHIFT U(0) 337 338 /* IWDG OTP */ 339 #define HCONF1_OTP_IWDG_HW_POS U(0) 340 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1) 341 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2) 342 343 /* NAND OTP */ 344 /* NAND parameter storage flag */ 345 #define NAND_PARAM_STORED_IN_OTP BIT_32(31) 346 347 /* NAND page size in bytes */ 348 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 349 #define NAND_PAGE_SIZE_SHIFT U(29) 350 #define NAND_PAGE_SIZE_2K U(0) 351 #define NAND_PAGE_SIZE_4K U(1) 352 #define NAND_PAGE_SIZE_8K U(2) 353 354 /* NAND block size in pages */ 355 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 356 #define NAND_BLOCK_SIZE_SHIFT U(27) 357 #define NAND_BLOCK_SIZE_64_PAGES U(0) 358 #define NAND_BLOCK_SIZE_128_PAGES U(1) 359 #define NAND_BLOCK_SIZE_256_PAGES U(2) 360 361 /* NAND number of block (in unit of 256 blocks) */ 362 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 363 #define NAND_BLOCK_NB_SHIFT U(19) 364 #define NAND_BLOCK_NB_UNIT U(256) 365 366 /* NAND bus width in bits */ 367 #define NAND_WIDTH_MASK BIT_32(18) 368 #define NAND_WIDTH_SHIFT U(18) 369 370 /* NAND number of ECC bits per 512 bytes */ 371 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 372 #define NAND_ECC_BIT_NB_SHIFT U(15) 373 #define NAND_ECC_BIT_NB_UNSET U(0) 374 #define NAND_ECC_BIT_NB_1_BITS U(1) 375 #define NAND_ECC_BIT_NB_4_BITS U(2) 376 #define NAND_ECC_BIT_NB_8_BITS U(3) 377 #define NAND_ECC_ON_DIE U(4) 378 379 /* NAND number of planes */ 380 #define NAND_PLANE_BIT_NB_MASK BIT_32(14) 381 382 /* NAND2 OTP */ 383 #define NAND2_PAGE_SIZE_SHIFT U(16) 384 385 /* NAND2 config distribution */ 386 #define NAND2_CONFIG_DISTRIB BIT_32(0) 387 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 388 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 389 390 /* MONOTONIC OTP */ 391 #define MAX_MONOTONIC_VALUE U(32) 392 393 /* UID OTP */ 394 #define UID_WORD_NB U(3) 395 396 /* Lifecycle OTP */ 397 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0) 398 399 /******************************************************************************* 400 * STM32MP2 TAMP 401 ******************************************************************************/ 402 #define PLAT_MAX_TAMP_INT U(5) 403 #define PLAT_MAX_TAMP_EXT U(3) 404 #define TAMP_BASE U(0x46010000) 405 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 406 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 407 #define TAMP_BKP_REG_CLK CK_BUS_RTC 408 #define TAMP_BKP_SEC_NUMBER U(10) 409 #define TAMP_COUNTR U(0x40) 410 411 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 412 static inline uintptr_t tamp_bkpr(uint32_t idx) 413 { 414 return TAMP_BKP_REGISTER_BASE + (idx << 2); 415 } 416 #endif 417 418 /******************************************************************************* 419 * STM32MP2 USB 420 ******************************************************************************/ 421 #define USB_DWC3_BASE U(0x48300000) 422 423 /******************************************************************************* 424 * STM32MP2 DDRCTRL 425 ******************************************************************************/ 426 #define DDRCTRL_BASE U(0x48040000) 427 428 /******************************************************************************* 429 * STM32MP2 DDRDBG 430 ******************************************************************************/ 431 #define DDRDBG_BASE U(0x48050000) 432 433 /******************************************************************************* 434 * STM32MP2 DDRPHYC 435 ******************************************************************************/ 436 #define DDRPHYC_BASE U(0x48C00000) 437 438 /******************************************************************************* 439 * Miscellaneous STM32MP2 peripherals base address 440 ******************************************************************************/ 441 #define BSEC_BASE U(0x44000000) 442 #define DBGMCU_BASE U(0x4A010000) 443 #define HASH_BASE U(0x42010000) 444 #define RTC_BASE U(0x46000000) 445 #define STGEN_BASE U(0x48080000) 446 #define SYSCFG_BASE U(0x44230000) 447 448 /******************************************************************************* 449 * STM32MP RIF 450 ******************************************************************************/ 451 #define RIFSC_BASE U(0x42080000) 452 #define RISAB1_BASE U(0x420F0000) 453 #define RISAB2_BASE U(0x42100000) 454 #define RISAB3_BASE U(0x42110000) 455 #define RISAB5_BASE U(0x42130000) 456 457 #define RISAF1_INST 0 458 #define RISAF2_INST 1 459 #define RISAF4_INST 3 460 #define RISAF5_INST 4 461 #define RISAF_MAX_INSTANCE 5 462 463 #define RISAF1_BASE U(0x420A0000) 464 #define RISAF2_BASE U(0x420B0000) 465 #define RISAF4_BASE U(0x420D0000) 466 #define RISAF5_BASE U(0x420E0000) 467 468 #define USE_RISAF2 469 #define USE_RISAF4 470 471 #ifdef USE_RISAF1 472 #define RISAF1_MAX_REGION 4 473 #else 474 #define RISAF1_MAX_REGION 0 475 #endif 476 #ifdef USE_RISAF2 477 #define RISAF2_MAX_REGION 4 478 #else 479 #define RISAF2_MAX_REGION 0 480 #endif 481 #ifdef USE_RISAF4 482 /* Consider only encrypted region maximum number, to save memory consumption */ 483 #define RISAF4_MAX_REGION 4 484 #else 485 #define RISAF4_MAX_REGION 0 486 #endif 487 #ifdef USE_RISAF5 488 #define RISAF5_MAX_REGION 2 489 #else 490 #define RISAF5_MAX_REGION 0 491 #endif 492 #define RISAF_MAX_REGION (RISAF1_MAX_REGION + RISAF2_MAX_REGION + \ 493 RISAF4_MAX_REGION + RISAF5_MAX_REGION) 494 495 #define RISAF_KEY_SIZE_IN_BYTES RISAF_ENCRYPTION_KEY_SIZE_IN_BYTES 496 #define RISAF_SEED_SIZE_IN_BYTES U(4) 497 498 /******************************************************************************* 499 * RIFSC 500 ******************************************************************************/ 501 #define STM32MP2_RIMU_USB3DR U(4) 502 503 /* 504 * USB3DR Secure/Priv Master (DMA) access 505 */ 506 #define RIFSC_USB_BOOT_USB3DR_RIMC_CONF (RIFSC_RIMC_ATTRx_MPRIV | RIFSC_RIMC_ATTRx_MSEC | \ 507 RIF_CID1 << RIFSC_RIMC_ATTRx_MCID_SHIFT | \ 508 RIFSC_RIMC_ATTRx_CIDSEL) 509 510 /******************************************************************************* 511 * STM32MP CA35SSC 512 ******************************************************************************/ 513 #define A35SSC_BASE U(0x48800000) 514 515 /******************************************************************************* 516 * REGULATORS 517 ******************************************************************************/ 518 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 519 #define PLAT_NB_RDEVS U(19) 520 /* 2 FIXED */ 521 #define PLAT_NB_FIXED_REGUS U(2) 522 /* No GPIO regu */ 523 #define PLAT_NB_GPIO_REGUS U(0) 524 525 /******************************************************************************* 526 * Device Tree defines 527 ******************************************************************************/ 528 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 529 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 530 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 531 #if STM32MP21 532 #define DT_RCC_CLK_COMPAT "st,stm32mp21-rcc" 533 #else 534 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 535 #endif 536 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2" 537 #define DT_UART_COMPAT "st,stm32h7-uart" 538 539 #endif /* STM32MP2_DEF_H */ 540