1 /* 2 * Copyright 2018-2021 NXP 3 * Copyright (c) 2025, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 * 7 */ 8 9 #ifndef PLAT_COMMON_H 10 #define PLAT_COMMON_H 11 12 #include <stdbool.h> 13 14 #include <dcfg.h> 15 #include <lib/el3_runtime/cpu_data.h> 16 17 #include <platform_def.h> 18 19 #ifdef IMAGE_BL31 20 21 #define BL31_END (uintptr_t)(&__BL31_END__) 22 23 /******************************************************************************* 24 * This structure represents the superset of information that can be passed to 25 * BL31 e.g. while passing control to it from BL2. The BL32 parameters will be 26 * populated only if BL2 detects its presence. A pointer to a structure of this 27 * type should be passed in X0 to BL31's cold boot entrypoint. 28 * 29 * Use of this structure and the X0 parameter is not mandatory: the BL31 30 * platform code can use other mechanisms to provide the necessary information 31 * about BL32 and BL33 to the common and SPD code. 32 * 33 * BL31 image information is mandatory if this structure is used. If either of 34 * the optional BL32 and BL33 image information is not provided, this is 35 * indicated by the respective image_info pointers being zero. 36 ******************************************************************************/ 37 typedef struct bl31_params { 38 param_header_t h; 39 image_info_t *bl31_image_info; 40 entry_point_info_t *bl32_ep_info; 41 image_info_t *bl32_image_info; 42 entry_point_info_t *bl33_ep_info; 43 image_info_t *bl33_image_info; 44 } bl31_params_t; 45 46 /* BL3 utility functions */ 47 void ls_bl31_early_platform_setup(void *from_bl2, 48 void *plat_params_from_bl2); 49 /* LS Helper functions */ 50 unsigned int plat_my_core_mask(void); 51 unsigned int plat_core_mask(u_register_t mpidr); 52 unsigned int plat_core_pos(u_register_t mpidr); 53 //unsigned int plat_my_core_pos(void); 54 55 /* BL31 Data API(s) */ 56 void _init_global_data(void); 57 void _initialize_psci(void); 58 uint32_t _getCoreState(u_register_t core_mask); 59 void _setCoreState(u_register_t core_mask, u_register_t core_state); 60 61 /* SoC defined structure and API(s) */ 62 void soc_runtime_setup(void); 63 void soc_init(void); 64 void soc_platform_setup(void); 65 void soc_early_platform_setup2(void); 66 #endif /* IMAGE_BL31 */ 67 68 #ifdef IMAGE_BL2 69 void soc_early_init(void); 70 void soc_mem_access(void); 71 void soc_preload_setup(void); 72 void soc_bl2_prepare_exit(void); 73 74 /* IO storage utility functions */ 75 int plat_io_setup(void); 76 int open_backend(const uintptr_t spec); 77 78 void ls_bl2_plat_arch_setup(void); 79 80 enum boot_device { 81 BOOT_DEVICE_IFC_NOR, 82 BOOT_DEVICE_IFC_NAND, 83 BOOT_DEVICE_QSPI, 84 BOOT_DEVICE_EMMC, 85 BOOT_DEVICE_SDHC2_EMMC, 86 BOOT_DEVICE_FLEXSPI_NOR, 87 BOOT_DEVICE_FLEXSPI_NAND, 88 BOOT_DEVICE_NONE 89 }; 90 91 enum boot_device get_boot_dev(void); 92 93 /* DDR Related functions */ 94 #if DDR_INIT 95 #ifdef NXP_WARM_BOOT 96 long long init_ddr(uint32_t wrm_bt_flg); 97 #else 98 long long init_ddr(void); 99 #endif 100 #endif 101 102 /* Board specific weak functions */ 103 bool board_enable_povdd(void); 104 bool board_disable_povdd(void); 105 106 void mmap_add_ddr_region_dynamically(void); 107 #endif /* IMAGE_BL2 */ 108 109 typedef struct { 110 uint64_t addr; 111 uint64_t size; 112 } region_info_t; 113 114 typedef struct { 115 uint64_t num_dram_regions; 116 int64_t total_dram_size; 117 region_info_t region[NUM_DRAM_REGIONS]; 118 } dram_regions_info_t; 119 120 dram_regions_info_t *get_dram_regions_info(void); 121 122 void ls_setup_page_tables(uintptr_t total_base, 123 size_t total_size, 124 uintptr_t code_start, 125 uintptr_t code_limit, 126 uintptr_t rodata_start, 127 uintptr_t rodata_limit 128 #if USE_COHERENT_MEM 129 , uintptr_t coh_start, 130 uintptr_t coh_limit 131 #endif 132 ); 133 134 #define SOC_NAME_MAX_LEN (20) 135 136 /* Structure to define SoC personality */ 137 struct soc_type { 138 char name[SOC_NAME_MAX_LEN]; 139 uint32_t version; 140 uint8_t num_clusters; 141 uint8_t cores_per_cluster; 142 }; 143 void get_cluster_info(const struct soc_type *soc_list, uint8_t ps_count, 144 uint8_t *num_clusters, uint8_t *cores_per_cluster); 145 146 #define SOC_ENTRY(n, v, ncl, nc) { \ 147 .name = #n, \ 148 .version = SVR_##v, \ 149 .num_clusters = (ncl), \ 150 .cores_per_cluster = (nc)} 151 152 #endif /* PLAT_COMMON_H */ 153