1 /* 2 * Copyright (c) 2013-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <arch_features.h> 14 #include <bl31/interrupt_mgmt.h> 15 #include <bl31/sync_handle.h> 16 #include <bl31/ea_handle.h> 17 #include <common/debug.h> 18 #include <common/runtime_svc.h> 19 #include <context.h> 20 #include <lib/cpus/cpu_ops.h> 21 #include <plat/common/platform.h> 22 23 /******************************************************************************* 24 * The 'rt_svc_descs' array holds the runtime service descriptors exported by 25 * services by placing them in the 'rt_svc_descs' linker section. 26 * The 'rt_svc_descs_indices' array holds the index of a descriptor in the 27 * 'rt_svc_descs' array. When an SMC arrives, the OEN[29:24] bits and the call 28 * type[31] bit in the function id are combined to get an index into the 29 * 'rt_svc_descs_indices' array. This gives the index of the descriptor in the 30 * 'rt_svc_descs' array which contains the SMC handler. 31 ******************************************************************************/ 32 uint8_t rt_svc_descs_indices[MAX_RT_SVCS]; 33 34 void __dead2 report_unhandled_exception(void); 35 36 #define RT_SVC_DECS_NUM ((RT_SVC_DESCS_END - RT_SVC_DESCS_START)\ 37 / sizeof(rt_svc_desc_t)) 38 39 static bool get_handler_for_smc_fid(uint32_t smc_fid, rt_svc_handle_t *handler) 40 { 41 unsigned int index; 42 unsigned int idx; 43 const rt_svc_desc_t *rt_svc_descs; 44 45 idx = get_unique_oen_from_smc_fid(smc_fid); 46 assert(idx < MAX_RT_SVCS); 47 index = rt_svc_descs_indices[idx]; 48 49 if (index >= RT_SVC_DECS_NUM) 50 return false; 51 52 rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START; 53 assert(handler != NULL); 54 *handler = rt_svc_descs[index].handle; 55 assert(*handler != NULL); 56 57 return true; 58 } 59 60 #if __aarch64__ 61 #include <lib/extensions/ras_arch.h> 62 63 #if FFH_SUPPORT 64 static void ea_proceed(uint32_t ea_reason, u_register_t esr_el3, cpu_context_t *ctx) 65 { 66 /* 67 * If it is a double fault invoke platform handler. Double fault 68 * scenario would arise when platform is handling a fault in lower EL 69 * using plat_ea_handler() and another fault happens which would trap 70 * into EL3 as FFH_SUPPORT is enabled for the platform. 71 */ 72 el3_state_t *state = get_el3state_ctx(ctx); 73 if (read_ctx_reg(state, CTX_DOUBLE_FAULT_ESR) != 0) { 74 return plat_handle_double_fault(ea_reason, esr_el3); 75 } 76 77 /* 78 * Save CTX_DOUBLE_FAULT_ESR, so that if another fault happens in lower 79 * EL, we catch it as DoubleFault in next invocation of ea_proceed() 80 * along with preserving original ESR_EL3. 81 */ 82 write_ctx_reg(state, CTX_DOUBLE_FAULT_ESR, esr_el3); 83 84 /* Call platform External Abort handler. */ 85 plat_ea_handler(ea_reason, esr_el3, NULL, ctx, read_scr_el3() & SCR_NS_BIT); 86 87 /* Clear Double Fault storage */ 88 write_ctx_reg(state, CTX_DOUBLE_FAULT_ESR, 0); 89 } 90 91 /* 92 * This function handles SErrors from lower ELs. 93 * 94 * It delegates the handling of the EA to platform handler, and upon 95 * successfully handling the EA, exits EL3 96 */ 97 void handler_lower_el_async_ea(cpu_context_t *ctx) 98 { 99 u_register_t esr_el3 = read_esr_el3(); 100 101 #if ENABLE_FEAT_RAS 102 /* should only be invoked for SError */ 103 assert(EXTRACT(ESR_EC, esr_el3) == EC_SERROR); 104 105 /* 106 * Check for Implementation Defined Syndrome. If so, skip checking 107 * Uncontainable error type from the syndrome as the format is unknown. 108 */ 109 if ((esr_el3 & SERROR_IDS_BIT) != 0) { 110 /* AET only valid when DFSC is 0x11. Route to platform fatal 111 * error handler if it is an uncontainable error type */ 112 if (EXTRACT(EABORT_DFSC, esr_el3) == DFSC_SERROR && 113 EXTRACT(EABORT_AET, esr_el3) == ERROR_STATUS_UET_UC) { 114 return plat_handle_uncontainable_ea(); 115 } 116 } 117 #endif 118 return ea_proceed(ERROR_EA_ASYNC, esr_el3, ctx); 119 } 120 121 #endif /* FFH_SUPPORT */ 122 123 /* 124 * This function handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 125 * interrupts. 126 */ 127 void handler_interrupt_exception(cpu_context_t *ctx) 128 { 129 /* 130 * Find out whether this is a valid interrupt type. 131 * If the interrupt controller reports a spurious interrupt then return 132 * to where we came from. 133 */ 134 uint32_t type = plat_ic_get_pending_interrupt_type(); 135 if (type == INTR_TYPE_INVAL) { 136 return; 137 } 138 139 /* 140 * Get the registered handler for this interrupt type. 141 * A NULL return value could be 'cause of the following conditions: 142 * 143 * a. An interrupt of a type was routed correctly but a handler for its 144 * type was not registered. 145 * 146 * b. An interrupt of a type was not routed correctly so a handler for 147 * its type was not registered. 148 * 149 * c. An interrupt of a type was routed correctly to EL3, but was 150 * deasserted before its pending state could be read. Another 151 * interrupt of a different type pended at the same time and its 152 * type was reported as pending instead. However, a handler for this 153 * type was not registered. 154 * 155 * a. and b. can only happen due to a programming error. The 156 * occurrence of c. could be beyond the control of Trusted Firmware. 157 * It makes sense to return from this exception instead of reporting an 158 * error. 159 */ 160 interrupt_type_handler_t handler = get_interrupt_type_handler(type); 161 if (handler == NULL) { 162 return; 163 } 164 165 handler(INTR_ID_UNAVAILABLE, read_scr_el3() & SCR_NS_BIT, ctx, NULL); 166 } 167 168 static void smc_unknown(cpu_context_t *ctx) 169 { 170 /* 171 * Unknown SMC call. Populate return value with SMC_UNK and call 172 * el3_exit() which will restore the remaining architectural state 173 * i.e., SYS, GP and PAuth registers(if any) prior to issuing the ERET 174 * to the desired lower EL. 175 */ 176 write_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0, SMC_UNK); 177 } 178 179 static u_register_t get_flags(uint32_t smc_fid, u_register_t scr_el3) 180 { 181 u_register_t flags = 0; 182 183 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 184 flags |= scr_el3 & SCR_NS_BIT; 185 #if ENABLE_RME 186 /* Copy SCR_EL3.NSE bit to the flag to indicate caller's security Shift 187 * copied SCR_EL3.NSE bit by 5 to create space for SCR_EL3.NS bit. Bit 5 188 * of the flag corresponds to the SCR_EL3.NSE bit. 189 */ 190 flags |= ((scr_el3 & SCR_NSE_BIT) >> SCR_NSE_SHIFT) << 5; 191 #endif /* ENABLE_RME */ 192 193 /* 194 * Per SMCCCv1.3 a caller can set the SVE hint bit in the SMC FID passed 195 * through x0. Copy the SVE hint bit to flags and mask the bit in 196 * smc_fid passed to the standard service dispatcher. A 197 * service/dispatcher can retrieve the SVE hint bit state from flags 198 * using the appropriate helper. 199 */ 200 flags |= smc_fid & MASK(FUNCID_SVE_HINT); 201 202 return flags; 203 } 204 205 static void sync_handler(cpu_context_t *ctx, uint32_t smc_fid) 206 { 207 u_register_t scr_el3 = read_scr_el3(); 208 rt_svc_handle_t handler; 209 210 /* 211 * Per SMCCC documentation, bits [23:17] must be zero for Fast SMCs. 212 * Other values are reserved for future use. Ensure that these bits are 213 * zeroes, if not report as unknown SMC. 214 */ 215 if (EXTRACT(FUNCID_TYPE, smc_fid) == SMC_TYPE_FAST && 216 EXTRACT(FUNCID_FC_RESERVED, smc_fid) != 0) { 217 return smc_unknown(ctx); 218 } 219 220 smc_fid &= ~MASK(FUNCID_SVE_HINT); 221 222 /* Get the descriptor using the index */ 223 if (!get_handler_for_smc_fid(smc_fid, &handler)) { 224 return smc_unknown(ctx); 225 } 226 227 u_register_t x1, x2, x3, x4; 228 get_smc_params_from_ctx(ctx, x1, x2, x3, x4); 229 handler(smc_fid, x1, x2, x3, x4, NULL, ctx, get_flags(smc_fid, scr_el3)); 230 } 231 232 void handler_sync_exception(cpu_context_t *ctx) 233 { 234 uint32_t smc_fid = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X0); 235 u_register_t esr_el3 = read_esr_el3(); 236 u_register_t exc_class = EXTRACT(ESR_EC, esr_el3); 237 el3_state_t *state = get_el3state_ctx(ctx); 238 239 if (exc_class == EC_AARCH32_SMC || exc_class == EC_AARCH64_SMC) { 240 if (exc_class == EC_AARCH32_SMC && EXTRACT(FUNCID_CC, smc_fid) != 0) { 241 return smc_unknown(ctx); 242 } 243 return sync_handler(ctx, smc_fid); 244 } else if (exc_class == EC_AARCH64_SYS) { 245 int ret = handle_sysreg_trap(esr_el3, ctx, get_flags(smc_fid, read_scr_el3())); 246 247 /* unhandled trap, UNDEF injection into lower. The support is 248 * only provided for lower EL in AArch64 mode. */ 249 if (ret == TRAP_RET_UNHANDLED) { 250 if (read_spsr_el3() & MASK(SPSR_M)) { 251 ERROR("Trapped an instruction from AArch32 %s mode\n", 252 get_mode_str((unsigned int)GET_M32(read_spsr_el3()))); 253 ERROR("at address 0x%lx, reason 0x%lx\n", read_elr_el3(), read_esr_el3()); 254 panic(); 255 } 256 inject_undef64(ctx); 257 } else if (ret == TRAP_RET_CONTINUE) { 258 /* advance the PC to continue after the instruction */ 259 write_ctx_reg(state, CTX_ELR_EL3, read_ctx_reg(state, CTX_ELR_EL3) + 4); 260 } /* otherwise return to the trapping instruction (repeating it) */ 261 return; 262 /* If FFH Support then try to handle lower EL EA exceptions. */ 263 } else if ((exc_class == EC_IABORT_LOWER_EL || exc_class == EC_DABORT_LOWER_EL) 264 && ((read_ctx_reg(state, CTX_SCR_EL3) & SCR_EA_BIT) != 0UL)) { 265 #if FFH_SUPPORT 266 /* 267 * Check for Uncontainable error type. If so, route to the 268 * platform fatal error handler rather than the generic EA one. 269 */ 270 if (is_feat_ras_supported() && 271 (EXTRACT(EABORT_SET, esr_el3) == ERROR_STATUS_SET_UC || 272 EXTRACT(EABORT_DFSC, esr_el3) == SYNC_EA_FSC)) { 273 return plat_handle_uncontainable_ea(); 274 } 275 /* Setup exception class and syndrome arguments for platform handler */ 276 return ea_proceed(ERROR_EA_SYNC, esr_el3, ctx); 277 #endif /* FFH_SUPPORT */ 278 } 279 280 /* Synchronous exceptions other than the above are unhandled */ 281 report_unhandled_exception(); 282 } 283 #endif /* __aarch64__ */ 284 285 /******************************************************************************* 286 * Function to invoke the registered `handle` corresponding to the smc_fid in 287 * AArch32 mode. 288 ******************************************************************************/ 289 uintptr_t handle_runtime_svc(uint32_t smc_fid, 290 void *cookie, 291 void *handle, 292 unsigned int flags) 293 { 294 u_register_t x1, x2, x3, x4; 295 rt_svc_handle_t handler; 296 297 assert(handle != NULL); 298 299 if (!get_handler_for_smc_fid(smc_fid, &handler)) { 300 SMC_RET1(handle, SMC_UNK); 301 } 302 303 get_smc_params_from_ctx(handle, x1, x2, x3, x4); 304 305 return handler(smc_fid, x1, x2, x3, x4, cookie, handle, flags); 306 } 307 308 /******************************************************************************* 309 * Simple routine to sanity check a runtime service descriptor before using it 310 ******************************************************************************/ 311 static int32_t validate_rt_svc_desc(const rt_svc_desc_t *desc) 312 { 313 if (desc == NULL) { 314 return -EINVAL; 315 } 316 if (desc->start_oen > desc->end_oen) { 317 return -EINVAL; 318 } 319 if (desc->end_oen >= OEN_LIMIT) { 320 return -EINVAL; 321 } 322 if ((desc->call_type != SMC_TYPE_FAST) && 323 (desc->call_type != SMC_TYPE_YIELD)) { 324 return -EINVAL; 325 } 326 /* A runtime service having no init or handle function doesn't make sense */ 327 if ((desc->init == NULL) && (desc->handle == NULL)) { 328 return -EINVAL; 329 } 330 return 0; 331 } 332 333 /******************************************************************************* 334 * This function calls the initialisation routine in the descriptor exported by 335 * a runtime service. Once a descriptor has been validated, its start & end 336 * owning entity numbers and the call type are combined to form a unique oen. 337 * The unique oen is used as an index into the 'rt_svc_descs_indices' array. 338 * The index of the runtime service descriptor is stored at this index. 339 ******************************************************************************/ 340 void __init runtime_svc_init(void) 341 { 342 int rc = 0; 343 uint8_t index, start_idx, end_idx; 344 rt_svc_desc_t *rt_svc_descs; 345 346 /* Assert the number of descriptors detected are less than maximum indices */ 347 assert((RT_SVC_DESCS_END >= RT_SVC_DESCS_START) && 348 (RT_SVC_DECS_NUM < MAX_RT_SVCS)); 349 350 /* If no runtime services are implemented then simply bail out */ 351 if (RT_SVC_DECS_NUM == 0U) { 352 return; 353 } 354 /* Initialise internal variables to invalid state */ 355 (void)memset(rt_svc_descs_indices, -1, sizeof(rt_svc_descs_indices)); 356 357 rt_svc_descs = (rt_svc_desc_t *) RT_SVC_DESCS_START; 358 for (index = 0U; index < RT_SVC_DECS_NUM; index++) { 359 rt_svc_desc_t *service = &rt_svc_descs[index]; 360 361 /* 362 * An invalid descriptor is an error condition since it is 363 * difficult to predict the system behaviour in the absence 364 * of this service. 365 */ 366 rc = validate_rt_svc_desc(service); 367 if (rc != 0) { 368 ERROR("Invalid runtime service descriptor %p\n", 369 (void *) service); 370 panic(); 371 } 372 373 /* 374 * The runtime service may have separate rt_svc_desc_t 375 * for its fast smc and yielding smc. Since the service itself 376 * need to be initialized only once, only one of them will have 377 * an initialisation routine defined. Call the initialisation 378 * routine for this runtime service, if it is defined. 379 */ 380 if (service->init != NULL) { 381 rc = service->init(); 382 if (rc != 0) { 383 ERROR("Error initializing runtime service %s\n", 384 service->name); 385 continue; 386 } 387 } 388 389 /* 390 * Fill the indices corresponding to the start and end 391 * owning entity numbers with the index of the 392 * descriptor which will handle the SMCs for this owning 393 * entity range. 394 */ 395 start_idx = (uint8_t)get_unique_oen(service->start_oen, 396 service->call_type); 397 end_idx = (uint8_t)get_unique_oen(service->end_oen, 398 service->call_type); 399 assert(start_idx <= end_idx); 400 assert(end_idx < MAX_RT_SVCS); 401 for (; start_idx <= end_idx; start_idx++) { 402 rt_svc_descs_indices[start_idx] = index; 403 } 404 } 405 } 406