1 /* 2 * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef ARCH_H 9 #define ARCH_H 10 11 #include <lib/utils_def.h> 12 13 /******************************************************************************* 14 * MIDR bit definitions 15 ******************************************************************************/ 16 #define MIDR_IMPL_MASK U(0xff) 17 #define MIDR_IMPL_SHIFT U(0x18) 18 #define MIDR_VAR_SHIFT U(20) 19 #define MIDR_VAR_BITS U(4) 20 #define MIDR_VAR_MASK U(0xf) 21 #define MIDR_REV_SHIFT U(0) 22 #define MIDR_REV_BITS U(4) 23 #define MIDR_REV_MASK U(0xf) 24 #define MIDR_PN_MASK U(0xfff) 25 #define MIDR_PN_SHIFT U(0x4) 26 27 /* Extracts the CPU part number from MIDR for checking CPU match */ 28 #define EXTRACT_PARTNUM(x) ((x >> MIDR_PN_SHIFT) & MIDR_PN_MASK) 29 30 /******************************************************************************* 31 * MPIDR macros 32 ******************************************************************************/ 33 #define MPIDR_MT_MASK (ULL(1) << 24) 34 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 35 #define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS) 36 #define MPIDR_AFFINITY_BITS U(8) 37 #define MPIDR_AFFLVL_MASK ULL(0xff) 38 #define MPIDR_AFF0_SHIFT U(0) 39 #define MPIDR_AFF1_SHIFT U(8) 40 #define MPIDR_AFF2_SHIFT U(16) 41 #define MPIDR_AFF3_SHIFT U(32) 42 #define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT 43 #define MPIDR_AFFINITY_MASK ULL(0xff00ffffff) 44 #define MPIDR_AFFLVL_SHIFT U(3) 45 #define MPIDR_AFFLVL0 ULL(0x0) 46 #define MPIDR_AFFLVL1 ULL(0x1) 47 #define MPIDR_AFFLVL2 ULL(0x2) 48 #define MPIDR_AFFLVL3 ULL(0x3) 49 #define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n 50 #define MPIDR_AFFLVL0_VAL(mpidr) \ 51 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) 52 #define MPIDR_AFFLVL1_VAL(mpidr) \ 53 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) 54 #define MPIDR_AFFLVL2_VAL(mpidr) \ 55 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) 56 #define MPIDR_AFFLVL3_VAL(mpidr) \ 57 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) 58 /* 59 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 60 * add one while using this macro to define array sizes. 61 * TODO: Support only the first 3 affinity levels for now. 62 */ 63 #define MPIDR_MAX_AFFLVL U(2) 64 65 #define MPID_MASK (MPIDR_MT_MASK | \ 66 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \ 67 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \ 68 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \ 69 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT)) 70 71 #define MPIDR_AFF_ID(mpid, n) \ 72 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK) 73 74 /* 75 * An invalid MPID. This value can be used by functions that return an MPID to 76 * indicate an error. 77 */ 78 #define INVALID_MPID U(0xFFFFFFFF) 79 80 /******************************************************************************* 81 * Definitions for Exception vector offsets 82 ******************************************************************************/ 83 #define CURRENT_EL_SP0 0x0 84 #define CURRENT_EL_SPX 0x200 85 #define LOWER_EL_AARCH64 0x400 86 #define LOWER_EL_AARCH32 0x600 87 88 #define SYNC_EXCEPTION 0x0 89 #define IRQ_EXCEPTION 0x80 90 #define FIQ_EXCEPTION 0x100 91 #define SERROR_EXCEPTION 0x180 92 93 /******************************************************************************* 94 * Encodings for GICv5 EL3 system registers 95 ******************************************************************************/ 96 #define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4 97 #define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5 98 #define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6 99 #define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7 100 101 #define ICC_PPI_DOMAINR_FIELD_MASK ULL(0x3) 102 #define ICC_PPI_DOMAINR_COUNT (32) 103 104 /******************************************************************************* 105 * Definitions for CPU system register interface to GICv3 106 ******************************************************************************/ 107 #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 108 #define ICC_SGI1R S3_0_C12_C11_5 109 #define ICC_ASGI1R S3_0_C12_C11_6 110 #define ICC_SRE_EL1 S3_0_C12_C12_5 111 #define ICC_SRE_EL2 S3_4_C12_C9_5 112 #define ICC_SRE_EL3 S3_6_C12_C12_5 113 #define ICC_CTLR_EL1 S3_0_C12_C12_4 114 #define ICC_CTLR_EL3 S3_6_C12_C12_4 115 #define ICC_PMR_EL1 S3_0_C4_C6_0 116 #define ICC_RPR_EL1 S3_0_C12_C11_3 117 #define ICC_IGRPEN1_EL3 S3_6_c12_c12_7 118 #define ICC_IGRPEN0_EL1 S3_0_c12_c12_6 119 #define ICC_HPPIR0_EL1 S3_0_c12_c8_2 120 #define ICC_HPPIR1_EL1 S3_0_c12_c12_2 121 #define ICC_IAR0_EL1 S3_0_c12_c8_0 122 #define ICC_IAR1_EL1 S3_0_c12_c12_0 123 #define ICC_EOIR0_EL1 S3_0_c12_c8_1 124 #define ICC_EOIR1_EL1 S3_0_c12_c12_1 125 #define ICC_SGI0R_EL1 S3_0_c12_c11_7 126 127 /******************************************************************************* 128 * Definitions for EL2 system registers for save/restore routine 129 ******************************************************************************/ 130 #define CNTPOFF_EL2 S3_4_C14_C0_6 131 #define HDFGRTR2_EL2 S3_4_C3_C1_0 132 #define HDFGWTR2_EL2 S3_4_C3_C1_1 133 #define HFGRTR2_EL2 S3_4_C3_C1_2 134 #define HFGWTR2_EL2 S3_4_C3_C1_3 135 #define HDFGRTR_EL2 S3_4_C3_C1_4 136 #define HDFGWTR_EL2 S3_4_C3_C1_5 137 #define HAFGRTR_EL2 S3_4_C3_C1_6 138 #define HFGITR2_EL2 S3_4_C3_C1_7 139 #define HFGITR_EL2 S3_4_C1_C1_6 140 #define HFGRTR_EL2 S3_4_C1_C1_4 141 #define HFGWTR_EL2 S3_4_C1_C1_5 142 #define ICH_HCR_EL2 S3_4_C12_C11_0 143 #define ICH_VMCR_EL2 S3_4_C12_C11_7 144 #define MPAMVPM0_EL2 S3_4_C10_C6_0 145 #define MPAMVPM1_EL2 S3_4_C10_C6_1 146 #define MPAMVPM2_EL2 S3_4_C10_C6_2 147 #define MPAMVPM3_EL2 S3_4_C10_C6_3 148 #define MPAMVPM4_EL2 S3_4_C10_C6_4 149 #define MPAMVPM5_EL2 S3_4_C10_C6_5 150 #define MPAMVPM6_EL2 S3_4_C10_C6_6 151 #define MPAMVPM7_EL2 S3_4_C10_C6_7 152 #define MPAMVPMV_EL2 S3_4_C10_C4_1 153 #define VNCR_EL2 S3_4_C2_C2_0 154 #define PMSCR_EL2 S3_4_C9_C9_0 155 #define TFSR_EL2 S3_4_C5_C6_0 156 #define CONTEXTIDR_EL2 S3_4_C13_C0_1 157 #define TTBR1_EL2 S3_4_C2_C0_1 158 159 /******************************************************************************* 160 * Generic timer memory mapped registers & offsets 161 ******************************************************************************/ 162 #define CNTCR_OFF U(0x000) 163 #define CNTCV_OFF U(0x008) 164 #define CNTFID_OFF U(0x020) 165 166 #define CNTCR_EN (U(1) << 0) 167 #define CNTCR_HDBG (U(1) << 1) 168 #define CNTCR_FCREQ(x) ((x) << 8) 169 170 /******************************************************************************* 171 * System register bit definitions 172 ******************************************************************************/ 173 /* CLIDR definitions */ 174 #define LOUIS_SHIFT U(21) 175 #define LOC_SHIFT U(24) 176 #define CTYPE_SHIFT(n) U(3 * (n - 1)) 177 #define CLIDR_FIELD_WIDTH U(3) 178 179 /* CSSELR definitions */ 180 #define LEVEL_SHIFT U(1) 181 182 /* Data cache set/way op type defines */ 183 #define DCISW U(0x0) 184 #define DCCISW U(0x1) 185 #if ERRATA_A53_827319 186 #define DCCSW DCCISW 187 #else 188 #define DCCSW U(0x2) 189 #endif 190 191 #define ID_REG_FIELD_MASK ULL(0xf) 192 193 /******************************************************************************* 194 * PFR0_EL1 - Definitions for AArch32 Processor Feature Register 0 195 ******************************************************************************/ 196 #define ID_PFR0_EL1 S3_0_C0_C1_0 197 198 /******************************************************************************* 199 * PFR2_EL1 - Definitions for AArch32 Processor Feature Register 2 200 ******************************************************************************/ 201 #define ID_PFR2_EL1 S3_0_C0_C3_4 202 203 /******************************************************************************* 204 * ID_ISAR6_EL1 - Definition for AArch32 Instruction Set Attribute Register 6 205 ******************************************************************************/ 206 #define ID_ISAR6_EL1 S3_0_C0_C2_7 207 208 /******************************************************************************* 209 * ID_DFR1_EL1 - Definition for AArch32 Debug Feature Register 1 210 ******************************************************************************/ 211 #define ID_DFR1_EL1 S3_0_C0_C3_5 212 213 /* ID_AA64PFR0_EL1 definitions */ 214 #define ID_AA64PFR0_EL0_SHIFT U(0) 215 #define ID_AA64PFR0_EL1_SHIFT U(4) 216 #define ID_AA64PFR0_EL2_SHIFT U(8) 217 #define ID_AA64PFR0_EL3_SHIFT U(12) 218 219 #define ID_AA64PFR0_AMU_SHIFT U(44) 220 #define ID_AA64PFR0_AMU_MASK ULL(0xf) 221 #define ID_AA64PFR0_AMU_V1 ULL(0x1) 222 #define ID_AA64PFR0_AMU_V1P1 U(0x2) 223 224 #define ID_AA64PFR0_ELX_MASK ULL(0xf) 225 #define ID_AA64PFR0_EL0_MASK ID_AA64PFR0_ELX_MASK 226 #define ID_AA64PFR0_EL1_MASK ID_AA64PFR0_ELX_MASK 227 #define ID_AA64PFR0_EL2_MASK ID_AA64PFR0_ELX_MASK 228 #define ID_AA64PFR0_EL3_MASK ID_AA64PFR0_ELX_MASK 229 230 #define ID_AA64PFR0_GIC_SHIFT U(24) 231 #define ID_AA64PFR0_GIC_WIDTH U(4) 232 #define ID_AA64PFR0_GIC_MASK ULL(0xf) 233 234 #define ID_AA64PFR0_SVE_SHIFT U(32) 235 #define ID_AA64PFR0_SVE_MASK ULL(0xf) 236 #define ID_AA64PFR0_SVE_LENGTH U(4) 237 #define SVE_IMPLEMENTED ULL(0x1) 238 239 #define ID_AA64PFR0_SEL2_SHIFT U(36) 240 #define ID_AA64PFR0_SEL2_MASK ULL(0xf) 241 242 #define ID_AA64PFR0_MPAM_SHIFT U(40) 243 #define ID_AA64PFR0_MPAM_MASK ULL(0xf) 244 245 #define ID_AA64PFR0_DIT_SHIFT U(48) 246 #define ID_AA64PFR0_DIT_MASK ULL(0xf) 247 #define ID_AA64PFR0_DIT_LENGTH U(4) 248 #define DIT_IMPLEMENTED ULL(1) 249 250 #define ID_AA64PFR0_CSV2_SHIFT U(56) 251 #define ID_AA64PFR0_CSV2_MASK ULL(0xf) 252 #define ID_AA64PFR0_CSV2_LENGTH U(4) 253 #define CSV2_2_IMPLEMENTED ULL(0x2) 254 #define CSV2_3_IMPLEMENTED ULL(0x3) 255 256 #define ID_AA64PFR0_FEAT_RME_SHIFT U(52) 257 #define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf) 258 #define ID_AA64PFR0_FEAT_RME_LENGTH U(4) 259 #define RME_NOT_IMPLEMENTED ULL(0) 260 #define RME_GPC2_IMPLEMENTED ULL(0x2) 261 262 #define ID_AA64PFR0_RAS_SHIFT U(28) 263 #define ID_AA64PFR0_RAS_MASK ULL(0xf) 264 #define ID_AA64PFR0_RAS_LENGTH U(4) 265 266 /* Exception level handling */ 267 #define EL_IMPL_NONE ULL(0) 268 #define EL_IMPL_A64ONLY ULL(1) 269 #define EL_IMPL_A64_A32 ULL(2) 270 271 /* ID_AA64DFR0_EL1.DebugVer definitions */ 272 #define ID_AA64DFR0_DEBUGVER_SHIFT U(0) 273 #define ID_AA64DFR0_DEBUGVER_MASK ULL(0xf) 274 #define DEBUGVER_V8P9_IMPLEMENTED ULL(0xb) 275 276 /* ID_AA64DFR0_EL1.TraceVer definitions */ 277 #define ID_AA64DFR0_TRACEVER_SHIFT U(4) 278 #define ID_AA64DFR0_TRACEVER_MASK ULL(0xf) 279 #define ID_AA64DFR0_TRACEVER_LENGTH U(4) 280 281 #define ID_AA64DFR0_TRACEFILT_SHIFT U(40) 282 #define ID_AA64DFR0_TRACEFILT_MASK U(0xf) 283 #define ID_AA64DFR0_TRACEFILT_LENGTH U(4) 284 #define TRACEFILT_IMPLEMENTED ULL(1) 285 286 #define ID_AA64DFR0_PMUVER_LENGTH U(4) 287 #define ID_AA64DFR0_PMUVER_SHIFT U(8) 288 #define ID_AA64DFR0_PMUVER_MASK U(0xf) 289 #define ID_AA64DFR0_PMUVER_PMUV3 U(1) 290 #define ID_AA64DFR0_PMUVER_PMUV3P9 U(9) 291 #define ID_AA64DFR0_PMUVER_IMP_DEF U(0xf) 292 293 /* ID_AA64DFR0_EL1.SEBEP definitions */ 294 #define ID_AA64DFR0_SEBEP_SHIFT U(24) 295 #define ID_AA64DFR0_SEBEP_MASK ULL(0xf) 296 #define SEBEP_IMPLEMENTED ULL(1) 297 298 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */ 299 #define ID_AA64DFR0_PMS_SHIFT U(32) 300 #define ID_AA64DFR0_PMS_MASK ULL(0xf) 301 #define SPE_IMPLEMENTED ULL(0x1) 302 #define SPE_NOT_IMPLEMENTED ULL(0x0) 303 304 /* ID_AA64DFR0_EL1.TraceBuffer definitions */ 305 #define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44) 306 #define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf) 307 #define TRACEBUFFER_IMPLEMENTED ULL(1) 308 309 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */ 310 #define ID_AA64DFR0_MTPMU_SHIFT U(48) 311 #define ID_AA64DFR0_MTPMU_MASK ULL(0xf) 312 #define MTPMU_IMPLEMENTED ULL(1) 313 #define MTPMU_NOT_IMPLEMENTED ULL(15) 314 315 /* ID_AA64DFR0_EL1.BRBE definitions */ 316 #define ID_AA64DFR0_BRBE_SHIFT U(52) 317 #define ID_AA64DFR0_BRBE_MASK ULL(0xf) 318 #define BRBE_IMPLEMENTED ULL(1) 319 320 /* ID_AA64DFR1_EL1 definitions */ 321 #define ID_AA64DFR1_EBEP_SHIFT U(48) 322 #define ID_AA64DFR1_EBEP_MASK ULL(0xf) 323 #define EBEP_IMPLEMENTED ULL(1) 324 325 #define ID_AA64DFR1_BRP_SHIFT U(8) 326 #define ID_AA64DFR1_BRP_WIDTH U(8) 327 328 #define ID_AA64ZFR0_EL1 S3_0_C0_C4_4 329 #define ID_AA64FPFR0_EL1 S3_0_C0_C4_7 330 #define ID_AA64DFR2_EL1 S3_0_C0_C5_2 331 #define GMID_EL1 S3_1_C0_C0_4 332 333 /* ID_AA64ISAR0_EL1 definitions */ 334 #define ID_AA64ISAR0_ATOMIC_SHIFT U(20) 335 #define ID_AA64ISAR0_ATOMIC_MASK ULL(0xf) 336 #define ID_AA64ISAR0_RNDR_SHIFT U(60) 337 #define ID_AA64ISAR0_RNDR_MASK ULL(0xf) 338 339 /* ID_AA64ISAR1_EL1 definitions */ 340 #define ID_AA64ISAR1_EL1 S3_0_C0_C6_1 341 342 #define ID_AA64ISAR1_LS64_SHIFT U(60) 343 #define ID_AA64ISAR1_LS64_MASK ULL(0xf) 344 #define LS64_ACCDATA_IMPLEMENTED ULL(0x3) 345 #define LS64_V_IMPLEMENTED ULL(0x2) 346 #define LS64_IMPLEMENTED ULL(0x1) 347 #define LS64_NOT_IMPLEMENTED ULL(0x0) 348 349 #define ID_AA64ISAR1_SB_SHIFT U(36) 350 #define ID_AA64ISAR1_SB_MASK ULL(0xf) 351 #define SB_IMPLEMENTED ULL(0x1) 352 #define SB_NOT_IMPLEMENTED ULL(0x0) 353 354 #define ID_AA64ISAR1_GPI_SHIFT U(28) 355 #define ID_AA64ISAR1_GPI_MASK ULL(0xf) 356 #define ID_AA64ISAR1_GPA_SHIFT U(24) 357 #define ID_AA64ISAR1_GPA_MASK ULL(0xf) 358 359 #define ID_AA64ISAR1_API_SHIFT U(8) 360 #define ID_AA64ISAR1_API_MASK ULL(0xf) 361 #define ID_AA64ISAR1_APA_SHIFT U(4) 362 #define ID_AA64ISAR1_APA_MASK ULL(0xf) 363 364 /* ID_AA64ISAR2_EL1 definitions */ 365 #define ID_AA64ISAR2_EL1 S3_0_C0_C6_2 366 #define ID_AA64ISAR2_EL1_MOPS_SHIFT U(16) 367 #define ID_AA64ISAR2_EL1_MOPS_MASK ULL(0xf) 368 369 #define MOPS_IMPLEMENTED ULL(0x1) 370 371 #define ID_AA64ISAR2_GPA3_SHIFT U(8) 372 #define ID_AA64ISAR2_GPA3_MASK ULL(0xf) 373 374 #define ID_AA64ISAR2_APA3_SHIFT U(12) 375 #define ID_AA64ISAR2_APA3_MASK ULL(0xf) 376 377 #define ID_AA64ISAR2_CLRBHB_SHIFT U(28) 378 #define ID_AA64ISAR2_CLRBHB_MASK ULL(0xf) 379 380 #define ID_AA64ISAR2_SYSREG128_SHIFT U(32) 381 #define ID_AA64ISAR2_SYSREG128_MASK ULL(0xf) 382 383 /* ID_AA64ISAR3_EL1 definitions */ 384 #define ID_AA64ISAR3_EL1 S3_0_C0_C6_3 385 #define ID_AA64ISAR3_EL1_CPA_SHIFT U(0) 386 #define ID_AA64ISAR3_EL1_CPA_MASK ULL(0xf) 387 388 #define CPA2_IMPLEMENTED ULL(0x2) 389 390 /* ID_AA64MMFR0_EL1 definitions */ 391 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0) 392 #define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf) 393 394 #define PARANGE_0000 U(32) 395 #define PARANGE_0001 U(36) 396 #define PARANGE_0010 U(40) 397 #define PARANGE_0011 U(42) 398 #define PARANGE_0100 U(44) 399 #define PARANGE_0101 U(48) 400 #define PARANGE_0110 U(52) 401 #define PARANGE_0111 U(56) 402 403 #define ID_AA64MMFR0_EL1_ECV_SHIFT U(60) 404 #define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf) 405 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2) 406 #define ECV_IMPLEMENTED ULL(0x1) 407 408 #define ID_AA64MMFR0_EL1_FGT_SHIFT U(56) 409 #define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf) 410 #define FGT2_IMPLEMENTED ULL(0x2) 411 #define FGT_IMPLEMENTED ULL(0x1) 412 #define FGT_NOT_IMPLEMENTED ULL(0x0) 413 414 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28) 415 #define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf) 416 417 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24) 418 #define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf) 419 420 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20) 421 #define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf) 422 #define TGRAN16_IMPLEMENTED ULL(0x1) 423 424 /* ID_AA64MMFR1_EL1 definitions */ 425 #define ID_AA64MMFR1_EL1_TWED_SHIFT U(32) 426 #define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf) 427 #define TWED_IMPLEMENTED ULL(0x1) 428 429 #define ID_AA64MMFR1_EL1_PAN_SHIFT U(20) 430 #define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf) 431 #define PAN_IMPLEMENTED ULL(0x1) 432 #define PAN2_IMPLEMENTED ULL(0x2) 433 #define PAN3_IMPLEMENTED ULL(0x3) 434 435 #define ID_AA64MMFR1_EL1_VHE_SHIFT U(8) 436 #define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf) 437 438 #define ID_AA64MMFR1_EL1_HCX_SHIFT U(40) 439 #define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf) 440 #define HCX_IMPLEMENTED ULL(0x1) 441 442 /* ID_AA64MMFR2_EL1 definitions */ 443 #define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 444 445 #define ID_AA64MMFR2_EL1_IDS_SHIFT U(36) 446 #define ID_AA64MMFR2_EL1_IDS_MASK ULL(0xf) 447 448 #define ID_AA64MMFR2_EL1_ST_SHIFT U(28) 449 #define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf) 450 451 #define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20) 452 #define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf) 453 #define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4) 454 455 #define ID_AA64MMFR2_EL1_UAO_SHIFT U(4) 456 #define ID_AA64MMFR2_EL1_UAO_MASK ULL(0xf) 457 458 #define ID_AA64MMFR2_EL1_CNP_SHIFT U(0) 459 #define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf) 460 461 #define ID_AA64MMFR2_EL1_NV_SHIFT U(24) 462 #define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf) 463 #define NV2_IMPLEMENTED ULL(0x2) 464 465 /* ID_AA64MMFR3_EL1 definitions */ 466 #define ID_AA64MMFR3_EL1 S3_0_C0_C7_3 467 468 #define ID_AA64MMFR3_EL1_D128_SHIFT U(32) 469 #define ID_AA64MMFR3_EL1_D128_MASK ULL(0xf) 470 #define D128_IMPLEMENTED ULL(0x1) 471 472 #define ID_AA64MMFR3_EL1_MEC_SHIFT U(28) 473 #define ID_AA64MMFR3_EL1_MEC_MASK ULL(0xf) 474 475 #define ID_AA64MMFR3_EL1_AIE_SHIFT U(24) 476 #define ID_AA64MMFR3_EL1_AIE_MASK ULL(0xf) 477 478 #define ID_AA64MMFR3_EL1_S2POE_SHIFT U(20) 479 #define ID_AA64MMFR3_EL1_S2POE_MASK ULL(0xf) 480 481 #define ID_AA64MMFR3_EL1_S1POE_SHIFT U(16) 482 #define ID_AA64MMFR3_EL1_S1POE_MASK ULL(0xf) 483 484 #define ID_AA64MMFR3_EL1_S2PIE_SHIFT U(12) 485 #define ID_AA64MMFR3_EL1_S2PIE_MASK ULL(0xf) 486 487 #define ID_AA64MMFR3_EL1_S1PIE_SHIFT U(8) 488 #define ID_AA64MMFR3_EL1_S1PIE_MASK ULL(0xf) 489 490 #define ID_AA64MMFR3_EL1_SCTLR2_SHIFT U(4) 491 #define ID_AA64MMFR3_EL1_SCTLR2_MASK ULL(0xf) 492 #define SCTLR2_IMPLEMENTED ULL(1) 493 494 #define ID_AA64MMFR3_EL1_TCRX_SHIFT U(0) 495 #define ID_AA64MMFR3_EL1_TCRX_MASK ULL(0xf) 496 497 /* ID_AA64MMFR4_EL1 definitions */ 498 #define ID_AA64MMFR4_EL1 S3_0_C0_C7_4 499 500 #define ID_AA64MMFR4_EL1_FGWTE3_SHIFT U(16) 501 #define ID_AA64MMFR4_EL1_FGWTE3_MASK ULL(0xf) 502 #define FGWTE3_IMPLEMENTED ULL(0x1) 503 504 #define ID_AA64MMFR4_EL1_RME_GDI_SHIFT U(28) 505 #define ID_AA64MMFR4_EL1_RME_GDI_MASK ULL(0xf) 506 #define ID_AA64MMFR4_EL1_RME_GDI_LENGTH U(4) 507 #define RME_GDI_IMPLEMENTED ULL(0x1) 508 509 /* ID_AA64PFR1_EL1 definitions */ 510 511 #define ID_AA64PFR1_EL1_BT_SHIFT U(0) 512 #define ID_AA64PFR1_EL1_BT_MASK ULL(0xf) 513 #define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */ 514 515 #define ID_AA64PFR1_EL1_SSBS_SHIFT U(4) 516 #define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf) 517 #define SSBS_NOT_IMPLEMENTED ULL(0) /* No architectural SSBS support */ 518 519 #define ID_AA64PFR1_EL1_MTE_SHIFT U(8) 520 #define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf) 521 522 #define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28) 523 #define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf) 524 #define RNG_TRAP_IMPLEMENTED ULL(0x1) 525 526 #define ID_AA64PFR1_EL1_NMI_SHIFT U(36) 527 #define ID_AA64PFR1_EL1_NMI_MASK ULL(0xf) 528 #define NMI_IMPLEMENTED ULL(1) 529 530 #define ID_AA64PFR1_EL1_GCS_SHIFT U(44) 531 #define ID_AA64PFR1_EL1_GCS_MASK ULL(0xf) 532 #define GCS_IMPLEMENTED ULL(1) 533 534 #define ID_AA64PFR1_EL1_THE_SHIFT U(48) 535 #define ID_AA64PFR1_EL1_THE_MASK ULL(0xf) 536 #define THE_IMPLEMENTED ULL(1) 537 538 #define ID_AA64PFR1_EL1_PFAR_SHIFT U(60) 539 #define ID_AA64PFR1_EL1_PFAR_MASK ULL(0xf) 540 541 /* ID_AA64PFR1_EL1.CE field: Morello architecture presence (bits [23:20]) */ 542 #define ID_AA64PFR1_EL1_CE_SHIFT U(20) 543 #define ID_AA64PFR1_EL1_CE_MASK ULL(0xf) 544 /* 0b0000 means Morello arch is not present, 0b0001 means it is present */ 545 #define MORELLO_EXTENSION_IMPLEMENTED ULL(0x1) 546 #define CSCR_EL3_SETTAG ULL(0x1) 547 548 /* ID_AA64PFR2_EL1 definitions */ 549 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 550 551 #define ID_AA64PFR2_EL1_MTEPERM_SHIFT U(0) 552 #define ID_AA64PFR2_EL1_MTEPERM_MASK ULL(0xf) 553 554 #define ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT U(4) 555 #define ID_AA64PFR2_EL1_MTESTOREONLY_MASK ULL(0xf) 556 557 #define ID_AA64PFR2_EL1_MTEFAR_SHIFT U(8) 558 #define ID_AA64PFR2_EL1_MTEFAR_MASK ULL(0xf) 559 560 #define ID_AA64PFR2_EL1_UINJ_SHIFT U(16) 561 #define ID_AA64PFR2_EL1_UINJ_MASK ULL(0xf) 562 #define UINJ_IMPLEMENTED ULL(0x1) 563 564 #define ID_AA64PFR2_EL1_FPMR_SHIFT U(32) 565 #define ID_AA64PFR2_EL1_FPMR_MASK ULL(0xf) 566 567 #define FPMR_IMPLEMENTED ULL(0x1) 568 569 #define VDISR_EL2 S3_4_C12_C1_1 570 #define VSESR_EL2 S3_4_C5_C2_3 571 572 /* Memory Tagging Extension is not implemented */ 573 #define MTE_UNIMPLEMENTED U(0) 574 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */ 575 #define MTE_IMPLEMENTED_EL0 U(1) 576 /* FEAT_MTE2: Full MTE is implemented */ 577 #define MTE_IMPLEMENTED_ELX U(2) 578 /* 579 * FEAT_MTE3: MTE is implemented with support for 580 * asymmetric Tag Check Fault handling 581 */ 582 #define MTE_IMPLEMENTED_ASY U(3) 583 584 #define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16) 585 #define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf) 586 587 #define ID_AA64PFR1_EL1_SME_SHIFT U(24) 588 #define ID_AA64PFR1_EL1_SME_MASK ULL(0xf) 589 #define ID_AA64PFR1_EL1_SME_WIDTH U(4) 590 #define SME_IMPLEMENTED ULL(0x1) 591 #define SME2_IMPLEMENTED ULL(0x2) 592 #define SME_NOT_IMPLEMENTED ULL(0x0) 593 594 /* ID_AA64PFR2_EL1 definitions */ 595 #define ID_AA64PFR2_EL1 S3_0_C0_C4_2 596 #define ID_AA64PFR2_EL1_GCIE_SHIFT 12 597 #define ID_AA64PFR2_EL1_GCIE_MASK ULL(0xf) 598 599 /* ID_PFR1_EL1 definitions */ 600 #define ID_PFR1_VIRTEXT_SHIFT U(12) 601 #define ID_PFR1_VIRTEXT_MASK U(0xf) 602 #define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \ 603 & ID_PFR1_VIRTEXT_MASK) 604 605 /* SCTLR definitions */ 606 #define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 607 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 608 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 609 610 #define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \ 611 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11)) 612 613 #define SCTLR_AARCH32_EL1_RES1 \ 614 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \ 615 (U(1) << 4) | (U(1) << 3)) 616 617 #define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \ 618 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \ 619 (U(1) << 11) | (U(1) << 5) | (U(1) << 4)) 620 621 #define SCTLR_M_BIT (ULL(1) << 0) 622 #define SCTLR_A_BIT (ULL(1) << 1) 623 #define SCTLR_C_BIT (ULL(1) << 2) 624 #define SCTLR_SA_BIT (ULL(1) << 3) 625 #define SCTLR_SA0_BIT (ULL(1) << 4) 626 #define SCTLR_CP15BEN_BIT (ULL(1) << 5) 627 #define SCTLR_nAA_BIT (ULL(1) << 6) 628 #define SCTLR_ITD_BIT (ULL(1) << 7) 629 #define SCTLR_SED_BIT (ULL(1) << 8) 630 #define SCTLR_UMA_BIT (ULL(1) << 9) 631 #define SCTLR_EnRCTX_BIT (ULL(1) << 10) 632 #define SCTLR_EOS_BIT (ULL(1) << 11) 633 #define SCTLR_I_BIT (ULL(1) << 12) 634 #define SCTLR_EnDB_BIT (ULL(1) << 13) 635 #define SCTLR_DZE_BIT (ULL(1) << 14) 636 #define SCTLR_UCT_BIT (ULL(1) << 15) 637 #define SCTLR_NTWI_BIT (ULL(1) << 16) 638 #define SCTLR_NTWE_BIT (ULL(1) << 18) 639 #define SCTLR_WXN_BIT (ULL(1) << 19) 640 #define SCTLR_TSCXT_BIT (ULL(1) << 20) 641 #define SCTLR_IESB_BIT (ULL(1) << 21) 642 #define SCTLR_EIS_BIT (ULL(1) << 22) 643 #define SCTLR_SPAN_BIT (ULL(1) << 23) 644 #define SCTLR_E0E_BIT (ULL(1) << 24) 645 #define SCTLR_EE_BIT (ULL(1) << 25) 646 #define SCTLR_UCI_BIT (ULL(1) << 26) 647 #define SCTLR_EnDA_BIT (ULL(1) << 27) 648 #define SCTLR_nTLSMD_BIT (ULL(1) << 28) 649 #define SCTLR_LSMAOE_BIT (ULL(1) << 29) 650 #define SCTLR_EnIB_BIT (ULL(1) << 30) 651 #define SCTLR_EnIA_BIT (ULL(1) << 31) 652 #define SCTLR_BT0_BIT (ULL(1) << 35) 653 #define SCTLR_BT1_BIT (ULL(1) << 36) 654 #define SCTLR_BT_BIT (ULL(1) << 36) 655 #define SCTLR_ITFSB_BIT (ULL(1) << 37) 656 #define SCTLR_TCF0_SHIFT U(38) 657 #define SCTLR_TCF0_MASK ULL(3) 658 #define SCTLR_ENTP2_BIT (ULL(1) << 60) 659 #define SCTLR_SPINTMASK_BIT (ULL(1) << 62) 660 661 /* Tag Check Faults in EL0 have no effect on the PE */ 662 #define SCTLR_TCF0_NO_EFFECT U(0) 663 /* Tag Check Faults in EL0 cause a synchronous exception */ 664 #define SCTLR_TCF0_SYNC U(1) 665 /* Tag Check Faults in EL0 are asynchronously accumulated */ 666 #define SCTLR_TCF0_ASYNC U(2) 667 /* 668 * Tag Check Faults in EL0 cause a synchronous exception on reads, 669 * and are asynchronously accumulated on writes 670 */ 671 #define SCTLR_TCF0_SYNCR_ASYNCW U(3) 672 673 #define SCTLR_TCF_SHIFT U(40) 674 #define SCTLR_TCF_MASK ULL(3) 675 676 /* Tag Check Faults in EL1 have no effect on the PE */ 677 #define SCTLR_TCF_NO_EFFECT U(0) 678 /* Tag Check Faults in EL1 cause a synchronous exception */ 679 #define SCTLR_TCF_SYNC U(1) 680 /* Tag Check Faults in EL1 are asynchronously accumulated */ 681 #define SCTLR_TCF_ASYNC U(2) 682 /* 683 * Tag Check Faults in EL1 cause a synchronous exception on reads, 684 * and are asynchronously accumulated on writes 685 */ 686 #define SCTLR_TCF_SYNCR_ASYNCW U(3) 687 688 #define SCTLR_ATA0_BIT (ULL(1) << 42) 689 #define SCTLR_ATA_BIT (ULL(1) << 43) 690 #define SCTLR_DSSBS_SHIFT U(44) 691 #define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT) 692 #define SCTLR_TWEDEn_BIT (ULL(1) << 45) 693 #define SCTLR_TWEDEL_SHIFT U(46) 694 #define SCTLR_TWEDEL_MASK ULL(0xf) 695 #define SCTLR_EnASR_BIT (ULL(1) << 54) 696 #define SCTLR_EnAS0_BIT (ULL(1) << 55) 697 #define SCTLR_EnALS_BIT (ULL(1) << 56) 698 #define SCTLR_EPAN_BIT (ULL(1) << 57) 699 #define SCTLR_RESET_VAL SCTLR_EL3_RES1 700 701 #define SCTLR2_EnPACM_BIT (ULL(1) << 7) 702 #define SCTLR2_CPTA_BIT (ULL(1) << 9) 703 #define SCTLR2_CPTM_BIT (ULL(1) << 11) 704 705 /* SCTLR2 currently has no RES1 fields so reset to 0 */ 706 #define SCTLR2_RESET_VAL ULL(0) 707 708 /* CPACR_EL1 definitions */ 709 #define CPACR_EL1_FPEN(x) ((x) << 20) 710 #define CPACR_EL1_FP_TRAP_EL0 UL(0x1) 711 #define CPACR_EL1_FP_TRAP_ALL UL(0x2) 712 #define CPACR_EL1_FP_TRAP_NONE UL(0x3) 713 #define CPACR_EL1_SMEN_SHIFT U(24) 714 #define CPACR_EL1_SMEN_MASK ULL(0x3) 715 716 /* SCR definitions */ 717 #if ENABLE_FEAT_GCIE 718 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT) 719 #else 720 #define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5)) 721 #endif 722 #define SCR_NSE_SHIFT U(62) 723 #define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT) 724 #define SCR_FGTEN2_BIT (UL(1) << 59) 725 #define SCR_PFAREn_BIT (UL(1) << 53) 726 #define SCR_EnFPM_BIT (ULL(1) << 50) 727 #define SCR_MECEn_BIT (UL(1) << 49) 728 #define SCR_GPF_BIT (UL(1) << 48) 729 #define SCR_D128En_BIT (UL(1) << 47) 730 #define SCR_AIEn_BIT (UL(1) << 46) 731 #define SCR_TWEDEL_SHIFT U(30) 732 #define SCR_TWEDEL_MASK ULL(0xf) 733 #define SCR_PIEN_BIT (UL(1) << 45) 734 #define SCR_SCTLR2En_BIT (UL(1) << 44) 735 #define SCR_TCR2EN_BIT (UL(1) << 43) 736 #define SCR_RCWMASKEn_BIT (UL(1) << 42) 737 #define SCR_ENTP2_SHIFT U(41) 738 #define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT) 739 #define SCR_TRNDR_BIT (UL(1) << 40) 740 #define SCR_GCSEn_BIT (UL(1) << 39) 741 #define SCR_HXEn_BIT (UL(1) << 38) 742 #define SCR_ADEn_BIT (UL(1) << 37) 743 #define SCR_EnAS0_BIT (UL(1) << 36) 744 #define SCR_AMVOFFEN_SHIFT U(35) 745 #define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT) 746 #define SCR_TWEDEn_BIT (UL(1) << 29) 747 #define SCR_ECVEN_BIT (UL(1) << 28) 748 #define SCR_FGTEN_BIT (UL(1) << 27) 749 #define SCR_ATA_BIT (UL(1) << 26) 750 #define SCR_EnSCXT_BIT (UL(1) << 25) 751 #define SCR_TID5_BIT (UL(1) << 23) 752 #define SCR_TID3_BIT (UL(1) << 22) 753 #define SCR_FIEN_BIT (UL(1) << 21) 754 #define SCR_EEL2_BIT (UL(1) << 18) 755 #define SCR_API_BIT (UL(1) << 17) 756 #define SCR_APK_BIT (UL(1) << 16) 757 #define SCR_TERR_BIT (UL(1) << 15) 758 #define SCR_TWE_BIT (UL(1) << 13) 759 #define SCR_TWI_BIT (UL(1) << 12) 760 #define SCR_ST_BIT (UL(1) << 11) 761 #define SCR_RW_BIT (UL(1) << 10) 762 #define SCR_SIF_BIT (UL(1) << 9) 763 #define SCR_HCE_BIT (UL(1) << 8) 764 #define SCR_SMD_BIT (UL(1) << 7) 765 #define SCR_EA_BIT (UL(1) << 3) 766 #define SCR_FIQ_BIT (UL(1) << 2) 767 #define SCR_IRQ_BIT (UL(1) << 1) 768 #define SCR_NS_BIT (UL(1) << 0) 769 #define SCR_VALID_BIT_MASK U(0x24000002F8F) 770 #define SCR_RESET_VAL SCR_RES1_BITS 771 772 /* MDCR_EL3 definitions */ 773 #define MDCR_EBWE_BIT (ULL(1) << 43) 774 #define MDCR_EnPMS3_BIT (ULL(1) << 42) 775 #define MDCR_PMEE(x) ((x) << 40) 776 #define MDCR_PMEE_CTRL_EL2 ULL(0x1) 777 #define MDCR_E3BREC_BIT (ULL(1) << 38) 778 #define MDCR_E3BREW_BIT (ULL(1) << 37) 779 #define MDCR_EnPMSN_BIT (ULL(1) << 36) 780 #define MDCR_MPMX_BIT (ULL(1) << 35) 781 #define MDCR_MCCD_BIT (ULL(1) << 34) 782 #define MDCR_SBRBE_SHIFT U(32) 783 #define MDCR_SBRBE(x) ((x) << MDCR_SBRBE_SHIFT) 784 #define MDCR_SBRBE_ALL ULL(0x3) 785 #define MDCR_SBRBE_NS ULL(0x1) 786 #define MDCR_NSTB_EN_BIT (ULL(1) << 24) 787 #define MDCR_NSTB_SS_BIT (ULL(1) << 25) 788 #define MDCR_NSTBE_BIT (ULL(1) << 26) 789 #define MDCR_MTPME_BIT (ULL(1) << 28) 790 #define MDCR_TDCC_BIT (ULL(1) << 27) 791 #define MDCR_SCCD_BIT (ULL(1) << 23) 792 #define MDCR_EPMAD_BIT (ULL(1) << 21) 793 #define MDCR_EDAD_BIT (ULL(1) << 20) 794 #define MDCR_TTRF_BIT (ULL(1) << 19) 795 #define MDCR_STE_BIT (ULL(1) << 18) 796 #define MDCR_SPME_BIT (ULL(1) << 17) 797 #define MDCR_SDD_BIT (ULL(1) << 16) 798 #define MDCR_SPD32(x) ((x) << 14) 799 #define MDCR_SPD32_LEGACY ULL(0x0) 800 #define MDCR_SPD32_DISABLE ULL(0x2) 801 #define MDCR_SPD32_ENABLE ULL(0x3) 802 #define MDCR_NSPB_SS_BIT (ULL(1) << 13) 803 #define MDCR_NSPB_EN_BIT (ULL(1) << 12) 804 #define MDCR_NSPBE_BIT (ULL(1) << 11) 805 #define MDCR_TDOSA_BIT (ULL(1) << 10) 806 #define MDCR_TDA_BIT (ULL(1) << 9) 807 #define MDCR_EnPM2_BIT (ULL(1) << 7) 808 #define MDCR_TPM_BIT (ULL(1) << 6) 809 #define MDCR_RLTE_BIT (ULL(1) << 0) 810 #define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT 811 812 /* MDCR_EL2 definitions */ 813 #define MDCR_EL2_MTPME (ULL(1) << 28) 814 #define MDCR_EL2_HLP_BIT (ULL(1) << 26) 815 #define MDCR_EL2_E2TB(x) ULL((x) << 24) 816 #define MDCR_EL2_E2TB_EL1 ULL(0x3) 817 #define MDCR_EL2_HCCD_BIT (ULL(1) << 23) 818 #define MDCR_EL2_TTRF (ULL(1) << 19) 819 #define MDCR_EL2_HPMD_BIT (ULL(1) << 17) 820 #define MDCR_EL2_TPMS (ULL(1) << 14) 821 #define MDCR_EL2_E2PB(x) ULL((x) << 12) 822 #define MDCR_EL2_E2PB_EL1 ULL(0x3) 823 #define MDCR_EL2_TDRA_BIT (ULL(1) << 11) 824 #define MDCR_EL2_TDOSA_BIT (ULL(1) << 10) 825 #define MDCR_EL2_TDA_BIT (ULL(1) << 9) 826 #define MDCR_EL2_TDE_BIT (ULL(1) << 8) 827 #define MDCR_EL2_HPME_BIT (ULL(1) << 7) 828 #define MDCR_EL2_TPM_BIT (ULL(1) << 6) 829 #define MDCR_EL2_TPMCR_BIT (ULL(1) << 5) 830 #define MDCR_EL2_HPMN_MASK ULL(0x1f) 831 #define MDCR_EL2_RESET_VAL ULL(0x0) 832 833 /* HSTR_EL2 definitions */ 834 #define HSTR_EL2_RESET_VAL U(0x0) 835 #define HSTR_EL2_T_MASK U(0xff) 836 837 /* CNTHP_CTL_EL2 definitions */ 838 #define CNTHP_CTL_ENABLE_BIT (U(1) << 0) 839 #define CNTHP_CTL_RESET_VAL U(0x0) 840 841 /* VTTBR_EL2 definitions */ 842 #define VTTBR_RESET_VAL ULL(0x0) 843 #define VTTBR_VMID_MASK ULL(0xff) 844 #define VTTBR_VMID_SHIFT U(48) 845 #define VTTBR_BADDR_MASK ULL(0xffffffffffff) 846 #define VTTBR_BADDR_SHIFT U(0) 847 848 /* HCR definitions */ 849 #define HCR_RESET_VAL ULL(0x0) 850 #define HCR_AMVOFFEN_SHIFT U(51) 851 #define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT) 852 #define HCR_TEA_BIT (ULL(1) << 47) 853 #define HCR_API_BIT (ULL(1) << 41) 854 #define HCR_APK_BIT (ULL(1) << 40) 855 #define HCR_E2H_BIT (ULL(1) << 34) 856 #define HCR_HCD_BIT (ULL(1) << 29) 857 #define HCR_TGE_BIT (ULL(1) << 27) 858 #define HCR_RW_SHIFT U(31) 859 #define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT) 860 #define HCR_TWE_BIT (ULL(1) << 14) 861 #define HCR_TWI_BIT (ULL(1) << 13) 862 #define HCR_AMO_BIT (ULL(1) << 5) 863 #define HCR_IMO_BIT (ULL(1) << 4) 864 #define HCR_FMO_BIT (ULL(1) << 3) 865 866 /* ISR definitions */ 867 #define ISR_A_SHIFT U(8) 868 #define ISR_I_SHIFT U(7) 869 #define ISR_F_SHIFT U(6) 870 871 /* CNTHCTL_EL2 definitions */ 872 #define CNTHCTL_RESET_VAL U(0x0) 873 #define EVNTEN_BIT (U(1) << 2) 874 #define EL1PCEN_BIT (U(1) << 1) 875 #define EL1PCTEN_BIT (U(1) << 0) 876 877 /* CNTKCTL_EL1 definitions */ 878 #define EL0PTEN_BIT (U(1) << 9) 879 #define EL0VTEN_BIT (U(1) << 8) 880 #define EL0PCTEN_BIT (U(1) << 0) 881 #define EL0VCTEN_BIT (U(1) << 1) 882 #define EVNTEN_BIT (U(1) << 2) 883 #define EVNTDIR_BIT (U(1) << 3) 884 #define EVNTI_SHIFT U(4) 885 #define EVNTI_MASK U(0xf) 886 887 /* CPTR_EL3 definitions */ 888 #define TCPAC_BIT (U(1) << 31) 889 #define TAM_SHIFT U(30) 890 #define TAM_BIT (U(1) << TAM_SHIFT) 891 #define TTA_BIT (U(1) << 20) 892 #define ESM_BIT (U(1) << 12) 893 #define TFP_BIT (U(1) << 10) 894 #define CPTR_EZ_BIT (U(1) << 8) 895 896 #if ENABLE_FEAT_MORELLO 897 #define EC_BIT (U(1) << 9) 898 /* 899 * Even though the morello spec doesnot have TAM_BIT defined it is included 900 * to keep the definition as close to other hardware as possible. Since bit 30 901 * is reserved in Morello it should not have any effect anyways. 902 */ 903 #define CPTR_EL3_RESET_VAL ((TAM_BIT | TTA_BIT | EC_BIT) & \ 904 ~(CPTR_EZ_BIT | ESM_BIT | TFP_BIT | TCPAC_BIT)) 905 #else 906 /* TCPAC is always set by default as the register is always present */ 907 #define CPTR_EL3_RESET_VAL ((TAM_BIT | TTA_BIT) & \ 908 ~(CPTR_EZ_BIT | ESM_BIT | TFP_BIT | TCPAC_BIT)) 909 #endif 910 911 /* CPTR_EL2 definitions */ 912 #define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff))) 913 #define CPTR_EL2_TCPAC_BIT (U(1) << 31) 914 #define CPTR_EL2_TAM_SHIFT U(30) 915 #define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT) 916 #define CPTR_EL2_SMEN_MASK ULL(0x3) 917 #define CPTR_EL2_SMEN_SHIFT U(24) 918 #define CPTR_EL2_TTA_BIT (U(1) << 20) 919 #define CPTR_EL2_ZEN_MASK ULL(0x3) 920 #define CPTR_EL2_ZEN_SHIFT U(16) 921 #define CPTR_EL2_TSM_BIT (U(1) << 12) 922 #define CPTR_EL2_TFP_BIT (ULL(1) << 10) 923 #define CPTR_EL2_TZ_BIT (ULL(1) << 8) 924 #define CPTR_EL2_RESET_VAL CPTR_EL2_RES1 925 926 /* VTCR_EL2 definitions */ 927 #define VTCR_RESET_VAL U(0x0) 928 #define VTCR_EL2_MSA (U(1) << 31) 929 930 /* CPSR/SPSR definitions */ 931 #define DAIF_FIQ_BIT (U(1) << 0) 932 #define DAIF_IRQ_BIT (U(1) << 1) 933 #define DAIF_ABT_BIT (U(1) << 2) 934 #define DAIF_DBG_BIT (U(1) << 3) 935 #define SPSR_V_BIT (U(1) << 28) 936 #define SPSR_C_BIT (U(1) << 29) 937 #define SPSR_Z_BIT (U(1) << 30) 938 #define SPSR_N_BIT (U(1) << 31) 939 #define SPSR_DAIF_SHIFT U(6) 940 #define SPSR_DAIF_MASK U(0xf) 941 942 #define SPSR_AIF_SHIFT U(6) 943 #define SPSR_AIF_MASK U(0x7) 944 945 #define SPSR_E_SHIFT U(9) 946 #define SPSR_E_MASK U(0x1) 947 #define SPSR_E_LITTLE U(0x0) 948 #define SPSR_E_BIG U(0x1) 949 950 #define SPSR_T_SHIFT U(5) 951 #define SPSR_T_MASK U(0x1) 952 #define SPSR_T_ARM U(0x0) 953 #define SPSR_T_THUMB U(0x1) 954 955 #define SPSR_M_SHIFT U(4) 956 #define SPSR_M_MASK U(0x1) 957 #define SPSR_M_WIDTH U(1) 958 #define SPSR_M_AARCH64 U(0x0) 959 #define SPSR_M_AARCH32 U(0x1) 960 #define SPSR_M_EL1H U(0x5) 961 #define SPSR_M_EL2H U(0x9) 962 963 #define SPSR_EL_SHIFT U(2) 964 #define SPSR_EL_WIDTH U(2) 965 966 #define SPSR_BTYPE_SHIFT_AARCH64 U(10) 967 #define SPSR_BTYPE_MASK_AARCH64 U(0x3) 968 #define SPSR_SSBS_SHIFT_AARCH64 U(12) 969 #define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64) 970 #define SPSR_SSBS_SHIFT_AARCH32 U(23) 971 #define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32) 972 #define SPSR_ALLINT_BIT_AARCH64 BIT_64(13) 973 #define SPSR_IL_BIT BIT_64(20) 974 #define SPSR_SS_BIT BIT_64(21) 975 #define SPSR_PAN_BIT BIT_64(22) 976 #define SPSR_UAO_BIT_AARCH64 BIT_64(23) 977 #define SPSR_DIT_BIT BIT(24) 978 #define SPSR_TCO_BIT_AARCH64 BIT_64(25) 979 #define SPSR_PM_BIT_AARCH64 BIT_64(32) 980 #define SPSR_PPEND_BIT BIT(33) 981 #define SPSR_EXLOCK_BIT_AARCH64 BIT_64(34) 982 #define SPSR_NZCV (SPSR_V_BIT | SPSR_C_BIT | SPSR_Z_BIT | SPSR_N_BIT) 983 #define SPSR_PACM_BIT_AARCH64 BIT_64(35) 984 #define SPSR_UINJ_BIT BIT_64(36) 985 986 /* 987 * SPSR_EL2 988 * M=0x9 (0b1001 EL2h) 989 * M[4]=0 990 * DAIF=0xF Exceptions masked on entry. 991 * BTYPE=0 BTI not yet supported. 992 * SSBS=0 Not yet supported. 993 * IL=0 Not an illegal exception return. 994 * SS=0 Not single stepping. 995 * PAN=1 RMM shouldn't access Unprivileged memory when running in VHE mode. 996 * UAO=0 997 * DIT=0 998 * TCO=0 999 * NZCV=0 1000 */ 1001 #define SPSR_EL2_REALM (SPSR_M_EL2H | (0xF << SPSR_DAIF_SHIFT) | \ 1002 SPSR_PAN_BIT) 1003 1004 #define DISABLE_ALL_EXCEPTIONS \ 1005 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 1006 #define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT) 1007 1008 /* 1009 * RMR_EL3 definitions 1010 */ 1011 #define RMR_EL3_RR_BIT (U(1) << 1) 1012 #define RMR_EL3_AA64_BIT (U(1) << 0) 1013 1014 /* 1015 * HI-VECTOR address for AArch32 state 1016 */ 1017 #define HI_VECTOR_BASE U(0xFFFF0000) 1018 1019 /* 1020 * TCR definitions 1021 */ 1022 #define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 1023 #define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23)) 1024 #define TCR_EL1_IPS_SHIFT U(32) 1025 #define TCR_EL2_PS_SHIFT U(16) 1026 #define TCR_EL3_PS_SHIFT U(16) 1027 1028 #define TCR_TxSZ_MIN ULL(16) 1029 #define TCR_TxSZ_MAX ULL(39) 1030 #define TCR_TxSZ_MAX_TTST ULL(48) 1031 1032 #define TCR_T0SZ_SHIFT U(0) 1033 #define TCR_T1SZ_SHIFT U(16) 1034 1035 /* (internal) physical address size bits in EL3/EL1 */ 1036 #define TCR_PS_BITS_4GB ULL(0x0) 1037 #define TCR_PS_BITS_64GB ULL(0x1) 1038 #define TCR_PS_BITS_1TB ULL(0x2) 1039 #define TCR_PS_BITS_4TB ULL(0x3) 1040 #define TCR_PS_BITS_16TB ULL(0x4) 1041 #define TCR_PS_BITS_256TB ULL(0x5) 1042 1043 #define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000) 1044 #define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000) 1045 #define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000) 1046 #define ADDR_MASK_40_TO_41 ULL(0x0000030000000000) 1047 #define ADDR_MASK_36_TO_39 ULL(0x000000F000000000) 1048 #define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000) 1049 1050 #define TCR_RGN_INNER_NC (ULL(0x0) << 8) 1051 #define TCR_RGN_INNER_WBA (ULL(0x1) << 8) 1052 #define TCR_RGN_INNER_WT (ULL(0x2) << 8) 1053 #define TCR_RGN_INNER_WBNA (ULL(0x3) << 8) 1054 1055 #define TCR_RGN_OUTER_NC (ULL(0x0) << 10) 1056 #define TCR_RGN_OUTER_WBA (ULL(0x1) << 10) 1057 #define TCR_RGN_OUTER_WT (ULL(0x2) << 10) 1058 #define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10) 1059 1060 #define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12) 1061 #define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12) 1062 #define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12) 1063 1064 #define TCR_RGN1_INNER_NC (ULL(0x0) << 24) 1065 #define TCR_RGN1_INNER_WBA (ULL(0x1) << 24) 1066 #define TCR_RGN1_INNER_WT (ULL(0x2) << 24) 1067 #define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24) 1068 1069 #define TCR_RGN1_OUTER_NC (ULL(0x0) << 26) 1070 #define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26) 1071 #define TCR_RGN1_OUTER_WT (ULL(0x2) << 26) 1072 #define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26) 1073 1074 #define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28) 1075 #define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28) 1076 #define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28) 1077 1078 #define TCR_TG0_SHIFT U(14) 1079 #define TCR_TG0_MASK ULL(3) 1080 #define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT) 1081 #define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT) 1082 #define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT) 1083 1084 #define TCR_HPD_BIT (ULL(1) << 24) 1085 #define TCR_HWU59_BIT (ULL(1) << 25) 1086 #define TCR_HWU60_BIT (ULL(1) << 26) 1087 #define TCR_HWU61_BIT (ULL(1) << 27) 1088 #define TCR_HWU62_BIT (ULL(1) << 28) 1089 1090 #define TCR_TG1_SHIFT U(30) 1091 #define TCR_TG1_MASK ULL(3) 1092 #define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT) 1093 #define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT) 1094 #define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT) 1095 1096 #define TCR_EPD0_BIT (ULL(1) << 7) 1097 #define TCR_EPD1_BIT (ULL(1) << 23) 1098 1099 #define MODE_SP_SHIFT U(0x0) 1100 #define MODE_SP_MASK U(0x1) 1101 #define MODE_SP_EL0 U(0x0) 1102 #define MODE_SP_ELX U(0x1) 1103 1104 #define MODE_RW_SHIFT U(0x4) 1105 #define MODE_RW_MASK U(0x1) 1106 #define MODE_RW_64 U(0x0) 1107 #define MODE_RW_32 U(0x1) 1108 1109 #define MODE_EL_SHIFT U(0x2) 1110 #define MODE_EL_MASK U(0x3) 1111 #define MODE_EL_WIDTH U(0x2) 1112 #define MODE_EL3 U(0x3) 1113 #define MODE_EL2 U(0x2) 1114 #define MODE_EL1 U(0x1) 1115 #define MODE_EL0 U(0x0) 1116 1117 #define MODE32_SHIFT U(0) 1118 #define MODE32_MASK U(0xf) 1119 #define MODE32_usr U(0x0) 1120 #define MODE32_fiq U(0x1) 1121 #define MODE32_irq U(0x2) 1122 #define MODE32_svc U(0x3) 1123 #define MODE32_mon U(0x6) 1124 #define MODE32_abt U(0x7) 1125 #define MODE32_hyp U(0xa) 1126 #define MODE32_und U(0xb) 1127 #define MODE32_sys U(0xf) 1128 1129 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 1130 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 1131 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 1132 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 1133 1134 #define SPSR_64(el, sp, daif) \ 1135 (((MODE_RW_64 << MODE_RW_SHIFT) | \ 1136 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \ 1137 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \ 1138 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \ 1139 (~(SPSR_SSBS_BIT_AARCH64))) 1140 1141 #define SPSR_MODE32(mode, isa, endian, aif) \ 1142 (((MODE_RW_32 << MODE_RW_SHIFT) | \ 1143 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \ 1144 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \ 1145 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \ 1146 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \ 1147 (~(SPSR_SSBS_BIT_AARCH32))) 1148 1149 /* 1150 * TTBR Definitions 1151 */ 1152 #define TTBR_CNP_BIT ULL(0x1) 1153 1154 /* 1155 * CTR_EL0 definitions 1156 */ 1157 #define CTR_CWG_SHIFT U(24) 1158 #define CTR_CWG_MASK U(0xf) 1159 #define CTR_ERG_SHIFT U(20) 1160 #define CTR_ERG_MASK U(0xf) 1161 #define CTR_DMINLINE_SHIFT U(16) 1162 #define CTR_DMINLINE_MASK U(0xf) 1163 #define CTR_L1IP_SHIFT U(14) 1164 #define CTR_L1IP_MASK U(0x3) 1165 #define CTR_IMINLINE_SHIFT U(0) 1166 #define CTR_IMINLINE_MASK U(0xf) 1167 1168 #define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */ 1169 1170 /* Physical timer control register bit fields shifts and masks */ 1171 #define CNTP_CTL_ENABLE_SHIFT U(0) 1172 #define CNTP_CTL_IMASK_SHIFT U(1) 1173 #define CNTP_CTL_ISTATUS_SHIFT U(2) 1174 1175 #define CNTP_CTL_ENABLE_MASK U(1) 1176 #define CNTP_CTL_IMASK_MASK U(1) 1177 #define CNTP_CTL_ISTATUS_MASK U(1) 1178 1179 /* Physical timer control macros */ 1180 #define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT) 1181 #define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT) 1182 1183 /* Exception Syndrome register bits and bobs */ 1184 #define ESR_EC_SHIFT U(26) 1185 #define ESR_EC_MASK U(0x3f) 1186 #define ESR_EC_LENGTH U(6) 1187 #define ESR_EC_WIDTH U(6) 1188 #define ESR_ISS_SHIFT U(0) 1189 #define ESR_ISS_LENGTH U(25) 1190 #define ESR_IL_BIT (U(1) << 25) 1191 #define EC_UNKNOWN U(0x0) 1192 #define EC_WFE_WFI U(0x1) 1193 #define EC_AARCH32_CP15_MRC_MCR U(0x3) 1194 #define EC_AARCH32_CP15_MRRC_MCRR U(0x4) 1195 #define EC_AARCH32_CP14_MRC_MCR U(0x5) 1196 #define EC_AARCH32_CP14_LDC_STC U(0x6) 1197 #define EC_FP_SIMD U(0x7) 1198 #define EC_AARCH32_CP10_MRC U(0x8) 1199 #define EC_AARCH32_CP14_MRRC_MCRR U(0xc) 1200 #define EC_ILLEGAL U(0xe) 1201 #define EC_AARCH32_SVC U(0x11) 1202 #define EC_AARCH32_HVC U(0x12) 1203 #define EC_AARCH32_SMC U(0x13) 1204 #define EC_AARCH64_SVC U(0x15) 1205 #define EC_AARCH64_HVC U(0x16) 1206 #define EC_AARCH64_SMC U(0x17) 1207 #define EC_AARCH64_SYS U(0x18) 1208 #define EC_IMP_DEF_EL3 U(0x1f) 1209 #define EC_IABORT_LOWER_EL U(0x20) 1210 #define EC_IABORT_CUR_EL U(0x21) 1211 #define EC_PC_ALIGN U(0x22) 1212 #define EC_DABORT_LOWER_EL U(0x24) 1213 #define EC_DABORT_CUR_EL U(0x25) 1214 #define EC_SP_ALIGN U(0x26) 1215 #define EC_AARCH32_FP U(0x28) 1216 #define EC_AARCH64_FP U(0x2c) 1217 #define EC_SERROR U(0x2f) 1218 #define EC_BRK U(0x3c) 1219 1220 /* 1221 * External Abort bit in Instruction and Data Aborts synchronous exception 1222 * syndromes. 1223 */ 1224 #define ESR_ISS_EABORT_EA_BIT U(9) 1225 1226 #define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK) 1227 1228 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */ 1229 #define RMR_RESET_REQUEST_SHIFT U(0x1) 1230 #define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT) 1231 1232 /******************************************************************************* 1233 * Definitions of register offsets, fields and macros for CPU system 1234 * instructions. 1235 ******************************************************************************/ 1236 1237 #define TLBI_ADDR_SHIFT U(12) 1238 #define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF) 1239 #define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK) 1240 1241 /******************************************************************************* 1242 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 1243 * system level implementation of the Generic Timer. 1244 ******************************************************************************/ 1245 #define CNTCTLBASE_CNTFRQ U(0x0) 1246 #define CNTNSAR U(0x4) 1247 #define CNTNSAR_NS_SHIFT(x) (x) 1248 1249 #define CNTACR_BASE(x) (U(0x40) + ((x) << 2)) 1250 #define CNTACR_RPCT_SHIFT U(0x0) 1251 #define CNTACR_RVCT_SHIFT U(0x1) 1252 #define CNTACR_RFRQ_SHIFT U(0x2) 1253 #define CNTACR_RVOFF_SHIFT U(0x3) 1254 #define CNTACR_RWVT_SHIFT U(0x4) 1255 #define CNTACR_RWPT_SHIFT U(0x5) 1256 1257 /******************************************************************************* 1258 * Definitions of register offsets and fields in the CNTBaseN Frame of the 1259 * system level implementation of the Generic Timer. 1260 ******************************************************************************/ 1261 /* Physical Count register. */ 1262 #define CNTPCT_LO U(0x0) 1263 /* Counter Frequency register. */ 1264 #define CNTBASEN_CNTFRQ U(0x10) 1265 /* Physical Timer CompareValue register. */ 1266 #define CNTP_CVAL_LO U(0x20) 1267 /* Physical Timer Control register. */ 1268 #define CNTP_CTL U(0x2c) 1269 1270 /* PMCR_EL0 definitions */ 1271 #define PMCR_EL0_RESET_VAL U(0x0) 1272 #define PMCR_EL0_N_SHIFT U(11) 1273 #define PMCR_EL0_N_MASK U(0x1f) 1274 #define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT) 1275 #define PMCR_EL0_LP_BIT (U(1) << 7) 1276 #define PMCR_EL0_LC_BIT (U(1) << 6) 1277 #define PMCR_EL0_DP_BIT (U(1) << 5) 1278 #define PMCR_EL0_X_BIT (U(1) << 4) 1279 #define PMCR_EL0_D_BIT (U(1) << 3) 1280 #define PMCR_EL0_C_BIT (U(1) << 2) 1281 #define PMCR_EL0_P_BIT (U(1) << 1) 1282 #define PMCR_EL0_E_BIT (U(1) << 0) 1283 1284 /******************************************************************************* 1285 * Definitions for system register interface to SVE 1286 ******************************************************************************/ 1287 #define ZCR_EL3 S3_6_C1_C2_0 1288 #define ZCR_EL2 S3_4_C1_C2_0 1289 1290 /* ZCR_EL3 definitions */ 1291 #define ZCR_EL3_LEN_MASK U(0xf) 1292 1293 /* ZCR_EL2 definitions */ 1294 #define ZCR_EL2_LEN_MASK U(0xf) 1295 1296 /******************************************************************************* 1297 * Definitions for system register interface to SME as needed in EL3 1298 ******************************************************************************/ 1299 #define ID_AA64SMFR0_EL1 S3_0_C0_C4_5 1300 #define SMCR_EL3 S3_6_C1_C2_6 1301 #define SVCR S3_3_C4_C2_2 1302 1303 /* ID_AA64SMFR0_EL1 definitions */ 1304 #define ID_AA64SMFR0_EL1_SME_FA64_SHIFT U(63) 1305 #define ID_AA64SMFR0_EL1_SME_FA64_MASK U(0x1) 1306 #define SME_FA64_IMPLEMENTED U(0x1) 1307 #define ID_AA64SMFR0_EL1_SME_VER_SHIFT U(55) 1308 #define ID_AA64SMFR0_EL1_SME_VER_MASK ULL(0xf) 1309 #define SME_INST_IMPLEMENTED ULL(0x0) 1310 #define SME2_INST_IMPLEMENTED ULL(0x1) 1311 1312 /* SMCR_ELx definitions */ 1313 #define SMCR_ELX_LEN_SHIFT U(0) 1314 #define SMCR_ELX_LEN_MAX U(0x1ff) 1315 #define SMCR_ELX_FA64_BIT (U(1) << 31) 1316 #define SMCR_ELX_EZT0_BIT (U(1) << 30) 1317 1318 /******************************************************************************* 1319 * Definitions of MAIR encodings for device and normal memory 1320 ******************************************************************************/ 1321 /* 1322 * MAIR encodings for device memory attributes. 1323 */ 1324 #define MAIR_DEV_nGnRnE ULL(0x0) 1325 #define MAIR_DEV_nGnRE ULL(0x4) 1326 #define MAIR_DEV_nGRE ULL(0x8) 1327 #define MAIR_DEV_GRE ULL(0xc) 1328 1329 /* 1330 * MAIR encodings for normal memory attributes. 1331 * 1332 * Cache Policy 1333 * WT: Write Through 1334 * WB: Write Back 1335 * NC: Non-Cacheable 1336 * 1337 * Transient Hint 1338 * NTR: Non-Transient 1339 * TR: Transient 1340 * 1341 * Allocation Policy 1342 * RA: Read Allocate 1343 * WA: Write Allocate 1344 * RWA: Read and Write Allocate 1345 * NA: No Allocation 1346 */ 1347 #define MAIR_NORM_WT_TR_WA ULL(0x1) 1348 #define MAIR_NORM_WT_TR_RA ULL(0x2) 1349 #define MAIR_NORM_WT_TR_RWA ULL(0x3) 1350 #define MAIR_NORM_NC ULL(0x4) 1351 #define MAIR_NORM_WB_TR_WA ULL(0x5) 1352 #define MAIR_NORM_WB_TR_RA ULL(0x6) 1353 #define MAIR_NORM_WB_TR_RWA ULL(0x7) 1354 #define MAIR_NORM_WT_NTR_NA ULL(0x8) 1355 #define MAIR_NORM_WT_NTR_WA ULL(0x9) 1356 #define MAIR_NORM_WT_NTR_RA ULL(0xa) 1357 #define MAIR_NORM_WT_NTR_RWA ULL(0xb) 1358 #define MAIR_NORM_WB_NTR_NA ULL(0xc) 1359 #define MAIR_NORM_WB_NTR_WA ULL(0xd) 1360 #define MAIR_NORM_WB_NTR_RA ULL(0xe) 1361 #define MAIR_NORM_WB_NTR_RWA ULL(0xf) 1362 1363 #define MAIR_NORM_OUTER_SHIFT U(4) 1364 1365 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \ 1366 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT)) 1367 1368 /* PAR_EL1 fields */ 1369 #define PAR_F_SHIFT U(0) 1370 #define PAR_F_MASK ULL(0x1) 1371 1372 #define PAR_D128_ADDR_MASK GENMASK(55, 12) /* 44-bits-wide page address */ 1373 #define PAR_ADDR_MASK GENMASK(51, 12) /* 40-bits-wide page address */ 1374 1375 /******************************************************************************* 1376 * Definitions for system register interface to SPE 1377 ******************************************************************************/ 1378 #define PMBLIMITR_EL1 S3_0_C9_C10_0 1379 1380 /******************************************************************************* 1381 * Definitions for system register interface, shifts and masks for MPAM 1382 ******************************************************************************/ 1383 #define MPAMIDR_EL1 S3_0_C10_C4_4 1384 #define MPAM2_EL2 S3_4_C10_C5_0 1385 #define MPAMHCR_EL2 S3_4_C10_C4_0 1386 #define MPAM3_EL3 S3_6_C10_C5_0 1387 1388 #define MPAMIDR_EL1_VPMR_MAX_SHIFT ULL(18) 1389 #define MPAMIDR_EL1_VPMR_MAX_MASK ULL(0x7) 1390 /******************************************************************************* 1391 * Definitions for system register interface to AMU for FEAT_AMUv1 1392 ******************************************************************************/ 1393 #define AMCR_EL0 S3_3_C13_C2_0 1394 #define AMCFGR_EL0 S3_3_C13_C2_1 1395 #define AMCGCR_EL0 S3_3_C13_C2_2 1396 #define AMUSERENR_EL0 S3_3_C13_C2_3 1397 #define AMCNTENCLR0_EL0 S3_3_C13_C2_4 1398 #define AMCNTENSET0_EL0 S3_3_C13_C2_5 1399 #define AMCNTENCLR1_EL0 S3_3_C13_C3_0 1400 #define AMCNTENSET1_EL0 S3_3_C13_C3_1 1401 1402 /* Activity Monitor Group 0 Event Counter Registers */ 1403 #define AMEVCNTR00_EL0 S3_3_C13_C4_0 1404 #define AMEVCNTR01_EL0 S3_3_C13_C4_1 1405 #define AMEVCNTR02_EL0 S3_3_C13_C4_2 1406 #define AMEVCNTR03_EL0 S3_3_C13_C4_3 1407 1408 /* Activity Monitor Group 0 Event Type Registers */ 1409 #define AMEVTYPER00_EL0 S3_3_C13_C6_0 1410 #define AMEVTYPER01_EL0 S3_3_C13_C6_1 1411 #define AMEVTYPER02_EL0 S3_3_C13_C6_2 1412 #define AMEVTYPER03_EL0 S3_3_C13_C6_3 1413 1414 /* Activity Monitor Group 1 Event Counter Registers */ 1415 #define AMEVCNTR10_EL0 S3_3_C13_C12_0 1416 #define AMEVCNTR11_EL0 S3_3_C13_C12_1 1417 #define AMEVCNTR12_EL0 S3_3_C13_C12_2 1418 #define AMEVCNTR13_EL0 S3_3_C13_C12_3 1419 #define AMEVCNTR14_EL0 S3_3_C13_C12_4 1420 #define AMEVCNTR15_EL0 S3_3_C13_C12_5 1421 #define AMEVCNTR16_EL0 S3_3_C13_C12_6 1422 #define AMEVCNTR17_EL0 S3_3_C13_C12_7 1423 #define AMEVCNTR18_EL0 S3_3_C13_C13_0 1424 #define AMEVCNTR19_EL0 S3_3_C13_C13_1 1425 #define AMEVCNTR1A_EL0 S3_3_C13_C13_2 1426 #define AMEVCNTR1B_EL0 S3_3_C13_C13_3 1427 #define AMEVCNTR1C_EL0 S3_3_C13_C13_4 1428 #define AMEVCNTR1D_EL0 S3_3_C13_C13_5 1429 #define AMEVCNTR1E_EL0 S3_3_C13_C13_6 1430 #define AMEVCNTR1F_EL0 S3_3_C13_C13_7 1431 1432 /* Activity Monitor Group 1 Event Type Registers */ 1433 #define AMEVTYPER10_EL0 S3_3_C13_C14_0 1434 #define AMEVTYPER11_EL0 S3_3_C13_C14_1 1435 #define AMEVTYPER12_EL0 S3_3_C13_C14_2 1436 #define AMEVTYPER13_EL0 S3_3_C13_C14_3 1437 #define AMEVTYPER14_EL0 S3_3_C13_C14_4 1438 #define AMEVTYPER15_EL0 S3_3_C13_C14_5 1439 #define AMEVTYPER16_EL0 S3_3_C13_C14_6 1440 #define AMEVTYPER17_EL0 S3_3_C13_C14_7 1441 #define AMEVTYPER18_EL0 S3_3_C13_C15_0 1442 #define AMEVTYPER19_EL0 S3_3_C13_C15_1 1443 #define AMEVTYPER1A_EL0 S3_3_C13_C15_2 1444 #define AMEVTYPER1B_EL0 S3_3_C13_C15_3 1445 #define AMEVTYPER1C_EL0 S3_3_C13_C15_4 1446 #define AMEVTYPER1D_EL0 S3_3_C13_C15_5 1447 #define AMEVTYPER1E_EL0 S3_3_C13_C15_6 1448 #define AMEVTYPER1F_EL0 S3_3_C13_C15_7 1449 1450 /* AMCNTENSET0_EL0 definitions */ 1451 #define AMCNTENSET0_EL0_Pn_ALWAYS_ON ULL(0x3) 1452 #define AMCNTENSET0_EL0_Pn_CONTEXTED ULL(0xc) 1453 #define AMCNTENSET0_EL0_Pn_ALL ULL(0xf) 1454 1455 /* AMCNTENSET1_EL0 definitions */ 1456 #define AMCNTENSET1_EL0_Pn_SHIFT U(0) 1457 #define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff) 1458 1459 /* AMCNTENCLR0_EL0 definitions */ 1460 #define AMCNTENCLR0_EL0_Pn_ALWAYS_ON ULL(0x3) 1461 #define AMCNTENCLR0_EL0_Pn_CONTEXTED ULL(0xc) 1462 #define AMCNTENCLR0_EL0_Pn_ALL ULL(0xf) 1463 1464 /* AMCNTENCLR1_EL0 definitions */ 1465 #define AMCNTENCLR1_EL0_Pn_SHIFT U(0) 1466 #define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff) 1467 1468 /* AMCFGR_EL0 definitions */ 1469 #define AMCFGR_EL0_NCG_SHIFT U(28) 1470 #define AMCFGR_EL0_NCG_MASK U(0xf) 1471 #define AMCFGR_EL0_N_SHIFT U(0) 1472 #define AMCFGR_EL0_N_MASK U(0xff) 1473 1474 /* AMCGCR_EL0 definitions */ 1475 #define AMCGCR_EL0_CG0NC_SHIFT U(0) 1476 #define AMCGCR_EL0_CG0NC_MASK U(0xff) 1477 #define AMCGCR_EL0_CG1NC_SHIFT U(8) 1478 #define AMCGCR_EL0_CG1NC_MASK U(0xff) 1479 1480 /* MPAM register definitions */ 1481 #define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63) 1482 #define MPAM3_EL3_TRAPLOWER_BIT (ULL(1) << 62) 1483 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31) 1484 #define MPAM3_EL3_RESET_VAL MPAM3_EL3_TRAPLOWER_BIT 1485 1486 #define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49) 1487 #define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48) 1488 1489 #define MPAMIDR_HAS_BW_CTRL_BIT (ULL(1) << 56) 1490 #define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17) 1491 1492 /* MPAM_PE_BW_CTRL register definitions */ 1493 #define MPAMBW2_EL2 S3_4_C10_C5_4 1494 #define MPAMBW2_EL2_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1495 #define MPAMBW2_EL2_ENABLED_BIT (ULL(1) << 62) 1496 #define MPAMBW2_EL2_HARDLIM_BIT (ULL(1) << 61) 1497 #define MPAMBW2_EL2_NTRAP_MPAMBWIDR_EL1_BIT (ULL(1) << 52) 1498 #define MPAMBW2_EL2_NTRAP_MPAMBW0_EL1_BIT (ULL(1) << 51) 1499 #define MPAMBW2_EL2_NTRAP_MPAMBW1_EL1_BIT (ULL(1) << 50) 1500 #define MPAMBW2_EL2_NTRAP_MPAMBWSM_EL1_BIT (ULL(1) << 49) 1501 1502 #define MPAMBW3_EL3 S3_6_C10_C5_4 1503 #define MPAMBW3_EL3_HW_SCALE_ENABLE_BIT (ULL(1) << 63) 1504 #define MPAMBW3_EL3_ENABLED_BIT (ULL(1) << 62) 1505 #define MPAMBW3_EL3_HARDLIM_BIT (ULL(1) << 61) 1506 #define MPAMBW3_EL3_NTRAPLOWER_BIT (ULL(1) << 49) 1507 1508 /******************************************************************************* 1509 * Definitions for system register interface to AMU for FEAT_AMUv1p1 1510 ******************************************************************************/ 1511 1512 /* Definition for register defining which virtual offsets are implemented. */ 1513 #define AMCG1IDR_EL0 S3_3_C13_C2_6 1514 #define AMCG1IDR_CTR_MASK ULL(0xffff) 1515 #define AMCG1IDR_CTR_SHIFT U(0) 1516 #define AMCG1IDR_VOFF_MASK ULL(0xffff) 1517 #define AMCG1IDR_VOFF_SHIFT U(16) 1518 1519 /* New bit added to AMCR_EL0 */ 1520 #define AMCR_CG1RZ_SHIFT U(17) 1521 #define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT) 1522 1523 /* 1524 * Definitions for virtual offset registers for architected activity monitor 1525 * event counters. 1526 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist. 1527 */ 1528 #define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0 1529 #define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2 1530 #define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3 1531 1532 /* 1533 * Definitions for virtual offset registers for auxiliary activity monitor event 1534 * counters. 1535 */ 1536 #define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0 1537 #define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1 1538 #define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2 1539 #define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3 1540 #define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4 1541 #define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5 1542 #define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6 1543 #define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7 1544 #define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0 1545 #define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1 1546 #define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2 1547 #define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3 1548 #define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4 1549 #define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5 1550 #define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6 1551 #define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7 1552 1553 /******************************************************************************* 1554 * Realm management extension register definitions 1555 ******************************************************************************/ 1556 #define GPCCR_EL3 S3_6_C2_C1_6 1557 #define GPTBR_EL3 S3_6_C2_C1_4 1558 1559 #define SCXTNUM_EL2 S3_4_C13_C0_7 1560 #define SCXTNUM_EL1 S3_0_C13_C0_7 1561 #define SCXTNUM_EL0 S3_3_C13_C0_7 1562 1563 /******************************************************************************* 1564 * RAS system registers 1565 ******************************************************************************/ 1566 #define DISR_EL1 S3_0_C12_C1_1 1567 #define DISR_A_BIT U(31) 1568 1569 #define ERRIDR_EL1 S3_0_C5_C3_0 1570 #define ERRIDR_MASK U(0xffff) 1571 1572 #define ERRSELR_EL1 S3_0_C5_C3_1 1573 1574 /* System register access to Standard Error Record registers */ 1575 #define ERXFR_EL1 S3_0_C5_C4_0 1576 #define ERXCTLR_EL1 S3_0_C5_C4_1 1577 #define ERXSTATUS_EL1 S3_0_C5_C4_2 1578 #define ERXADDR_EL1 S3_0_C5_C4_3 1579 #define ERXPFGF_EL1 S3_0_C5_C4_4 1580 #define ERXPFGCTL_EL1 S3_0_C5_C4_5 1581 #define ERXPFGCDN_EL1 S3_0_C5_C4_6 1582 #define ERXMISC0_EL1 S3_0_C5_C5_0 1583 #define ERXMISC1_EL1 S3_0_C5_C5_1 1584 1585 #define ERXCTLR_ED_SHIFT U(0) 1586 #define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT) 1587 #define ERXCTLR_UE_BIT (U(1) << 4) 1588 1589 #define ERXPFGCTL_UC_BIT (U(1) << 1) 1590 #define ERXPFGCTL_UEU_BIT (U(1) << 2) 1591 #define ERXPFGCTL_CDEN_BIT (U(1) << 31) 1592 1593 /******************************************************************************* 1594 * Armv8.3 Pointer Authentication Registers 1595 ******************************************************************************/ 1596 #define APIAKeyLo_EL1 S3_0_C2_C1_0 1597 #define APIAKeyHi_EL1 S3_0_C2_C1_1 1598 #define APIBKeyLo_EL1 S3_0_C2_C1_2 1599 #define APIBKeyHi_EL1 S3_0_C2_C1_3 1600 #define APDAKeyLo_EL1 S3_0_C2_C2_0 1601 #define APDAKeyHi_EL1 S3_0_C2_C2_1 1602 #define APDBKeyLo_EL1 S3_0_C2_C2_2 1603 #define APDBKeyHi_EL1 S3_0_C2_C2_3 1604 #define APGAKeyLo_EL1 S3_0_C2_C3_0 1605 #define APGAKeyHi_EL1 S3_0_C2_C3_1 1606 1607 /******************************************************************************* 1608 * Armv8.4 Data Independent Timing Registers 1609 ******************************************************************************/ 1610 #define DIT S3_3_C4_C2_5 1611 #define DIT_BIT BIT(24) 1612 1613 /******************************************************************************* 1614 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field 1615 ******************************************************************************/ 1616 #define SSBS S3_3_C4_C2_6 1617 1618 /******************************************************************************* 1619 * Armv8.5 - Memory Tagging Extension Registers 1620 ******************************************************************************/ 1621 #define TFSRE0_EL1 S3_0_C5_C6_1 1622 #define TFSR_EL1 S3_0_C5_C6_0 1623 #define RGSR_EL1 S3_0_C1_C0_5 1624 #define GCR_EL1 S3_0_C1_C0_6 1625 1626 #define GCR_EL1_RRND_BIT (UL(1) << 16) 1627 1628 /******************************************************************************* 1629 * Armv8.5 - Random Number Generator Registers 1630 ******************************************************************************/ 1631 #define RNDR S3_3_C2_C4_0 1632 #define RNDRRS S3_3_C2_C4_1 1633 1634 /******************************************************************************* 1635 * FEAT_HCX - Extended Hypervisor Configuration Register 1636 ******************************************************************************/ 1637 #define HCRX_EL2 S3_4_C1_C2_2 1638 #define HCRX_EL2_MSCEn_BIT (UL(1) << 11) 1639 #define HCRX_EL2_MCE2_BIT (UL(1) << 10) 1640 #define HCRX_EL2_CMOW_BIT (UL(1) << 9) 1641 #define HCRX_EL2_VFNMI_BIT (UL(1) << 8) 1642 #define HCRX_EL2_VINMI_BIT (UL(1) << 7) 1643 #define HCRX_EL2_TALLINT_BIT (UL(1) << 6) 1644 #define HCRX_EL2_SMPME_BIT (UL(1) << 5) 1645 #define HCRX_EL2_FGTnXS_BIT (UL(1) << 4) 1646 #define HCRX_EL2_FnXS_BIT (UL(1) << 3) 1647 #define HCRX_EL2_EnASR_BIT (UL(1) << 2) 1648 #define HCRX_EL2_EnALS_BIT (UL(1) << 1) 1649 #define HCRX_EL2_EnAS0_BIT (UL(1) << 0) 1650 #define HCRX_EL2_INIT_VAL ULL(0x0) 1651 1652 /******************************************************************************* 1653 * FEAT_FGT - Definitions for Fine-Grained Trap registers 1654 ******************************************************************************/ 1655 #define HFGITR_EL2_INIT_VAL ULL(0x180000000000000) 1656 #define HFGRTR_EL2_INIT_VAL ULL(0xC4000000000000) 1657 #define HFGWTR_EL2_INIT_VAL ULL(0xC4000000000000) 1658 1659 /******************************************************************************* 1660 * FEAT_TCR2 - Extended Translation Control Registers 1661 ******************************************************************************/ 1662 #define TCR2_EL1 S3_0_C2_C0_3 1663 #define TCR2_EL2 S3_4_C2_C0_3 1664 1665 /******************************************************************************* 1666 * Permission indirection and overlay Registers 1667 ******************************************************************************/ 1668 1669 #define PIRE0_EL1 S3_0_C10_C2_2 1670 #define PIRE0_EL2 S3_4_C10_C2_2 1671 #define PIR_EL1 S3_0_C10_C2_3 1672 #define PIR_EL2 S3_4_C10_C2_3 1673 #define POR_EL1 S3_0_C10_C2_4 1674 #define POR_EL2 S3_4_C10_C2_4 1675 #define S2PIR_EL2 S3_4_C10_C2_5 1676 #define S2POR_EL1 S3_0_C10_C2_5 1677 1678 /******************************************************************************* 1679 * FEAT_GCS - Guarded Control Stack Registers 1680 ******************************************************************************/ 1681 #define GCSCR_EL2 S3_4_C2_C5_0 1682 #define GCSPR_EL2 S3_4_C2_C5_1 1683 #define GCSCR_EL1 S3_0_C2_C5_0 1684 #define GCSCRE0_EL1 S3_0_C2_C5_2 1685 #define GCSPR_EL1 S3_0_C2_C5_1 1686 #define GCSPR_EL0 S3_3_C2_C5_1 1687 1688 #define GCSCR_EXLOCK_EN_BIT (UL(1) << 6) 1689 1690 /******************************************************************************* 1691 * FEAT_TRF - Trace Filter Control Registers 1692 ******************************************************************************/ 1693 #define TRFCR_EL2 S3_4_C1_C2_1 1694 #define TRFCR_EL1 S3_0_C1_C2_1 1695 1696 /******************************************************************************* 1697 * FEAT_THE - Translation Hardening Extension Registers 1698 ******************************************************************************/ 1699 #define RCWMASK_EL1 S3_0_C13_C0_6 1700 #define RCWSMASK_EL1 S3_0_C13_C0_3 1701 1702 /******************************************************************************* 1703 * FEAT_SCTLR2 - Extension to SCTLR_ELx Registers 1704 ******************************************************************************/ 1705 #define SCTLR2_EL3 S3_6_C1_C0_3 1706 #define SCTLR2_EL2 S3_4_C1_C0_3 1707 #define SCTLR2_EL1 S3_0_C1_C0_3 1708 1709 /******************************************************************************* 1710 * FEAT_BRBE - Branch Record Buffer Extension Registers 1711 ******************************************************************************/ 1712 #define BRBCR_EL2 S2_4_C9_C0_0 1713 1714 /******************************************************************************* 1715 * FEAT_LS64_ACCDATA - LoadStore64B with status data 1716 ******************************************************************************/ 1717 #define ACCDATA_EL1 S3_0_C13_C0_5 1718 1719 /******************************************************************************* 1720 * Definitions for DynamicIQ Shared Unit registers 1721 ******************************************************************************/ 1722 #define CLUSTERPWRDN_EL1 S3_0_C15_C3_6 1723 1724 /******************************************************************************* 1725 * FEAT_FPMR - Floating point Mode Register 1726 ******************************************************************************/ 1727 #define FPMR S3_3_C4_C4_2 1728 1729 /* CLUSTERPWRDN_EL1 register definitions */ 1730 #define DSU_CLUSTER_PWR_OFF 0 1731 #define DSU_CLUSTER_PWR_ON 1 1732 #define DSU_CLUSTER_PWR_MASK U(1) 1733 #define DSU_CLUSTER_MEM_RET BIT(1) 1734 1735 /* CLUSTERPMMDCR register definitions */ 1736 #define CLUSTERPMMDCR_SPME U(1) 1737 1738 /******************************************************************************* 1739 * Definitions for CPU Power/Performance Management registers 1740 ******************************************************************************/ 1741 1742 #define CPUPPMCR_EL3 S3_6_C15_C2_0 1743 #define CPUPPMCR_EL3_MPMMPINCTL_BIT BIT(0) 1744 1745 #define CPUMPMMCR_EL3 S3_6_C15_C2_1 1746 #define CPUMPMMCR_EL3_MPMM_EN_BIT BIT(0) 1747 1748 /* alternative system register encoding for the "sb" speculation barrier */ 1749 #define SYSREG_SB S0_3_C3_C0_7 1750 1751 #define CLUSTERPMCR_EL1 S3_0_C15_C5_0 1752 #define CLUSTERPMCNTENSET_EL1 S3_0_C15_C5_1 1753 #define CLUSTERPMCCNTR_EL1 S3_0_C15_C6_0 1754 #define CLUSTERPMOVSSET_EL1 S3_0_C15_C5_3 1755 #define CLUSTERPMOVSCLR_EL1 S3_0_C15_C5_4 1756 #define CLUSTERPMSELR_EL1 S3_0_C15_C5_5 1757 #define CLUSTERPMXEVTYPER_EL1 S3_0_C15_C6_1 1758 #define CLUSTERPMXEVCNTR_EL1 S3_0_C15_C6_2 1759 #define CLUSTERPMMDCR_EL3 S3_6_C15_C6_3 1760 1761 #define CLUSTERPMCR_E_BIT BIT(0) 1762 #define CLUSTERPMCR_N_SHIFT U(11) 1763 #define CLUSTERPMCR_N_MASK U(0x1f) 1764 1765 /******************************************************************************* 1766 * FEAT_MEC - Memory Encryption Contexts 1767 ******************************************************************************/ 1768 #define MECIDR_EL2 S3_4_C10_C8_7 1769 #define MECIDR_EL2_MECIDWidthm1_MASK U(0xf) 1770 #define MECIDR_EL2_MECIDWidthm1_SHIFT U(0) 1771 1772 /****************************************************************************** 1773 * FEAT_FGWTE3 - Fine Grained Write Trap 1774 ******************************************************************************/ 1775 #define FGWTE3_EL3 S3_6_C1_C1_5 1776 1777 /* FGWTE3_EL3 Defintions */ 1778 #define FGWTE3_EL3_VBAR_EL3_BIT (U(1) << 21) 1779 #define FGWTE3_EL3_TTBR0_EL3_BIT (U(1) << 20) 1780 #define FGWTE3_EL3_TPIDR_EL3_BIT (U(1) << 19) 1781 #define FGWTE3_EL3_TCR_EL3_BIT (U(1) << 18) 1782 #define FGWTE3_EL3_SPMROOTCR_EL3_BIT (U(1) << 17) 1783 #define FGWTE3_EL3_SCTLR2_EL3_BIT (U(1) << 16) 1784 #define FGWTE3_EL3_SCTLR_EL3_BIT (U(1) << 15) 1785 #define FGWTE3_EL3_PIR_EL3_BIT (U(1) << 14) 1786 #define FGWTE3_EL3_MECID_RL_A_EL3_BIT (U(1) << 12) 1787 #define FGWTE3_EL3_MAIR2_EL3_BIT (U(1) << 10) 1788 #define FGWTE3_EL3_MAIR_EL3_BIT (U(1) << 9) 1789 #define FGWTE3_EL3_GPTBR_EL3_BIT (U(1) << 8) 1790 #define FGWTE3_EL3_GPCCR_EL3_BIT (U(1) << 7) 1791 #define FGWTE3_EL3_GCSPR_EL3_BIT (U(1) << 6) 1792 #define FGWTE3_EL3_GCSCR_EL3_BIT (U(1) << 5) 1793 #define FGWTE3_EL3_AMAIR2_EL3_BIT (U(1) << 4) 1794 #define FGWTE3_EL3_AMAIR_EL3_BIT (U(1) << 3) 1795 #define FGWTE3_EL3_AFSR1_EL3_BIT (U(1) << 2) 1796 #define FGWTE3_EL3_AFSR0_EL3_BIT (U(1) << 1) 1797 #define FGWTE3_EL3_ACTLR_EL3_BIT (U(1) << 0) 1798 1799 #define FGWTE3_EL3_EARLY_INIT_VAL ( \ 1800 FGWTE3_EL3_VBAR_EL3_BIT | \ 1801 FGWTE3_EL3_TTBR0_EL3_BIT | \ 1802 FGWTE3_EL3_SPMROOTCR_EL3_BIT | \ 1803 FGWTE3_EL3_SCTLR2_EL3_BIT | \ 1804 FGWTE3_EL3_PIR_EL3_BIT | \ 1805 FGWTE3_EL3_MECID_RL_A_EL3_BIT | \ 1806 FGWTE3_EL3_MAIR2_EL3_BIT | \ 1807 FGWTE3_EL3_MAIR_EL3_BIT | \ 1808 FGWTE3_EL3_GPTBR_EL3_BIT | \ 1809 FGWTE3_EL3_GPCCR_EL3_BIT | \ 1810 FGWTE3_EL3_GCSPR_EL3_BIT | \ 1811 FGWTE3_EL3_GCSCR_EL3_BIT | \ 1812 FGWTE3_EL3_AMAIR2_EL3_BIT | \ 1813 FGWTE3_EL3_AMAIR_EL3_BIT | \ 1814 FGWTE3_EL3_AFSR1_EL3_BIT | \ 1815 FGWTE3_EL3_AFSR0_EL3_BIT) 1816 1817 #if HW_ASSISTED_COHERENCY 1818 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT FGWTE3_EL3_SCTLR_EL3_BIT | 1819 #else 1820 #define FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT 1821 #endif 1822 1823 #if !(CRASH_REPORTING) 1824 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT FGWTE3_EL3_TPIDR_EL3_BIT | 1825 #else 1826 #define FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT 1827 #endif 1828 1829 #define FGWTE3_EL3_LATE_INIT_VAL ( \ 1830 FGWTE3_EL3_EARLY_INIT_VAL | \ 1831 FGWTE3_EL3_LATE_INIT_SCTLR_EL3_BIT \ 1832 FGWTE3_EL3_LATE_INIT_TPIDR_EL3_BIT \ 1833 FGWTE3_EL3_TCR_EL3_BIT | \ 1834 FGWTE3_EL3_ACTLR_EL3_BIT) 1835 1836 #endif /* ARCH_H */ 1837