1Arm Development Platform Build Options 2====================================== 3 4Arm Platform Build Options 5-------------------------- 6 7- ``ARM_BL31_IN_DRAM``: Boolean option to select loading of BL31 in TZC secured 8 DRAM. By default, BL31 is in the secure SRAM. Set this flag to 1 to load 9 BL31 in TZC secured DRAM. If TSP is present, then setting this option also 10 sets the TSP location to DRAM and ignores the ``ARM_TSP_RAM_LOCATION`` build 11 flag. 12 13- ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>`` 14 frame registers by setting the ``CNTCTLBase.CNTACR<N>`` register bits. The 15 frame number ``<N>`` is defined by ``PLAT_ARM_NSTIMER_FRAME_ID``, which 16 should match the frame used by the Non-Secure image (normally the Linux 17 kernel). Default is true (access to the frame is allowed). 18 19- ``ARM_FW_CONFIG_LOAD_ENABLE``: Boolean option to enable the loading of 20 FW_CONFIG device trees from the Firmware Image Package (FIP). When enabled, 21 BL2 is responsible for loading, parsing, and validating the FW_CONFIG device 22 trees from the FIP. The option depends on RESET_TO_BL2. 23 24- ``ARM_DISABLE_TRUSTED_WDOG``: boolean option to disable the Trusted Watchdog. 25 By default, Arm platforms use a watchdog to trigger a system reset in case 26 an error is encountered during the boot process (for example, when an image 27 could not be loaded or authenticated). The watchdog is enabled in the early 28 platform setup hook at BL1 and disabled in the BL1 prepare exit hook. The 29 Trusted Watchdog may be disabled at build time for testing or development 30 purposes. 31 32- ``ARM_LINUX_KERNEL_AS_BL33``: The Linux kernel expects registers x0-x3 to 33 have specific values at boot. This boolean option allows the Trusted Firmware 34 to have a Linux kernel image as BL33 by preparing the registers to these 35 values before jumping to BL33. This option defaults to 0 (disabled). When 36 enabled (1), the address of the Linux image must be provided via the 37 ``PRELOADED_BL33_BASE`` option. Additionally, either the ``HW_CONFIG_BASE`` 38 or ``ARM_PRELOADED_DTB_BASE`` option must specify the memory location of a 39 preloaded device tree blob (DTB). This option implies 40 ``USE_KERNEL_DT_CONVENTION``. 41 42- ``ARM_PLAT_MT``: This flag determines whether the Arm platform layer has to 43 cater for the multi-threading ``MT`` bit when accessing MPIDR. When this flag 44 is set, the functions which deal with MPIDR assume that the ``MT`` bit in 45 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of 46 this flag is 0. Note that this option is not used on FVP platforms. 47 48- ``ARM_PLAT_PROVIDES_BL2_MEM_PARAMS``: This flag can be overriden to 1 in the Arm 49 platform’s ``platform.mk`` to indicate that the platform supplies its own 50 bl2_mem_params_desc.c implementation. When enabled, the common implementation 51 in ``plat/arm/common/`` is omitted, and the platform must add its own 52 bl2_mem_params_desc.c file to ``BL2_SOURCES``. The default value is 0. 53 54- ``ARM_RECOM_STATE_ID_ENC``: The PSCI1.0 specification recommends an encoding 55 for the construction of composite state-ID in the power-state parameter. 56 The existing PSCI clients currently do not support this encoding of 57 State-ID yet. Hence this flag is used to configure whether to use the 58 recommended State-ID encoding or not. The default value of this flag is 0, 59 in which case the platform is configured to expect NULL in the State-ID 60 field of power-state parameter. 61 62- ``ARM_ROTPK_LOCATION``: used when ``TRUSTED_BOARD_BOOT=1``. It specifies the 63 location of the ROTPK returned by the function ``plat_get_rotpk_info()`` 64 for Arm platforms. Depending on the selected option, the proper private key 65 must be specified using the ``ROT_KEY`` option when building the Trusted 66 Firmware. This private key will be used by the certificate generation tool 67 to sign the BL2 and Trusted Key certificates. Available options for 68 ``ARM_ROTPK_LOCATION`` are: 69 70 - ``regs`` : return the ROTPK hash stored in the Trusted root-key storage 71 registers. 72 - ``devel_rsa`` : return a development public key hash embedded in the BL1 73 and BL2 binaries. This hash corresponds to the development private key 74 ``plat/arm/board/common/rotpk/arm_rotprivk_rsa.pem``. 75 The hashing algorithm is selected by ``HASH_ALG``; sha256 is used if 76 ``HASH_ALG`` is not specified. A different RSA key can be specified by setting 77 ``ROT_KEY``, there are 3k and 4k RSA keys in ``plat/arm/board/common/rotpk/``. 78 - ``devel_ecdsa`` : return a development public key hash embedded in the BL1 79 and BL2 binaries. This hash corresponds to the development private key 80 ``plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem`` unless a different key 81 is specified with ``ROT_KEY``, such as the 384 bit key in the same directory. 82 he hashing algorithm is selected by ``HASH_ALG``; sha256 is used if ``HASH_ALG`` 83 is not specified. 84 - ``devel_full_dev_rsa_key`` : return a development public key embedded in 85 the BL1 and BL2 binaries. This key corresponds to the RSA private 86 key ``plat/arm/board/common/rotpk/arm_rotprivk.pem`` by default, but can 87 be changed by setting ``ROT_KEY``, there are 3k and 4k RSA keys in 88 ``plat/arm/board/common/rotpk/``. 89 - ``devel_full_dev_ecdsa_key`` : return a development public key embedded in 90 the BL1 and BL2 binaries. This key corresponds to the EC private key 91 ``plat/arm/board/common/rotpk/arm_rotprivk_ecdsa.pem``, unless a different 92 ECDSA key is specified by ``ROT_KEY``, such as the 384 bit key in the same directory. 93 94- ``ARM_TSP_RAM_LOCATION``: location of the TSP binary. Options: 95 96 - ``tsram`` : Trusted SRAM (default option when TBB is not enabled) 97 - ``tdram`` : Trusted DRAM (if available) 98 - ``dram`` : Secure region in DRAM (default option when TBB is enabled, 99 configured by the TrustZone controller) 100 101- ``ARM_XLAT_TABLES_LIB_V1``: boolean option to compile TF-A with version 1 102 of the translation tables library instead of version 2. It is set to 0 by 103 default, which selects version 2. 104 105- ``ARM_GPT_SUPPORT``: Enable GPT parser to get the entry address and length of 106 the various partitions present in the GPT image. This support is available 107 only for the BL2 component, and it is disabled by default. 108 The following diagram shows the view of the FIP partition inside the GPT 109 image: 110 111 |FIP in a GPT image| 112 113For a better understanding of these options, the Arm development platform memory 114map is explained in the :ref:`Firmware Design`. 115 116.. _build_options_arm_css_platform: 117 118Arm CSS Platform-Specific Build Options 119--------------------------------------- 120 121- ``CSS_DETECT_PRE_1_7_0_SCP``: Boolean flag to detect SCP version 122 incompatibility. Version 1.7.0 of the SCP firmware made a non-backwards 123 compatible change to the MTL protocol, used for AP/SCP communication. 124 TF-A no longer supports earlier SCP versions. If this option is set to 1 125 then TF-A will detect if an earlier version is in use. Default is 1. 126 127- ``CSS_LOAD_SCP_IMAGES``: Boolean flag, which when set, adds SCP_BL2 and 128 SCP_BL2U to the FIP and FWU_FIP respectively, and enables them to be loaded 129 during boot. Default is 1. 130 131- ``CSS_USE_SCMI_SDS_DRIVER``: Boolean flag which selects SCMI/SDS drivers 132 instead of SCPI/BOM driver for communicating with the SCP during power 133 management operations and for SCP RAM Firmware transfer. If this option 134 is set to 1, then SCMI/SDS drivers will be used. Default is 0. 135 136- ``CSS_SYSTEM_GRACEFUL_RESET``: Build option to enable graceful powerdown of 137 CPU core on reset. This build option can be used on CSS platforms that 138 require all the CPUs to execute the CPU specific power down sequence to 139 complete a warm reboot sequence in which only the CPUs are power cycled. 140 141Arm FVP Build Options 142--------------------- 143 144- ``FVP_TRUSTED_SRAM_SIZE``: Size (in kilobytes) of the Trusted SRAM region to 145 utilize when building for the FVP platform. This option defaults to 256 with 146 build option ENABLE_RME=0 and 384 for ENABLE_RME=1. 147 148Arm Juno Build Options 149---------------------- 150 151- ``JUNO_AARCH32_EL3_RUNTIME``: This build flag enables you to execute EL3 152 runtime software in AArch32 mode, which is required to run AArch32 on Juno. 153 By default this flag is set to '0'. Enabling this flag builds BL1 and BL2 in 154 AArch64 and facilitates the loading of ``SP_MIN`` and BL33 as AArch32 executable 155 images. 156 157Arm Neoverse RD Platform Build Options 158-------------------------------------- 159 160 - ``NRD_CHIP_COUNT``: Configures the number of chips on a Neoverse RD platform 161 which supports multi-chip operation. If ``NRD_CHIP_COUNT`` is set to any 162 valid value greater than 1, the platform code performs required configuration 163 to support multi-chip operation. 164 165- ``NRD_PLATFORM_VARIANT``: Selects the variant of a Neoverse RD platform. A 166 particular Neoverse RD platform may have multiple variants which may differ in 167 core count, cluster count or other peripherals. This build option is used to 168 select the appropriate platform variant for the build. The range of valid 169 values is platform specific. 170 171-------------- 172 173.. |FIP in a GPT image| image:: ../../resources/diagrams/FIP_in_a_GPT_image.png 174 175*Copyright (c) 2019-2025, Arm Limited. All rights reserved.* 176
