1/* 2 * Copyright (c) 2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include "rdaspen-defs.dtsi" 11 12/ { 13 model = "RD-Aspen"; 14 compatible = "arm,rdaspen"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { 20 stdout-path = &soc_serial0; 21 }; 22 23 cpus { 24 #address-cells = <2>; 25 #size-cells = <0>; 26 27 /* Up to 4 clusters with up to 4 CPU cores in each cluster */ 28 CPU_MAP 29 CPUS 30 }; 31 32 L3_CACHE 33 DSU_PMU 34 35 memory@80000000 { 36 device_type = "memory"; 37 38 /* Bank 0: start = 0x0000_0000_8000_0000, size = ~2 GiB (0x7F00_0000) */ 39 /* Bank 1: start = 0x0000_0200_0000_0000, size = 2 GiB (0x8000_0000) */ 40 reg = < 41 0x00000000 0x80000000 0x00000000 0x7F000000 42 0x00000200 0x00000000 0x00000000 0x80000000 43 >; 44 }; 45 46 timer { 47 compatible = "arm,armv8-timer"; 48 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 49 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 50 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 51 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 52 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 53 }; 54 55 soc_clk24mhz: clk24mhz { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <24000000>; 59 clock-output-names = "refclk24mhz"; 60 }; 61 62 reserved-memory { 63 #address-cells = <2>; 64 #size-cells = <2>; 65 ranges; 66 ras_buffer: cper@ffa00000 { 67 reg = <0x0 0xffa00000 0x0 0x00100000>; 68 no-map; 69 }; 70 }; 71 72 soc { 73 compatible = "simple-bus"; 74 #address-cells = <2>; 75 #size-cells = <2>; 76 ranges; 77 78 timer@1a810000 { 79 compatible = "arm,armv7-timer-mem"; 80 reg = <0x0 0x1a810000 0 0x10000>; 81 #address-cells = <1>; 82 #size-cells = <1>; 83 /* Map child space [0x0..0x30000) to parent @ 0x1a810000 */ 84 ranges = <0x0 0x0 0x1a810000 0x00030000>; 85 86 frame@20000 { 87 frame-number = <1>; 88 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 89 reg = <0x20000 0x10000>; 90 }; 91 }; 92 93 gic: interrupt-controller@20000000 { 94 compatible = "arm,gic-v3"; 95 reg = <0x0 0x20000000 0x0 0x10000>, /* GICD */ 96 <0x0 0x200c0000 0x0 0x400000>; /* 16 * GICR */ 97 #interrupt-cells = <3>; 98 #address-cells = <2>; 99 #size-cells = <2>; 100 ranges; 101 interrupt-controller; 102 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 103 104 its1: msi-controller@20040000 { 105 compatible = "arm,gic-v3-its"; 106 reg = <0x0 0x20040000 0x0 0x40000>; 107 msi-controller; 108 #msi-cells = <1>; 109 }; 110 its2: msi-controller@20080000 { 111 compatible = "arm,gic-v3-its"; 112 reg = <0x0 0x20080000 0x0 0x40000>; 113 msi-controller; 114 #msi-cells = <1>; 115 }; 116 }; 117 118 /* UART is fixed as 24MHz, both UARTCLK and PCLK */ 119 soc_serial0: serial@1a400000 { 120 compatible = "arm,pl011", "arm,primecell"; 121 reg = <0x0 0x1a400000 0x0 0x10000>; 122 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 123 clocks = <&soc_clk24mhz>, <&soc_clk24mhz>; 124 clock-names = "uartclk", "apb_pclk"; 125 }; 126 127 watchdog@1a420000 { 128 compatible = "arm,sbsa-gwdt"; 129 reg = <0x0 0x1a420000 0x0 0x10000>, 130 <0x0 0x1a430000 0x0 0x10000>; 131 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 132 }; 133 134 rtc@300d0000 { 135 compatible = "arm,pl031", "arm,primecell"; 136 reg = <0x0 0x300d0000 0x0 0x10000>; 137 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 138 clocks = <&soc_clk24mhz>; 139 clock-names = "apb_pclk"; 140 }; 141 142 virtio-net@30060000 { 143 compatible = "virtio,mmio"; 144 reg = <0x0 0x30060000 0x0 0x10000>; 145 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 146 }; 147 148 /* OS storage */ 149 virtio-block@30020000 { 150 compatible = "virtio,mmio"; 151 reg = <0x0 0x30020000 0x0 0x10000>; 152 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>; 153 }; 154 155 /* Distro installation media */ 156 virtio-block@30030000 { 157 compatible = "virtio,mmio"; 158 reg = <0x0 0x30030000 0x0 0x10000>; 159 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 160 }; 161 162 /* SystemReady ACS validation media */ 163 virtio-block@30040000 { 164 compatible = "virtio,mmio"; 165 reg = <0x0 0x30040000 0x0 0x10000>; 166 interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 167 }; 168 169 /* User data media */ 170 virtio-block@30050000 { 171 compatible = "virtio,mmio"; 172 reg = <0x0 0x30050000 0x0 0x10000>; 173 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 174 }; 175 176 virtio-rng@30080000 { 177 compatible = "virtio,mmio"; 178 reg = <0x0 0x30080000 0x0 0x10000>; 179 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; 180 }; 181 182 ras-ffh@ffa00000 { 183 compatible = "arm,ras-ffh"; 184 reg = <0x0 0xffa00000 0x0 0x00100000>; 185 status-block-size = <0x00010000>; 186 memory-region = <&ras_buffer>; 187 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 188 }; 189 }; 190 191 psci { 192 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 193 method = "smc"; 194 cpu_suspend = <0xc4000001>; 195 cpu_off = <0x84000002>; 196 cpu_on = <0xc4000003>; 197 }; 198 199}; 200