1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <arch.h> 11 #include <plat/common/common_def.h> 12 13 #include <arch_def.h> 14 15 #define PLAT_PRIMARY_CPU (0x0) 16 17 #define MT_GIC_BASE (0x0C400000) 18 #define MCUCFG_BASE (0x0C000000) 19 #define MCUCFG_REG_SIZE (0x50000) 20 #define IO_PHYS (0x10000000) 21 22 #define MT_UTILITYBUS_BASE (0x0C800000) 23 #define MT_UTILITYBUS_SIZE (0x800000) 24 25 /* Aggregate of all devices for MMU mapping */ 26 #define MTK_DEV_RNG1_BASE (IO_PHYS) 27 #define MTK_DEV_RNG1_SIZE (0x10000000) 28 29 #define TOPCKGEN_BASE (IO_PHYS) 30 31 /******************************************************************************* 32 * AUDIO related constants 33 ******************************************************************************/ 34 #define AUDIO_BASE (IO_PHYS + 0x0a110000) 35 36 /******************************************************************************* 37 * APUSYS related constants 38 ******************************************************************************/ 39 #define APUSYS_BASE (IO_PHYS + 0x09000000) 40 #define APU_MD32_SYSCTRL (IO_PHYS + 0x09001000) 41 #define APU_MD32_WDT (IO_PHYS + 0x09002000) 42 #define APU_LOGTOP (IO_PHYS + 0x09024000) 43 #define APUSYS_CTRL_DAPC_RCX_BASE (IO_PHYS + 0x09030000) 44 #define APU_REVISER (IO_PHYS + 0x0903C000) 45 #define APU_RCX_UPRV_TCU (IO_PHYS + 0x09060000) 46 #define APU_RCX_EXTM_TCU (IO_PHYS + 0x09061000) 47 #define APU_CMU_TOP (IO_PHYS + 0x09067000) 48 #define APUSYS_CE_BASE (IO_PHYS + 0x090B0000) 49 #define APU_ARE_REG_BASE (IO_PHYS + 0x090B0000) 50 #define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090E0000) 51 #define APU_AO_CTRL (IO_PHYS + 0x090F2000) 52 #define APU_SEC_CON (IO_PHYS + 0x090F5000) 53 #define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000) 54 55 #define APU_MBOX0 (0x4C200000) 56 #define APU_MD32_TCM (0x4D000000) 57 58 #define APU_MD32_TCM_SZ (0x50000) 59 #define APU_MBOX0_SZ (0x100000) 60 #define APU_INFRA_BASE (0x1002C000) 61 #define APU_INFRA_SZ (0x1000) 62 63 #define APU_RESERVE_MEMORY (0x95000000) 64 #define APU_SEC_INFO_OFFSET (0x100000) 65 #define APU_RESERVE_SIZE (0x1400000) 66 #define APUSYS_CE_MEM_BASE (0x190A4400) 67 #define APUSYS_CE_MEM_SIZE (0x3000) 68 69 /******************************************************************************* 70 * SPM related constants 71 ******************************************************************************/ 72 #define SPM_BASE (IO_PHYS + 0x0C004000) 73 #define SPM_REG_SIZE (0x1000) 74 #define SPM_SRAM_BASE (IO_PHYS + 0x0C00C000) 75 #define SPM_SRAM_REG_SIZE (0x1000) 76 #define SPM_PBUS_BASE (IO_PHYS + 0x0C00D000) 77 #define SPM_PBUS_REG_SIZE (0x1000) 78 79 #ifdef SPM_BASE 80 #define SPM_EXT_INT_WAKEUP_REQ (SPM_BASE + 0x210) 81 #define SPM_EXT_INT_WAKEUP_REQ_SET (SPM_BASE + 0x214) 82 #define SPM_EXT_INT_WAKEUP_REQ_CLR (SPM_BASE + 0x218) 83 #define SPM_CPU_BUCK_ISO_CON (SPM_BASE + 0xEF8) 84 #define SPM_CPU_BUCK_ISO_DEFAUT (0x0) 85 #define SPM_AUDIO_PWR_CON (SPM_BASE + 0xE4C) 86 #endif 87 88 /******************************************************************************* 89 * GPIO related constants 90 ******************************************************************************/ 91 #define GPIO_BASE (IO_PHYS + 0x0002D000) 92 #define RGU_BASE (IO_PHYS + 0x0C010000) 93 #define DRM_BASE (IO_PHYS + 0x0000D000) 94 #define IOCFG_RT_BASE (IO_PHYS + 0x02000000) 95 #define IOCFG_RM1_BASE (IO_PHYS + 0x02020000) 96 #define IOCFG_RM2_BASE (IO_PHYS + 0x02040000) 97 #define IOCFG_RB_BASE (IO_PHYS + 0x02060000) 98 #define IOCFG_BM1_BASE (IO_PHYS + 0x02820000) 99 #define IOCFG_BM2_BASE (IO_PHYS + 0x02840000) 100 #define IOCFG_BM3_BASE (IO_PHYS + 0x02860000) 101 #define IOCFG_LT_BASE (IO_PHYS + 0x03000000) 102 #define IOCFG_LM1_BASE (IO_PHYS + 0x03020000) 103 #define IOCFG_LM2_BASE (IO_PHYS + 0x03040000) 104 #define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000) 105 #define IOCFG_LB2_BASE (IO_PHYS + 0x03110000) 106 #define IOCFG_TM1_BASE (IO_PHYS + 0x03800000) 107 #define IOCFG_TM2_BASE (IO_PHYS + 0x03820000) 108 #define IOCFG_TM3_BASE (IO_PHYS + 0x03860000) 109 110 /******************************************************************************* 111 * UART related constants 112 ******************************************************************************/ 113 #define UART0_BASE (IO_PHYS + 0x06000000) 114 #define UART_BAUDRATE (115200) 115 116 /******************************************************************************* 117 * PMIF address 118 ******************************************************************************/ 119 #define PMIF_SPMI_M_BASE (IO_PHYS + 0x0C01A000) 120 #define PMIF_SPMI_P_BASE (IO_PHYS + 0x0C018000) 121 #define PMIF_SPMI_SIZE 0x1000 122 123 /******************************************************************************* 124 * SPMI address 125 ******************************************************************************/ 126 #define SPMI_MST_M_BASE (IO_PHYS + 0x0C01C000) 127 #define SPMI_MST_P_BASE (IO_PHYS + 0x0C01C800) 128 #define SPMI_MST_SIZE 0x1000 129 130 /******************************************************************************* 131 * Infra IOMMU related constants 132 ******************************************************************************/ 133 #define INFRACFG_AO_BASE (IO_PHYS + 0x00001000) 134 #define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000) 135 #define PERICFG_AO_BASE (IO_PHYS + 0x06630000) 136 #define PERICFG_AO_REG_SIZE (0x1000) 137 138 /******************************************************************************* 139 * GIC-600 & interrupt handling related constants 140 ******************************************************************************/ 141 /* Base MTK_platform compatible GIC memory map */ 142 #define BASE_GICD_BASE (MT_GIC_BASE) 143 #define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000) 144 #define MTK_GIC_REG_SIZE 0x400000 145 #define SGI_MASK 0xffff 146 #define DEV_IRQ_ID 982 147 148 #define PLATFORM_G1S_PROPS(grp) \ 149 INTR_PROP_DESC(DEV_IRQ_ID, GIC_HIGHEST_SEC_PRIORITY, grp, \ 150 GIC_INTR_CFG_LEVEL) 151 152 /******************************************************************************* 153 * CIRQ related constants 154 ******************************************************************************/ 155 #define SYS_CIRQ_BASE (IO_PHYS + 0x1CB000) 156 #define MD_WDT_IRQ_BIT_ID (397) 157 #define CIRQ_REG_NUM (26) 158 #define CIRQ_SPI_START (128) 159 #define CIRQ_IRQ_NUM (831) 160 161 /******************************************************************************* 162 * MM IOMMU & SMI related constants 163 ******************************************************************************/ 164 #define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000) 165 #define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000) 166 #define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000) 167 #define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000) 168 #define SMI_LARB_4_BASE (IO_PHYS + 0x04013000) 169 #define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000) 170 #define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000) 171 #define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000) 172 #define SMI_LARB_9_BASE (IO_PHYS + 0x05001000) 173 #define SMI_LARB_10_BASE (IO_PHYS + 0x05120000) 174 #define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000) 175 #define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000) 176 #define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000) 177 #define SMI_LARB_12_BASE (IO_PHYS + 0x05340000) 178 #define SMI_LARB_13_BASE (IO_PHYS + 0x06001000) 179 #define SMI_LARB_14_BASE (IO_PHYS + 0x06002000) 180 #define SMI_LARB_15_BASE (IO_PHYS + 0x05140000) 181 #define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000) 182 #define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000) 183 #define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000) 184 #define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000) 185 #define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000) 186 #define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000) 187 #define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000) 188 #define SMI_LARB_27_BASE (IO_PHYS + 0x07201000) 189 #define SMI_LARB_28_BASE (IO_PHYS + 0x00000000) 190 #define SMI_LARB_REG_RNG_SIZE (0x1000) 191 192 /******************************************************************************* 193 * APMIXEDSYS related constants 194 ******************************************************************************/ 195 #define APMIXEDSYS (IO_PHYS + 0x0000C000) 196 197 /******************************************************************************* 198 * VPPSYS related constants 199 ******************************************************************************/ 200 #define VPPSYS0_BASE (IO_PHYS + 0x04000000) 201 #define VPPSYS1_BASE (IO_PHYS + 0x04f00000) 202 203 /******************************************************************************* 204 * VDOSYS related constants 205 ******************************************************************************/ 206 #define VDOSYS0_BASE (IO_PHYS + 0x0C01D000) 207 #define VDOSYS1_BASE (IO_PHYS + 0x0C100000) 208 209 /******************************************************************************* 210 * DP related constants 211 ******************************************************************************/ 212 #define EDP_SEC_BASE (IO_PHYS + 0x2EC54000) 213 #define DP_SEC_BASE (IO_PHYS + 0x2EC14000) 214 #define EDP_SEC_SIZE (0x1000) 215 #define DP_SEC_SIZE (0x1000) 216 217 /******************************************************************************* 218 * EMI MPU related constants 219 *******************************************************************************/ 220 #define EMI_MPU_BASE (IO_PHYS + 0x00428000) 221 #define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000) 222 #define EMI_SLB_BASE (IO_PHYS + 0x0042e000) 223 #define SUB_EMI_SLB_BASE (IO_PHYS + 0x0052e000) 224 #define CHN0_EMI_APB_BASE (IO_PHYS + 0x00201000) 225 #define CHN1_EMI_APB_BASE (IO_PHYS + 0x00205000) 226 #define CHN2_EMI_APB_BASE (IO_PHYS + 0x00209000) 227 #define CHN3_EMI_APB_BASE (IO_PHYS + 0x0020D000) 228 #define EMI_APB_BASE (IO_PHYS + 0x00429000) 229 #define INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00425000) 230 #define NEMI_SMPU_BASE (IO_PHYS + 0x0042f000) 231 #define SEMI_SMPU_BASE (IO_PHYS + 0x0052f000) 232 #define SUB_EMI_APB_BASE (IO_PHYS + 0x00529000) 233 #define SUB_INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00525000) 234 #define SUB_INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00504000) 235 #define EMI_MPU_ALIGN_BITS 12 236 237 /******************************************************************************* 238 * System counter frequency related constants 239 ******************************************************************************/ 240 #define SYS_COUNTER_FREQ_IN_HZ (13000000) 241 #define SYS_COUNTER_FREQ_IN_MHZ (13) 242 243 /******************************************************************************* 244 * Generic platform constants 245 ******************************************************************************/ 246 #define PLATFORM_STACK_SIZE (0x800) 247 #define SOC_CHIP_ID U(0x8196) 248 249 /******************************************************************************* 250 * Platform memory map related constants 251 ******************************************************************************/ 252 #define TZRAM_BASE (0x94600000) 253 #define TZRAM_SIZE (0x00200000) 254 255 /******************************************************************************* 256 * BL31 specific defines. 257 ******************************************************************************/ 258 /* 259 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 260 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 261 * little space for growth. 262 */ 263 #define BL31_BASE (TZRAM_BASE + 0x1000) 264 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 265 266 /******************************************************************************* 267 * Platform specific page table and MMU setup constants 268 ******************************************************************************/ 269 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39) 270 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39) 271 #define MAX_XLAT_TABLES (128) 272 #define MAX_MMAP_REGIONS (512) 273 274 /******************************************************************************* 275 * CPU_EB TCM handling related constants 276 ******************************************************************************/ 277 #define CPU_EB_TCM_BASE 0x0C2CF000 278 #define CPU_EB_TCM_SIZE 0x1000 279 #define CPU_EB_TCM_CNT_BASE 0x0C2CC000 280 281 /******************************************************************************* 282 * CPU PM definitions 283 ******************************************************************************/ 284 #define PLAT_CPU_PM_B_BUCK_ISO_ID (6) 285 #define PLAT_CPU_PM_ILDO_ID (6) 286 287 /******************************************************************************* 288 * SYSTIMER related definitions 289 ******************************************************************************/ 290 #define SYSTIMER_BASE (0x1C400000) 291 292 /******************************************************************************* 293 * CKSYS related constants 294 ******************************************************************************/ 295 #define CKSYS_BASE (IO_PHYS) 296 297 /******************************************************************************* 298 * VLP AO related constants 299 ******************************************************************************/ 300 #define VLPCFG_BUS_BASE (IO_PHYS + 0x0C001000) 301 #define VLPCFG_BUS_SIZE (0x1000) 302 #define VLP_AO_DEVAPC_APB_BASE (IO_PHYS + 0x0C550000) 303 #define VLP_AO_DEVAPC_APB_SIZE (0x1000) 304 305 /******************************************************************************* 306 * SCP registers 307 ******************************************************************************/ 308 #define SCP_CLK_CTRL_BASE (IO_PHYS + 0x0CF21000) 309 #define SCP_CLK_CTRL_SIZE (0x1000) 310 311 #define SCP_CFGREG_BASE (IO_PHYS + 0x0CF24000) 312 #define SCP_CFGREG_SIZE (0x1000) 313 314 /******************************************************************************* 315 * VLP CKSYS related constants 316 ******************************************************************************/ 317 #define VLP_CKSYS_BASE (IO_PHYS + 0x0C016000) 318 #define VLP_CKSYS_SIZE 0x1000 319 320 /******************************************************************************* 321 * PERI related constants use PERI secure address to garuantee access 322 ******************************************************************************/ 323 #define PERICFG_AO_SIZE 0x1000 324 #define PERI_CG0_STA (PERICFG_AO_BASE + 0x10) 325 #define PERI_CLK_CON (PERICFG_AO_BASE + 0x20) 326 #define PERI_CG1_CLR (PERICFG_AO_BASE + 0x30) 327 328 /****************************************************************************** 329 * LPM syssram related constants 330 *****************************************************************************/ 331 #define MTK_LPM_SRAM_BASE 0x11B000 332 #define MTK_LPM_SRAM_MAP_SIZE 0x1000 333 334 /******************************************************************************* 335 * SSPM_MBOX_3 related constants 336 ******************************************************************************/ 337 #define SSPM_MBOX_3_BASE (IO_PHYS + 0x0C380000) 338 #define SSPM_MBOX_3_SIZE 0x1000 339 340 /******************************************************************************* 341 * SSPM related constants 342 ******************************************************************************/ 343 #define SSPM_REG_OFFSET (0x40000) 344 #define SSPM_CFGREG_BASE (IO_PHYS + 0x0C300000 + SSPM_REG_OFFSET) 345 #define SSPM_CFGREG_SIZE (0x1000) 346 347 /******************************************************************************* 348 * MMinfra related constants 349 ******************************************************************************/ 350 #define MTK_VLP_TRACER_MON_BASE (IO_PHYS + 0x0c000000) 351 #define MTK_VLP_TRACER_MON_REG_SIZE (0x1000) 352 353 #endif /* PLATFORM_DEF_H */ 354