1 /* 2 * Copyright (c) 2020-2026, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <libfdt.h> 10 #include <tc_plat.h> 11 12 #include <arch_helpers.h> 13 #include <common/debug.h> 14 #include <drivers/arm/css/css_mhu_doorbell.h> 15 #include <drivers/arm/css/scmi.h> 16 #include <drivers/arm/dsu.h> 17 #include <drivers/arm/sbsa.h> 18 #include <drivers/arm/sfcp.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <plat/arm/common/plat_arm.h> 22 23 #ifdef PLATFORM_TEST_TFM_TESTSUITE 24 #include <psa/crypto_platform.h> 25 #include <psa/crypto_types.h> 26 #include <psa/crypto_values.h> 27 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 28 #include <psa/error.h> 29 30 #include <plat/common/platform.h> 31 32 #ifdef PLATFORM_TEST_TFM_TESTSUITE 33 /* 34 * We pretend using an external RNG (through MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG 35 * mbedTLS config option) so we need to provide an implementation of 36 * mbedtls_psa_external_get_random(). Provide a fake one, since we do not 37 * actually use any of external RNG and this function is only needed during 38 * the execution of TF-M testsuite during exporting the public part of the 39 * delegated attestation key. 40 */ 41 psa_status_t mbedtls_psa_external_get_random( 42 mbedtls_psa_external_random_context_t *context, 43 uint8_t *output, size_t output_size, 44 size_t *output_length) 45 { 46 for (size_t i = 0U; i < output_size; i++) { 47 output[i] = (uint8_t)(read_cntpct_el0() & 0xFFU); 48 } 49 50 *output_length = output_size; 51 52 return PSA_SUCCESS; 53 } 54 #endif /* PLATFORM_TEST_TFM_TESTSUITE */ 55 56 static scmi_channel_plat_info_t tc_scmi_plat_info = { 57 .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, 58 .db_reg_addr = PLAT_CSS_MHU_BASE + MHU_V3_SENDER_REG_SET(0), 59 .db_preserve_mask = 0xfffffffe, 60 .db_modify_mask = 0x1, 61 .ring_doorbell = &mhu_ring_doorbell, 62 }; 63 64 /* the bottom 3 AMU group 1 counters */ 65 #define MPMM_GEARS ((1 << 0) | (1 << 1) | (1 << 2)) 66 67 uint16_t plat_amu_aux_enables[PLATFORM_CORE_COUNT] = { 68 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 69 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 70 #if PLATFORM_CORE_COUNT == 14 71 MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, MPMM_GEARS, 72 MPMM_GEARS, MPMM_GEARS 73 #endif 74 }; 75 76 const dsu_driver_data_t plat_dsu_data = { 77 .clusterpwrdwn_pwrdn = false, 78 .clusterpwrdwn_memret = false, 79 .clusterpwrctlr_cachepwr = CLUSTERPWRCTLR_CACHEPWR_RESET, 80 .clusterpwrctlr_funcret = CLUSTERPWRCTLR_FUNCRET_RESET 81 }; 82 83 static void enable_ns_mcn_pmu(void) 84 { 85 /* 86 * Enable non-secure access to MCN PMU registers 87 */ 88 for (int i = 0; i < MCN_INSTANCES; i++) { 89 uintptr_t mcn_scr = MCN_MICROARCH_BASE_ADDR(i) + 90 MCN_SCR_OFFSET; 91 mmio_setbits_32(mcn_scr, 1 << MCN_SCR_PMU_BIT); 92 } 93 } 94 95 #if TARGET_PLATFORM == 3 96 static void set_mcn_slc_alloc_mode(void) 97 { 98 /* 99 * SLC WRALLOCMODE and RDALLOCMODE are configured by default to 100 * 0b01 (always alloc), configure both to 0b10 (use bus signal 101 * attribute from interface). 102 */ 103 for (int i = 0; i < MCN_INSTANCES; i++) { 104 uintptr_t slccfg_ctl_ns = MCN_MPAM_NS_BASE_ADDR(i) + 105 MPAM_SLCCFG_CTL_OFFSET; 106 uintptr_t slccfg_ctl_s = MCN_MPAM_S_BASE_ADDR(i) + 107 MPAM_SLCCFG_CTL_OFFSET; 108 109 mmio_clrsetbits_32(slccfg_ctl_ns, 110 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 111 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 112 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 113 mmio_clrsetbits_32(slccfg_ctl_s, 114 (SLC_RDALLOCMODE_MASK | SLC_WRALLOCMODE_MASK), 115 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_RDALLOCMODE_SHIFT) | 116 (SLC_ALLOC_BUS_SIGNAL_ATTR << SLC_WRALLOCMODE_SHIFT)); 117 } 118 } 119 #endif 120 121 #if defined(TARGET_FLAVOUR_FPGA) && TARGET_PLATFORM == 4 122 /* 123 * Configure MTU tag registers to initialize the MTE carveout. 124 * This isn't required for FVP builds, as FVPs do not emulate 125 * MTE in such a way that it requires a physical careveout. 126 */ 127 static void set_mcn_mtu_tag_addr(void) 128 { 129 for (int i = 0; i < MCN_INSTANCES; i++) { 130 uintptr_t mtu_tag_addr_base_lo = MCN_MTU_BASE_ADDR(i) + 131 MTU_TAG_ADDR_BASE_OFFSET; 132 uintptr_t mtu_tag_addr_base_hi = MCN_MTU_BASE_ADDR(i) + 133 MTU_TAG_ADDR_BASE_OFFSET + 4; 134 135 /* Enter MCN config state. */ 136 mmio_write_32(MCN_CRP_BASE_ADDR(i) + 137 MCN_CRP_ARCH_STATE_REQ_OFFSET, MCN_CONFIG_STATE); 138 while (mmio_read_32(MCN_CRP_BASE_ADDR(i) + 139 MCN_CRP_ARCH_STATE_CUR_OFFSET) != MCN_CONFIG_STATE) 140 ; 141 142 dsb(); 143 isb(); 144 145 mmio_write_32(mtu_tag_addr_base_lo, 146 (uint32_t)(TC_MTU_TAG_ADDR_BASE & 0xFFFFFFFF)); 147 mmio_write_32(mtu_tag_addr_base_hi, 148 (uint32_t)((TC_MTU_TAG_ADDR_BASE >> 32) & 0xFFFFFFFF)); 149 150 dsb(); 151 isb(); 152 153 /* Return to MCN run state. */ 154 mmio_write_32(MCN_CRP_BASE_ADDR(i) + 155 MCN_CRP_ARCH_STATE_REQ_OFFSET, MCN_RUN_STATE); 156 while (mmio_read_32(MCN_CRP_BASE_ADDR(i) + 157 MCN_CRP_ARCH_STATE_CUR_OFFSET) != MCN_RUN_STATE) 158 ; 159 } 160 } 161 #endif 162 163 void bl31_platform_setup(void) 164 { 165 enum sfcp_error_t sfcp_err; 166 167 tc_bl31_common_platform_setup(); 168 enable_ns_mcn_pmu(); 169 #if TARGET_PLATFORM == 3 170 set_mcn_slc_alloc_mode(); 171 plat_arm_ni_setup(NCI_BASE_ADDR); 172 #endif 173 174 /* Initialize SFCP for communications between AP and RSE */ 175 sfcp_err = sfcp_init(); 176 if (sfcp_err != SFCP_ERROR_SUCCESS) { 177 ERROR("Unable to initialize SFCP: %d\n", sfcp_err); 178 plat_panic_handler(); 179 } 180 #if defined(TARGET_FLAVOUR_FPGA) && TARGET_PLATFORM == 4 181 set_mcn_mtu_tag_addr(); 182 #endif 183 } 184 185 scmi_channel_plat_info_t *plat_css_get_scmi_info(unsigned int channel_id __unused) 186 { 187 188 return &tc_scmi_plat_info; 189 190 } 191 192 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 193 u_register_t arg2, u_register_t arg3) 194 { 195 /* Initialize the console to provide early debug support */ 196 arm_console_boot_init(); 197 198 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); 199 200 #if !TRANSFER_LIST 201 /* Fill the properties struct with the info from the config dtb */ 202 fconf_populate("FW_CONFIG", arg1); 203 #endif 204 } 205 206 #ifdef PLATFORM_TESTS 207 static __dead2 void tc_run_platform_tests(void) 208 { 209 int tests_failed; 210 211 printf("\nStarting platform tests...\n"); 212 213 #ifdef PLATFORM_TEST_NV_COUNTERS 214 tests_failed = nv_counter_test(); 215 #elif PLATFORM_TEST_TFM_TESTSUITE 216 tests_failed = run_platform_tests(); 217 #endif 218 219 printf("Platform tests %s.\n", 220 (tests_failed != 0) ? "failed" : "succeeded"); 221 222 /* Suspend booting, no matter the tests outcome. */ 223 printf("Suspend booting...\n"); 224 plat_error_handler(-1); 225 } 226 #endif 227 228 void tc_bl31_common_platform_setup(void) 229 { 230 arm_bl31_platform_setup(); 231 232 gic_set_gicr_frames(arm_gicr_base_addrs); 233 234 #ifdef PLATFORM_TESTS 235 tc_run_platform_tests(); 236 #endif 237 } 238 239 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 240 { 241 return css_scmi_override_pm_ops(ops); 242 } 243 244 void __init bl31_plat_arch_setup(void) 245 { 246 arm_bl31_plat_arch_setup(); 247 248 /* 249 * When TRANSFER_LIST is enabled, HW_CONFIG is included in Transfer List 250 * as an entry with the tag TL_TAG_FDT. In this case, the configuration 251 * is already available, so the fconf_populate mechanism is not needed. 252 * The code block below is only required when TRANSFER_LIST is not used. 253 */ 254 #if !TRANSFER_LIST 255 /* HW_CONFIG was also loaded by BL2 */ 256 const struct dyn_cfg_dtb_info_t *hw_config_info; 257 258 hw_config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, HW_CONFIG_ID); 259 assert(hw_config_info != NULL); 260 261 fconf_populate("HW_CONFIG", hw_config_info->config_addr); 262 #endif 263 } 264 265 #if defined(SPD_spmd) && (SPMC_AT_EL3 == 0) 266 void tc_bl31_plat_runtime_setup(void) 267 { 268 /* Start secure watchdog timer. */ 269 plat_arm_secure_wdt_start(); 270 271 arm_bl31_plat_runtime_setup(); 272 } 273 274 void bl31_plat_runtime_setup(void) 275 { 276 tc_bl31_plat_runtime_setup(); 277 } 278 279 /* 280 * Platform handler for Group0 secure interrupt. 281 */ 282 int plat_spmd_handle_group0_interrupt(uint32_t intid) 283 { 284 /* Trusted Watchdog timer is the only source of Group0 interrupt now. */ 285 if (intid == SBSA_SECURE_WDOG_INTID) { 286 /* Refresh the timer. */ 287 plat_arm_secure_wdt_refresh(); 288 289 return 0; 290 } 291 292 return -1; 293 } 294 #endif /*defined(SPD_spmd) && (SPMC_AT_EL3 == 0)*/ 295