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Searched refs:REG_TOP_VP9 (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/hvd_v3/
H A DhalHVD_EX.c5997 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6001 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6008 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6013 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6018 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6023 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6028 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6033 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6038 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6043 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_EVDPLL, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DhalHVD_EX.c6350 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6354 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6361 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6366 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6371 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6376 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6381 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6386 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6391 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6396 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_EVDPLL, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DhalHVD_EX.c6629 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6633 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6640 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6645 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6650 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6655 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6660 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6665 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6670 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6675 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h535 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DhalHVD_EX.c6251 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6255 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6262 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6267 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6272 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6277 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6282 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6287 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6292 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6297 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h518 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DhalHVD_EX.c6251 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6255 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6262 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6267 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6272 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6277 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6282 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6287 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6292 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6297 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h518 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DhalHVD_EX.c6460 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6464 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6471 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6476 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6481 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6486 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6491 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6496 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6501 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6506 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h547 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c6229 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6233 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6240 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6245 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6250 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6255 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6260 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6265 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6270 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6275 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h519 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c6433 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6437 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6444 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6449 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6454 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6459 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6464 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6469 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6474 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6479 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h520 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DhalHVD_EX.c7730 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
7734 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
7741 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7746 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7751 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7756 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7761 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7766 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7771 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7776 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c6706 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6710 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6717 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6722 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6727 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6732 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6737 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6742 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6747 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6752 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h519 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DhalHVD_EX.c7517 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
7521 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
7528 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7533 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7538 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7543 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7548 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7553 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7558 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7563 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DhalHVD_EX.c6686 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6690 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6697 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6702 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6707 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6712 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6717 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6722 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6727 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6732 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h535 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DhalHVD_EX.c7575 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
7579 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
7586 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7591 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7596 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7601 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7606 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7611 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7616 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
7621 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c6648 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6652 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6659 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6664 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6669 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6674 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6679 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6684 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6689 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6694 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h519 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) macro
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DhalHVD_EX.c6785 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6789 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS); in HAL_VP9_EX_PowerCtrl()
6796 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6801 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6806 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6811 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6816 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6821 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6826 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
6831 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK); in HAL_VP9_EX_PowerCtrl()
[all …]
H A DregHVD_EX.h498 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) macro

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