1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
122 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
123
124 //-------------------------------------------------------------------------------------------------
125 // Local Defines
126 //-------------------------------------------------------------------------------------------------
127 #define RV_VLC_TABLE_SIZE 0x20000
128 /* Add for Mobile Platform by Ted Sun */
129 //#define HVD_DISPQ_PREFETCH_COUNT 2
130
131 #define VPU_QMEM_BASE 0x20000000UL
132
133 //max support pixel(by chip capacity)
134 #define HVD_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
135 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
136 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
137
138 #if 0
139 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
140 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
141 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
142 static MS_U16 _u16DispQPtr = 0;
143 #endif
144
145 #define IS_TASK_ALIVE(id) ((id) != -1)
146 #ifndef UNUSED
147 #define UNUSED(x) (void)(x)
148 #endif
149
150
151 //---------------------------------- Mutex settings -----------------------------------------
152 #if HAL_HVD_ENABLE_MUTEX_PROTECT
153 #define _HAL_HVD_MutexCreate() \
154 do \
155 { \
156 if (s32HVDMutexID < 0) \
157 { \
158 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
159 } \
160 } while (0)
161
162 #define _HAL_HVD_MutexDelete() \
163 do \
164 { \
165 if (s32HVDMutexID >= 0) \
166 { \
167 OSAL_HVD_MutexDelete(s32HVDMutexID); \
168 s32HVDMutexID = -1; \
169 } \
170 } while (0)
171
172 #define _HAL_HVD_Entry() \
173 do \
174 { \
175 if (s32HVDMutexID >= 0) \
176 { \
177 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
178 { \
179 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
180 } \
181 } \
182 } while (0)
183
184 #define _HAL_HVD_Return(_ret_) \
185 do \
186 { \
187 if (s32HVDMutexID >= 0) \
188 { \
189 OSAL_HVD_MutexRelease(s32HVDMutexID); \
190 } \
191 return _ret_; \
192 } while(0)
193
194 #define _HAL_HVD_Release() \
195 do \
196 { \
197 if (s32HVDMutexID >= 0) \
198 { \
199 OSAL_HVD_MutexRelease(s32HVDMutexID); \
200 } \
201 } while (0)
202 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
203
204 #define _HAL_HVD_MutexCreate()
205 #define _HAL_HVD_MutexDelete()
206 #define _HAL_HVD_Entry()
207 #define _HAL_HVD_Return(_ret) {return _ret;}
208 #define _HAL_HVD_Release()
209
210 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
211
212 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
213 #define IS_TASK_ALIVE(id) ((id) != -1)
214 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
215
216 //------------------------------ MIU SETTINGS ----------------------------------
217 #define _MaskMiuReq_MVD_RW_0( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
218 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
219 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
220 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
221 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
222 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
223
224 #define _MaskMiu1Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
225 #define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
226 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
227 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
228 #define _MaskMiu1Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(3))
229 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(0))
230
231 #define _MaskMiu2Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU2_REG_RQ2_MASK, m, BIT(4))
232 #define _MaskMiu2Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(6))
233 #define _MaskMiu2Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(4))
234 #define _MaskMiu2Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(2))
235 #define _MaskMiu2Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(3))
236 #define _MaskMiu2Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(0))
237
238
239 #define HVD_MVD_RW_0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == 0))
240 #define HVD_MVD_RW_1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == 0))
241 #define HVD_MVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == 0))
242 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == 0))
243 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == 0))
244 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == 0))
245
246 #define HVD_MVD_RW_0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == BIT(4)) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == 0))
247 #define HVD_MVD_RW_1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == 0))
248 #define HVD_MVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12)) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == 0))
249 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == 0))
250 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == 0))
251 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == 0))
252
253 #define HVD_MVD_RW_0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == BIT(4)))
254 #define HVD_MVD_RW_1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == BIT(6)))
255 #define HVD_MVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == BIT(12)))
256 #define HVD_HVD_RW_MIF0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == BIT(2)))
257 #define HVD_HVD_RW_MIF1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == BIT(3)))
258 #define HVD_HVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == BIT(0)))
259
260
261 #if SUPPORT_EVD
262 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
263 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
264 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
265 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
266 #define _MaskMiu2Req_EVD_RW( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
267 #define _MaskMiu2Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
268
269
270
271
272 #define HVD_EVD_RW_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
273 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
274 #define HVD_EVD_RW_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
275 #define HVD_EVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
276 #define HVD_EVD_RW_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == BIT(7)))
277 #define HVD_EVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == BIT(7)))
278 #endif
279
280 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
281 do \
282 { \
283 if (HVD_##miu_clients##_ON_MIU0 == 1) \
284 { \
285 _MaskMiuReq_##miu_clients(mask); \
286 } \
287 else \
288 { \
289 if (HVD_##miu_clients##_ON_MIU1 == 1) \
290 { \
291 _MaskMiu1Req_##miu_clients(mask); \
292 } \
293 else if (HVD_##miu_clients##_ON_MIU2 == 1) \
294 { \
295 _MaskMiu2Req_##miu_clients(mask); \
296 } \
297 } \
298 } while (0)
299
300 // check RM is supported or not
301 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
302 #ifdef VDEC3
303 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
304 #else
305 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
306 #endif
307
308 #define DIFF(a, b) (a > b ? (a-b) : (b-a)) // abs diff
309
310 //-------------------------------------------------------------------------------------------------
311 // Local Structures
312 //-------------------------------------------------------------------------------------------------
313
314 //-------------------------------------------------------------------------------------------------
315 // Local Functions Prototype
316 //-------------------------------------------------------------------------------------------------
317 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
318 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
319 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
320 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
321 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
322 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
323 static MS_U32 _HVD_EX_GetPC(void);
324 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
325 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
326 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
327 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
328 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
329 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
330 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
331 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
332 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
333 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
334 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
335 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
336 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
337 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
338 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
339 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
340 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
341 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed, MS_BOOL *isAVCUsed);
342 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable);
343 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable);
344 #if SUPPORT_EVD
345 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable);
346 #endif
347 #if SUPPORT_G2VP9 && defined(VDEC3)
348 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
349 #endif
350 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
351 #if SUPPORT_G2VP9 && defined(VDEC3)
352 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
353 #endif
354
355 //-------------------------------------------------------------------------------------------------
356 // Global Variables
357 //-------------------------------------------------------------------------------------------------
358 #if defined (__aeon__)
359 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
360 #else
361 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
362 #endif
363 #if HAL_HVD_ENABLE_MUTEX_PROTECT
364 MS_S32 s32HVDMutexID = -1;
365 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
366 #endif
367
368
369 #define HVD_EX_STACK_SIZE 4096
370 //-------------------------------------------------------------------------------------------------
371 // Local Variables
372 //-------------------------------------------------------------------------------------------------
373 typedef struct
374 {
375
376 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
377 MS_U8 g_hvd_nal_fill_pair[2][8];
378 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
379 MS_U16 _u16DispQPtr;
380 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
381
382 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
383 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
384 MS_U32 u32VPUClockType;
385 MS_U32 u32HVDClockType;//160
386 #if SUPPORT_EVD
387 MS_U32 u32EVDClockType;
388 #endif
389 #if SUPPORT_G2VP9 && defined(VDEC3)
390 MS_U32 u32VP9ClockType;
391 #endif
392 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
393
394 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
395 MS_BOOL g_RstFlag;
396 MS_U64 u64pts_real;
397 MS_PHY u32VP8BBUWptr;
398 MS_PHY u32EVDBBUWptr;
399 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
400 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
401 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
402 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
403 //pre_set
404 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
405 } HVD_Hal_CTX;
406
407 HVD_Hal_CTX* pHVDHalContext = NULL;
408 HVD_Hal_CTX gHVDHalContext;
409 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
410
411 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
412 {
413 {FALSE},
414 {FALSE},
415 {FALSE},
416 #ifdef VDEC3
417 {FALSE},
418 #endif
419 };
420
421 //-------------------------------------------------------------------------------------------------
422 // Debug Functions
423 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)424 void HVD_EX_SetRstFlag(MS_BOOL bRst)
425 {
426 pHVDHalContext->g_RstFlag = bRst;
427 }
HVD_EX_GetRstFlag(void)428 MS_BOOL HVD_EX_GetRstFlag(void)
429 {
430 return pHVDHalContext->g_RstFlag;
431 }
432
433 //-------------------------------------------------------------------------------------------------
434 // Local Functions
435 //-------------------------------------------------------------------------------------------------
436 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)437 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
438 {
439 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
440
441 if (u32CodecType == E_HVD_INIT_HW_HEVC || u32CodecType == E_HVD_INIT_HW_HEVC_DV
442 #if SUPPORT_MSVP9
443 || u32CodecType == E_HVD_INIT_HW_VP9
444 #endif
445 )
446 return TRUE;
447
448 return FALSE;
449 }
450
_HAL_EX_BBU_VP8_InUsed(void)451 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
452 {
453 if (!pHVDHalContext)
454 return FALSE;
455
456 MS_U32 i;
457 MS_BOOL bRet = FALSE;
458
459 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
460 {
461 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
462 {
463 bRet = TRUE;
464 break;
465 }
466 }
467
468 return bRet;
469 }
470
471 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
472 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)473 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
474 {
475
476 MS_U32 ret = TRUE;
477 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
478
479 if(pCtrl == NULL || pstTaskInfo == NULL)
480 return FALSE;
481
482 pstTaskInfo->u32Id = u32Id;
483
484 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
485 {
486 case E_HVD_INIT_HW_RM:
487 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
488 break;
489 case E_HVD_INIT_HW_VP8:
490 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
491 break;
492 case E_HVD_INIT_HW_MVC:
493 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
494 break;
495 case E_HVD_INIT_HW_HEVC:
496 case E_HVD_INIT_HW_HEVC_DV:
497 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
498 break;
499 #if SUPPORT_MSVP9
500 case E_HVD_INIT_HW_VP9:
501 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
502 break;
503 #endif
504 #if SUPPORT_G2VP9
505 case E_HVD_INIT_HW_VP9:
506 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
507 break;
508 #endif
509 default:
510 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
511 break;
512 }
513
514 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
515
516 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
517 {
518 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
519 }
520 else
521 {
522 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
523 }
524
525 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
526
527 #ifdef SUPPORT_EVD
528 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
529 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
530 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
531 #endif
532 return ret;
533
534 }
535
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)536 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
537 {
538 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
539 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
540 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
541 _HAL_HVD_Entry();
542
543 if(pCtrl == NULL)
544 _HAL_HVD_Return(ret);
545
546 VPU_EX_TaskInfo taskInfo;
547 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
548
549 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
550
551 taskInfo.u8HalId = u8Idx;
552 ret = HAL_VPU_EX_GetBBUId(u32Id, &taskInfo, pCtrl->bShareBBU);
553
554 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
555 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
556
557 _HAL_HVD_Return(ret);
558 }
559
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)560 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
561 {
562 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
563 MS_BOOL ret = FALSE;
564 _HAL_HVD_Entry();
565
566 if(pCtrl == NULL)
567 _HAL_HVD_Return(ret);
568 VPU_EX_TaskInfo taskInfo;
569 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
570
571 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
572
573 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
574
575 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
576 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
577
578 _HAL_HVD_Return(ret);
579 }
580
HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId)581 MS_BOOL HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId)
582 {
583 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
584 MS_BOOL ret = FALSE;
585 _HAL_HVD_Entry();
586
587 if(pCtrl == NULL)
588 _HAL_HVD_Return(ret);
589 VPU_EX_TaskInfo taskInfo;
590 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
591
592 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
593
594 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, taskInfo.eDecType);
595
596 _HAL_HVD_Return(TRUE);
597 }
598 #endif
599
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)600 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
601 {
602 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
603 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
604 pstHVDStream->s32HvdPpTaskId = -1;
605 }
606
_HVD_EX_Context_Init_HAL(void)607 static void _HVD_EX_Context_Init_HAL(void)
608 {
609 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
610 pHVDHalContext->u32VPUClockType = 432;
611 pHVDHalContext->u32HVDClockType = 384;
612 #if SUPPORT_EVD
613 pHVDHalContext->u32EVDClockType = 480;
614 #endif
615 #if SUPPORT_G2VP9 && defined(VDEC3)
616 pHVDHalContext->u32VP9ClockType = 384;
617 #endif
618 #ifdef VDEC3
619 MS_U8 i;
620
621 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
622 {
623 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
624 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
625 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
626 }
627 #else
628 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
629 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
630 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
631 #endif
632 }
633
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)634 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
635 {
636 MS_U16 u16Ret = 0;
637 #if (HVD_ENABLE_MVC || (!VDEC3))
638 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
639 #endif
640 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
641 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
642 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
643 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
644
645 #if HVD_ENABLE_MVC
646 if(HAL_HVD_EX_CheckMVCID(u32Id))
647 {
648 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
649 }
650 #endif /// HVD_ENABLE_MVC
651
652 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
653 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
654
655 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
656 {
657 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
658 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
659 }
660 else
661 #ifdef VDEC3
662 if (0 == pCtrl->u32BBUId)
663 #else
664 if (0 == u8TaskId)
665 #endif
666 {
667 //if(pCtrl->InitParams.bColocateBBUMode)
668 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
669 u16Ret = pShm->u32ColocateBBUReadPtr;
670 else
671 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
672 }
673 else
674 {
675 //if(pCtrl->InitParams.bColocateBBUMode)
676 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
677 u16Ret = pShm->u32ColocateBBUReadPtr;
678 else
679 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
680 }
681
682 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
683 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
684
685 return u16Ret;
686 }
687
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)688 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
689 {
690 MS_U16 u16Ret = 0;
691 #if (HVD_ENABLE_MVC || (!VDEC3))
692 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
693 #endif
694 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
695 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
696 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
697 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
698
699 #if HVD_ENABLE_MVC
700 if (HAL_HVD_EX_CheckMVCID(u32Id))
701 {
702 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
703 }
704 #endif /// HVD_ENABLE_MVC
705 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
706 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
707
708 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
709 {
710 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
711 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
712 }
713 else
714 #ifdef VDEC3
715 if (0 == pDrvCtrl->u32BBUId)
716 #else
717 if (0 == u8TaskId)
718 #endif
719 {
720 //if(pDrvCtrl->InitParams.bColocateBBUMode)
721 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
722 u16Ret = pShm->u32ColocateBBUWritePtr;
723 else
724 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
725 }
726 else
727 {
728 //if(pDrvCtrl->InitParams.bColocateBBUMode)
729 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
730 u16Ret = pShm->u32ColocateBBUWritePtr;
731 else
732 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
733 }
734
735 return u16Ret;
736 }
737
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)738 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
739 {
740 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
741 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
742
743 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
744 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
745 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
746 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
747 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
748 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
749 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
750 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
751 }
752
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)753 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
754 {
755 #if (HVD_ENABLE_MVC || (!VDEC3))
756 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
757 #endif
758 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
759 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
760 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
761 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
762
763 #if HVD_ENABLE_MVC
764 if (HAL_HVD_EX_CheckMVCID(u32Id))
765 {
766 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
767 }
768 #endif /// HVD_ENABLE_MVC
769
770 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
771 {
772 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
773 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
774 }
775 else
776 #ifdef VDEC3
777 if (0 == pCtrl->u32BBUId)
778 #else
779 if (0 == u8TaskId)
780 #endif
781 {
782 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
783 //if(pCtrl->InitParams.bColocateBBUMode)
784 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
785 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
786 }
787 else
788 {
789 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
790 //if(pCtrl->InitParams.bColocateBBUMode)
791 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
792 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
793 }
794
795 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
796 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
797
798 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
799 }
800
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)801 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
802 {
803 MS_BOOL bResult = TRUE;
804 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
805 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
806
807 switch (u8MBox)
808 {
809 case E_HVD_HI_0:
810 {
811 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
812 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
813 break;
814 }
815 case E_HVD_HI_1:
816 {
817 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
818 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
819 break;
820 }
821 case E_HVD_VPU_HI_0:
822 {
823 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
824 break;
825 }
826 case E_HVD_VPU_HI_1:
827 {
828 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
829 break;
830 }
831 default:
832 {
833 bResult = FALSE;
834 break;
835 }
836 }
837
838 return bResult;
839 }
840
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)841 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
842 {
843 MS_BOOL bResult = TRUE;
844 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
845 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
846
847 switch (u8MBox)
848 {
849 case E_HVD_HI_0:
850 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
851 break;
852 case E_HVD_HI_1:
853 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
854 break;
855 case E_HVD_RISC_0:
856 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
857 break;
858 case E_HVD_RISC_1:
859 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
860 break;
861 case E_HVD_VPU_HI_0:
862 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
863 break;
864 case E_HVD_VPU_HI_1:
865 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
866 break;
867 case E_HVD_VPU_RISC_0:
868 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
869 break;
870 case E_HVD_VPU_RISC_1:
871 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
872 break;
873 default:
874 break;
875 }
876
877 return bResult;
878 }
879
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)880 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
881 {
882 MS_BOOL bResult = TRUE;
883 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
884 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
885
886 switch (u8MBox)
887 {
888 case E_HVD_HI_0:
889 {
890 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
891 break;
892 }
893 case E_HVD_HI_1:
894 {
895 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
896 break;
897 }
898 case E_HVD_RISC_0:
899 {
900 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
901 break;
902 }
903 case E_HVD_RISC_1:
904 {
905 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
906 break;
907 }
908 case E_HVD_VPU_RISC_0:
909 {
910 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
911 break;
912 }
913 case E_HVD_VPU_RISC_1:
914 {
915 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
916 break;
917 }
918 default:
919 {
920 bResult = FALSE;
921 break;
922 }
923 }
924
925 return bResult;
926 }
927
928 #if 0
929 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
930 {
931 switch (u8MBox)
932 {
933 case E_HVD_RISC_0:
934 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
935 break;
936 case E_HVD_RISC_1:
937 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
938 break;
939 case E_HVD_VPU_RISC_0:
940 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
941 break;
942 case E_HVD_VPU_RISC_1:
943 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
944 break;
945 default:
946 break;
947 }
948 }
949 #endif
950
_HVD_EX_GetPC(void)951 static MS_U32 _HVD_EX_GetPC(void)
952 {
953 MS_U32 u32PC = 0;
954 u32PC = HAL_VPU_EX_GetProgCnt();
955 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
956 return u32PC;
957 }
958
_HVD_EX_GetESWritePtr(MS_U32 u32Id)959 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
960 {
961 MS_U32 u32Data = 0;
962 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
963 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
964
965 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
966 {
967 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
968
969 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
970 {
971 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
972
973 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
974 }
975 }
976 else
977 {
978 #if HVD_ENABLE_MVC
979 MS_U8 u8ViewIdx = 0;
980 if(HAL_HVD_EX_CheckMVCID(u32Id))
981 {
982 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
983 }
984 if(u8ViewIdx != 0) /// 2nd ES ptr.
985 {
986 u32Data = pShm->u32ES2WritePtr;
987 }
988 else
989 {
990 u32Data = pShm->u32ESWritePtr;
991 }
992 #else
993 u32Data = pShm->u32ESWritePtr;
994 #endif
995 }
996
997 return u32Data;
998 }
999
1000 #define NAL_UNIT_LEN_BITS 21
1001 #define NAL_UNIT_OFT_BITS 30
1002 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
1003 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
1004 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
1005
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)1006 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
1007 {
1008 MS_U32 u32Data = 0;
1009 MS_U8 u8TaskId = 0;
1010 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1011 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1012 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1013 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1014 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
1015
1016 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1017 #if HVD_ENABLE_MVC
1018 if(HAL_HVD_EX_CheckMVCID(u32Id))
1019 {
1020 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1021 }
1022 #endif /// HVD_ENABLE_MVC
1023
1024 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
1025 {
1026 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
1027 {
1028 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1029 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
1030 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
1031 MS_U32 *u32Adr;
1032 MS_U32 u32Tmp;
1033
1034 if (u16ReadPtr == u16WritePtr)
1035 {
1036 u32Data = _HVD_EX_GetESWritePtr(u32Id);
1037 }
1038 else
1039 {
1040 if (u16ReadPtr)
1041 u16ReadPtr--;
1042 else
1043 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
1044
1045 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
1046
1047 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
1048 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
1049 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
1050 u32Data = u32Data | u32Tmp;
1051
1052 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
1053 //while(1);
1054 }
1055 goto EXIT;
1056 }
1057 // set reg_poll_nal_rptr 0
1058 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
1059 // set reg_poll_nal_rptr 1
1060 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
1061
1062 // read reg_nal_rptr_hi
1063 #ifdef VDEC3
1064 if (0 == pCtrl->u32BBUId)
1065 #else
1066 if (0 == u8TaskId)
1067 #endif
1068 {
1069 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
1070 u32Data >>= 6;
1071 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
1072 }
1073 else
1074 {
1075 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
1076 u32Data >>= 6;
1077 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
1078 }
1079
1080 u32Data <<= 3; // unit
1081
1082 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1083 {
1084 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1085
1086 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1087 {
1088 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1089 u32Data = u32ESWptr;
1090 }
1091 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1092 {
1093 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1094 u32Data = u32ESWptr;
1095 }
1096 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1097 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1098 {
1099 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1100 u32Data = u32ESWptr;
1101 }
1102 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1103 && ((u32Data - u32ESWptr) < 32)
1104 && (pCtrl->u32FlushRstPtr == 1))
1105 {
1106 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1107 u32Data = u32ESWptr;
1108 }
1109 }
1110
1111 // remove illegal pointer
1112 #if 1
1113 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1114 {
1115 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1116
1117 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1118 (u32PacketStaddr <
1119 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1120 {
1121 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1122 u32Data = pCtrl->u32LastESRptr;
1123 }
1124 }
1125 #endif
1126 }
1127 else
1128 {
1129 #if HVD_ENABLE_MVC
1130 MS_U8 u8ViewIdx = 0;
1131 if(HAL_HVD_EX_CheckMVCID(u32Id))
1132 {
1133 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1134 }
1135 if(u8ViewIdx != 0) /// 2nd ES ptr.
1136 {
1137 u32Data = pShm->u32ES2ReadPtr;
1138 }
1139 else
1140 {
1141 u32Data = pShm->u32ESReadPtr;
1142 }
1143 #else
1144 u32Data = pShm->u32ESReadPtr;
1145 #endif
1146 }
1147
1148 EXIT:
1149
1150 pCtrl->u32LastESRptr = u32Data;
1151
1152 return u32Data;
1153 }
1154
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1155 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1156 {
1157 MS_U16 u16TimeOut = 0xFFFF;
1158 MS_BOOL bResult = FALSE;
1159
1160 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
1161
1162 while (--u16TimeOut)
1163 {
1164 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1165 {
1166 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1167 break;
1168 }
1169 }
1170
1171 return bResult;
1172 }
1173
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1174 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1175 {
1176 MS_U16 u16TimeOut = 0xFFFF;
1177 MS_BOOL bResult = FALSE;
1178 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1179
1180 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
1181
1182 #if HVD_ENABLE_MVC
1183 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1184 {
1185 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1186 }
1187 #endif /// HVD_ENABLE_MVC
1188
1189 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1190
1191 while (--u16TimeOut)
1192 {
1193 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1194 {
1195 u32Cmd |= (u8TaskId << 24);
1196 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1197 break;
1198 }
1199 }
1200 return bResult;
1201 }
1202
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)1203 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
1204 {
1205 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1206 #ifdef VDEC3
1207 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1208 MS_BOOL IsSent = FALSE;
1209 MS_BOOL IsMailBox = FALSE;
1210 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1211
1212 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
1213 {
1214 do {
1215 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1216 if (!SentRet)
1217 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1218 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1219 break;
1220 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1221 IsSent = TRUE;
1222 break;
1223 }
1224 else if (HVD_GetSysTime_ms() > u32timeout)
1225 {
1226 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1227 break;
1228 }
1229 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1230 }
1231 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
1232 {
1233 do {
1234 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1235 if (!SentRet)
1236 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1237 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1238 break;
1239 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1240 IsSent = TRUE;
1241 break;
1242 }
1243 else if (HVD_GetSysTime_ms() > u32timeout)
1244 {
1245 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1246 break;
1247 }
1248 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1249 }
1250 if (!IsSent)
1251 {
1252 IsMailBox = TRUE;
1253 u32timeout = HVD_GetSysTime_ms() + HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT;//pHVDHalContext->u32HVDCmdTimeout;
1254 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1255 #else
1256 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1257 #endif
1258 {
1259 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1260 if (HVD_GetSysTime_ms() > u32timeout)
1261 {
1262 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1263 return E_HVD_RETURN_TIMEOUT;
1264 }
1265 //#endif
1266
1267 #if 0
1268 if (u32Cmd == E_HVD_CMD_STOP)
1269 {
1270 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1271 #if HVD_ENABLE_MVC
1272 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1273 {
1274 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1275 }
1276 #endif /// HVD_ENABLE_MVC
1277 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1278
1279 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1280 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1281
1282 return E_HVD_RETURN_SUCCESS;
1283 }
1284 #endif
1285
1286 if(u32Cmd < E_DUAL_CMD_BASE)
1287 {
1288 //_HVD_EX_GetPC();
1289 HAL_HVD_EX_Dump_FW_Status(u32Id);
1290 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1291 }
1292 }
1293
1294 #ifdef VDEC3
1295 }
1296 IsSent = FALSE;
1297 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1298 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
1299 {
1300 do {
1301 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1302 if (!SentRet)
1303 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1304 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1305 break;
1306 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1307 IsSent = TRUE;
1308 break;
1309 }
1310 else if (HVD_GetSysTime_ms() > u32timeout)
1311 {
1312 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1313 break;
1314 }
1315 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1316 }
1317 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
1318 {
1319 do {
1320 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1321 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1322 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1323 }
1324 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1325 break;
1326 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1327 IsSent = TRUE;
1328 break;
1329 }
1330 else if (HVD_GetSysTime_ms() > u32timeout)
1331 {
1332 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1333 break;
1334 }
1335 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1336 }
1337 if (!IsSent)
1338 {
1339 u32timeout = HVD_GetSysTime_ms() + HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT;//pHVDHalContext->u32HVDCmdTimeout;
1340 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1341 #else
1342 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1343
1344 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1345 #endif
1346 {
1347 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1348 if (HVD_GetSysTime_ms() > u32timeout)
1349 {
1350 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
1351 return E_HVD_RETURN_TIMEOUT;
1352 }
1353 //#endif
1354 if(u32Cmd < E_DUAL_CMD_BASE)
1355 {
1356 //_HVD_EX_GetPC();
1357 HAL_HVD_EX_Dump_FW_Status(u32Id);
1358 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1359 }
1360 }
1361 #ifdef VDEC3
1362 }
1363 else
1364 {
1365 HAL_HVD_EX_FlushMemory();
1366 }
1367 #endif
1368 return E_HVD_RETURN_SUCCESS;
1369 }
1370
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)1371 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
1372 {
1373 #if HAL_HVD_ENABLE_MIU_PROTECT
1374 _HVD_MIU_SetReqMask(MVD_RW_0, bEnable);
1375 _HVD_MIU_SetReqMask(MVD_RW_1, bEnable);
1376 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1377 #if SUPPORT_EVD
1378 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
1379 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1380 #endif
1381 _HVD_MIU_SetReqMask(HVD_RW_MIF0, bEnable);
1382 _HVD_MIU_SetReqMask(HVD_RW_MIF1, bEnable);
1383 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1384 HAL_VPU_EX_MIU_RW_Protect(bEnable);
1385 //HVD_Delay_ms(1);
1386 #endif
1387 return;
1388 }
1389
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1390 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1391 {
1392 MS_U16 u16Reg = 0;
1393 MS_VIRT u32StAddr = 0;
1394 #ifdef VDEC3
1395 MS_U32 u32Length = 0;
1396 #endif
1397 MS_U8 u8BitMiuSel = 0;
1398 MS_U8 u8CodeMiuSel = 0;
1399 MS_U8 u8FBMiuSel = 0;
1400 MS_U8 u8TmpMiuSel = 0;
1401 MS_U32 u32BitStartOffset;
1402 MS_U32 u32CodeStartOffset;
1403 MS_U32 u32FBStartOffset;
1404
1405 #ifndef VDEC3
1406 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1407 #endif
1408 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1409 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1410 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1411
1412 _HAL_HVD_Entry();
1413
1414 if (pCtrl == NULL)
1415 {
1416 _HAL_HVD_Return();
1417 }
1418
1419 MS_BOOL bESBufferAlreadySet = FALSE;
1420 VPU_EX_TaskInfo taskInfo;
1421 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1422
1423 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
1424
1425 bESBufferAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
1426
1427
1428
1429 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1430 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1431 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1432
1433 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1434 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1435 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1436 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1437 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1438 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1439 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1440 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1441 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1442 (u8FBMiuSel << VDEC_PPIN_MIUSEL) |
1443 (u8FBMiuSel << VDEC_XCSHM_MIUSEL));
1444
1445 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1446 {
1447 // ES buffer
1448 #ifdef VDEC3
1449 if(pCtrl->bShareBBU)
1450 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1451 else
1452 #endif
1453 u32StAddr = u32BitStartOffset;
1454
1455 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1456
1457 #ifdef VDEC3
1458 if (!_HAL_EX_BBU_VP8_InUsed())
1459 #endif
1460 {
1461 HVD_EX_MSG_ERR("ESB start addr=%lx\n", (unsigned long)u32StAddr);
1462
1463 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1464 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1465
1466 #ifdef VDEC3
1467 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1468 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1469 #else
1470 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1471 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1472 #endif
1473
1474 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1475 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1476 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1477 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1478 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1479 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1480 }
1481
1482 _HAL_HVD_Return();
1483 }
1484
1485 // ES buffer
1486 #ifdef VDEC3
1487 if(!pCtrl->bShareBBU || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1488 {
1489 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1490 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1491 }
1492 else
1493 {
1494 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1495 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1496 }
1497 #else
1498 u32StAddr = u32BitStartOffset;
1499 #endif
1500
1501 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1502
1503 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1504
1505 #ifdef VDEC3
1506 if (!bESBufferAlreadySet)
1507 {
1508 if (pCtrl->u32BBUId == 0)
1509 {
1510 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1511 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1512
1513 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1514 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1515 }
1516 else
1517 {
1518 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1519 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1520
1521 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1522 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1523 }
1524 }
1525 #else
1526 if (0 == u8TaskId)
1527 {
1528 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1529 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1530
1531 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1532 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1533 }
1534 else
1535 {
1536 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1537 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1538
1539 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1540 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1541 }
1542 #endif
1543
1544 // others
1545 #ifdef VDEC3
1546 if (!bESBufferAlreadySet)
1547 {
1548 if (pCtrl->u32BBUId == 0)
1549 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1550 else
1551 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1552
1553 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1554 {
1555 if (pCtrl->u32BBUId == 0)
1556 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1557 else
1558 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1559 }
1560 else
1561 {
1562 if (pCtrl->u32BBUId == 0)
1563 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1564 else
1565 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1566 }
1567
1568 // do not set parsing setting in DRV, and we set it in FW (hvd_switch_bbu)
1569 if (pCtrl->u32BBUId == 0)
1570 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1571 else
1572 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1573
1574 if (pCtrl->u32BBUId == 0)
1575 {
1576 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1577 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1578 }
1579 else
1580 {
1581 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1582 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1583 }
1584 }
1585 #else
1586 if (0 == u8TaskId)
1587 {
1588 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1589
1590 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1591 {
1592 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1593 }
1594 else
1595 {
1596 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1597 }
1598
1599 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1600
1601 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1602 {
1603 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1604 }
1605 else // AVS or AVC
1606 {
1607 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1608 {
1609 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1610 }
1611 else // start code remained
1612 {
1613 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1614 }
1615 }
1616
1617 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1618
1619 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1620 }
1621 else
1622 {
1623 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1624
1625 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1626 {
1627 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1628 }
1629 else
1630 {
1631 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1632 }
1633
1634 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1635
1636 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1637 {
1638 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1639 }
1640 else // AVS or AVC
1641 {
1642 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1643 {
1644 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1645 }
1646 else // start code remained
1647 {
1648 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1649 }
1650 }
1651
1652 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1653
1654 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1655 }
1656 #endif
1657
1658 #if (HVD_ENABLE_MVC)
1659 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1660 {
1661 /// Used sub stream to record sub view data.
1662 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1663 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1664
1665 // ES buffer
1666 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1667
1668 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1669 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1670 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1671
1672 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1673 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1674
1675 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1676 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1677 {
1678 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1679 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1680 }
1681 else
1682 {
1683 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1684 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1685 }
1686 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1687 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1688 {
1689 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1690 }
1691 else // AVS or AVC
1692 {
1693 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1694 {
1695 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1696 }
1697 else // start code remained
1698 {
1699 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1700 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1701 }
1702 }
1703 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1704 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1705 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1706 }
1707 #endif
1708
1709 // MIF offset
1710 #if 0
1711 {
1712 MS_U16 offaddr = 0;
1713 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1714 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1715 {
1716 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1717 }
1718 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1719 offaddr = (MS_U16) ((u32StAddr) >> 20);
1720 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1721 //0x1FF; // 9 bits(L + H)
1722 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1723 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1724 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1725 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1726 {
1727 u16Reg |= HVD_REG_MIF_OFFSET_H;
1728 }
1729 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1730 }
1731 #endif
1732
1733 if (!bESBufferAlreadySet)
1734 {
1735 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
1736 }
1737
1738 _HAL_HVD_Return();
1739 }
1740
1741 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1742 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1743 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1744 {
1745 MS_U16 u16Reg = 0;
1746 MS_U32 u32StAddr = 0;
1747 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1748 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1749 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1750
1751 if(pCtrl == NULL) return;
1752
1753 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1754 {
1755 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1756
1757 // ES buffer
1758 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1759
1760 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1761 {
1762 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1763 }
1764
1765 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1766 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1767
1768 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1769 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1770
1771 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1772 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1773 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1774 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1775 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1776 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1777
1778 return;
1779 }
1780
1781 // ES buffer
1782 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1783
1784 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1785 {
1786 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1787 }
1788
1789 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1790
1791 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1792 {
1793 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1794 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1795
1796 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1797 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1798 }
1799 else
1800 {
1801 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1802 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1803
1804 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1805 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1806 }
1807 }
1808 #endif
1809
_HVD_EX_GetESLevel(MS_U32 u32Id)1810 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1811 {
1812 MS_U32 u32Wptr = 0;
1813 MS_U32 u32Rptr = 0;
1814 MS_U32 u32CurMBX = 0;
1815 MS_U32 u32ESsize = 0;
1816 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1817 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1818
1819 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1820 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1821 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1822
1823 if (u32Rptr >= u32Wptr)
1824 {
1825 u32CurMBX = u32Rptr - u32Wptr;
1826 }
1827 else
1828 {
1829 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1830 }
1831
1832 if (u32CurMBX == 0)
1833 {
1834 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1835 }
1836 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1837 {
1838 u32Ret = E_HVD_ESB_LEVEL_OVER;
1839 }
1840 else
1841 {
1842 u32CurMBX = u32ESsize - u32CurMBX;
1843 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1844 {
1845 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1846 }
1847 }
1848
1849 return u32Ret;
1850 }
1851
_HVD_EX_GetESQuantity(MS_U32 u32Id)1852 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1853 {
1854 MS_U32 u32Wptr = 0;
1855 MS_U32 u32Rptr = 0;
1856 MS_U32 u32ESsize = 0;
1857 MS_U32 u32Ret = 0;
1858 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1859
1860 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1861 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1862 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1863
1864
1865 if(u32Wptr >= u32Rptr)
1866 {
1867 u32Ret = u32Wptr - u32Rptr;
1868 }
1869 else
1870 {
1871 u32Ret = u32ESsize - u32Rptr + u32Wptr;
1872 }
1873 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
1874 return u32Ret;
1875 }
1876
1877 #if (HVD_ENABLE_IQMEM)
HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)1878 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
1879 {
1880
1881 MS_U32 u32Timeout = 20000;
1882
1883 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
1884 {
1885
1886 HAL_VPU_EX_IQMemSetDAMode(TRUE);
1887
1888 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
1889
1890
1891 while (u32Timeout)
1892 {
1893
1894 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
1895 {
1896 break;
1897 }
1898 u32Timeout--;
1899 HVD_Delay_ms(1);
1900 }
1901
1902 HAL_VPU_EX_IQMemSetDAMode(FALSE);
1903
1904 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
1905
1906 if (u32Timeout==0)
1907 {
1908 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
1909 return FALSE;
1910 }
1911
1912
1913 }
1914 return TRUE;
1915 }
1916
1917 #endif
1918
1919 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)1920 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
1921 #else
1922 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
1923 #endif
1924 {
1925 MS_U32 u32FirmVer = 0;
1926 MS_U32 u32Timeout = 20000;
1927 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1928
1929 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
1930
1931 #if HVD_ENABLE_TIME_MEASURE
1932 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
1933 #endif
1934
1935 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
1936
1937 VPU_EX_FWCodeCfg fwCfg;
1938 VPU_EX_TaskInfo taskInfo;
1939 VPU_EX_VLCTblCfg vlcCfg;
1940 #ifdef VDEC3
1941 VPU_EX_FBCfg fbCfg;
1942 #endif
1943 VPU_EX_NDecInitPara nDecInitPara;
1944
1945 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
1946 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1947 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
1948 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
1949 #ifdef VDEC3_FB
1950 nDecInitPara.pVLCCfg = NULL;
1951 #else
1952 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
1953 {
1954 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
1955 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
1956 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
1957 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
1958 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
1959 nDecInitPara.pVLCCfg = &vlcCfg;
1960 }
1961 #endif
1962 nDecInitPara.pFWCodeCfg = &fwCfg;
1963 nDecInitPara.pTaskInfo = &taskInfo;
1964 #ifdef VDEC3
1965 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
1966 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
1967
1968 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1969 {
1970 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1971 }
1972
1973 nDecInitPara.pFBCfg = &fbCfg;
1974 #endif
1975
1976 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
1977 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
1978 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
1979 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
1980 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
1981
1982 taskInfo.u32Id = u32Id;
1983
1984 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1985 {
1986 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
1987 }
1988 #ifdef VDEC3
1989 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
1990 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
1991 {
1992 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
1993 }
1994 #if SUPPORT_MSVP9
1995 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
1996 {
1997 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
1998 }
1999 #endif
2000 #if SUPPORT_G2VP9
2001 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2002 {
2003 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2004 }
2005 #endif
2006 #endif
2007 else
2008 {
2009 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2010 }
2011
2012 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2013
2014 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2015 {
2016 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2017 }
2018 else
2019 {
2020 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2021 }
2022 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2023
2024 #ifdef SUPPORT_EVD
2025 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2026 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2027 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2028 #endif
2029
2030 if(TRUE == HVD_EX_GetRstFlag())
2031 {
2032 //Delete task for Rst
2033 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2034 {
2035 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2036 }
2037 HVD_EX_SetRstFlag(FALSE);
2038 }
2039
2040 #if (HVD_ENABLE_IQMEM)
2041 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2042 #endif
2043
2044 #ifdef VDEC3
2045 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2046 #else
2047 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2048 #endif
2049 {
2050 HVD_EX_MSG_ERR("Task create fail!\n");
2051
2052 return FALSE;
2053 }
2054
2055 while (u32Timeout)
2056 {
2057 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2058
2059 if (u32FirmVer != 0)
2060 {
2061 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2062 break;
2063 }
2064 u32Timeout--;
2065 HVD_Delay_ms(1);
2066 }
2067
2068 #ifdef VDEC3_FB
2069 #if HVD_ENABLE_RV_FEATURE
2070 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2071
2072 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2073 {
2074 if(pShm->u32RM_VLCTableAddr == 0) {
2075 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2076 }
2077 else
2078 {
2079 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2080 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2081 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2082 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2083 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2084 nDecInitPara.pVLCCfg = &vlcCfg;
2085 }
2086 }
2087
2088 if (nDecInitPara.pVLCCfg)
2089 {
2090 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2091 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2092 {
2093 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2094 return FALSE;
2095 }
2096 }
2097 #endif
2098 #endif
2099 if (u32Timeout > 0)
2100 {
2101 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2102
2103 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2104
2105 #ifdef VDEC3
2106 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2107 {
2108 case E_HVD_INIT_HW_AVC:
2109 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2110 break;
2111 case E_HVD_INIT_HW_AVS:
2112 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2113 break;
2114 case E_HVD_INIT_HW_RM:
2115 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2116 break;
2117 case E_HVD_INIT_HW_MVC:
2118 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2119 break;
2120 case E_HVD_INIT_HW_VP8:
2121 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2122 break;
2123 case E_HVD_INIT_HW_MJPEG:
2124 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2125 break;
2126 case E_HVD_INIT_HW_VP6:
2127 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2128 break;
2129 case E_HVD_INIT_HW_HEVC:
2130 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2131 break;
2132 case E_HVD_INIT_HW_VP9:
2133 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2134 break;
2135 case E_HVD_INIT_HW_HEVC_DV:
2136 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC_DV;
2137 break;
2138 default:
2139 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2140 break;
2141 }
2142 #endif
2143
2144 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2145 }
2146 else
2147 {
2148 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2149 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2150
2151 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2152 {
2153 HVD_EX_MSG_ERR("Task delete fail!\n");
2154 }
2155
2156 return FALSE;
2157 }
2158
2159
2160
2161 #if (HVD_ENABLE_IQMEM)
2162
2163 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
2164 {
2165
2166 HAL_HVD_EX_IQMem_Init(u32Id);
2167 }
2168 else{
2169 HVD_EX_MSG_DBG("not support IQMEM\n");
2170 }
2171 #endif
2172
2173
2174
2175
2176
2177
2178 #if HVD_ENABLE_TIME_MEASURE
2179 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2180 #endif
2181
2182 return TRUE;
2183 }
2184
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2185 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2186 {
2187 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2188 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2189 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2190 {
2191 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2192 }
2193 else
2194 {
2195 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2196 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2197 }
2198 }
2199
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2200 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2201 {
2202 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2203 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2204
2205 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2206 {
2207 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2208 }
2209 else
2210 {
2211 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2212 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2213 }
2214 }
2215
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2216 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2217 {
2218 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2219 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2220
2221 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2222 {
2223 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2224 {
2225 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2226 }
2227 }
2228 else
2229 {
2230 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2231 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2232 }
2233 }
2234
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2235 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2236 {
2237 MS_VIRT u32PTSWptr = HVD_U32_MAX;
2238 MS_VIRT u32PTSRptr = HVD_U32_MAX;
2239 MS_VIRT u32DestAddr = 0;
2240 HVD_PTS_Entry PTSEntry;
2241 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2242 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2243 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2244
2245 // update R & W ptr
2246 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2247
2248 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
2249
2250 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2251 {
2252 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
2253 (MS_U32) MAX_PTS_TABLE_SIZE);
2254 return E_HVD_RETURN_FAIL;
2255 }
2256
2257 // check queue is full or not
2258 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2259 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2260
2261 if (u32PTSWptr == u32PTSRptr)
2262 {
2263 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
2264 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2265 return E_HVD_RETURN_FAIL;
2266 }
2267
2268 // add one PTS entry
2269 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2270 PTSEntry.u32ID_L = pInfo->u32ID_L;
2271 PTSEntry.u32ID_H = pInfo->u32ID_H;
2272 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2273
2274 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2275
2276 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
2277
2278 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2279
2280 HAL_HVD_EX_FlushMemory();
2281
2282 // update Write ptr
2283 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2284
2285 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2286
2287 return E_HVD_RETURN_SUCCESS;
2288 }
2289
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2290 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2291 {
2292 //---------------------------------------------------
2293 // item format in nal table:
2294 // reserved |borken| u32NalOffset | u32NalLen
2295 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2296 //---------------------------------------------------
2297 MS_VIRT u32Adr = 0;
2298 MS_U32 u32BBUNewWptr = 0;
2299 MS_U8 item[8];
2300 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2301 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2302 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2303 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2304
2305 #if HVD_ENABLE_MVC
2306 if(HAL_HVD_EX_CheckMVCID(u32Id))
2307 {
2308 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2309 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2310 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2311 {
2312 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2313 }
2314 }
2315 #endif /// HVD_ENABLE_MVC
2316
2317 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2318 {
2319 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
2320 }
2321 else
2322 {
2323 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2324 }
2325 u32BBUNewWptr++;
2326 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
2327
2328 // prepare nal entry
2329
2330 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
2331 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2332 {
2333 // NAL len 22 bits , HEVC level5 constrain
2334 item[0] = u32NalLen & 0xff;
2335 item[1] = (u32NalLen >> 8) & 0xff;
2336 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2337 item[3] = (u32NalOffset >> 2) & 0xff;
2338 item[4] = (u32NalOffset >> 10) & 0xff;
2339 item[5] = (u32NalOffset >> 18) & 0xff;
2340 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2341 item[7] = 0;
2342 }
2343 else
2344 {
2345 item[0] = u32NalLen & 0xff;
2346 item[1] = (u32NalLen >> 8) & 0xff;
2347 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2348 item[3] = (u32NalOffset >> 3) & 0xff;
2349 item[4] = (u32NalOffset >> 11) & 0xff;
2350 item[5] = (u32NalOffset >> 19) & 0xff;
2351 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2352 item[7] = 0;
2353 }
2354
2355 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2356 {
2357 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
2358 }
2359 else
2360 {
2361 // add nal entry
2362 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2363 }
2364
2365 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2366
2367 HAL_HVD_EX_FlushMemory();
2368
2369 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2370
2371 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2372 {
2373 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
2374 }
2375 else
2376 {
2377 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2378 }
2379
2380 return E_HVD_RETURN_SUCCESS;
2381 }
2382
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2383 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2384 {
2385 MS_U8 item[8];
2386 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2387 MS_VIRT u32Adr = 0;
2388 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2389 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2390 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2391
2392 /*
2393 printf("nal2 offset=0x%x, len=0x%x\n",
2394 u32NalOffset2, u32NalLen2);
2395 */
2396
2397 item[0] = u32NalLen2 & 0xff;
2398 item[1] = (u32NalLen2 >> 8) & 0xff;
2399 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2400 item[3] = (u32NalOffset2 >> 3) & 0xff;
2401 item[4] = (u32NalOffset2 >> 11) & 0xff;
2402 item[5] = (u32NalOffset2 >> 19) & 0xff;
2403 item[6] = (u32NalOffset2 >> 27) & 0x07;
2404 item[7] = 0;
2405
2406 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2407 {
2408 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
2409 }
2410 else
2411 {
2412 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2413 }
2414
2415 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2416
2417 HAL_HVD_EX_FlushMemory();
2418
2419 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2420 }
2421
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2422 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2423 {
2424 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2425 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2426
2427 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2428 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
2429 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
2430 {
2431 MS_U16 i;
2432 MS_PHY u32VUIAddr;
2433 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
2434
2435 HAL_HVD_EX_ReadMemory();
2436 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2437
2438 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2439 {
2440 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2441 {
2442 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2443 }
2444 else
2445 {
2446 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2447 }
2448 pData++;
2449 }
2450 }
2451 else
2452 {
2453 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2454 }
2455
2456 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
2457 }
2458
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2459 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2460 {
2461 MS_U32 u32ReadPtr = 0;
2462 MS_U32 eRet = 0;
2463 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2464 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2465
2466 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2467 MS_U32 u32WritePtr = 0;
2468
2469 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2470 {
2471 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
2472 }
2473 else
2474 {
2475 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2476 }
2477
2478 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
2479
2480 if (u32WritePtr >= u32ReadPtr)
2481 {
2482 eRet = u32WritePtr - u32ReadPtr;
2483 }
2484 else
2485 {
2486 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2487 }
2488
2489 #if 0
2490 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2491 {
2492 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2493 }
2494 else
2495 {
2496 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2497 }
2498
2499 #endif
2500 return eRet;
2501 }
2502
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2503 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2504 {
2505 MS_U32 u32ReadPtr = 0;
2506 MS_U32 eRet = 0;
2507 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2508
2509 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2510
2511 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2512 {
2513 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
2514 (MS_U32) MAX_PTS_TABLE_SIZE);
2515 return 0;
2516 }
2517
2518 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2519
2520 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2521 {
2522 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2523 }
2524 else
2525 {
2526 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2527 }
2528
2529 return eRet;
2530 }
2531
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)2532 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
2533 {
2534 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2535
2536 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
2537 }
2538
hevc_get_paired(HEVC_PIC_STRUCT pic_struct,int first_field)2539 static HEVC_PIC_STRUCT hevc_get_paired(HEVC_PIC_STRUCT pic_struct, int first_field)
2540 {
2541 if (pic_struct == EVD_TOP_FIELD)
2542 return EVD_BOTTOM_FIELD;
2543 else if (pic_struct == EVD_BOTTOM_FIELD)
2544 return EVD_TOP_FIELD;
2545
2546 if (first_field)
2547 {
2548 // pic_struct is the first field and must pair with the next one
2549 if (pic_struct == EVD_TOP_WITH_NEXT)
2550 return EVD_BOTTOM_WITH_PREV;
2551 else if (pic_struct == EVD_BOTTOM_WITH_NEXT)
2552 return EVD_TOP_WITH_PREV;
2553 }
2554 else
2555 {
2556 // pic_struct is the second field and must pair with the previous one
2557 if (pic_struct == EVD_TOP_WITH_PREV)
2558 return EVD_BOTTOM_WITH_NEXT;
2559 else if (pic_struct == EVD_BOTTOM_WITH_PREV)
2560 return EVD_TOP_WITH_NEXT;
2561 }
2562
2563 return EVD_UNKNOWN_TYPE;
2564 }
2565
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2566 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2567 {
2568 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2569 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2570 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2571 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2572 HAL_HVD_EX_ReadMemory();
2573 MS_U16 u16QNum = pShm->u16DispQNumb;
2574 MS_U16 u16QPtr = pShm->u16DispQPtr;
2575
2576 HVD_Frm_Information *pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2577 if (bDolbyVision)
2578 {
2579 if (pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone && u16QNum < 4) // first time we need to wait 4 pic to ensure we got the correct layer type
2580 {
2581 return NULL;
2582 }
2583 else
2584 {
2585 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = FALSE;
2586 }
2587 }
2588
2589 #if (HVD_ENABLE_MVC)
2590 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2591 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
2592 {
2593 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2594 {
2595 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
2596 MS_U16 u16UsedFrm = 0;
2597 MS_U16 u16ResvFrmNum = ((u16RealQPtr % 2) == 0) ? 1 : 0; // need to check the next frame num is exist when get first frame.
2598 if (u16RealQPtr != u16QPtr)
2599 {
2600 if (u16RealQPtr > u16QPtr)
2601 {
2602 u16UsedFrm = u16RealQPtr - u16QPtr;
2603 }
2604 else
2605 {
2606 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2607 }
2608 }
2609
2610 if (u16QNum > (u16UsedFrm + u16ResvFrmNum))
2611 {
2612 u16QNum -= u16UsedFrm;
2613 u16QPtr = u16RealQPtr;
2614 pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2615
2616 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2617 {
2618 if ((u16QPtr % 2) == 0)
2619 {
2620 HVD_Frm_Information *pHvdFrmNext = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr + 1];
2621
2622 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2623 {
2624 return NULL;
2625 }
2626
2627 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2628 if(bDolbyVision)
2629 {
2630 HVD_PRINT("BL pts: %d, u16QPtr: %d, u16QNum:%d, uid:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2631 }
2632 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2633 }
2634 else
2635 {
2636 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2637 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
2638 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2639 HVD_Frm_Information *pHvdFrmPrv = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr - 1]; // must be odd
2640
2641 if(bDolbyVision)
2642 {
2643 HVD_PRINT("EL pts: %d, u16QPtr: %d, u16QNum:%d, uid:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2644 #if 0 // dump dolby metadata calculated by FW
2645 unsigned char *dump_addr = (unsigned char *)((void *)pShm + pShm->u32HVD_DBG_DUMP_ADDR - (u8Idx * 0x100000 + HVD_SHARE_MEM_ST_OFFSET));
2646 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2647 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2648 unsigned int i = 0;
2649 unsigned char arr[33] = {0};
2650 if(pVsyncBridgeExt != NULL)
2651 {
2652 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[u16QPtr]);
2653 }
2654 dump_addr += 32 * pFrmInfoExt->u8CurrentIndex;
2655 for (i = 0; i < 32; i++)
2656 {
2657 arr[i] = *(dump_addr + i);
2658 }
2659 HVD_PRINT("[md5]%02d=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x %02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x", (unsigned int)pFrmInfoExt->u8CurrentIndex, arr[0], arr[1], arr[2], arr[3], arr[4], arr[5], arr[6], arr[7], arr[8], arr[9], arr[10], arr[11], arr[12], arr[13], arr[14], arr[15], arr[16], arr[17], arr[18], arr[19], arr[20], arr[21], arr[22], arr[23], arr[24], arr[25], arr[26], arr[27], arr[28], arr[29], arr[30], arr[31]);
2660 #endif
2661 if(DIFF(pHvdFrmPrv->u32TimeStamp, pHvdFrm->u32TimeStamp) > 1000)
2662 HVD_EX_MSG_ERR("BL pts: %d, EL pts: %d matched failed!!\n",pHvdFrmPrv->u32TimeStamp, pHvdFrm->u32TimeStamp);
2663 }
2664 pHvdFrmPrv->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2665 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2666 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2667 }
2668 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2669 u16QPtr++;
2670 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2671 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2672
2673 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2674 }
2675 }
2676
2677 return NULL;
2678 }
2679
2680 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2681 //search the next frame to display
2682 while (u16QNum > 0)
2683 {
2684 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2685 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2686 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2687
2688 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2689 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2690 {
2691 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2692 /// Check the depned view was initial when Output the base view.
2693 if((u16QPtr%2) == 0)
2694 {
2695 HVD_Frm_Information *pHvdFrm_sub = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2696 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2697 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2698 {
2699 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2700 ///printf("Return NULL.\n");
2701 return NULL;
2702 }
2703 }
2704
2705 //printf("V:%d.\n",u16QPtr);
2706 pHVDHalContext->_u16DispQPtr = u16QPtr;
2707 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2708 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2709 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2710 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2711 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2712 }
2713
2714 u16QNum--;
2715 //go to next frame in the dispQ
2716 u16QPtr++;
2717
2718 if (u16QPtr >= pShm->u16DispQSize)
2719 {
2720 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2721 }
2722 }
2723 }
2724 else
2725 #endif ///HVD_ENABLE_MVC
2726 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
2727 if (_HVD_EX_IsHevcInterlaceField(u32Id))
2728 {
2729 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
2730 HVD_Frm_Information *pHvdFrm_first = NULL;
2731
2732 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
2733 return NULL;
2734 }
2735
2736 while (u16QNum != 0)
2737 {
2738 pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2739 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2740 {
2741 if (!first_field) // second get frame, we will check at least one paired in disp queue.
2742 {
2743 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2744 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2745 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
2746
2747 if(pHvdFrm->u8FieldType == EVD_TOP_FIELD || pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
2748 pHvdFrm->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
2749 else
2750 pHvdFrm->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
2751 return pHvdFrm;
2752 }
2753 else // first get frame, we will check at least one paired in disp queue.
2754 {
2755 if (pHvdFrm_first == NULL)
2756 {
2757 pHvdFrm_first = pHvdFrm;
2758 }
2759 else
2760 {
2761 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2762 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
2763
2764 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV)
2765 {
2766 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV && pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_NEXT)
2767 {
2768 pHvdFrm_first->u32ID_L |= (1 << 16);
2769 pHvdFrm->u32ID_L |= (1 << 16);
2770 }
2771 else if (pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV && pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
2772 {
2773 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2774 pHvdFrm->u32ID_L &= (~(1 << 16));
2775 }
2776 else
2777 {
2778 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2779 return NULL;
2780 }
2781 }
2782 else
2783 {
2784 if (hevc_get_paired(pHvdFrm->u8FieldType, 0) != pHvdFrm_first->u8FieldType)
2785 {
2786 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2787 return NULL;
2788 }
2789 }
2790
2791 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
2792 if (pHvdFrm_first->u8FieldType == EVD_TOP_FIELD || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_NEXT)
2793 pHvdFrm_first->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
2794 else
2795 pHvdFrm_first->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
2796 return pHvdFrm_first;
2797 }
2798 }
2799 }
2800 u16QNum--;
2801 //go to next frame in the dispQ
2802 u16QPtr++;
2803
2804 if (u16QPtr == pShm->u16DispQSize)
2805 {
2806 u16QPtr = 0; //wrap to the begin
2807 }
2808
2809 }
2810 return NULL;
2811 }
2812 else
2813 {
2814 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2815 {
2816
2817 while (u16QNum != 0)
2818 {
2819 pHvdFrm = (HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
2820
2821 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2822 {
2823 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2824 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2825 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2826 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2827 }
2828 u16QNum--;
2829 //go to next frame in the dispQ
2830 if (bDolbyVision)
2831 u16QPtr += 2; // single layer must in even ptr
2832 else
2833 u16QPtr++;
2834
2835 if (u16QPtr >= pShm->u16DispQSize)
2836 {
2837 u16QPtr = 0; //wrap to the begin
2838 }
2839 }
2840
2841 return NULL;
2842 }
2843
2844 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2845 //search the next frame to display
2846 while (u16QNum != 0)
2847 {
2848 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2849
2850 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2851 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2852 {
2853 pHVDHalContext->_u16DispQPtr = u16QPtr;
2854 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2855 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2856 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2857 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2858 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2859 }
2860
2861 u16QNum--;
2862 //go to next frame in the dispQ
2863 u16QPtr++;
2864
2865 if (u16QPtr == pShm->u16DispQSize)
2866 {
2867 u16QPtr = 0; //wrap to the begin
2868 }
2869 }
2870 }
2871
2872 return NULL;
2873 }
2874
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2875 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2876 {
2877 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2878 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2879 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2880 {
2881 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2882 if(pVsyncBridgeExt != NULL)
2883 {
2884 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
2885 }
2886 }
2887 return pFrmInfoExt;
2888 }
2889
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)2890 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
2891 {
2892 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2893 MS_U64 u64Ret = 0;
2894
2895 #if SUPPORT_EVD
2896 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
2897 if (isEVD)
2898 {
2899 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
2900 }
2901 else
2902 #endif
2903 #if SUPPORT_G2VP9
2904 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2905 {
2906 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
2907 }
2908 else
2909 #endif
2910 {
2911 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
2912 }
2913
2914 return u64Ret;
2915 }
2916
2917 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)2918 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
2919 {
2920 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2921 MS_U16 u16QNum = pShm->u16DispQNumb;
2922 MS_U16 u16QPtr = pShm->u16DispQPtr;
2923 static volatile HVD_Frm_Information *pHvdFrm = NULL;
2924 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2925 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2926 MS_BOOL bMVC = FALSE;
2927 #if HVD_ENABLE_MVC
2928 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2929 #endif
2930
2931
2932 if (bMVC || (bDolbyVision && !pShm->bSingleLayer) || _HVD_EX_IsHevcInterlaceField(u32Id))
2933 {
2934 if (u16QNum == 1) return TRUE;
2935 }
2936
2937 while (u16QNum != 0)
2938 {
2939 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2940 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2941 {
2942 return FALSE;
2943 }
2944 u16QNum--;
2945
2946 if (bDolbyVision)
2947 u16QPtr += 2; // single layer must in even ptr
2948 else
2949 u16QPtr++;
2950
2951 if (u16QPtr >= pShm->u16DispQSize)
2952 {
2953 u16QPtr = 0; //wrap to the begin
2954 }
2955 }
2956
2957 return TRUE;
2958 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)2959 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
2960 {
2961 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
2962
2963 return &(_pHVDCtrls[u8DrvId]);
2964 }
2965
_HVD_EX_GetStreamIdx(MS_U32 u32Id)2966 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
2967 {
2968 MS_U8 u8OffsetIdx = 0;
2969 MS_U8 u8SidBaseMask = 0xF0;
2970 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
2971
2972 switch (eSidBase)
2973 {
2974 case E_HAL_HVD_MAIN_STREAM_BASE:
2975 {
2976 u8OffsetIdx = 0;
2977 break;
2978 }
2979 case E_HAL_VPU_SUB_STREAM_BASE:
2980 {
2981 u8OffsetIdx = 1;
2982 break;
2983 }
2984 case E_HAL_VPU_MVC_STREAM_BASE:
2985 {
2986 u8OffsetIdx = 0;
2987 break;
2988 }
2989 #ifdef VDEC3
2990 case E_HAL_VPU_N_STREAM_BASE:
2991 {
2992 u8OffsetIdx = (u32Id>>8) & 0xF;
2993 break;
2994 }
2995 #endif
2996 default:
2997 {
2998 u8OffsetIdx = 0;
2999 break;
3000 }
3001 }
3002
3003 return u8OffsetIdx;
3004 }
3005 /*
3006 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
3007 {
3008 MS_U32 i = 0;
3009 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3010 {
3011 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
3012 {
3013 return TRUE;
3014 }
3015 }
3016 return FALSE;
3017 }
3018 */
3019
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)3020 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
3021 {
3022 MS_PHY u32PhyAddr = 0x0;
3023 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3024
3025 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3026 {
3027 return 0;
3028 }
3029
3030 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3031
3032 if (u32PhyAddr == 0xFFFFFFFF) //boris
3033 {
3034 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3035 }
3036 else
3037 {
3038 // TEE, common + share_info
3039 u32PhyAddr += COMMON_AREA_SIZE;
3040 }
3041
3042 return MsOS_PA2KSEG1(u32PhyAddr);
3043 }
3044
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3045 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3046 {
3047 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3048 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3049
3050 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3051 {
3052 return 0;
3053 }
3054
3055 MS_PHY u32PhyAddr = 0x0;
3056 #if 0
3057 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3058
3059 if (u32PhyAddr == 0xFFFFFFFF)
3060 {
3061 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3062 }
3063 #endif
3064 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3065 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3066
3067 return MsOS_PA2KSEG1(u32PhyAddr);
3068 }
3069
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3070 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3071 {
3072
3073 if (u8MiuSel == E_CHIP_MIU_0)
3074 {
3075 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3076 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3077 }
3078 else if (u8MiuSel == E_CHIP_MIU_1)
3079 {
3080 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3081 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3082 }
3083 else // 2
3084 {
3085 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3086 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, MIU2_CLIENT_SELECT_GP4_HVD_MIF1, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3087 }
3088
3089 }
3090
3091 #if SUPPORT_G2VP9 && defined(VDEC3)
3092 #ifdef __ARM_NEON__
3093 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3094 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3095 {
3096 uint32x4x4_t data, data2;
3097 MS_U8* raster2 = raster + tile_w * 4;
3098
3099 data = vld4q_u32((const uint32_t *)tile);
3100 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3101
3102 vst1q_u32((uint32_t *)raster, data.val[0]);
3103 raster += stride;
3104 vst1q_u32((uint32_t *)raster, data.val[1]);
3105 raster += stride;
3106 vst1q_u32((uint32_t *)raster, data.val[2]);
3107 raster += stride;
3108 vst1q_u32((uint32_t *)raster, data.val[3]);
3109
3110
3111 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3112 raster2 += stride;
3113 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3114 raster2 += stride;
3115 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3116 raster2 += stride;
3117 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3118 }
3119 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3120 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3121 {
3122 MS_U8* tile0 = tile;
3123 MS_U8* tile1 = tile+16;
3124 MS_U8* tile2 = tile+32;
3125 MS_U8* tile3 = tile+48;
3126 int i;
3127
3128 for (i=0; i<4; i++) {
3129 raster[i] = tile0[i];
3130 raster[4+i] = tile1[i];
3131 raster[8+i] = tile2[i];
3132 raster[12+i] = tile3[i];
3133 }
3134
3135 for (i=0; i<4; i++) {
3136 raster[stride+i] = tile0[4+i];
3137 raster[stride+4+i] = tile1[4+i];
3138 raster[stride+8+i] = tile2[4+i];
3139 raster[stride+12+i] = tile3[4+i];
3140 }
3141
3142 for (i=0; i<4; i++) {
3143 raster[2*stride+i] = tile0[8+i];
3144 raster[2*stride+4+i] = tile1[8+i];
3145 raster[2*stride+8+i] = tile2[8+i];
3146 raster[2*stride+12+i] = tile3[8+i];
3147 }
3148
3149 for (i=0; i<4; i++) {
3150 raster[3*stride+i] = tile0[12+i];
3151 raster[3*stride+4+i] = tile1[12+i];
3152 raster[3*stride+8+i] = tile2[12+i];
3153 raster[3*stride+12+i] = tile3[12+i];
3154 }
3155 }
3156 #endif // #ifdef __ARM_NEON__
3157
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)3158 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
3159 {
3160 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
3161 u32Id,
3162 E_TASK_PRI_MEDIUM,
3163 TRUE,
3164 NULL,
3165 32, // stack size..
3166 "HVD_PostProcess_task");
3167
3168 if (s32HvdPpTaskId < 0)
3169 {
3170 HVD_EX_MSG_ERR("Pp Task create failed\n");
3171
3172 return FALSE;
3173 }
3174
3175 HVD_EX_MSG_DBG("Pp Task create success\n");
3176 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
3177
3178 return TRUE;
3179 }
3180
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3181 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3182 {
3183 return y * stride * h + x * w * h;
3184 }
3185
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3186 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3187 {
3188 return y * stride * h + x * w;
3189 }
3190
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3191 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3192 {
3193 raster[0] = tile[0];
3194 raster[1] = tile[1];
3195 raster[2] = tile[2];
3196 raster[3] = tile[3];
3197 raster[stride] = tile[4];
3198 raster[stride + 1] = tile[5];
3199 raster[stride + 2] = tile[6];
3200 raster[stride + 3] = tile[7];
3201 raster[2 * stride] = tile[8];
3202 raster[2 * stride + 1] = tile[9];
3203 raster[2 * stride + 2] = tile[10];
3204 raster[2 * stride + 3] = tile[11];
3205 raster[3 * stride] = tile[12];
3206 raster[3 * stride + 1] = tile[13];
3207 raster[3 * stride + 2] = tile[14];
3208 raster[3 * stride + 3] = tile[15];
3209 }
3210
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3211 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3212 {
3213 const MS_U32 tile_w = 4;
3214 const MS_U32 tile_h = 4;
3215 MS_U32 tile_stride = w;
3216 MS_U32 x, y;
3217 MS_U8 *dst1, *dst2;
3218 MS_U8 *src1, *src2;
3219
3220 #ifdef __ARM_NEON__
3221 // To overlap load and store, handle two blocks at the same time.
3222 dst1 = dst;
3223 src1 = src;
3224 for (y = 0; y < h / tile_h; y++)
3225 {
3226 dst2 = dst1;
3227 src2 = src1;
3228 for (x = 0; x <= (w/tile_w - 8); x+=8)
3229 {
3230 tile4x4_to_raster_8(
3231 dst2,
3232 src2,
3233 raster_stride, tile_w, tile_h);
3234 dst2 += tile_w * 8;
3235 src2 += tile_w * tile_h * 8;
3236 }
3237 dst1 += raster_stride * tile_h;
3238 src1 += tile_stride * tile_h;
3239 for (; x < w / tile_w; x++)
3240 {
3241 tile4x4_to_raster(
3242 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3243 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3244 raster_stride);
3245 }
3246 }
3247 #else
3248 dst1 = NULL;
3249 src1 = NULL;
3250 dst2 = NULL;
3251 src2 = NULL;
3252
3253 for (y = 0; y < h / tile_h; y++)
3254 {
3255 for (x = 0; x <= (w/tile_w - 4); x+=4)
3256 {
3257 tile4x4_to_raster_4(
3258 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3259 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3260 raster_stride);
3261 }
3262 for (; x < w / tile_w; x++)
3263 {
3264 tile4x4_to_raster(
3265 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3266 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3267 raster_stride);
3268 }
3269 }
3270 #endif
3271 }
3272
3273 #define FLUSH_CACHE_SIZE (256 * 1024)
3274
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3275 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3276 {
3277 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
3278 if (u32Size > FLUSH_CACHE_SIZE)
3279 u32Size = FLUSH_CACHE_SIZE;
3280
3281 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
3282 }
3283
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3284 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3285 {
3286 MS_U32 u32SkipSize = 0;
3287
3288 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3289 if (u32Size > FLUSH_CACHE_SIZE)
3290 {
3291 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3292 u32Size = FLUSH_CACHE_SIZE;
3293 }
3294
3295 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
3296 }
3297
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3298 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3299 {
3300 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
3301 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3302 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3303 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3304
3305 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3306
3307 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3308
3309 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3310 {
3311 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3312 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3313
3314 HVD_Delay_ms(1); // FIXME
3315
3316 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3317 continue;
3318
3319 HAL_HVD_EX_ReadMemory();
3320
3321 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3322 {
3323 MS_U8 *pSrcVA, *pDstVA;
3324 MS_U32 u32SrcPA, u32DstPA;
3325 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3326 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3327
3328 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3329 {
3330 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3331
3332 u16Width = pFrmInfo->u16Width;
3333 u16Height = pFrmInfo->u16Height;
3334 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3335 }
3336
3337 // Luma
3338 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3339 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3340
3341 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3342 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3343
3344 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3345 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3346
3347 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3348
3349 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3350
3351 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3352
3353 // Chroma
3354 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3355 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3356
3357 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3358 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3359
3360 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3361 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3362
3363 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3364
3365 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3366
3367 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3368
3369 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3370 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3371 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3372
3373 HAL_HVD_EX_FlushMemory();
3374
3375 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3376 break;
3377
3378 HAL_HVD_EX_ReadMemory();
3379 }
3380 }
3381
3382 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3383
3384 return TRUE;
3385 }
3386 #endif
3387
HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id,MS_BOOL * isVP8Used,MS_BOOL * isAECUsed,MS_BOOL * isAVCUsed)3388 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed , MS_BOOL *isAVCUsed)
3389 {
3390 MS_U8 i ;
3391 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3392
3393 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM ; i++)
3394 {
3395 if( _pHVDCtrls[i].bUsed && (i != u8DrvId))
3396 {
3397 MS_U32 u32TempModeFlag = (_pHVDCtrls[i].InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ;
3398 if((E_HVD_INIT_HW_VP8 == u32TempModeFlag))
3399 {
3400 *isVP8Used = TRUE ;
3401 }
3402 else if((E_HVD_INIT_HW_VP9 == u32TempModeFlag) || (E_HVD_INIT_HW_AVS == u32TempModeFlag))
3403 {
3404 *isAECUsed = TRUE ;
3405 }
3406 else if((E_HVD_INIT_HW_AVC == u32TempModeFlag))
3407 {
3408 *isAVCUsed = TRUE ;
3409 }
3410 }
3411 }
3412 }
3413
3414
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3415 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3416 {
3417 #ifndef VDEC3
3418 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3419 #endif
3420 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3421 MS_BOOL isVP8Used = FALSE;
3422 MS_BOOL isAECUsed = FALSE;
3423 MS_BOOL isAVCUsed = FALSE;
3424 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
3425 // MS_U8 u8MiuSel;
3426 // MS_U32 u32StartOffset;
3427
3428 #if SUPPORT_EVD
3429 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
3430 #else
3431 MS_BOOL isEVD = FALSE;
3432 #endif
3433 MS_BOOL isHVD = !isEVD;
3434
3435 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
3436 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3437
3438 if(pCtrl == NULL)
3439 {
3440 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
3441 //return FALSE;
3442 goto RESET;
3443 }
3444
3445 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3446 // re-setup clock.
3447 #if SUPPORT_G2VP9 && defined(VDEC3)
3448 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3449 #endif
3450
3451 if (isHVD)
3452 {
3453 if (!HAL_VPU_EX_HVDInUsed())
3454 {
3455 printf("HVD power on\n");
3456 HAL_HVD_EX_PowerCtrl(u32Id, TRUE);
3457 }
3458
3459 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3460 {
3461 HAL_VP8_PowerCtrl(TRUE);
3462 }
3463 else if(!isAECUsed &&( E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3464 {
3465 HAL_AEC_PowerCtrl(TRUE);
3466 }
3467
3468 #ifdef CONFIG_MSTAR_SRAMPD
3469 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3470 HVD_Delay_ms(1);
3471 #endif
3472 }
3473
3474 #if SUPPORT_EVD
3475 #ifdef VDEC3
3476 if (isEVD) /// Disable it for disable H264 IMI
3477 {
3478 if (!HAL_VPU_EX_EVDInUsed())
3479 {
3480 printf("EVD power on\n");
3481 HAL_EVD_EX_PowerCtrl(u32Id, TRUE);
3482 }
3483 if(!isAECUsed && (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3484 {
3485 HAL_AEC_PowerCtrl(TRUE);
3486 }
3487 }
3488 #endif
3489 #endif
3490
3491 #if SUPPORT_G2VP9 && defined(VDEC3)
3492 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3493 {
3494 if (!HAL_VPU_EX_G2VP9InUsed())
3495 {
3496 printf("G2 VP9 power on\n");
3497 HAL_VP9_EX_PowerCtrl(TRUE);
3498 }
3499 }
3500 #endif
3501
3502 if ((!HAL_VPU_EX_HVDInUsed()) )
3503 {
3504 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3505 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3506 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3507 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3508
3509 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3510
3511 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
3512 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
3513 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256);
3514 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256);
3515 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128);
3516 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128);
3517
3518 #if 0
3519 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
3520 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3521 {
3522 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
3523
3524 _HAL_HVD_Entry();
3525 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
3526 _HAL_HVD_Release();
3527
3528 }
3529 #endif
3530 }
3531
3532 #if SUPPORT_EVD
3533 if (isEVD)
3534 {
3535 #ifdef VDEC3
3536 if (!HAL_VPU_EX_EVDInUsed())
3537 #endif
3538 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3539 }
3540 #endif
3541
3542 #if SUPPORT_G2VP9 && defined(VDEC3)
3543 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3544 {
3545 if (!HAL_VPU_EX_G2VP9InUsed())
3546 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3547 }
3548 #endif
3549
3550 #if SUPPORT_EVD
3551 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
3552 {
3553 #ifdef VDEC3
3554 if (!HAL_VPU_EX_EVDInUsed())
3555 #endif
3556 {
3557 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3558 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3559 }
3560
3561 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3562 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3563 {
3564 #ifdef VDEC3
3565 if (0 == pCtrl->u32BBUId)
3566 #else
3567 if (0 == u8TaskId)
3568 #endif
3569 {
3570 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
3571 }
3572 else
3573 {
3574 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
3575 }
3576
3577 }
3578 goto RESET;
3579 }
3580 #endif
3581
3582 // HVD4, from JANUS and later chip
3583 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3584 {
3585 case E_HVD_INIT_HW_AVS:
3586 {
3587 #ifdef VDEC3
3588 if (0 == pCtrl->u32BBUId)
3589 #else
3590 if (0 == u8TaskId)
3591 #endif
3592 {
3593 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3594 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3595 }
3596 else
3597 {
3598 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3599 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3600 }
3601
3602 break;
3603 }
3604 case E_HVD_INIT_HW_RM:
3605 {
3606 #ifdef VDEC3
3607 if (0 == pCtrl->u32BBUId)
3608 #else
3609 if (0 == u8TaskId)
3610 #endif
3611 {
3612 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3613 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3614
3615 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3616 {
3617 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3618 }
3619 else // RV 8
3620 {
3621 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3622 }
3623 }
3624 else
3625 {
3626 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3627 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3628
3629 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3630 {
3631 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3632 }
3633 else // RV 8
3634 {
3635 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3636 }
3637
3638 }
3639
3640 break;
3641 }
3642 default:
3643 {
3644 #ifdef VDEC3
3645 if (0 == pCtrl->u32BBUId)
3646 #else
3647 if (0 == u8TaskId)
3648 #endif
3649 {
3650 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3651 }
3652 else
3653 {
3654 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3655 }
3656 break;
3657 }
3658 }
3659
3660 RESET:
3661
3662 #if 0 //use miu256bit
3663 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3664
3665 if (!HAL_VPU_EX_HVDInUsed())
3666 {
3667 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3668 }
3669
3670 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3671 #endif
3672
3673 #if SUPPORT_EVD
3674 if (isEVD)
3675 {
3676 #ifdef VDEC3
3677 if (!HAL_VPU_EX_EVDInUsed())
3678 #endif
3679 {
3680 printf("EVD miu 256 bits\n");
3681 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_128 & ~EVD_REG_RESET_MIU1_128));
3682 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_256 | EVD_REG_RESET_MIU1_256));
3683 }
3684 }
3685 #endif
3686 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3687 // Only ES buffer addrress needs to be set for VP8
3688 _HVD_EX_SetESBufferAddr(u32Id);
3689 #else
3690 if(DecoderType != E_VPU_EX_DECODER_MVD)
3691 {
3692 _HVD_EX_SetBufferAddr(u32Id);
3693 }
3694 #endif
3695 if (!HAL_VPU_EX_HVDInUsed())
3696 {
3697 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3698 }
3699
3700 #if SUPPORT_EVD
3701 if (isEVD)
3702 {
3703 #ifdef VDEC3
3704 if (!HAL_VPU_EX_EVDInUsed())
3705 #endif
3706 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
3707 }
3708 #endif
3709
3710 #if SUPPORT_G2VP9 && defined(VDEC3)
3711 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3712 {
3713 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3714
3715 if (!HAL_VPU_EX_G2VP9InUsed())
3716 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3717
3718 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3719 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
3720 }
3721 #endif
3722
3723 return TRUE;
3724 }
3725
HAL_HVD_EX_DeinitHW(MS_U32 u32Id)3726 MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id)
3727 {
3728 MS_U16 u16Timeout = 1000;
3729 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3730 MS_BOOL isVP8Used = FALSE;
3731 MS_BOOL isAECUsed = FALSE;
3732 MS_BOOL isAVCUsed = FALSE;
3733 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed , &isAVCUsed);
3734
3735 #if SUPPORT_EVD
3736 if(!isAVCUsed && E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) && !HAL_VPU_EX_EVDInUsed())
3737 {
3738 HAL_EVD_EX_DeinitHW(u32Id);//no AVC/EVD use , close EVD power
3739 }
3740 #endif
3741
3742 if(TRUE == HAL_VPU_EX_HVDInUsed())
3743 {
3744 #if 0 //Power control close Vp8 register in dynamic ,but bs4-nal-ready could be off.(Patch for maxim and maserati)
3745 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3746 {
3747 HAL_VP8_PowerCtrl(FALSE);
3748 }
3749 else
3750 #endif
3751 if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3752 {
3753 HAL_AEC_PowerCtrl(FALSE);
3754 }
3755 return FALSE;
3756 }
3757 else
3758 {
3759 _HVD_EX_SetMIUProtectMask(TRUE);
3760
3761 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3762
3763 while (u16Timeout)
3764 {
3765 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
3766 {
3767 break;
3768 }
3769 u16Timeout--;
3770 }
3771
3772 HAL_HVD_EX_PowerCtrl(u32Id, FALSE);
3773
3774 //Power control close Vp8 register in dynamic ,but bs4-nal-ready could be off.(Patch for maxim and maserati)
3775 HAL_VP8_PowerCtrl(FALSE);
3776 #if 0
3777 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3778 {
3779 HAL_VP8_PowerCtrl(FALSE);
3780 }
3781 else
3782 #endif
3783 if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3784 {
3785 HAL_AEC_PowerCtrl(FALSE);
3786 }
3787
3788 #ifdef CONFIG_MSTAR_SRAMPD
3789 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3790 HVD_Delay_ms(1);
3791 #endif
3792
3793 _HVD_EX_SetMIUProtectMask(FALSE);
3794
3795 return TRUE;
3796 }
3797
3798 return FALSE;
3799 }
3800
HAL_HVD_EX_FlushMemory(void)3801 void HAL_HVD_EX_FlushMemory(void)
3802 {
3803 MsOS_FlushMemory();
3804 }
3805
HAL_HVD_EX_ReadMemory(void)3806 void HAL_HVD_EX_ReadMemory(void)
3807 {
3808 MsOS_ReadMemory();
3809 }
3810
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)3811 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
3812 {
3813 _pHVDCtrls = pHVDCtrlsBase;
3814 }
3815
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)3816 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
3817 {
3818 return;
3819 }
3820
HAL_HVD_EX_GetHWVersionID(void)3821 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
3822 {
3823 return _HVD_Read2Byte(HVD_REG_REV_ID);
3824 }
3825
3826
HAL_HVD_EX_Init_Share_Mem(void)3827 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
3828 {
3829 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
3830 #if !defined(SUPPORT_X_MODEL_FEATURE)
3831 MS_U32 u32ShmId;
3832 MS_VIRT u32Addr;
3833 MS_U32 u32BufSize;
3834
3835
3836 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
3837 sizeof(HVD_Hal_CTX),
3838 &u32ShmId,
3839 &u32Addr,
3840 &u32BufSize,
3841 MSOS_SHM_QUERY))
3842 {
3843 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
3844 sizeof(HVD_Hal_CTX),
3845 &u32ShmId,
3846 &u32Addr,
3847 &u32BufSize,
3848 MSOS_SHM_CREATE))
3849 {
3850 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
3851 if(pHVDHalContext == NULL)
3852 {
3853 pHVDHalContext = &gHVDHalContext;
3854 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3855 _HVD_EX_Context_Init_HAL();
3856 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
3857 }
3858 else
3859 {
3860 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
3861 }
3862 //return FALSE;
3863 }
3864 else
3865 {
3866 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
3867 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
3868 _HVD_EX_Context_Init_HAL();
3869 }
3870 }
3871 else
3872 {
3873 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
3874 }
3875 #else
3876 if(pHVDHalContext == NULL)
3877 {
3878 pHVDHalContext = &gHVDHalContext;
3879 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3880 _HVD_EX_Context_Init_HAL();
3881 }
3882 #endif
3883 _HAL_HVD_MutexCreate();
3884 #else
3885 if(pHVDHalContext == NULL)
3886 {
3887 pHVDHalContext = &gHVDHalContext;
3888 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3889 _HVD_EX_Context_Init_HAL();
3890 }
3891 #endif
3892
3893 return TRUE;
3894 }
3895
3896
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)3897 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
3898 {
3899 MS_U32 i = 0;
3900
3901 if (eStreamType == E_HAL_HVD_MVC_STREAM)
3902 {
3903 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
3904 return pHVDHalContext->_stHVDStream[0].eStreamId;
3905 }
3906 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
3907 {
3908 for (i = 0;
3909 i <
3910 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3911 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3912 {
3913 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3914 {
3915 return pHVDHalContext->_stHVDStream[i].eStreamId;
3916 }
3917 }
3918 }
3919 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
3920 {
3921 for (i = 0;
3922 i <
3923 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3924 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3925 {
3926 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3927 {
3928 return pHVDHalContext->_stHVDStream[i].eStreamId;
3929 }
3930 }
3931 }
3932 #ifdef VDEC3
3933 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
3934 {
3935 i = eStreamType - E_HAL_HVD_N_STREAM;
3936 if (!pHVDHalContext->_stHVDStream[i].bUsed)
3937 return pHVDHalContext->_stHVDStream[i].eStreamId;
3938 }
3939 #endif
3940
3941 return E_HAL_HVD_STREAM_NONE;
3942 }
3943
HAL_VP8_PowerCtrl(MS_BOOL bEnable)3944 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable)
3945 {
3946 if (bEnable)
3947 {
3948 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3949
3950 switch (pHVDHalContext->u32HVDClockType)
3951 {
3952 case 384:
3953 {
3954 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3955 break;
3956 }
3957 case 345:
3958 {
3959 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3960 break;
3961 }
3962 case 320:
3963 {
3964 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3965 break;
3966 }
3967 case 288:
3968 {
3969 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3970 break;
3971 }
3972 case 240:
3973 {
3974 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
3975 break;
3976 }
3977 case 216:
3978 {
3979 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3980 break;
3981 }
3982 case 172:
3983 {
3984 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3985 break;
3986 }
3987 default:
3988 {
3989 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3990 break;
3991 }
3992 }
3993 }
3994 else
3995 {
3996 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3997 }
3998
3999 }
4000
HAL_AEC_PowerCtrl(MS_BOOL bEnable)4001 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable)
4002 {
4003 if (bEnable)
4004 {
4005 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4006
4007 switch (pHVDHalContext->u32HVDClockType)
4008 {
4009 case 384:
4010 {
4011 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4012 break;
4013 }
4014 case 345:
4015 {
4016 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4017 break;
4018 }
4019 case 320:
4020 {
4021 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4022 break;
4023 }
4024 case 288:
4025 {
4026 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4027 break;
4028 }
4029 case 240:
4030 {
4031 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4032 break;
4033 }
4034 case 216:
4035 {
4036 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4037 break;
4038 }
4039 case 172:
4040 {
4041 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4042 break;
4043 }
4044 default:
4045 {
4046 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4047 break;
4048 }
4049 }
4050 }
4051 else
4052 {
4053 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4054 }
4055
4056 }
4057
HAL_HVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)4058 void HAL_HVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
4059 {
4060 if (bEnable)
4061 {
4062 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4063 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4064 }
4065 else
4066 {
4067 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4068 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4069 }
4070
4071 // fix to not inverse
4072 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
4073
4074 switch (pHVDHalContext->u32HVDClockType)
4075 {
4076 #if 0 //for overclocking
4077 case 432:
4078 {
4079 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
4080 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4081 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_320MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4082 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK);
4083 break;
4084 }
4085 #endif
4086 case 384:
4087 {
4088 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4089 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4090 break;
4091 }
4092 case 345:
4093 {
4094 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_345MHZ, TOP_CKG_HVD_CLK_MASK);
4095 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4096 break;
4097 }
4098 case 320:
4099 {
4100 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_320MHZ, TOP_CKG_HVD_CLK_MASK);
4101 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_345MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4102 break;
4103 }
4104 case 288:
4105 {
4106 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
4107 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_320MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4108 break;
4109 }
4110 case 240:
4111 {
4112 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
4113 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4114 break;
4115 }
4116 case 216:
4117 {
4118 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
4119 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_240MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4120 break;
4121 }
4122 case 172:
4123 {
4124 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
4125 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_216MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4126 break;
4127 }
4128
4129 default:
4130 {
4131 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4132 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4133 break;
4134 }
4135 }
4136
4137 return;
4138 }
4139
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)4140 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
4141 {
4142 u32HVDRegOSBase = u32RegBase;
4143 HAL_VPU_EX_InitRegBase(u32RegBase);
4144 }
4145
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)4146 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
4147 {
4148 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
4149 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4150 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
4151 }
4152
HAL_HVD_EX_InitVariables(MS_U32 u32Id)4153 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
4154 {
4155 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4156 HVD_ShareMem *pShm = NULL;
4157 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4158 #if HVD_ENABLE_MVC
4159 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4160 #endif ///HVD_ENABLE_MVC
4161
4162 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4163 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4164 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4165 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
4166 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4167 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = TRUE;
4168 int i;
4169 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
4170 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
4171 #if HVD_ENABLE_MVC
4172 if(bMVC)
4173 {
4174 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
4175 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
4176 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
4177 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
4178 }
4179 #endif ///HVD_ENABLE_MVC
4180
4181 // set a local copy of FW code address; assuming there is only one copy of FW,
4182 // no matter how many task will be created.
4183
4184 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4185
4186 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
4187
4188 // global variables
4189 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
4190
4191
4192 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4193 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4194 // Create mutex
4195 //_HAL_HVD_MutexCreate();
4196
4197 // fill HVD init variables
4198 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4199 {
4200 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
4201 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
4202 }
4203 else
4204 #if HVD_ENABLE_RV_FEATURE
4205 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4206 {
4207 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
4208 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
4209 #ifdef VDEC3_FB
4210 pHVDHalContext->u32RV_VLCTableAddr = 0;
4211 #else
4212 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
4213 {
4214 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
4215 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
4216 }
4217 else
4218 {
4219 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
4220 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
4221 return E_HVD_RETURN_INVALID_PARAMETER;
4222 }
4223 #endif
4224 }
4225 else
4226 #endif
4227 {
4228 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
4229 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
4230 #if HVD_ENABLE_MVC
4231 if(bMVC)
4232 {
4233 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
4234 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
4235 }
4236 #endif /// HVD_ENABLE_MVC
4237 pHVDHalContext->u32RV_VLCTableAddr = 0;
4238 }
4239
4240 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
4241 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
4242 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
4243 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
4244 {
4245 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4246 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4247 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4248 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4249 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4250 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4251 #if HVD_ENABLE_MVC
4252 if(bMVC)
4253 {
4254 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
4255 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
4256 {
4257 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
4258 }
4259 }
4260 #endif /// HVD_ENABLE_MVC
4261
4262 return E_HVD_RETURN_SUCCESS;
4263 }
4264 else
4265 {
4266 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4267 (unsigned long)MS_VA2PA((MS_VIRT)pShm),
4268 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4269 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4270 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4271 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4272 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4273 return E_HVD_RETURN_INVALID_PARAMETER;
4274 }
4275 }
4276
4277 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)4278 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
4279 #else
4280 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
4281 #endif
4282 {
4283 MS_U32 u32Addr = 0;
4284 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4285 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4286 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4287
4288 MS_U32 u32TmpStartOffset;
4289 MS_U8 u8TmpMiuSel;
4290
4291
4292 memset(pShm, 0, sizeof(HVD_ShareMem));
4293
4294 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
4295
4296 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
4297 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
4298 #ifdef VDEC3
4299 if (bFWdecideFB || bCMAUsed)
4300 {
4301 pShm->u32FrameBufAddr = 0;
4302 pShm->u32FrameBufSize = 0;
4303 }
4304 else
4305 #endif
4306 {
4307 pShm->u32FrameBufAddr = u32Addr;
4308 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
4309 }
4310
4311 // FIXME: need to use the avaliable task resource instead of using next task resource
4312 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
4313 pShm->u8ExternalHeapIdx = u8Idx + 1;
4314 else
4315 pShm->u8ExternalHeapIdx = 0xFF;
4316 pShm->DispInfo.u16DispWidth = 1;
4317 pShm->DispInfo.u16DispHeight = 1;
4318 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
4319 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
4320 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
4321 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4322 //Chip info
4323 pShm->u16ChipID = E_MSTAR_CHIP_MASERATI;
4324 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4325 // PreSetControl
4326 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bOnePendingBuffer)
4327 {
4328 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4329 }
4330
4331 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bCalFrameRate)
4332 {
4333 pShm->u32PreSetControl |= PRESET_CAL_FRAMERATE;
4334 }
4335
4336 pShm->bUseTSPInBBUMode = FALSE;
4337
4338
4339 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable) &&
4340 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4341 {
4342 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4343
4344 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufAddr);
4345
4346 pShm->u32IapGnBufAddr = u32Addr;
4347 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufSize;
4348
4349 }
4350
4351 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
4352 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
4353 {
4354 case E_HVD_DEF_MFCODEC_DEFAULT:
4355 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4356 break;
4357 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
4358 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
4359 break;
4360 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
4361 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
4362 break;
4363 default:
4364 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4365 }
4366
4367 pShm->u8CodecFeature &= ~E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4368 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bDVSingleLayerMode)
4369 pShm->u8CodecFeature |= E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4370
4371 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
4372 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
4373 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
4374 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
4375 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
4376 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
4377
4378 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.bEnable))
4379 {
4380 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4381
4382 pShm->stDynmcDispPath.u8Connect = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.bConnect;
4383 pShm->stDynmcDispPath.u8DispPath = (MS_U8)(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.eMvopPath);
4384 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4385
4386 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, pShm->stDynmcDispPath.u8DispPath);
4387 }
4388 else
4389 {
4390 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4391
4392 MS_U8 u8Connect = FALSE;
4393 MS_U8 u8Path = E_CTL_DISPLAY_PATH_NONE;
4394 switch (pCtrl->eStream)
4395 {
4396 case E_HVD_ORIGINAL_MAIN_STREAM:
4397 u8Connect = TRUE;
4398 u8Path = E_CTL_DISPLAY_PATH_MVOP_0;
4399 break;
4400 case E_HVD_ORIGINAL_SUB_STREAM:
4401 u8Connect = TRUE;
4402 u8Path = E_CTL_DISPLAY_PATH_MVOP_1;
4403 break;
4404 case E_HVD_ORIGINAL_N_STREAM:
4405 default:
4406 u8Connect = FALSE;
4407 u8Path = E_CTL_DISPLAY_PATH_NONE;
4408 break;
4409 }
4410
4411 pShm->stDynmcDispPath.u8Connect = u8Connect;
4412 pShm->stDynmcDispPath.u8DispPath = u8Path;
4413 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4414
4415 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, u8Path);
4416 }
4417
4418 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
4419 {
4420 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.bEnable))
4421 {
4422 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
4423 pShm->u8InputTSP = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.u8InputTsp;
4424
4425 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
4426 }
4427 else
4428 {
4429 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
4430
4431 MS_U8 u8Input = E_CTL_INPUT_TSP_NONE;
4432 switch (pCtrl->eStream)
4433 {
4434 case E_HVD_ORIGINAL_MAIN_STREAM:
4435 u8Input = E_CTL_INPUT_TSP_0;
4436 break;
4437 case E_HVD_ORIGINAL_SUB_STREAM:
4438 u8Input = E_CTL_INPUT_TSP_1;
4439 break;
4440 case E_HVD_ORIGINAL_N_STREAM:
4441 default:
4442 u8Input = E_CTL_INPUT_TSP_NONE;
4443 break;
4444 }
4445
4446 pShm->u8InputTSP = u8Input;
4447
4448 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
4449 }
4450 }
4451 else
4452 {
4453 HVD_EX_MSG_DBG("[NDec][0x%x][%d] not TSP input, ignore PRESET_CONNECT_INPUT_TSP \n", u32Id, u8Idx);
4454 }
4455
4456 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4457 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4458 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4459 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4460 else
4461 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4462 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4463 {
4464 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4465 {
4466 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4467 }
4468 else
4469 {
4470 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4471 }
4472 }
4473 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4474 {
4475 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4476 {
4477 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4478 }
4479 else
4480 {
4481 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4482 }
4483 }
4484 else
4485 {
4486 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4487 }
4488
4489 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4490 {
4491 pShm->bHVDIMIEnable = TRUE;
4492 }
4493
4494 #if 0
4495 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bEnableDynamicCMA)
4496 {
4497 pShm->u8CodecFeature |= E_VDEC_DYNAMIC_CMA_MODE;
4498 }
4499 #endif
4500
4501 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4502 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4503 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4504 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4505 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4506 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4507 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4508 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4509 (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4510 {
4511 pShm->bUseWbMvop = 1;
4512 }
4513
4514 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
4515 E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4516 {
4517 #if 0 // Disable Fluidplay
4518 pShm->u8CodecFeature |= E_VDEC_TEMPORAL_SCALABILITY_MODE;
4519 #endif
4520 }
4521
4522 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4523
4524 #if (VPU_FORCE_MIU_MODE)
4525 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4526
4527 pShm->u32FWBaseAddr = u32TmpStartOffset;
4528
4529 #else
4530 ///TODO:
4531 /*
4532 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4533
4534 if(u8TmpMiuSel == E_CHIP_MIU_0)
4535 {
4536 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4537 }
4538 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4539 {
4540 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4541 }
4542 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4543 {
4544 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4545 }
4546 */
4547 #endif
4548 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4549 #else
4550 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4551 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4552 {
4553 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4554 }
4555 pShm->u32FWBaseAddr = u32Addr;
4556 #endif
4557
4558 // RM only
4559 #if HVD_ENABLE_RV_FEATURE
4560 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4561 && (pCtrl->InitParams.pRVFileInfo != NULL))
4562 {
4563 MS_U32 i = 0;
4564
4565 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4566 {
4567 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4568 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4569 }
4570
4571 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4572 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4573 #ifdef VDEC3_FB
4574 pShm->u32RM_VLCTableAddr = 0;
4575 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4576 #else
4577 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
4578
4579 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4580 u32Addr = u32TmpStartOffset;
4581
4582 pShm->u32RM_VLCTableAddr = u32Addr;
4583 #endif
4584 }
4585 #endif
4586
4587 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4588 && (pCtrl->InitParams.pRVFileInfo != NULL))
4589 {
4590 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4591 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4592 }
4593
4594 //if(pCtrl->InitParams.bColocateBBUMode)
4595 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4596 {
4597 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4598 }
4599
4600 #if SUPPORT_G2VP9
4601 // Enable SW detile support for G2 VP9
4602 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4603 {
4604 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4605 }
4606 #endif
4607
4608 HAL_HVD_EX_FlushMemory();
4609
4610 return E_HVD_RETURN_SUCCESS;
4611 }
4612 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4613 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4614 #else
4615 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4616 #endif
4617 {
4618 MS_BOOL bInitRet = FALSE;
4619
4620 #if 0
4621 // check MVD power on
4622 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4623 {
4624 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4625 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4626 HVD_Delay_ms(1);
4627 }
4628 // Check VPU power on
4629 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4630 {
4631 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4632 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4633 HVD_Delay_ms(1);
4634 }
4635 // check HVD power on
4636 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4637 {
4638 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4639 HAL_HVD_EX_PowerCtrl(TRUE);
4640 HVD_Delay_ms(1);
4641 }
4642 #endif
4643 #ifdef VDEC3
4644 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4645 #else
4646 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4647 #endif
4648 if (!bInitRet)
4649 {
4650 return E_HVD_RETURN_FAIL;
4651 }
4652
4653 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4654
4655 if (!bInitRet)
4656 {
4657 return E_HVD_RETURN_FAIL;
4658 }
4659
4660 return E_HVD_RETURN_SUCCESS;
4661 }
4662
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4663 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4664 {
4665 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4666
4667 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4668
4669 return E_HVD_RETURN_SUCCESS;
4670 }
4671
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)4672 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
4673 {
4674 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4675 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4676 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4677 MS_BOOL bMVC = FALSE;
4678 #if HVD_ENABLE_MVC
4679 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4680 #endif
4681
4682 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4683 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
4684
4685 switch (u32type)
4686 {
4687 // share memory
4688 // switch
4689 case E_HVD_SDATA_FRAMEBUF_ADDR:
4690 {
4691 pShm->u32FrameBufAddr = u32Data;
4692 break;
4693 }
4694 case E_HVD_SDATA_FRAMEBUF_SIZE:
4695 {
4696 pShm->u32FrameBufSize = u32Data;
4697 break;
4698 }
4699 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4700 {
4701 pShm->u32FrameBuf2Addr = u32Data;
4702 break;
4703 }
4704 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4705 {
4706 pShm->u32FrameBuf2Size = u32Data;
4707 break;
4708 }
4709 case E_HVD_SDATA_MAX_CMA_SIZE:
4710 {
4711 pShm->u32MaxCMAFrameBufSize = u32Data;
4712 break;
4713 }
4714 case E_HVD_SDATA_MAX_CMA_SIZE2:
4715 {
4716 pShm->u32MaxCMAFrameBuf2Size = u32Data;
4717 break;
4718 }
4719 case E_HVD_SDATA_CMA_USED:
4720 {
4721 pShm->bCMA_Use = u32Data;
4722 break;
4723 }
4724 case E_HVD_SDATA_CMA_ALLOC_DONE:
4725 {
4726 pShm->bCMA_AllocDone = u32Data;
4727 break;
4728 }
4729 case E_HVD_SDATA_CMA_TWO_MIU:
4730 {
4731 pShm->bCMA_TwoMIU = u32Data;
4732 break;
4733 }
4734 case E_HVD_SDATA_RM_PICTURE_SIZES:
4735 {
4736 if(u32Data != NULL)
4737 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4738 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4739 break;
4740 }
4741 case E_HVD_SDATA_ERROR_CODE:
4742 {
4743 pShm->u16ErrCode = (MS_U16) u32Data;
4744 break;
4745 }
4746 case E_HVD_SDATA_DISP_INFO_TH:
4747 {
4748 if(u32Data != NULL)
4749 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4750 sizeof(HVD_DISP_THRESHOLD));
4751 break;
4752 }
4753 case E_HVD_SDATA_FW_FLUSH_STATUS:
4754 {
4755 pShm->u8FlushStatus = (MS_U8)u32Data;
4756 break;
4757 }
4758 case E_HVD_SDATA_DMX_FRAMERATE:
4759 {
4760 pShm->u32DmxFrameRate = u32Data;
4761 break;
4762 }
4763 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4764 {
4765 pShm->u32DmxFrameRateBase = u32Data;
4766 break;
4767 }
4768 case E_HVD_SDATA_MIU_SEL:
4769 {
4770 pShm->u32VDEC_MIU_SEL = u32Data;
4771 break;
4772 }
4773 case E_HVD_SDATA_DV_XC_SHM_SIZE:
4774 {
4775 pShm->u32DolbyVisionXCShmSize = u32Data;
4776 break;
4777 }
4778 // SRAM
4779
4780 // Mailbox
4781 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4782 {
4783 if (u32Data != 0)
4784 {
4785 pShm->bEnableDispCtrl = TRUE;
4786 pShm->bIsTrigDisp = TRUE;
4787 }
4788 else
4789 {
4790 pShm->bEnableDispCtrl = FALSE;
4791 }
4792
4793 break;
4794 }
4795 case E_HVD_SDATA_GET_DISP_INFO_START:
4796 {
4797 pShm->bSpsChange = FALSE;
4798 break;
4799 }
4800 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4801 {
4802 pShm->u32VirtualBoxWidth = u32Data;
4803 break;
4804 }
4805 case E_HVD_SDATA_DV_INFO:
4806 {
4807 pShm->u8DVLevelFromDriverAPI = (MS_U8)(u32Data & 0xff);
4808 pShm->u8DVProfileFromDriverAPI = (MS_U8)((u32Data >> 8) & 0xff);
4809 pShm->u8DolbyMetaReorder = (MS_U8)((u32Data >> 16) & 0xff);
4810
4811 break;
4812 }
4813 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4814 {
4815 pShm->u32VirtualBoxHeight = u32Data;
4816 break;
4817 }
4818 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4819 {
4820 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4821 {
4822 //printf("DispFrame DqPtr: %d\n", u32Data);
4823 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4824 }
4825 break;
4826 }
4827 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4828 {
4829 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
4830 {
4831 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4832 {
4833 //printf("DispFrame DqPtr: %ld\n", u32Data);
4834 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4835 }
4836 }
4837 break;
4838 }
4839 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4840 {
4841 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4842 {
4843 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
4844 {
4845 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4846 {
4847 //ALOGE("R1: %x", u32Data);
4848 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
4849 }
4850 else
4851 {
4852 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4853 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4854 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
4855 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4856 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4857 }
4858 }
4859 else
4860 {
4861 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4862 }
4863 }
4864 else
4865 {
4866 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4867 {
4868 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4869 }
4870 }
4871 break;
4872 }
4873 #if (HVD_ENABLE_IQMEM)
4874 case E_HVD_SDATA_FW_IQMEM_CTRL:
4875 {
4876 pShm->u8IQmemCtrl= (MS_U8)u32Data;
4877 break;
4878
4879 }
4880 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
4881 {
4882 if (u32Data != 0)
4883 {
4884 pShm->bIQmemEnableIfSupport= TRUE;
4885 }
4886 else
4887 {
4888 pShm->bIQmemEnableIfSupport= FALSE;
4889 }
4890
4891
4892 break;
4893
4894 }
4895 #endif
4896 case E_HVD_SDATA_DYNMC_DISP_PATH_STATUS:
4897 {
4898 pShm->stDynmcDispPath.u8ConnectStatus = u32Data;
4899 break;
4900 }
4901 case E_HVD_SDATA_VP9HDR10INFO:
4902 {
4903 int i,j;
4904 HVD_Config_VP9HDR10* stVP9HDR10Info = (HVD_Config_VP9HDR10*) u32Data;
4905
4906 pShm->VP9HDR10Info.u32Version = stVP9HDR10Info->u32Version;
4907 pShm->VP9HDR10Info.u8MatrixCoefficients = stVP9HDR10Info->u8MatrixCoefficients;
4908 pShm->VP9HDR10Info.u8BitsPerChannel = stVP9HDR10Info->u8BitsPerChannel;
4909 pShm->VP9HDR10Info.u8ChromaSubsamplingHorz = stVP9HDR10Info->u8ChromaSubsamplingHorz;
4910 pShm->VP9HDR10Info.u8ChromaSubsamplingVert = stVP9HDR10Info->u8ChromaSubsamplingVert;
4911 pShm->VP9HDR10Info.u8CbSubsamplingHorz = stVP9HDR10Info->u8CbSubsamplingHorz;
4912 pShm->VP9HDR10Info.u8CbSubsamplingVert = stVP9HDR10Info->u8CbSubsamplingVert;
4913 pShm->VP9HDR10Info.u8ChromaSitingHorz = stVP9HDR10Info->u8ChromaSitingHorz;
4914 pShm->VP9HDR10Info.u8ChromaSitingVert = stVP9HDR10Info->u8ChromaSitingVert;
4915 pShm->VP9HDR10Info.u8ColorRange = stVP9HDR10Info->u8ColorRange;
4916 pShm->VP9HDR10Info.u8TransferCharacteristics = stVP9HDR10Info->u8TransferCharacteristics;
4917 pShm->VP9HDR10Info.u8ColourPrimaries = stVP9HDR10Info->u8ColourPrimaries;
4918 pShm->VP9HDR10Info.u16MaxCLL = stVP9HDR10Info->u16MaxCLL;
4919 pShm->VP9HDR10Info.u16MaxFALL = stVP9HDR10Info->u16MaxFALL;
4920 pShm->VP9HDR10Info.u32MaxLuminance = stVP9HDR10Info->u32MaxLuminance;
4921 pShm->VP9HDR10Info.u32MinLuminance = stVP9HDR10Info->u32MinLuminance;
4922
4923 for(i=0;i<2;i++)
4924 {
4925 pShm->VP9HDR10Info.u16WhitePoint[i] = stVP9HDR10Info->u16WhitePoint[i];
4926 }
4927
4928 for(i=0;i<3;i++)
4929 {
4930 for(j=0;j<2;j++)
4931 {
4932 pShm->VP9HDR10Info.u16Primaries[i][j] = stVP9HDR10Info->u16Primaries[i][j];
4933 }
4934 }
4935 pShm->u8VP9HDR10InfoVaild = TRUE;
4936 break;
4937 }
4938 default:
4939 break;
4940 }
4941
4942 HAL_HVD_EX_FlushMemory();
4943
4944 return eRet;
4945 }
4946
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4947 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4948 {
4949 MS_S64 s64Ret = 0;
4950 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4951
4952 HAL_HVD_EX_ReadMemory();
4953
4954 switch (eType)
4955 {
4956 case E_HVD_GDATA_PTS_STC_DIFF:
4957 s64Ret = pShm->s64PtsStcDiff;
4958 break;
4959 default:
4960 break;
4961 }
4962
4963 return s64Ret;
4964 }
4965
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4966 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4967 {
4968 MS_VIRT u32Ret = 0;
4969 //static MS_U64 u64pts_real = 0;
4970 MS_U64 u64pts_low = 0;
4971 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4972 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4973
4974 HAL_HVD_EX_ReadMemory();
4975
4976 if(pShm == NULL)
4977 {
4978 printf("########## VDEC patch for Debug ###########\n");
4979 return 0x0;
4980 }
4981
4982 switch (eType)
4983 {
4984 // share memory
4985 // switch
4986 case E_HVD_GDATA_DISP_INFO_ADDR:
4987 {
4988 u32Ret = (MS_VIRT) (&pShm->DispInfo);
4989 break;
4990 }
4991 case E_HVD_GDATA_MIU_SEL:
4992 u32Ret = pShm->u32VDEC_MIU_SEL;
4993 break;
4994 case E_HVD_GDATA_FRAMEBUF_ADDR:
4995 u32Ret = pShm->u32FrameBufAddr;
4996 break;
4997 case E_HVD_GDATA_FRAMEBUF_SIZE:
4998 u32Ret = pShm->u32FrameBufSize;
4999 break;
5000 case E_HVD_GDATA_FRAMEBUF2_ADDR:
5001 u32Ret = pShm->u32FrameBuf2Addr;
5002 break;
5003 case E_HVD_GDATA_FRAMEBUF2_SIZE:
5004 u32Ret = pShm->u32FrameBuf2Size;
5005 break;
5006 case E_HVD_GDATA_CMA_ALLOC_DONE:
5007 u32Ret = pShm->bCMA_AllocDone;
5008 break;
5009 case E_HVD_GDATA_CMA_USED:
5010 u32Ret = pShm->bCMA_Use;
5011 break;
5012 case E_HVD_GDATA_DYNMC_DISP_PATH_STATUS:
5013 u32Ret = pShm->stDynmcDispPath.u8ConnectStatus;//pShm->u8SetDynmcDispPathStatus;
5014 break;
5015 // report
5016 case E_HVD_GDATA_PTS:
5017 {
5018 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
5019 break;
5020 }
5021 case E_HVD_GDATA_U64PTS:
5022 {
5023 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
5024 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
5025 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
5026 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
5027 break;
5028 }
5029 case E_HVD_GDATA_U64PTS_PRE_PARSE:
5030 {
5031 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
5032 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
5033 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
5034 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
5035 break;
5036 }
5037 case E_HVD_GDATA_DECODE_CNT:
5038 {
5039 u32Ret = pShm->u32DecodeCnt;
5040 break;
5041 }
5042 case E_HVD_GDATA_DATA_ERROR_CNT:
5043 {
5044 u32Ret = pShm->u32DataErrCnt;
5045 break;
5046 }
5047 case E_HVD_GDATA_DEC_ERROR_CNT:
5048 {
5049 u32Ret = pShm->u32DecErrCnt;
5050 break;
5051 }
5052 case E_HVD_GDATA_ERROR_CODE:
5053 {
5054 u32Ret = (MS_U32) (pShm->u16ErrCode);
5055 break;
5056 }
5057 case E_HVD_GDATA_VPU_IDLE_CNT:
5058 {
5059 u32Ret = pShm->u32VPUIdleCnt;
5060 break;
5061 }
5062 case E_HVD_GDATA_DISP_FRM_INFO:
5063 {
5064 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
5065 break;
5066 }
5067 case E_HVD_GDATA_DEC_FRM_INFO:
5068 {
5069 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
5070 break;
5071 }
5072 case E_HVD_GDATA_ES_LEVEL:
5073 {
5074 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
5075 break;
5076 }
5077 #if HVD_ENABLE_MVC
5078 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
5079 {
5080 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
5081 break;
5082 }
5083 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
5084 {
5085 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
5086 break;
5087 }
5088 #endif
5089
5090 // user data
5091 case E_HVD_GDATA_USERDATA_WPTR:
5092 {
5093 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
5094 break;
5095 }
5096 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
5097 {
5098 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
5099 break;
5100 }
5101 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
5102 {
5103 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
5104 break;
5105 }
5106 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
5107 {
5108 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
5109 break;
5110 }
5111 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
5112 {
5113 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
5114 break;
5115 }
5116 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
5117 {
5118 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
5119 break;
5120 }
5121 // report - modes
5122 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
5123 {
5124 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
5125 break;
5126 }
5127 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
5128 {
5129 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
5130 break;
5131 }
5132 case E_HVD_GDATA_IS_ERR_CONCEAL:
5133 {
5134 u32Ret = pShm->ModeStatus.bIsErrConceal;
5135 break;
5136 }
5137 case E_HVD_GDATA_IS_SYNC_ON:
5138 {
5139 u32Ret = pShm->ModeStatus.bIsSyncOn;
5140 break;
5141 }
5142 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
5143 {
5144 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
5145 break;
5146 }
5147 case E_HVD_GDATA_SYNC_MODE:
5148 {
5149 u32Ret = pShm->ModeStatus.u8SyncType;
5150 break;
5151 }
5152 case E_HVD_GDATA_SKIP_MODE:
5153 {
5154 u32Ret = pShm->ModeStatus.u8SkipMode;
5155 break;
5156 }
5157 case E_HVD_GDATA_DROP_MODE:
5158 {
5159 u32Ret = pShm->ModeStatus.u8DropMode;
5160 break;
5161 }
5162 case E_HVD_GDATA_DISPLAY_DURATION:
5163 {
5164 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
5165 break;
5166 }
5167 case E_HVD_GDATA_FRC_MODE:
5168 {
5169 u32Ret = pShm->ModeStatus.u8FrcMode;
5170 break;
5171 }
5172 case E_HVD_GDATA_NEXT_PTS:
5173 {
5174 u32Ret = pShm->u32NextPTS;
5175 break;
5176 }
5177 case E_HVD_GDATA_DISP_Q_SIZE:
5178 {
5179 u32Ret = pShm->u16DispQSize;
5180 break;
5181 }
5182 case E_HVD_GDATA_DISP_Q_PTR:
5183 {
5184 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
5185 break;
5186 }
5187 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
5188 {
5189 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
5190 break;
5191 }
5192 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
5193 {
5194 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
5195 break;
5196 }
5197 case E_HVD_GDATA_REAL_FRAMERATE:
5198 {
5199 // return VPS/VUI timing info framerate, and 0 if timing info not exist
5200 u32Ret = pShm->u32RealFrameRate;
5201 break;
5202 }
5203 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
5204 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
5205 break;
5206 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
5207 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
5208 break;
5209 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
5210 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
5211 break;
5212 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
5213 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
5214 break;
5215 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
5216 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
5217 break;
5218 case E_HVD_GDATA_FW_STATUS_FLAG:
5219 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
5220 break;
5221
5222 // internal control
5223 case E_HVD_GDATA_IS_1ST_FRM_RDY:
5224 {
5225 u32Ret = pShm->bIs1stFrameRdy;
5226 break;
5227 }
5228 case E_HVD_GDATA_IS_I_FRM_FOUND:
5229 {
5230 u32Ret = pShm->bIsIFrmFound;
5231 break;
5232 }
5233 case E_HVD_GDATA_IS_SYNC_START:
5234 {
5235 u32Ret = pShm->bIsSyncStart;
5236 break;
5237 }
5238 case E_HVD_GDATA_IS_SYNC_REACH:
5239 {
5240 u32Ret = pShm->bIsSyncReach;
5241 break;
5242 }
5243 case E_HVD_GDATA_FW_VERSION_ID:
5244 {
5245 u32Ret = pShm->u32FWVersionID;
5246 break;
5247 }
5248 case E_HVD_GDATA_FW_IF_VERSION_ID:
5249 {
5250 u32Ret = pShm->u32FWIfVersionID;
5251 break;
5252 }
5253 case E_HVD_GDATA_BBU_Q_NUMB:
5254 {
5255 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
5256 break;
5257 }
5258 case E_HVD_GDATA_DEC_Q_NUMB:
5259 {
5260 u32Ret = pShm->u16DecQNumb;
5261 break;
5262 }
5263 case E_HVD_GDATA_DISP_Q_NUMB:
5264 {
5265 u32Ret = pShm->u16DispQNumb;
5266 break;
5267 }
5268 case E_HVD_GDATA_PTS_Q_NUMB:
5269 {
5270 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
5271 break;
5272 }
5273 case E_HVD_GDATA_FW_INIT_DONE:
5274 {
5275 u32Ret = pShm->bInitDone;
5276 break;
5277 }
5278 // debug
5279 case E_HVD_GDATA_SKIP_CNT:
5280 {
5281 u32Ret = pShm->u32SkipCnt;
5282 break;
5283 }
5284 case E_HVD_GDATA_GOP_CNT:
5285 {
5286 u32Ret = pShm->u32DropCnt;
5287 break;
5288 }
5289 case E_HVD_GDATA_DISP_CNT:
5290 {
5291 u32Ret = pShm->u32DispCnt;
5292 break;
5293 }
5294 case E_HVD_GDATA_DROP_CNT:
5295 {
5296 u32Ret = pShm->u32DropCnt;
5297 break;
5298 }
5299 case E_HVD_GDATA_DISP_STC:
5300 {
5301 u32Ret = pShm->u32DispSTC;
5302 break;
5303 }
5304 case E_HVD_GDATA_VSYNC_CNT:
5305 {
5306 u32Ret = pShm->u32VsyncCnt;
5307 break;
5308 }
5309 case E_HVD_GDATA_MAIN_LOOP_CNT:
5310 {
5311 u32Ret = pShm->u32MainLoopCnt;
5312 break;
5313 }
5314
5315 // AVC
5316 case E_HVD_GDATA_AVC_LEVEL_IDC:
5317 {
5318 u32Ret = pShm->u16AVC_SPS_LevelIDC;
5319 break;
5320 }
5321 case E_HVD_GDATA_AVC_LOW_DELAY:
5322 {
5323 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
5324 break;
5325 }
5326 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
5327 {
5328 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
5329 break;
5330 }
5331 case E_HVD_GDATA_FW_FLUSH_STATUS:
5332 {
5333 u32Ret = (MS_U32) (pShm->u8FlushStatus);
5334 break;
5335 }
5336 case E_HVD_GDATA_FW_CODEC_TYPE:
5337 {
5338 u32Ret = pShm->u32CodecType;
5339 break;
5340 }
5341 case E_HVD_GDATA_FW_ES_BUF_STATUS:
5342 {
5343 u32Ret = (MS_U32)pShm->u8ESBufStatus;
5344 break;
5345 }
5346 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
5347 {
5348 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
5349 {
5350 u32Ret = 1;
5351 }
5352 else
5353 {
5354 u32Ret = 0;
5355 }
5356 break;
5357 }
5358
5359 // SRAM
5360
5361 // Mailbox
5362 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
5363 {
5364 u32Ret = pShm->u32FwState;
5365 break;
5366 }
5367 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
5368 {
5369 u32Ret = pShm->bSpsChange;
5370 break;
5371 }
5372 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
5373 {
5374 u32Ret = pShm->bSpsChange;
5375
5376 if (pShm->bSpsChange &&
5377 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
5378 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
5379 {
5380 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
5381 }
5382
5383 break;
5384 }
5385 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
5386 {
5387 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5388
5389 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
5390 {
5391 u32Ret = pShm->u32FwInfo;
5392 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
5393 }
5394 break;
5395 }
5396 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
5397 {
5398 if (pShm->bIsTrigDisp) // not clear yet
5399 {
5400 u32Ret = FALSE;
5401 }
5402 else
5403 {
5404 u32Ret = TRUE;
5405 }
5406 break;
5407 }
5408 case E_HVD_GDATA_ES_READ_PTR:
5409 {
5410 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5411 break;
5412 }
5413 case E_HVD_GDATA_ES_WRITE_PTR:
5414 {
5415 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
5416 break;
5417 }
5418 case E_HVD_GDATA_BBU_READ_PTR:
5419 {
5420 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
5421 break;
5422 }
5423 case E_HVD_GDATA_BBU_WRITE_PTR:
5424 {
5425 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5426 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5427 {
5428 u32Ret = pHVDHalContext->u32VP8BBUWptr;
5429 }
5430 else
5431 {
5432 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5433 }
5434 break;
5435 }
5436 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
5437 {
5438 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5439
5440 u32Ret = pCtrl->u32BBUWptr_Fired;
5441
5442 break;
5443 }
5444 case E_HVD_GDATA_VPU_PC_CNT:
5445 {
5446 u32Ret = _HVD_EX_GetPC();
5447 break;
5448 }
5449 case E_HVD_GDATA_ES_QUANTITY:
5450 {
5451 u32Ret=_HVD_EX_GetESQuantity(u32Id);
5452 break;
5453 }
5454
5455
5456 // FW def
5457 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
5458 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
5459 break;
5460
5461 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
5462 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
5463 break;
5464 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
5465 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
5466 break;
5467 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
5468 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5469 break;
5470 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
5471 u32Ret = MAX_PTS_TABLE_SIZE;
5472 break;
5473 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
5474 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
5475 break;
5476 case E_HVD_GDATA_FW_DS_BUF_ADDR:
5477 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
5478 break;
5479 case E_HVD_GDATA_FW_DS_BUF_SIZE:
5480 u32Ret = pShm->u32DSBuffSize; //3k or 6k
5481 break;
5482 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
5483 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
5484 break;
5485 case E_HVD_GDATA_FW_DS_INFO_ADDR:
5486 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
5487 break;
5488 case E_HVD_GDATA_FW_DS_IS_ENABLED:
5489 {
5490 if (pShm->bDSIsRunning)
5491 {
5492 u32Ret = TRUE;
5493 }
5494 else
5495 {
5496 u32Ret = FALSE;
5497 }
5498 break;
5499 }
5500 #if (HVD_ENABLE_IQMEM)
5501 case E_HVD_GDATA_FW_IQMEM_CTRL:
5502 {
5503
5504 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
5505
5506 break;
5507 }
5508 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
5509 {
5510 if(pShm->bIsIQMEMSupport){
5511 u32Ret = TRUE;
5512 }
5513 else{
5514
5515 u32Ret = FALSE;
5516 }
5517
5518 break;
5519 }
5520 #endif
5521 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
5522 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
5523 break;
5524 case E_HVD_GDATA_FIELD_PIC_FLAG:
5525 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
5526 break;
5527 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
5528 u32Ret = pShm->u32SeamlessTSStatus;
5529 break;
5530 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
5531 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
5532 break;
5533 #ifdef VDEC3
5534 case E_HVD_GDATA_FW_VBBU_ADDR:
5535 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
5536 break;
5537 #endif
5538 case E_HVD_GDATA_SEQ_CHANGE_INFO:
5539 u32Ret = (MS_U32)pShm->u32SeqChangeInfo;
5540 break;
5541 default:
5542 break;
5543 }
5544 return u32Ret;
5545 }
5546
HAL_HVD_EX_GetDVSupportProfiles(void)5547 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
5548 {
5549 #if 0 // wait avc finish DV dual job
5550 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5551 #else
5552 return E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5553 #endif
5554 }
5555
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)5556 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
5557 {
5558 switch (u32DV_Stream_Profile)
5559 {
5560 #if 0 // wait avc finish DV dual job
5561 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
5562 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
5563 #endif
5564
5565 #if 0 // unsupported profile
5566 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
5567 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5568 #endif
5569
5570 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
5571 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5572
5573 #if 0 // unsupported profile
5574 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
5575 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5576 #endif
5577
5578 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
5579 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5580
5581 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
5582 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5583
5584 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
5585 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5586
5587 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
5588 default:
5589 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5590 }
5591 }
5592
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)5593 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
5594 {
5595 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5596 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
5597 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5598 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5599 {
5600 // skip mutex
5601 }
5602 else
5603 {
5604 _HAL_HVD_Entry();
5605 }
5606 // check if old SVD cmds
5607 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5608 {
5609 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
5610
5611 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5612 {
5613 return E_HVD_RETURN_INVALID_PARAMETER;
5614 }
5615 else
5616 {
5617 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5618 }
5619 }
5620
5621 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5622 {
5623 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5624 }
5625
5626 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5627 {
5628 if (u32Cmd == E_HVD_CMD_FLUSH)
5629 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5630 }
5631
5632 if (u32Cmd == E_HVD_CMD_FLUSH &&
5633 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5634 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5635 {
5636 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5637 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5638 {
5639 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5640 {
5641 HVD_Delay_ms(1);
5642 }
5643 else
5644 {
5645 _HAL_HVD_Release();
5646 HVD_Delay_ms(1);
5647 _HAL_HVD_Entry();
5648 }
5649 }
5650 }
5651
5652 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
5653
5654 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5655 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5656 {
5657 return eRet;
5658 }
5659 else
5660 {
5661 _HAL_HVD_Return(eRet);
5662 }
5663 }
5664
HAL_HVD_EX_DeInit(MS_U32 u32Id)5665 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5666 {
5667 HVD_Return eRet = E_HVD_RETURN_FAIL;
5668 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5669 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5670 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5671 MS_U8 u8MiuSel;
5672 MS_U32 u32StartOffset;
5673 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5674
5675 #if HVD_ENABLE_TIME_MEASURE
5676 MS_U32 ExitTimeCnt = 0;
5677 ExitTimeCnt = HVD_GetSysTime_ms();
5678 #endif
5679
5680 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
5681
5682 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5683
5684 if (E_HVD_RETURN_SUCCESS != eRet)
5685 {
5686 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5687 }
5688
5689 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5690
5691 if (E_HVD_RETURN_SUCCESS != eRet)
5692 {
5693 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5694 }
5695
5696 // check FW state to make sure it's STOP DONE
5697 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5698 {
5699 if (HVD_GetSysTime_ms() > u32Timeout)
5700 {
5701 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
5702
5703 //return E_HVD_RETURN_TIMEOUT;
5704 eRet = E_HVD_RETURN_TIMEOUT;
5705 break;
5706 }
5707 }
5708
5709 if (pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt)
5710 {
5711 HVD_EX_MSG_INF("VDEC PLUS: DropRatio %d, Drop:0.%d (%d), Dec:0.%d (%d), Disp:0.%d\n",
5712 pShm->u8VdecPlusDropRatio,
5713 100*pShm->u32VdecPlusDropCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5714 pShm->u32VdecPlusDropCnt,
5715 100*pShm->u32VdecPlusDecCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5716 pShm->u32VdecPlusDecCnt,
5717 100*pShm->u32VdecPlusDispPicCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt));
5718 }
5719 else
5720 {
5721 HVD_EX_MSG_INF("VDEC PLUS DISABLE: DropRatio %d, Drop: %d, Dec: %d, Disp: %d\n",
5722 pShm->u8VdecPlusDropRatio,
5723 pShm->u32VdecPlusDropCnt,
5724 pShm->u32VdecPlusDecCnt,
5725 pShm->u32VdecPlusDispPicCnt);
5726 }
5727
5728 VPU_EX_FWCodeCfg fwCfg;
5729 VPU_EX_TaskInfo taskInfo;
5730 VPU_EX_NDecInitPara nDecInitPara;
5731
5732 nDecInitPara.pFWCodeCfg = &fwCfg;
5733 nDecInitPara.pTaskInfo = &taskInfo;
5734
5735 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5736 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5737
5738 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);//power control
5739 #if 0
5740 taskInfo.u32Id = u32Id;
5741 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5742 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5743 #endif
5744
5745 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5746 {
5747 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5748 }
5749 else
5750 {
5751 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5752 }
5753
5754 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5755 {
5756 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5757 }
5758
5759 /* clear es buffer */
5760 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5761 {
5762 //printf("Clear ES buffer\n");
5763
5764 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5765 }
5766
5767 //_HAL_HVD_MutexDelete();
5768
5769 #if HVD_ENABLE_TIME_MEASURE
5770 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5771 #endif
5772
5773 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
5774 #ifndef VDEC3
5775 // reset bbu wptr
5776 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5777 {
5778 if(TRUE == HAL_VPU_EX_HVDInUsed())
5779 {
5780 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5781 {
5782 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5783 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5784 }
5785 else
5786 {
5787 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5788 {
5789 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5790 }
5791 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5792 }
5793 }
5794 else
5795 {
5796 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
5797 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
5798 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
5799 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5800 {
5801 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5802 {
5803 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5804 }
5805 }
5806 else
5807 {
5808 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5809 }
5810 }
5811 }
5812 #endif
5813 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5814
5815 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5816 {
5817 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
5818 }
5819
5820 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
5821 {
5822
5823 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
5824
5825 _HAL_HVD_Entry();
5826 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
5827 _HAL_HVD_Release();
5828
5829 }
5830
5831 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
5832 HVD_EX_MSG_DBG("success\n");
5833
5834 return eRet;
5835 }
5836
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5837 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5838 {
5839 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5840 MS_U32 u32Addr = 0;
5841 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5842 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5843
5844 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5845
5846 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5847 {
5848 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5849
5850 if (E_HVD_RETURN_SUCCESS != eRet)
5851 {
5852 return eRet;
5853 }
5854 }
5855
5856 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5857
5858 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5859 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5860 {
5861 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5862
5863 if (E_HVD_RETURN_SUCCESS != eRet)
5864 {
5865 return eRet;
5866 }
5867 }
5868
5869 u32Addr = pInfo->u32Staddr;
5870
5871 if (pInfo->bRVBrokenPacket)
5872 {
5873 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5874 }
5875
5876 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5877 {
5878 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5879 }
5880 else
5881 {
5882 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5883 }
5884
5885 if (E_HVD_RETURN_SUCCESS != eRet)
5886 {
5887 return eRet;
5888 }
5889
5890 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5891 {
5892 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5893 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5894
5895 if (E_HVD_RETURN_SUCCESS != eRet)
5896 {
5897 return eRet;
5898 }
5899 }
5900
5901 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5902
5903 // do not add local pointer
5904 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5905 {
5906 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5907
5908 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5909 (u32PacketStAddr <
5910 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5911 {
5912 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5913 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5914 }
5915 else
5916 {
5917 //null packet
5918 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5919 pCtrl->LastNal.u32NalSize = 0;
5920 }
5921 }
5922 else
5923 {
5924 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5925 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5926 }
5927
5928 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5929 pCtrl->u32BBUPacketCnt++;
5930
5931 return eRet;
5932 }
5933
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5934 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5935 {
5936 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5937 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5938 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
5939 if(bCurrentStatus == bEnable)
5940 return;
5941
5942 if (bEnable)
5943 {
5944 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5945 }
5946 else
5947 {
5948 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5949 }
5950 }
5951
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5952 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5953 {
5954 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5955 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5956
5957 if (bEnable)
5958 {
5959 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5960 }
5961 else
5962 {
5963 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5964 }
5965 }
5966
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)5967 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
5968 {
5969 MS_U32 u32RB = 0;
5970 switch(eISRType)
5971 {
5972 case E_HWDEC_ISR_HVD:
5973 u32RB = REG_HVD_BASE;
5974 break;
5975 #if SUPPORT_EVD
5976 case E_HWDEC_ISR_EVD:
5977 u32RB = REG_EVD_BASE;
5978 break;
5979 #endif
5980 #if SUPPORT_G2VP9
5981 case E_HWDEC_ISR_G2VP9:
5982 break;
5983 #endif
5984 default:
5985 break;
5986 }
5987 if(u32RB)
5988 {
5989 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5990 }
5991 }
5992
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5993 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5994 {
5995 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5996 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5997
5998 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5999 }
6000
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)6001 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
6002 {
6003 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6004 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6005
6006 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
6007 {
6008 return FALSE;
6009 }
6010 else
6011 {
6012 return TRUE;
6013 }
6014 }
6015
HAL_HVD_EX_IsAlive(MS_U32 u32Id)6016 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
6017 {
6018 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6019
6020 if (pCtrl)
6021 {
6022 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
6023 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
6024 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
6025 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
6026 {
6027 return FALSE;
6028 }
6029 else
6030 {
6031 return TRUE;
6032 }
6033 }
6034 else
6035 {
6036 return FALSE;
6037 }
6038 }
6039
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)6040 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
6041 {
6042 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6043 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6044 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6045
6046 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6047 {
6048 HAL_HVD_EX_ReadMemory();
6049
6050 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
6051 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
6052
6053 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
6054 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
6055 }
6056
6057 return TRUE;
6058 }
6059
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)6060 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
6061 {
6062 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6063 HVD_EX_Drv_Ctrl *pCtrl = NULL;
6064 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6065 MS_U32 u32Data;
6066 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6067
6068 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
6069
6070 HAL_HVD_EX_FlushMemory();
6071 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
6072 {
6073 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
6074 pCtrl->LastNal.u32NalAddr = u32Data;
6075 pCtrl->LastNal.u32NalSize = 0;
6076 }
6077
6078 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
6079 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
6080
6081 return TRUE;
6082 }
6083
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)6084 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
6085 {
6086 if (bEnable)
6087 {
6088 if (HAL_VPU_EX_IsEVDR2())
6089 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6090 else
6091 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
6092 }
6093 else
6094 {
6095 #if defined (__aeon__)
6096 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6097 #else // defined (__mips__)
6098 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
6099 #endif
6100 }
6101 }
6102
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)6103 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
6104 {
6105 return 0;
6106 }
6107
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)6108 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
6109 {
6110 return;
6111 }
6112
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)6113 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
6114 {
6115 //if( u16Clock == 0 )
6116 return 216; //140;
6117 //if( )
6118 }
6119
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)6120 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
6121 {
6122 //MS_BOOL bBitMIU1 = FALSE;
6123 //MS_BOOL bCodeMIU1 = FALSE;
6124 MS_U8 u8BitMiuSel = 0;
6125 MS_U8 u8CodeMiuSel = 0;
6126 MS_U32 u32BitStartOffset;
6127 MS_U32 u32CodeStartOffset;
6128 //MS_U8 u8MiuSel;
6129 //MS_U32 u32StartOffset;
6130 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6131 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6132 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6133 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
6134
6135 #if HVD_ENABLE_MVC
6136 if(HAL_HVD_EX_CheckMVCID(u32Id))
6137 {
6138 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
6139 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
6140 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
6141 {
6142 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
6143 }
6144 }
6145 #endif /// HVD_ENABLE_MVC
6146
6147 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6148 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6149
6150
6151
6152
6153 if (u8BitMiuSel != u8CodeMiuSel)
6154 {
6155 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
6156 BDMA_Result bdmaRlt;
6157 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6158
6159 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6160 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
6161 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6162
6163 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
6164
6165 if (E_BDMA_OK != bdmaRlt)
6166 {
6167 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
6168 }
6169 #else
6170 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6171
6172 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6173 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
6174 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6175
6176 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
6177 #endif
6178 }
6179
6180 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
6181
6182 HAL_HVD_EX_FlushMemory();
6183
6184 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6185 {
6186 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
6187 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
6188 }
6189 else
6190 {
6191 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
6192
6193 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
6194 }
6195 }
6196
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)6197 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
6198 {
6199 if (bEnable)
6200 {
6201 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
6202 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
6203 }
6204 else
6205 {
6206 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
6207 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
6208 }
6209 }
6210
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)6211 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
6212 {
6213 MS_U32 tmp1 = 0;
6214 MS_U32 tmp2 = 0;
6215 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6216
6217 HAL_HVD_EX_ReadMemory();
6218
6219 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
6220 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
6221
6222 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6223 {
6224 MS_U32 u32Tmp = u32UartCtrl;
6225
6226 HVD_EX_MSG_DBG("\n");
6227 u32UartCtrl = 0; // turn off debug message to prevent other function prints
6228 printf("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
6229 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
6230
6231 printf("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
6232 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
6233 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
6234 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
6235
6236 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
6237 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
6238 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
6239
6240 printf("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
6241 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
6242 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
6243 _HVD_EX_GetESLevel(u32Id));
6244
6245 printf("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
6246 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
6247 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
6248 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
6249 printf
6250 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
6251 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
6252 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
6253 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
6254 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
6255 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
6256 pShm->ModeStatus.bShowOneField);
6257
6258 u32UartCtrl = u32Tmp; // recover debug level
6259 }
6260 }
6261
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)6262 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
6263 {
6264 MS_U8 *u32Addr = NULL;
6265 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6266 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6267
6268 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6269 {
6270 return;
6271 }
6272
6273 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
6274
6275 *u32NalSize = *(u32Addr + 2) & 0x1f;
6276 *u32NalSize <<= 8;
6277 *u32NalSize |= *(u32Addr + 1) & 0xff;
6278 *u32NalSize <<= 8;
6279 *u32NalSize |= *(u32Addr) & 0xff;
6280
6281 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
6282 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
6283 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
6284 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
6285 }
6286
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)6287 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
6288 {
6289 MS_U32 u32CurIdx = 0;
6290 MS_BOOL bFinished = FALSE;
6291 MS_U32 u32NalOffset = 0;
6292 MS_U32 u32NalSize = 0;
6293 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6294
6295 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
6296 {
6297 return;
6298 }
6299
6300 u32CurIdx = u32StartIdx;
6301
6302 do
6303 {
6304 if (u32CurIdx == u32EndIdx)
6305 {
6306 bFinished = TRUE;
6307 }
6308
6309 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
6310
6311 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
6312 {
6313 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
6314 }
6315
6316 u32CurIdx++;
6317
6318 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6319 {
6320 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
6321 }
6322 } while (bFinished == TRUE);
6323 }
6324
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)6325 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
6326 {
6327 MS_U32 i = 0;
6328 MS_U32 value = 0;
6329
6330 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6331 {
6332 HVD_EX_MSG_DBG("\n");
6333
6334 for (i = 0; i <= u32Num; i++)
6335 {
6336 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
6337 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
6338 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
6339
6340 if (value == 0)
6341 {
6342 break;
6343 }
6344
6345 printf(" %08x", value);
6346
6347 if (((i % 8) + 1) == 8)
6348 {
6349 printf(" |%u\n", i + 1);
6350 }
6351 }
6352
6353 printf("\nHVD Dump HW status End: total number:%u\n", i);
6354 }
6355 }
6356
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)6357 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
6358 {
6359 if (pDrvCtrl)
6360 {
6361 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
6362 }
6363 }
6364
6365 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)6366 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
6367 {
6368 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
6369 }
6370
HAL_HVD_EX_GetView(MS_U32 u32Id)6371 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
6372 {
6373 if( (0xFF & (u32Id >> 8)) == 0x10)
6374 return E_VDEC_EX_MAIN_VIEW;
6375 else
6376 return E_VDEC_EX_SUB_VIEW;
6377 }
6378 #endif ///HVD_ENABLE_MVC
6379
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)6380 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
6381 {
6382 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
6383 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
6384 return;
6385 }
6386
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)6387 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
6388 {
6389 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
6390 return;
6391 }
6392
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)6393 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
6394 {
6395 MS_U64 _hw_max_pixel = 0;
6396 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
6397
6398 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
6399 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
6400 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
6401 }
6402
6403
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)6404 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
6405 {
6406 #if 1
6407 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6408 MS_U16 u16QNum = pShm->u16DispQNumb;
6409 MS_U16 u16QPtr = pShm->u16DispQPtr;
6410 // MS_U16 u16QSize = pShm->u16DispQSize;
6411 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
6412 MS_U32 u32DispQNum = 0;
6413 #if HVD_ENABLE_MVC
6414 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
6415
6416 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6417 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
6418
6419 if(bMVC || bDolbyVision)
6420 {
6421 #if 0
6422 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
6423 {
6424 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
6425 }
6426 #endif
6427
6428 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
6429 //search the next frame to display
6430 while (u16QNum > 0)
6431 {
6432 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
6433 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
6434 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6435
6436 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
6437 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6438 {
6439 /// For MVC. Output views after the pair of (base and depend) views were decoded.
6440 /// Check the depned view was initial when Output the base view.
6441 if((u16QPtr%2) == 0)
6442 {
6443 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
6444 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
6445 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
6446 {
6447 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
6448 ///printf("Return NULL.\n");
6449 break;
6450 }
6451 }
6452 u32DispQNum++;
6453 }
6454
6455 u16QNum--;
6456 //go to next frame in the dispQ
6457 u16QPtr++;
6458
6459 if (u16QPtr >= pShm->u16DispQSize)
6460 {
6461 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
6462 }
6463 }
6464 }
6465 else
6466 #endif ///HVD_ENABLE_MVC
6467 {
6468 #if 0
6469 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
6470 {
6471 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
6472 }
6473 #endif
6474 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
6475 //search the next frame to display
6476 while (u16QNum != 0)
6477 {
6478 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6479
6480 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
6481 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6482 {
6483 u32DispQNum++;
6484 }
6485
6486 u16QNum--;
6487 //go to next frame in the dispQ
6488 u16QPtr++;
6489
6490 if (u16QPtr == pShm->u16DispQSize)
6491 {
6492 u16QPtr = 0; //wrap to the begin
6493 }
6494 }
6495 }
6496
6497 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
6498 return u32DispQNum;
6499 #else
6500 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
6501 return pShm->u16DispQNumb;
6502 #endif
6503 }
6504
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)6505 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
6506 {
6507 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6508 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
6509 (u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
6510 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6511 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
6512 #if SUPPORT_G2VP9 && defined(VDEC3)
6513 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
6514 #else // Not using G2 VP9 implies using Mstar EVD VP9
6515 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6516 #endif
6517 else
6518 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
6519 }
6520
6521 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)6522 void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
6523 {
6524 #ifdef CONFIG_MSTAR_CLKM
6525 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD, bEnable);
6526 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_PPU, bEnable);
6527 #else
6528 if (bEnable)
6529 {
6530 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6531 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6532 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6533 }
6534 else
6535 {
6536 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6537 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6538 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6539 }
6540
6541 switch (pHVDHalContext->u32EVDClockType)
6542 {
6543 case 576:
6544 {
6545 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6546 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6547 break;
6548 }
6549 case 532:
6550 {
6551 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
6552 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
6553 break;
6554 }
6555 case 456:
6556 {
6557 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6558 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6559 _HVD_WriteWordMask(REG_EVDPLL_LOOP_DIV_SECOND, REG_EVDPLL_LOOP_DIV_SECOND_456MHZ, REG_EVDPLL_LOOP_DIV_SECOND_MASK);
6560 break;
6561 }
6562 case 466:
6563 {
6564 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6565 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
6566 break;
6567 }
6568 case 480:
6569 {
6570 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
6571 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6572 break;
6573 }
6574 case 384:
6575 {
6576 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
6577 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
6578 break;
6579 }
6580 case 320:
6581 {
6582 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
6583 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
6584 break;
6585 }
6586 case 240:
6587 {
6588 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
6589 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6590 break;
6591 }
6592 case 192:
6593 {
6594 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
6595 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
6596 break;
6597 }
6598 default:
6599 {
6600 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6601 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6602 break;
6603 }
6604 }
6605 #endif
6606 #ifdef CONFIG_MSTAR_SRAMPD
6607 if (bEnable)
6608 {
6609 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6610 HVD_Delay_ms(1);
6611 }
6612 else
6613 {
6614 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6615 HVD_Delay_ms(1);
6616 }
6617 #endif
6618 return;
6619 }
6620
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)6621 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
6622 {
6623 #ifndef VDEC3
6624 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6625 #endif
6626 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6627 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6628 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6629
6630 #ifdef VDEC3
6631 if (0 == pCtrl->u32BBUId)
6632 #else
6633 if (0 == u8TaskId)
6634 #endif
6635 {
6636 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
6637 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6638 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)) & (~HVD_REG_BBU_TSP_INPUT));
6639 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)));
6640 }
6641 else
6642 {
6643 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
6644 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6645 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)) & (~HVD_REG_BBU_TSP_INPUT_BS2));
6646 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)));
6647 }
6648
6649 return;
6650 }
6651
HAL_EVD_EX_DeinitHW(MS_U32 u32Id)6652 MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id)
6653 {
6654 MS_U16 u16Timeout = 1000;
6655 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6656 MS_BOOL isVP8Used = FALSE;
6657 MS_BOOL isAECUsed = FALSE;
6658 MS_BOOL isAVCUsed = FALSE;
6659 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
6660
6661 if(TRUE == HAL_VPU_EX_EVDInUsed())
6662 {
6663 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6664 {
6665 HAL_AEC_PowerCtrl(FALSE);
6666 }
6667 return FALSE;
6668 }
6669 else if(!isAVCUsed)//no AVC/EVD use , close EVD power
6670 {
6671 _HVD_EX_SetMIUProtectMask(TRUE);
6672
6673 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
6674
6675 while (u16Timeout)
6676 {
6677 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
6678 {
6679 break;
6680 }
6681 u16Timeout--;
6682 }
6683
6684 HAL_EVD_EX_PowerCtrl(u32Id, FALSE);
6685
6686 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6687 {
6688 HAL_AEC_PowerCtrl(FALSE);
6689 }
6690
6691 _HVD_EX_SetMIUProtectMask(FALSE);
6692
6693 return TRUE;
6694 }
6695
6696 return FALSE;
6697
6698 }
6699 #endif
6700
6701 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)6702 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
6703 {
6704 if (bEnable)
6705 {
6706 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6707 }
6708 else
6709 {
6710 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6711 }
6712
6713 switch (pHVDHalContext->u32VP9ClockType)
6714 {
6715 case 432:
6716 {
6717 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6718 break;
6719 }
6720 case 384:
6721 {
6722 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6723 break;
6724 }
6725 case 345:
6726 {
6727 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6728 break;
6729 }
6730 case 320:
6731 {
6732 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6733 break;
6734 }
6735 case 288:
6736 {
6737 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6738 break;
6739 }
6740 case 240:
6741 {
6742 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6743 break;
6744 }
6745 case 216:
6746 {
6747 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6748 break;
6749 }
6750 case 172:
6751 {
6752 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
6753 break;
6754 }
6755 default:
6756 {
6757 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6758 break;
6759 }
6760 }
6761
6762 return;
6763 }
6764
HAL_VP9_EX_DeinitHW(void)6765 MS_BOOL HAL_VP9_EX_DeinitHW(void)
6766 {
6767 MS_U16 u16Timeout = 1000;
6768
6769 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6770
6771 while (u16Timeout)
6772 {
6773 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6774 {
6775 break;
6776 }
6777 u16Timeout--;
6778 }
6779
6780 HAL_VP9_EX_PowerCtrl(FALSE);
6781
6782 return TRUE;
6783 }
6784 #endif
6785
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6786 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6787 {
6788 return TRUE;
6789 }
6790
HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)6791 void HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)
6792 {
6793 MS_VIRT u32StAddr = 0;
6794 MS_U8 u8BitMiuSel = 0;
6795 MS_U8 u8CodeMiuSel = 0;
6796 MS_U8 u8TmpMiuSel = 0;
6797 MS_U32 u32BitStartOffset;
6798 MS_U32 u32CodeStartOffset;
6799
6800 #ifndef VDEC3
6801 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6802 #endif
6803 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6804 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6805 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6806 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6807
6808 _HAL_HVD_Entry();
6809
6810 if (pCtrl == NULL)
6811 {
6812 _HAL_HVD_Return();
6813 }
6814
6815 MS_BOOL bNalTblAlreadySet = FALSE;
6816 VPU_EX_TaskInfo taskInfo;
6817 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
6818 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
6819
6820 bNalTblAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
6821
6822
6823
6824 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6825 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6826
6827 if (u8BitMiuSel != u8CodeMiuSel)
6828 {
6829 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
6830 }
6831 else
6832 {
6833 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
6834 }
6835
6836 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6837 {
6838 #ifdef VDEC3
6839 if (!_HAL_EX_BBU_VP8_InUsed())
6840 #endif
6841 {
6842 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
6843
6844 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
6845 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
6846 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6847
6848 u32StAddr += VP8_BBU_TBL_SIZE;
6849
6850 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
6851 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
6852 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6853 }
6854
6855 _HAL_HVD_Return();
6856 }
6857
6858 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
6859
6860 #ifdef VDEC3
6861 if (!bNalTblAlreadySet)
6862 {
6863 if (pCtrl->u32BBUId == 0)
6864 {
6865 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
6866 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
6867 // -1 is for NAL_TAB_LEN counts from zero.
6868 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6869 }
6870 else
6871 {
6872 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
6873 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
6874 // -1 is for NAL_TAB_LEN counts from zero.
6875 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6876 }
6877 }
6878 #else
6879 if (0 == u8TaskId)
6880 {
6881 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
6882 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
6883 // -1 is for NAL_TAB_LEN counts from zero.
6884 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6885 }
6886 else
6887 {
6888 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
6889 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
6890 // -1 is for NAL_TAB_LEN counts from zero.
6891 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6892 }
6893 #endif
6894
6895
6896 #if (HVD_ENABLE_MVC)
6897 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
6898 {
6899 /// Used sub stream to record sub view data.
6900 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
6901 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
6902
6903 if (u8BitMiuSel != u8CodeMiuSel)
6904 {
6905 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
6906 }
6907 else
6908 {
6909 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
6910 }
6911
6912 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
6913 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
6914 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
6915 // -1 is for NAL_TAB_LEN counts from zero.
6916 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
6917 }
6918 #endif
6919
6920 if (!bNalTblAlreadySet)
6921 {
6922 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
6923 }
6924
6925 _HAL_HVD_Return();
6926 }
6927
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)6928 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6929 {
6930 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6931
6932 if(pCtrl->InitParams.u16ChipECONum == 0)
6933 return FALSE;
6934 else
6935 return TRUE;
6936 }
6937
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6938 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6939 {
6940
6941 }
6942
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6943 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6944 {
6945
6946 }
6947 #else // (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
6948
HAL_HVD_EX_GetVpuShmAddr(MS_U8 u8Idx,MS_PHY pVPUCodecAddr)6949 MS_VIRT HAL_HVD_EX_GetVpuShmAddr(MS_U8 u8Idx, MS_PHY pVPUCodecAddr)
6950 {
6951 MS_PHY u32PhyAddr = 0x0;
6952
6953 if (pVPUCodecAddr == 0)
6954 {
6955 return 0;
6956 }
6957
6958 u32PhyAddr = pVPUCodecAddr + (u8Idx * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
6959
6960 return MsOS_PA2KSEG1(u32PhyAddr);
6961 }
6962 #endif
6963