1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126 #define RV_VLC_TABLE_SIZE 0x20000
127 /* Add for Mobile Platform by Ted Sun */
128 //#define HVD_DISPQ_PREFETCH_COUNT 2
129 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
130 #define VPU_QMEM_BASE 0x20000000UL
131
132 //max support pixel(by chip capacity)
133 #define HVD_HW_MAX_PIXEL (4096*2160*31000ULL) // 4kx2k@30p
134 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
135 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
136
137 #define EVD_HW_BUFFER 0x200000 //0x800000: support MFcodec, 0x200000: not support MFcodec
138
139 #if 0
140 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
141 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
142 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
143 static MS_U16 _u16DispQPtr = 0;
144 #endif
145
146 //---------------------------------- Mutex settings -----------------------------------------
147 #if HAL_HVD_ENABLE_MUTEX_PROTECT
148 #define _HAL_HVD_MutexCreate() \
149 do \
150 { \
151 if (s32HVDMutexID < 0) \
152 { \
153 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
154 } \
155 } while (0)
156
157 #define _HAL_HVD_MutexDelete() \
158 do \
159 { \
160 if (s32HVDMutexID >= 0) \
161 { \
162 OSAL_HVD_MutexDelete(s32HVDMutexID); \
163 s32HVDMutexID = -1; \
164 } \
165 } while (0)
166
167 #define _HAL_HVD_Entry() \
168 do \
169 { \
170 if (s32HVDMutexID >= 0) \
171 { \
172 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
173 { \
174 HVD_PRINT("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
175 } \
176 } \
177 } while (0)
178
179 #define _HAL_HVD_Return(_ret_) \
180 do \
181 { \
182 if (s32HVDMutexID >= 0) \
183 { \
184 OSAL_HVD_MutexRelease(s32HVDMutexID); \
185 } \
186 return _ret_; \
187 } while(0)
188
189 #define _HAL_HVD_Release() \
190 do \
191 { \
192 if (s32HVDMutexID >= 0) \
193 { \
194 OSAL_HVD_MutexRelease(s32HVDMutexID); \
195 } \
196 } while (0)
197 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
198
199 #define _HAL_HVD_MutexCreate()
200 #define _HAL_HVD_MutexDelete()
201 #define _HAL_HVD_Entry()
202 #define _HAL_HVD_Return(_ret) {return _ret;}
203 #define _HAL_HVD_Release()
204
205 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
206
207 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
208 #define IS_TASK_ALIVE(id) ((id) != -1)
209 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
210
211 //------------------------------ MIU SETTINGS ----------------------------------
212 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(6))
213 #define _MaskMiuReq_MVD_RW_RTO( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(1))
214 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(2))
215 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
216 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(5))
217 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(3))
218
219 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(6))
220 #define _MaskMiu1Req_MVD_RW_RTO( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK+1, m, BIT(1))
221 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(2))
222 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(4))
223 #define _MaskMiu1Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(5))
224 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK+1, m, BIT(3))
225
226 #define _MaskMiu2Req_MVD_RW( m ) _HVD_WriteRegBit(MIU2_REG_RQ2_MASK, m, BIT(6))
227 #define _MaskMiu2Req_MVD_RW_RTO( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK+1, m, BIT(1))
228 #define _MaskMiu2Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(2))
229 #define _MaskMiu2Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(4))
230 #define _MaskMiu2Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(5))
231 #define _MaskMiu2Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK+1, m, BIT(3))
232
233
234 #define HVD_MVD_RW_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(6)) == 0))
235 #define HVD_MVD_RW_RTO_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(9)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(9)) == 0))
236 #define HVD_MVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(10)) == 0))
237 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(4)) == 0))
238 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(5)) == 0))
239 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(11)) == 0))
240
241 #define HVD_MVD_RW_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == BIT(6)) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(6)) == 0))
242 #define HVD_MVD_RW_RTO_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(9)) == BIT(9)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(9)) == 0))
243 #define HVD_MVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == BIT(10)) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(10)) == 0))
244 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(4)) == 0))
245 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == BIT(5)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(5)) == 0))
246 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == BIT(11)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(11)) == 0))
247
248 #define HVD_MVD_RW_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(6)) == BIT(6)))
249 #define HVD_MVD_RW_RTO_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(9)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(9)) == BIT(9)))
250 #define HVD_MVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(10)) == BIT(10)))
251 #define HVD_HVD_RW_MIF0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(4)) == BIT(4)))
252 #define HVD_HVD_RW_MIF1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(5)) == BIT(5)))
253 #define HVD_HVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(11)) == BIT(11)))
254
255
256 #if SUPPORT_EVD
257 #define _MaskMiuReq_EVD_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
258 #define _MaskMiuReq_EVD_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(1))
259 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(2))
260 #define _MaskMiuReq_EVD_LITE_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
261 #define _MaskMiuReq_EVD_LITE_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
262 #define _MaskMiuReq_EVD_LITE_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
263
264 #define _MaskMiu1Req_EVD_RW1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
265 #define _MaskMiu1Req_EVD_RW2( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(1))
266 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK+1, m, BIT(2))
267 #define _MaskMiu1Req_EVD_LITE_RW1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
268 #define _MaskMiu1Req_EVD_LITE_RW2( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(3))
269 #define _MaskMiu1Req_EVD_LITE_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
270
271 #define _MaskMiu2Req_EVD_RW1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
272 #define _MaskMiu2Req_EVD_RW2( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(1))
273 #define _MaskMiu2Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK+1, m, BIT(2))
274 #define _MaskMiu2Req_EVD_LITE_RW1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(2))
275 #define _MaskMiu2Req_EVD_LITE_RW2( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(3))
276 #define _MaskMiu2Req_EVD_LITE_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(6))
277
278
279 #define HVD_EVD_RW1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
280 #define HVD_EVD_RW2_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(1)) == 0))
281 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(10)) == 0))
282 #define HVD_EVD_LITE_RW1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == 0))
283 #define HVD_EVD_LITE_RW2_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == 0))
284 #define HVD_EVD_LITE_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == 0))
285
286 #define HVD_EVD_RW1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
287 #define HVD_EVD_RW2_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == BIT(1)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(1)) == 0))
288 #define HVD_EVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == BIT(10)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(10)) == 0))
289 #define HVD_EVD_LITE_RW1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == 0))
290 #define HVD_EVD_LITE_RW2_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == 0))
291 #define HVD_EVD_LITE_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == 0))
292
293 #define HVD_EVD_RW1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == BIT(7)))
294 #define HVD_EVD_RW2_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(1)) == BIT(1)))
295 #define HVD_EVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(10)) == BIT(10)))
296 #define HVD_EVD_LITE_RW1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == BIT(2)))
297 #define HVD_EVD_LITE_RW2_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == BIT(3)))
298 #define HVD_EVD_LITE_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == BIT(6)))
299 #endif
300
301 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
302 do \
303 { \
304 if (HVD_##miu_clients##_ON_MIU0 == 1) \
305 { \
306 _MaskMiuReq_##miu_clients(mask); \
307 } \
308 else \
309 { \
310 if (HVD_##miu_clients##_ON_MIU1 == 1) \
311 { \
312 _MaskMiu1Req_##miu_clients(mask); \
313 } \
314 else if (HVD_##miu_clients##_ON_MIU2 == 1) \
315 { \
316 _MaskMiu2Req_##miu_clients(mask); \
317 } \
318 } \
319 } while (0)
320
321 // check RM is supported or not
322 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
323 #ifdef VDEC3
324 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
325 #else
326 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
327 #endif
328
329 //=============================================================================
330 #define MAX_HVD_EVD_NUM 2
331 //=============================================================================
332
333
334
335 //-------------------------------------------------------------------------------------------------
336 // Local Structures
337 //-------------------------------------------------------------------------------------------------
338
339 //-------------------------------------------------------------------------------------------------
340 // Local Functions Prototype
341 //-------------------------------------------------------------------------------------------------
342 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
343 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
344 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
345 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
346 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
347 //static void _HVD_EX_MBoxClear(MS_U32 u32Id, MS_U8 u8MBox);
348 static MS_U32 _HVD_EX_GetPC(MS_U32 u32Id);
349 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
350 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
351 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
352 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
353 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
354 static void _HVD_EX_SetMIUProtectMask(MS_U32 u32Id, MS_BOOL bEnable);
355 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
356 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
357 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
358 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
359 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
360 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
361 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
362 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
363 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
364 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
365 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
366 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id);
367 #if SUPPORT_EVD
368 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable);
369 static MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id);
370 #endif
371 #if SUPPORT_G2VP9 && defined(VDEC3)
372 static void HAL_VP9_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable);
373 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
374 #endif
375 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
376
377
378 //-------------------------------------------------------------------------------------------------
379 // Global Variables
380 //-------------------------------------------------------------------------------------------------
381 #if defined (__aeon__)
382 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
383 #else
384 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
385 #endif
386 #if HAL_HVD_ENABLE_MUTEX_PROTECT
387 MS_S32 s32HVDMutexID = -1;
388 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
389 #endif
390
391
392 #define HVD_EX_STACK_SIZE 4096
393 //-------------------------------------------------------------------------------------------------
394 // Local Variables
395 //-------------------------------------------------------------------------------------------------
396 typedef struct
397 {
398
399 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
400 MS_U8 g_hvd_nal_fill_pair[2][8];
401 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
402 MS_U16 _u16DispQPtr;
403 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
404
405 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
406 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
407 MS_U32 u32VPUClockType;
408 MS_U32 u32HVDClockType;//160
409 #if SUPPORT_EVD
410 MS_U32 u32EVDClockType;
411 #endif
412 #if SUPPORT_G2VP9 && defined(VDEC3)
413 MS_U32 u32VP9ClockType;
414 #endif
415 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
416
417 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
418 MS_BOOL g_RstFlag;
419 MS_U64 u64pts_real;
420 MS_PHY u32VP8BBUWptr;
421 MS_PHY u32EVDBBUWptr;
422 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
423 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
424 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
425 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
426 //pre_set
427 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
428 } HVD_Unit_Ctx;
429
430 typedef struct
431 {
432 HVD_Unit_Ctx _stCtx[MAX_HVD_EVD_NUM];
433 MS_U8 u8Cidx[HAL_HVD_EX_MAX_SUPPORT_STREAM];
434
435 } HVD_Hal_CTX;
436
437 HVD_Hal_CTX* pHVDHalContext = NULL;
438 HVD_Hal_CTX gHVDHalContext;
439 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
440
441 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
442 {
443 {FALSE},
444 {FALSE},
445 {FALSE},
446 #ifdef VDEC3
447 {FALSE},
448 #endif
449 };
450
451 //-------------------------------------------------------------------------------------------------
452 // Debug Functions
453 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_U32 u32Id,MS_BOOL bRst)454 void HVD_EX_SetRstFlag(MS_U32 u32Id, MS_BOOL bRst)
455 {
456 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
457 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
458
459 pHVDCtx->g_RstFlag = bRst;
460 }
461
HVD_EX_GetRstFlag(MS_U32 u32Id)462 MS_BOOL HVD_EX_GetRstFlag(MS_U32 u32Id)
463 {
464 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
465 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
466
467 return pHVDCtx->g_RstFlag;
468 }
469
470 //-------------------------------------------------------------------------------------------------
471 // Local Functions
472 //-------------------------------------------------------------------------------------------------
473
474 #ifdef VDEC3
475 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
476 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)477 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
478 {
479
480 MS_U32 ret = TRUE;
481 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
482
483 if(pCtrl == NULL || pstTaskInfo == NULL)
484 return FALSE;
485
486 pstTaskInfo->u32Id = u32Id;
487
488 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
489 {
490 case E_HVD_INIT_HW_RM:
491 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
492 break;
493 case E_HVD_INIT_HW_VP8:
494 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
495 break;
496 case E_HVD_INIT_HW_MVC:
497 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
498 break;
499 case E_HVD_INIT_HW_HEVC:
500 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
501 break;
502 #if SUPPORT_MSVP9
503 case E_HVD_INIT_HW_VP9:
504 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
505 break;
506 #endif
507 #if SUPPORT_G2VP9
508 case E_HVD_INIT_HW_VP9:
509 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
510 break;
511 #endif
512 default:
513 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
514 break;
515 }
516
517 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
518
519 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
520 {
521 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
522 }
523 else
524 {
525 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
526 }
527
528 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
529
530 #ifdef SUPPORT_EVD
531 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
532 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
533 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
534 #endif
535 return ret;
536
537 }
538
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)539 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
540 {
541 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
542 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
543 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
544 _HAL_HVD_Entry();
545
546 if(pCtrl == NULL)
547 _HAL_HVD_Return(ret);
548
549 VPU_EX_TaskInfo taskInfo;
550 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
551
552 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
553
554 taskInfo.u8HalId = u8Idx;
555 ret = HAL_VPU_EX_GetBBUId(u32Id,&taskInfo, pCtrl->bNStreamMode);
556
557 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
558 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
559
560 _HAL_HVD_Return(ret);
561 }
562
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)563 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
564 {
565 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
566 MS_BOOL ret = FALSE;
567 _HAL_HVD_Entry();
568
569 if(pCtrl == NULL)
570 _HAL_HVD_Return(ret);
571 VPU_EX_TaskInfo taskInfo;
572 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
573
574 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
575
576 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
577
578 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
579 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
580
581 _HAL_HVD_Return(ret);
582 }
583 #endif
584
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)585 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
586 {
587 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
588 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
589 pstHVDStream->s32HvdPpTaskId = -1;
590 }
591
_HVD_EX_Context_Init_HAL(void)592 static void _HVD_EX_Context_Init_HAL(void)
593 {
594 MS_U8 i,j;
595 HVD_Unit_Ctx *pHVDCtx = NULL;
596
597 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
598 {
599 pHVDHalContext->u8Cidx[i] = 0xFF;
600 }
601
602 for (j = 0; j < MAX_HVD_EVD_NUM; j++)
603 {
604 pHVDCtx = &pHVDHalContext->_stCtx[j];
605
606 pHVDCtx->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
607 pHVDCtx->u32VPUClockType = 432;
608 pHVDCtx->u32HVDClockType = 384;
609 #if SUPPORT_EVD
610 pHVDCtx->u32EVDClockType = 576;
611 #endif
612 #if SUPPORT_G2VP9 && defined(VDEC3)
613 pHVDCtx->u32VP9ClockType = 384;
614 #endif
615
616 #ifdef VDEC3
617 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
618 {
619 pHVDCtx->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
620 pHVDCtx->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
621 pHVDCtx->_stHVDStream[i].s32HvdPpTaskId = -1;
622 }
623 #else
624 pHVDCtx->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
625 pHVDCtx->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
626 pHVDCtx->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
627 #endif
628 }
629 }
630
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)631 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
632 {
633 MS_U16 u16Ret = 0;
634 #if (HVD_ENABLE_MVC || (!VDEC3))
635 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
636 #endif
637 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
638 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
639 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
640 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
641 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
642
643 #if HVD_ENABLE_MVC
644 if(HAL_HVD_EX_CheckMVCID(u32Id))
645 {
646 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
647 }
648 #endif /// HVD_ENABLE_MVC
649
650 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
651 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
652
653 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
654 {
655 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
656 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
657 }
658 else
659 #ifdef VDEC3
660 if (0 == pCtrl->u32BBUId)
661 #else
662 if (0 == u8TaskId)
663 #endif
664 {
665 //if(pCtrl->InitParams.bColocateBBUMode)
666 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
667 u16Ret = pShm->u32ColocateBBUReadPtr;
668 else
669 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
670 }
671 else
672 {
673 //if(pCtrl->InitParams.bColocateBBUMode)
674 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
675 u16Ret = pShm->u32ColocateBBUReadPtr;
676 else
677 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
678 }
679
680 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
681 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
682
683 return u16Ret;
684 }
685
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)686 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
687 {
688 MS_U16 u16Ret = 0;
689 #if (HVD_ENABLE_MVC || (!VDEC3))
690 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
691 #endif
692 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
693 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
694 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
695 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
696 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
697
698 #if HVD_ENABLE_MVC
699 if (HAL_HVD_EX_CheckMVCID(u32Id))
700 {
701 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
702 }
703 #endif /// HVD_ENABLE_MVC
704 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
705 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
706
707 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
708 {
709 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
710 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
711 }
712 else
713 #ifdef VDEC3
714 if (0 == pDrvCtrl->u32BBUId)
715 #else
716 if (0 == u8TaskId)
717 #endif
718 {
719 //if(pDrvCtrl->InitParams.bColocateBBUMode)
720 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
721 u16Ret = pShm->u32ColocateBBUWritePtr;
722 else
723 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
724 }
725 else
726 {
727 //if(pDrvCtrl->InitParams.bColocateBBUMode)
728 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
729 u16Ret = pShm->u32ColocateBBUWritePtr;
730 else
731 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
732 }
733
734 return u16Ret;
735 }
736
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)737 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
738 {
739 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
740 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
741 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
742
743 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
744 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
745 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
746 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
747 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
748 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
749 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
750 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
751 }
752
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)753 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
754 {
755 #if (HVD_ENABLE_MVC || (!VDEC3))
756 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
757 #endif
758 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
759 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
760 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
761 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
762 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
763
764 #if HVD_ENABLE_MVC
765 if (HAL_HVD_EX_CheckMVCID(u32Id))
766 {
767 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
768 }
769 #endif /// HVD_ENABLE_MVC
770
771 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
772 {
773 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
774 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
775 }
776 else
777 #ifdef VDEC3
778 if (0 == pCtrl->u32BBUId)
779 #else
780 if (0 == u8TaskId)
781 #endif
782 {
783 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
784 //if(pCtrl->InitParams.bColocateBBUMode)
785 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
786 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
787 }
788 else
789 {
790 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
791 //if(pCtrl->InitParams.bColocateBBUMode)
792 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
793 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
794 }
795
796 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
797 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
798
799 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
800 }
801
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)802 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
803 {
804 MS_BOOL bResult = TRUE;
805 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
806 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
807 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
808
809 switch (u8MBox)
810 {
811 case E_HVD_HI_0:
812 {
813 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
814 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
815 break;
816 }
817 case E_HVD_HI_1:
818 {
819 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
820 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
821 break;
822 }
823 case E_HVD_VPU_HI_0:
824 {
825 bResult = HAL_VPU_EX_MBoxSend(u32Id, VPU_HI_MBOX0, u32Msg);
826 break;
827 }
828 case E_HVD_VPU_HI_1:
829 {
830 bResult = HAL_VPU_EX_MBoxSend(u32Id, VPU_HI_MBOX1, u32Msg);
831 break;
832 }
833 default:
834 {
835 bResult = FALSE;
836 break;
837 }
838 }
839
840 return bResult;
841 }
842
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)843 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
844 {
845 MS_BOOL bResult = TRUE;
846 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
847 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
848 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
849
850 switch (u8MBox)
851 {
852 case E_HVD_HI_0:
853 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
854 break;
855 case E_HVD_HI_1:
856 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
857 break;
858 case E_HVD_RISC_0:
859 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
860 break;
861 case E_HVD_RISC_1:
862 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
863 break;
864 case E_HVD_VPU_HI_0:
865 bResult = HAL_VPU_EX_MBoxRdy(u32Id, VPU_HI_MBOX0);
866 break;
867 case E_HVD_VPU_HI_1:
868 bResult = HAL_VPU_EX_MBoxRdy(u32Id, VPU_HI_MBOX1);
869 break;
870 case E_HVD_VPU_RISC_0:
871 bResult = HAL_VPU_EX_MBoxRdy(u32Id, VPU_RISC_MBOX0);
872 break;
873 case E_HVD_VPU_RISC_1:
874 bResult = HAL_VPU_EX_MBoxRdy(u32Id, VPU_RISC_MBOX1);
875 break;
876 default:
877 break;
878 }
879
880 return bResult;
881 }
882
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)883 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
884 {
885 MS_BOOL bResult = TRUE;
886 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
887 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
888 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
889
890 switch (u8MBox)
891 {
892 case E_HVD_HI_0:
893 {
894 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
895 break;
896 }
897 case E_HVD_HI_1:
898 {
899 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
900 break;
901 }
902 case E_HVD_RISC_0:
903 {
904 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
905 break;
906 }
907 case E_HVD_RISC_1:
908 {
909 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
910 break;
911 }
912 case E_HVD_VPU_RISC_0:
913 {
914 bResult = HAL_VPU_EX_MBoxRead(u32Id, VPU_RISC_MBOX0, u32Msg);
915 break;
916 }
917 case E_HVD_VPU_RISC_1:
918 {
919 bResult = HAL_VPU_EX_MBoxRead(u32Id, VPU_RISC_MBOX1, u32Msg);
920 break;
921 }
922 default:
923 {
924 bResult = FALSE;
925 break;
926 }
927 }
928
929 return bResult;
930 }
931
932 #if 0
933 static void _HVD_EX_MBoxClear(MS_U32 u32Id, MS_U8 u8MBox)
934 {
935 switch (u8MBox)
936 {
937 case E_HVD_RISC_0:
938 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
939 break;
940 case E_HVD_RISC_1:
941 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
942 break;
943 case E_HVD_VPU_RISC_0:
944 HAL_VPU_EX_MBoxClear(u32Id, VPU_RISC_MBOX0);
945 break;
946 case E_HVD_VPU_RISC_1:
947 HAL_VPU_EX_MBoxClear(u32Id, VPU_RISC_MBOX1);
948 break;
949 default:
950 break;
951 }
952 }
953 #endif
954
_HVD_EX_GetPC(MS_U32 u32Id)955 static MS_U32 _HVD_EX_GetPC(MS_U32 u32Id)
956 {
957 MS_U32 u32PC = 0;
958 u32PC = HAL_VPU_EX_GetProgCnt(u32Id);
959 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
960 return u32PC;
961 }
962
_HVD_EX_GetESWritePtr(MS_U32 u32Id)963 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
964 {
965 MS_U32 u32Data = 0;
966 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
967 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
968
969 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
970 {
971 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
972
973 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
974 {
975 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
976
977 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
978 }
979 }
980 else
981 {
982 #if HVD_ENABLE_MVC
983 MS_U8 u8ViewIdx = 0;
984 if(HAL_HVD_EX_CheckMVCID(u32Id))
985 {
986 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
987 }
988 if(u8ViewIdx != 0) /// 2nd ES ptr.
989 {
990 u32Data = pShm->u32ES2WritePtr;
991 }
992 else
993 {
994 u32Data = pShm->u32ESWritePtr;
995 }
996 #else
997 u32Data = pShm->u32ESWritePtr;
998 #endif
999 }
1000
1001 return u32Data;
1002 }
1003
1004 #define NAL_UNIT_LEN_BITS 21
1005 #define NAL_UNIT_OFT_BITS 30
1006 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
1007 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
1008 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
1009
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)1010 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
1011 {
1012 MS_U32 u32Data = 0;
1013 MS_U8 u8TaskId = 0;
1014 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1015 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1016 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1017 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
1018 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
1019 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
1020
1021 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1022 #if HVD_ENABLE_MVC
1023 if(HAL_HVD_EX_CheckMVCID(u32Id))
1024 {
1025 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1026 }
1027 #endif /// HVD_ENABLE_MVC
1028
1029 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
1030 {
1031 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
1032 {
1033 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1034 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
1035 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
1036 MS_U32 *u32Adr;
1037 MS_U32 u32Tmp;
1038
1039 if (u16ReadPtr == u16WritePtr)
1040 {
1041 u32Data = _HVD_EX_GetESWritePtr(u32Id);
1042 }
1043 else
1044 {
1045 if (u16ReadPtr)
1046 u16ReadPtr--;
1047 else
1048 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
1049
1050 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
1051
1052 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
1053 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
1054 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
1055 u32Data = u32Data | u32Tmp;
1056
1057 //HVD_PRINT("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
1058 //while(1);
1059 }
1060 goto EXIT;
1061 }
1062 // set reg_poll_nal_rptr 0
1063 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
1064 // set reg_poll_nal_rptr 1
1065 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
1066
1067 // read reg_nal_rptr_hi
1068 #ifdef VDEC3
1069 if (0 == pCtrl->u32BBUId)
1070 #else
1071 if (0 == u8TaskId)
1072 #endif
1073 {
1074 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
1075 u32Data >>= 6;
1076 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
1077 }
1078 else
1079 {
1080 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
1081 u32Data >>= 6;
1082 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
1083 }
1084
1085 u32Data <<= 3; // unit
1086
1087 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1088 {
1089 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1090
1091 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1092 {
1093 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1094 u32Data = u32ESWptr;
1095 }
1096 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1097 {
1098 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1099 u32Data = u32ESWptr;
1100 }
1101 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1102 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1103 {
1104 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1105 u32Data = u32ESWptr;
1106 }
1107 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1108 && ((u32Data - u32ESWptr) < 32)
1109 && (pCtrl->u32FlushRstPtr == 1))
1110 {
1111 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1112 u32Data = u32ESWptr;
1113 }
1114 }
1115
1116 // remove illegal pointer
1117 #if 1
1118 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1119 {
1120 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1121
1122 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1123 (u32PacketStaddr <
1124 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1125 {
1126 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1127 u32Data = pCtrl->u32LastESRptr;
1128 }
1129 }
1130 #endif
1131 }
1132 else
1133 {
1134 #if HVD_ENABLE_MVC
1135 MS_U8 u8ViewIdx = 0;
1136 if(HAL_HVD_EX_CheckMVCID(u32Id))
1137 {
1138 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1139 }
1140 if(u8ViewIdx != 0) /// 2nd ES ptr.
1141 {
1142 u32Data = pShm->u32ES2ReadPtr;
1143 }
1144 else
1145 {
1146 u32Data = pShm->u32ESReadPtr;
1147 }
1148 #else
1149 u32Data = pShm->u32ESReadPtr;
1150 #endif
1151 }
1152
1153 EXIT:
1154
1155 pCtrl->u32LastESRptr = u32Data;
1156
1157 return u32Data;
1158 }
1159
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1160 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1161 {
1162 MS_U16 u16TimeOut = 0xFFFF;
1163 MS_BOOL bResult = FALSE;
1164
1165 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
1166
1167 while (--u16TimeOut)
1168 {
1169 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1170 {
1171 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1172 break;
1173 }
1174 }
1175
1176 return bResult;
1177 }
1178
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1179 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1180 {
1181 MS_U16 u16TimeOut = 0xFFFF;
1182 MS_BOOL bResult = FALSE;
1183 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1184
1185 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
1186
1187 #if HVD_ENABLE_MVC
1188 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1189 {
1190 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1191 }
1192 #endif /// HVD_ENABLE_MVC
1193
1194 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1195
1196 while (--u16TimeOut)
1197 {
1198 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1199 {
1200 u32Cmd |= (u8TaskId << 24);
1201 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1202 break;
1203 }
1204 }
1205 return bResult;
1206 }
1207
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)1208 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
1209 {
1210 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1211 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
1212 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDCtx->u32HVDCmdTimeout;
1213 #ifdef VDEC3
1214 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1215 MS_BOOL IsSent = FALSE;
1216 MS_BOOL IsMailBox = FALSE;
1217 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1218
1219 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
1220 {
1221 do {
1222 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1223 if (!SentRet)
1224 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1225 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1226 break;
1227 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1228 IsSent = TRUE;
1229 break;
1230 }
1231 else if (HVD_GetSysTime_ms() > u32timeout)
1232 {
1233 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1234 break;
1235 }
1236 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1237 }
1238 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
1239 {
1240 do {
1241 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1242 if (!SentRet)
1243 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1244 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1245 break;
1246 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1247 IsSent = TRUE;
1248 break;
1249 }
1250 else if (HVD_GetSysTime_ms() > u32timeout)
1251 {
1252 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1253 break;
1254 }
1255 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1256 }
1257 if (!IsSent) {
1258 IsMailBox = TRUE;
1259 u32timeout = HVD_GetSysTime_ms() + pHVDCtx->u32HVDCmdTimeout;
1260 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1261 #else
1262 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1263 #endif
1264 {
1265 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1266 if (HVD_GetSysTime_ms() > u32timeout)
1267 {
1268 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1269 return E_HVD_RETURN_TIMEOUT;
1270 }
1271 #endif
1272
1273 #if 0
1274 if (u32Cmd == E_HVD_CMD_STOP)
1275 {
1276 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1277 #if HVD_ENABLE_MVC
1278 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1279 {
1280 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1281 }
1282 #endif /// HVD_ENABLE_MVC
1283 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1284
1285 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1286 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1287
1288 return E_HVD_RETURN_SUCCESS;
1289 }
1290 #endif
1291 // coverity[copy_paste_error]
1292 if(u32Cmd < E_DUAL_CMD_BASE)
1293 {
1294 //_HVD_EX_GetPC(u32Id);
1295 HAL_HVD_EX_Dump_FW_Status(u32Id);
1296 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1297 }
1298 }
1299
1300 #ifdef VDEC3
1301 }
1302 IsSent = FALSE;
1303 u32timeout = HVD_GetSysTime_ms() + pHVDCtx->u32HVDCmdTimeout;
1304 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
1305 {
1306 do {
1307 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1308 if (!SentRet)
1309 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1310 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1311 break;
1312 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1313 IsSent = TRUE;
1314 break;
1315 }
1316 else if (HVD_GetSysTime_ms() > u32timeout)
1317 {
1318 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1319 break;
1320 }
1321 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1322 }
1323 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
1324 {
1325 do {
1326 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1327 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1328 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1329 }
1330 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1331 break;
1332 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1333 IsSent = TRUE;
1334 break;
1335 }
1336 else if (HVD_GetSysTime_ms() > u32timeout)
1337 {
1338 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1339 break;
1340 }
1341 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1342 }
1343 if (!IsSent)
1344 {
1345 u32timeout = HVD_GetSysTime_ms() + pHVDCtx->u32HVDCmdTimeout;
1346 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1347 #else
1348 u32timeout = HVD_GetSysTime_ms() + pHVDCtx->u32HVDCmdTimeout;
1349
1350 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1351 #endif
1352 {
1353 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1354 if (HVD_GetSysTime_ms() > u32timeout)
1355 {
1356 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
1357 return E_HVD_RETURN_TIMEOUT;
1358 }
1359 #endif
1360 if(u32Cmd < E_DUAL_CMD_BASE)
1361 {
1362 //_HVD_EX_GetPC(u32Id);
1363 HAL_HVD_EX_Dump_FW_Status(u32Id);
1364 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1365 }
1366 }
1367 #ifdef VDEC3
1368 }
1369 else
1370 {
1371 HAL_HVD_EX_FlushMemory();
1372 }
1373 #endif
1374 return E_HVD_RETURN_SUCCESS;
1375 }
1376
_HVD_EX_SetMIUProtectMask(MS_U32 u32Id,MS_BOOL bEnable)1377 static void _HVD_EX_SetMIUProtectMask(MS_U32 u32Id, MS_BOOL bEnable)
1378 {
1379 #if HAL_HVD_ENABLE_MIU_PROTECT
1380 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
1381 _HVD_MIU_SetReqMask(MVD_RW_RTO, bEnable);
1382 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1383 #if SUPPORT_EVD
1384 _HVD_MIU_SetReqMask(EVD_RW1, bEnable);
1385 _HVD_MIU_SetReqMask(EVD_RW2, bEnable);
1386 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1387 _HVD_MIU_SetReqMask(EVD_LITE_RW1, bEnable);
1388 _HVD_MIU_SetReqMask(EVD_LITE_RW2, bEnable);
1389 _HVD_MIU_SetReqMask(EVD_LITE_BBU_R, bEnable);
1390 #endif
1391 _HVD_MIU_SetReqMask(HVD_RW_MIF0, bEnable);
1392 _HVD_MIU_SetReqMask(HVD_RW_MIF1, bEnable);
1393 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1394 HAL_VPU_EX_MIU_RW_Protect(u32Id, bEnable);
1395 //HVD_Delay_ms(1);
1396 #endif
1397 return;
1398 }
1399
1400 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)1401 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
1402 {
1403 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1404
1405 if (u32CodecType == E_HVD_INIT_HW_HEVC
1406 #if SUPPORT_MSVP9
1407 || u32CodecType == E_HVD_INIT_HW_VP9
1408 #endif
1409 )
1410 return TRUE;
1411
1412 return FALSE;
1413 }
1414
_HAL_EX_IS_HVD(MS_U32 u32ModeFlag)1415 static MS_BOOL _HAL_EX_IS_HVD(MS_U32 u32ModeFlag) // VP8 isn't included
1416 {
1417 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1418
1419 if ((u32CodecType == E_HVD_INIT_HW_MVC) ||
1420 (u32CodecType == E_HVD_INIT_HW_AVC) ||
1421 (u32CodecType == E_HVD_INIT_HW_AVS) ||
1422 (u32CodecType == E_HVD_INIT_HW_RM))
1423 return TRUE;
1424
1425 return FALSE;
1426 }
1427
_HAL_EX_BBU_EVD_InUsed(MS_U32 u32Id)1428 static MS_BOOL _HAL_EX_BBU_EVD_InUsed(MS_U32 u32Id)
1429 {
1430 if (!pHVDHalContext)
1431 return FALSE;
1432
1433 MS_U32 i;
1434 MS_BOOL bRet = FALSE;
1435 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1436 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
1437
1438 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1439 {
1440 if (pHVDCtx->_stHVDStream[i].bUsed &&
1441 ((pHVDCtx->_stHVDStream[i].u32CodecType == E_HAL_HVD_HEVC)
1442 #if SUPPORT_MSVP9
1443 ||(pHVDCtx->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP9)
1444 #endif
1445 ))
1446 {
1447 bRet = TRUE;
1448 break;
1449 }
1450 }
1451
1452 return bRet;
1453 }
1454
_HAL_EX_BBU_HVD_InUsed(MS_U32 u32Id)1455 static MS_BOOL _HAL_EX_BBU_HVD_InUsed(MS_U32 u32Id) // VP8 isn't included
1456 {
1457 if (!pHVDHalContext)
1458 return FALSE;
1459
1460 MS_U32 i;
1461 MS_BOOL bRet = FALSE;
1462 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1463 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
1464
1465 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1466 {
1467 if (pHVDCtx->_stHVDStream[i].bUsed &&
1468 ((pHVDCtx->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVC) ||
1469 (pHVDCtx->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVS) ||
1470 (pHVDCtx->_stHVDStream[i].u32CodecType == E_HAL_HVD_RM)))
1471 {
1472 bRet = TRUE;
1473 break;
1474 }
1475 }
1476
1477 return bRet;
1478 }
1479
_HAL_EX_BBU_VP8_InUsed(MS_U32 u32Id)1480 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(MS_U32 u32Id)
1481 {
1482 if (!pHVDHalContext)
1483 return FALSE;
1484
1485 MS_U32 i;
1486 MS_BOOL bRet = FALSE;
1487 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1488 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
1489
1490 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1491 {
1492 if (pHVDCtx->_stHVDStream[i].bUsed && pHVDCtx->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
1493 {
1494 bRet = TRUE;
1495 break;
1496 }
1497 }
1498
1499 return bRet;
1500 }
1501
1502 #endif
1503
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1504 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1505 {
1506 MS_U16 u16Reg = 0;
1507 MS_VIRT u32StAddr = 0;
1508 #ifdef VDEC3
1509 MS_U32 u32Length = 0;
1510 #endif
1511 //MS_BOOL bBitMIU1 = FALSE;
1512 //MS_BOOL bCodeMIU1 = FALSE;
1513 MS_U8 u8BitMiuSel = 0;
1514 MS_U8 u8CodeMiuSel = 0;
1515 MS_U8 u8FBMiuSel = 0;
1516 MS_U32 u32BitStartOffset;
1517 MS_U32 u32CodeStartOffset;
1518 MS_U32 u32FBStartOffset;
1519
1520 MS_U8 u8TaskId = 0;
1521 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1522 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1523 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
1524 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
1525 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1526
1527
1528
1529 // MS_U32 u32TmpStartOffset;
1530 MS_U8 u8TmpMiuSel;
1531
1532
1533
1534 if(pCtrl == NULL) return;
1535
1536 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1537 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1538 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1539
1540 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1541 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1542 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1543 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1544 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1545 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1546 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1547 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1548 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1549 (u8FBMiuSel << VDEC_PPIN_MIUSEL) |
1550 (u8FBMiuSel << VDEC_XCSHM_MIUSEL));
1551
1552 if (u8BitMiuSel != u8CodeMiuSel)
1553 {
1554 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
1555 }
1556 else
1557 {
1558 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
1559 }
1560
1561 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1562 {
1563 #ifdef VDEC3
1564 if (!_HAL_EX_BBU_VP8_InUsed(u32Id))
1565 #endif
1566 {
1567 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1568
1569 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
1570 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
1571 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1572
1573 u32StAddr += VP8_BBU_TBL_SIZE;
1574
1575 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
1576 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
1577 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1578 }
1579
1580 // ES buffer
1581 #ifdef VDEC3
1582 if(pCtrl->bNStreamMode)
1583 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1584 else
1585 #endif
1586 u32StAddr = u32BitStartOffset;
1587
1588 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1589
1590 #ifdef VDEC3
1591 if (!_HAL_EX_BBU_VP8_InUsed(u32Id))
1592 #endif
1593 {
1594 HVD_EX_MSG_ERR("ESB start addr=%lx\n", (unsigned long)u32StAddr);
1595
1596 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1597 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1598
1599 #ifdef VDEC3
1600 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1601 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1602 #else
1603 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1604 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1605 #endif
1606
1607 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1608 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1609 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1610 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1611 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1612 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1613 }
1614
1615 return;
1616 }
1617
1618 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1619
1620 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
1621
1622 #ifdef VDEC3
1623 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed(u32Id)) ||
1624 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed(u32Id)) ||
1625 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1626 {
1627 if (pCtrl->u32BBUId == 0)
1628 {
1629 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1630 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1631 // -1 is for NAL_TAB_LEN counts from zero.
1632 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1633 }
1634 else
1635 {
1636 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1637 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1638 // -1 is for NAL_TAB_LEN counts from zero.
1639 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1640 }
1641 }
1642 #else
1643 if (0 == u8TaskId)
1644 {
1645 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1646 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1647 // -1 is for NAL_TAB_LEN counts from zero.
1648 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1649 }
1650 else
1651 {
1652 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1653 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1654 // -1 is for NAL_TAB_LEN counts from zero.
1655 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1656 }
1657 #endif
1658
1659 // ES buffer
1660 #ifdef VDEC3
1661 if(!pCtrl->bNStreamMode || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1662 {
1663 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1664 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1665 }
1666 else
1667 {
1668 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1669 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1670 }
1671 #else
1672 u32StAddr = u32BitStartOffset;
1673 #endif
1674
1675 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1676
1677 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1678
1679 #ifdef VDEC3
1680 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed(u32Id)) ||
1681 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed(u32Id)) ||
1682 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1683 {
1684 if (pCtrl->u32BBUId == 0)
1685 {
1686 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1687 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1688
1689 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1690 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1691 }
1692 else
1693 {
1694 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1695 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1696
1697 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1698 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1699 }
1700 }
1701 #else
1702 if (0 == u8TaskId)
1703 {
1704 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1705 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1706
1707 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1708 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1709 }
1710 else
1711 {
1712 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1713 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1714
1715 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1716 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1717 }
1718 #endif
1719
1720 // others
1721 #ifdef VDEC3
1722 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed(u32Id)) ||
1723 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed(u32Id)) ||
1724 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1725 {
1726 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1727
1728 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1729 {
1730 if (pCtrl->u32BBUId == 0)
1731 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1732 else
1733 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1734 }
1735 else
1736 {
1737 if (pCtrl->u32BBUId == 0)
1738 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1739 else
1740 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1741 }
1742
1743 if (pCtrl->u32BBUId == 0)
1744 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1745 else
1746 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1747
1748 if (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // RM
1749 {
1750 if (pCtrl->u32BBUId == 0) // force BBU to remove nothing, RM only
1751 u16Reg |= HVD_REG_BBU_PASER_DISABLE;
1752 else
1753 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2;
1754 }
1755 #if SUPPORT_MSVP9
1756 else if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1757 {
1758 if (pCtrl->u32BBUId == 0)
1759 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03;
1760 else
1761 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03_BS2;
1762 }
1763 #endif
1764 else // AVS or AVC or HEVC
1765 {
1766 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1767 {
1768 if (pCtrl->u32BBUId == 0)
1769 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1770 else
1771 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1772 }
1773 else // start code remained
1774 {
1775 if (pCtrl->u32BBUId == 0)
1776 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1777 else
1778 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1779 }
1780 }
1781
1782 if (pCtrl->u32BBUId == 0)
1783 {
1784 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1785 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1786 }
1787 else
1788 {
1789 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1790 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1791 }
1792
1793 //----------- reg_hk_sel_hi_or_hilite -----------
1794 u16Reg = (pHVDHalContext->u8Cidx[u8Idx] == HWDEC_EVD_LITE)?(MVD_REG_SEL_HILITE):(0);
1795
1796 if (pCtrl->u32BBUId == 0)
1797 {
1798 _HVD_WriteWordMask(MVD_REG_PAS1_SEL_HI_OR_HILITE, u16Reg, MVD_REG_SEL_HILITE);
1799 }
1800 else
1801 {
1802 _HVD_WriteWordMask(MVD_REG_PAS2_SEL_HI_OR_HILITE, u16Reg, MVD_REG_SEL_HILITE);
1803 }
1804 //----------- reg_hk_sel_hi_or_hilite -----------
1805 }
1806 #else
1807 if (0 == u8TaskId)
1808 {
1809 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1810
1811 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1812 {
1813 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1814 }
1815 else
1816 {
1817 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1818 }
1819
1820 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1821
1822 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1823 {
1824 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1825 }
1826 else // AVS or AVC
1827 {
1828 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1829 {
1830 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1831 }
1832 else // start code remained
1833 {
1834 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1835 }
1836 }
1837
1838 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1839
1840 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1841
1842 //----------- reg_hk_sel_hi_or_hilite -----------
1843 u16Reg = (pHVDHalContext->u8Cidx[u8Idx] == HWDEC_EVD_LITE)?(MVD_REG_SEL_HILITE):(0);
1844 _HVD_WriteWordMask(MVD_REG_PAS1_SEL_HI_OR_HILITE, u16Reg, MVD_REG_SEL_HILITE);
1845 //----------- reg_hk_sel_hi_or_hilite -----------
1846 }
1847 else
1848 {
1849 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1850
1851 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1852 {
1853 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1854 }
1855 else
1856 {
1857 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1858 }
1859
1860 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1861
1862 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1863 {
1864 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1865 }
1866 else // AVS or AVC
1867 {
1868 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1869 {
1870 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1871 }
1872 else // start code remained
1873 {
1874 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1875 }
1876 }
1877
1878 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1879
1880 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1881
1882 //----------- reg_hk_sel_hi_or_hilite -----------
1883 u16Reg = (pHVDHalContext->u8Cidx[u8Idx] == HWDEC_EVD_LITE)?(MVD_REG_SEL_HILITE):(0);
1884 _HVD_WriteWordMask(MVD_REG_PAS2_SEL_HI_OR_HILITE, u16Reg, MVD_REG_SEL_HILITE);
1885 //----------- reg_hk_sel_hi_or_hilite -----------
1886 }
1887 #endif
1888
1889 #if (HVD_ENABLE_MVC)
1890 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1891 {
1892 /// Used sub stream to record sub view data.
1893 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1894 //HVD_PRINT("**************** Buffer setting for MVC dual-BBU *************\n");
1895
1896 if (u8BitMiuSel != u8CodeMiuSel)
1897 {
1898 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
1899 }
1900 else
1901 {
1902 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
1903 }
1904
1905
1906 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
1907 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
1908 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
1909 // -1 is for NAL_TAB_LEN counts from zero.
1910 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDCtx->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
1911
1912 // ES buffer
1913 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1914
1915 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1916 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1917 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1918
1919 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1920 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1921
1922 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1923 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1924 {
1925 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1926 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1927 }
1928 else
1929 {
1930 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1931 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1932 }
1933 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1934 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1935 {
1936 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1937 }
1938 else // AVS or AVC
1939 {
1940 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1941 {
1942 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1943 }
1944 else // start code remained
1945 {
1946 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1947 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1948 }
1949 }
1950 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1951 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1952 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1953 }
1954 #endif
1955
1956 // MIF offset
1957 #if 0
1958 {
1959 MS_U16 offaddr = 0;
1960 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1961 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1962 {
1963 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1964 }
1965 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1966 offaddr = (MS_U16) ((u32StAddr) >> 20);
1967 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1968 //0x1FF; // 9 bits(L + H)
1969 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1970 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1971 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1972 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1973 {
1974 u16Reg |= HVD_REG_MIF_OFFSET_H;
1975 }
1976 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1977 }
1978 #endif
1979 }
1980
1981 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1982 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1983 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1984 {
1985 MS_U16 u16Reg = 0;
1986 MS_U32 u32StAddr = 0;
1987 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1988 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1989 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
1990 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
1991
1992 if(pCtrl == NULL) return;
1993
1994 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1995 {
1996 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1997
1998 // ES buffer
1999 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2000
2001 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2002 {
2003 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2004 }
2005
2006 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
2007 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
2008
2009 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2010 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2011
2012 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
2013 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
2014 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
2015 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
2016 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
2017 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
2018
2019 return;
2020 }
2021
2022 // ES buffer
2023 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2024
2025 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2026 {
2027 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2028 }
2029
2030 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
2031
2032 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
2033 {
2034 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
2035 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
2036
2037 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2038 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2039 }
2040 else
2041 {
2042 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
2043 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
2044
2045 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2046 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2047 }
2048 }
2049 #endif
2050
_HVD_EX_GetESLevel(MS_U32 u32Id)2051 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
2052 {
2053 MS_U32 u32Wptr = 0;
2054 MS_U32 u32Rptr = 0;
2055 MS_U32 u32CurMBX = 0;
2056 MS_U32 u32ESsize = 0;
2057 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
2058 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2059
2060 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
2061 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
2062 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
2063
2064 if (u32Rptr >= u32Wptr)
2065 {
2066 u32CurMBX = u32Rptr - u32Wptr;
2067 }
2068 else
2069 {
2070 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
2071 }
2072
2073 if (u32CurMBX == 0)
2074 {
2075 u32Ret = E_HVD_ESB_LEVEL_UNDER;
2076 }
2077 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
2078 {
2079 u32Ret = E_HVD_ESB_LEVEL_OVER;
2080 }
2081 else
2082 {
2083 u32CurMBX = u32ESsize - u32CurMBX;
2084 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
2085 {
2086 u32Ret = E_HVD_ESB_LEVEL_UNDER;
2087 }
2088 }
2089
2090 return u32Ret;
2091 }
2092
_HVD_EX_GetESQuantity(MS_U32 u32Id)2093 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
2094 {
2095 MS_U32 u32Wptr = 0;
2096 MS_U32 u32Rptr = 0;
2097 MS_U32 u32ESsize = 0;
2098 MS_U32 u32Ret = 0;
2099 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2100
2101 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
2102 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
2103 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
2104
2105
2106 if(u32Wptr >= u32Rptr)
2107 {
2108 u32Ret = u32Wptr - u32Rptr;
2109 }
2110 else
2111 {
2112 u32Ret = u32ESsize - u32Rptr + u32Wptr;
2113 }
2114 //HVD_PRINT("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
2115 return u32Ret;
2116 }
2117
2118 #if (HVD_ENABLE_IQMEM)
HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)2119 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
2120 {
2121
2122 MS_U32 u32Timeout = 20000;
2123
2124 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
2125 {
2126
2127 HAL_VPU_EX_IQMemSetDAMode(u32Id, TRUE);
2128
2129 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
2130
2131
2132 while (u32Timeout)
2133 {
2134
2135 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
2136 {
2137 break;
2138 }
2139 u32Timeout--;
2140 HVD_Delay_ms(1);
2141 }
2142
2143 HAL_VPU_EX_IQMemSetDAMode(u32Id, FALSE);
2144
2145 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
2146
2147 if (u32Timeout==0)
2148 {
2149 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
2150 return FALSE;
2151 }
2152
2153
2154 }
2155 return TRUE;
2156 }
2157
2158 #endif
2159
2160 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)2161 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
2162 #else
2163 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
2164 #endif
2165 {
2166 MS_U32 u32FirmVer = 0;
2167 MS_U32 u32Timeout = 20000;
2168 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2169 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2170 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
2171
2172 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
2173
2174 #if HVD_ENABLE_TIME_MEASURE
2175 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2176 #endif
2177
2178 HAL_VPU_EX_SetFWReload(u32Id, !pCtrl->bTurboFWMode);
2179
2180 VPU_EX_FWCodeCfg fwCfg;
2181 VPU_EX_TaskInfo taskInfo;
2182 VPU_EX_VLCTblCfg vlcCfg;
2183 #ifdef VDEC3
2184 VPU_EX_FBCfg fbCfg;
2185 #endif
2186 VPU_EX_NDecInitPara nDecInitPara;
2187
2188 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
2189 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2190 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
2191 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
2192 #ifdef VDEC3_FB
2193 nDecInitPara.pVLCCfg = NULL;
2194 #else
2195 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2196 {
2197 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDCtx->u32RV_VLCTableAddr);
2198 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2199 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2200 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
2201 vlcCfg.u32VLCTableOffset = pHVDCtx->u32RV_VLCTableAddr;
2202 nDecInitPara.pVLCCfg = &vlcCfg;
2203 }
2204 #endif
2205 nDecInitPara.pFWCodeCfg = &fwCfg;
2206 nDecInitPara.pTaskInfo = &taskInfo;
2207 #ifdef VDEC3
2208 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
2209 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2210
2211 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2212 {
2213 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2214 }
2215
2216 nDecInitPara.pFBCfg = &fbCfg;
2217 #endif
2218
2219 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
2220 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
2221 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
2222 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
2223 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
2224
2225 taskInfo.u32Id = u32Id;
2226
2227 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2228 {
2229 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
2230 }
2231 #ifdef VDEC3
2232 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
2233 {
2234 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2235 }
2236 #if SUPPORT_MSVP9
2237 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2238 {
2239 HVD_PRINT("SUPPORT_MSVP9\n");
2240 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2241 }
2242 #endif
2243 #if SUPPORT_G2VP9
2244 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2245 {
2246 HVD_PRINT("SUPPORT_G2VP9\n");
2247 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2248 }
2249 #endif
2250 #endif
2251 else
2252 {
2253 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2254 }
2255
2256 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2257
2258 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2259 {
2260 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2261 }
2262 else
2263 {
2264 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2265 }
2266 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2267
2268 #ifdef SUPPORT_EVD
2269 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2270 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2271 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2272 #endif
2273
2274 if(TRUE == HVD_EX_GetRstFlag(u32Id))
2275 {
2276 //Delete task for Rst
2277 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2278 {
2279 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2280 }
2281 HVD_EX_SetRstFlag(u32Id, FALSE);
2282 }
2283
2284 #if (HVD_ENABLE_IQMEM)
2285 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2286 #endif
2287
2288 #ifdef VDEC3
2289 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2290 #else
2291 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2292 #endif
2293 {
2294 HVD_EX_MSG_ERR("Task create fail!\n");
2295
2296 return FALSE;
2297 }
2298
2299 while (u32Timeout)
2300 {
2301 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2302
2303 if (u32FirmVer != 0)
2304 {
2305 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2306 break;
2307 }
2308 u32Timeout--;
2309 HVD_Delay_ms(1);
2310 }
2311
2312 #ifdef VDEC3_FB
2313 #if HVD_ENABLE_RV_FEATURE
2314 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2315
2316 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2317 {
2318 if(pShm->u32RM_VLCTableAddr == 0) {
2319 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2320 }
2321 else
2322 {
2323 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2324 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2325 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2326 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2327 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2328 nDecInitPara.pVLCCfg = &vlcCfg;
2329 }
2330 }
2331
2332 if (nDecInitPara.pVLCCfg)
2333 {
2334 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2335 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2336 {
2337 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2338 return FALSE;
2339 }
2340 }
2341 #endif
2342 #endif
2343 if (u32Timeout > 0)
2344 {
2345 pHVDCtx->_stHVDStream[u8Idx].bUsed = TRUE;
2346
2347 #ifdef VDEC3
2348 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2349 {
2350 case E_HVD_INIT_HW_AVC:
2351 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2352 break;
2353 case E_HVD_INIT_HW_AVS:
2354 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2355 break;
2356 case E_HVD_INIT_HW_RM:
2357 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2358 break;
2359 case E_HVD_INIT_HW_MVC:
2360 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2361 break;
2362 case E_HVD_INIT_HW_VP8:
2363 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2364 break;
2365 case E_HVD_INIT_HW_MJPEG:
2366 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2367 break;
2368 case E_HVD_INIT_HW_VP6:
2369 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2370 break;
2371 case E_HVD_INIT_HW_HEVC:
2372 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2373 break;
2374 case E_HVD_INIT_HW_VP9:
2375 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2376 break;
2377 default:
2378 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2379 break;
2380 }
2381 #endif
2382
2383 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2384 }
2385 else
2386 {
2387 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2388 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2389
2390 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2391 {
2392 HVD_EX_MSG_ERR("Task delete fail!\n");
2393 }
2394
2395 return FALSE;
2396 }
2397
2398
2399
2400 #if (HVD_ENABLE_IQMEM)
2401
2402 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
2403 {
2404
2405 HAL_HVD_EX_IQMem_Init(u32Id);
2406 }
2407 else{
2408 HVD_EX_MSG_DBG("not support IQMEM\n");
2409 }
2410 #endif
2411
2412
2413
2414
2415
2416
2417 #if HVD_ENABLE_TIME_MEASURE
2418 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2419 #endif
2420
2421 return TRUE;
2422 }
2423
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2424 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2425 {
2426 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2427 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2428 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2429 {
2430 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2431 }
2432 else
2433 {
2434 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2435 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2436 }
2437 }
2438
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2439 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2440 {
2441 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2442 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2443
2444 if (pShm == NULL)
2445 {
2446 return NULL;
2447 }
2448
2449 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2450 {
2451 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2452 }
2453 else
2454 {
2455 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2456 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2457 }
2458 }
2459
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2460 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2461 {
2462 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2463 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2464
2465 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2466 {
2467 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2468 {
2469 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2470 }
2471 }
2472 else
2473 {
2474 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2475 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2476 }
2477 }
2478
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2479 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2480 {
2481 MS_VIRT u32PTSWptr = HVD_U32_MAX;
2482 MS_VIRT u32PTSRptr = HVD_U32_MAX;
2483 MS_VIRT u32DestAddr = 0;
2484 HVD_PTS_Entry PTSEntry;
2485 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2486 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
2487 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2488 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2489
2490 // update R & W ptr
2491 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2492
2493 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
2494
2495 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2496 {
2497 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
2498 (MS_U32) MAX_PTS_TABLE_SIZE);
2499 return E_HVD_RETURN_FAIL;
2500 }
2501
2502 // check queue is full or not
2503 u32PTSWptr = pHVDCtx->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2504 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2505
2506 if (u32PTSWptr == u32PTSRptr)
2507 {
2508 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
2509 (unsigned long)u32PTSWptr, (unsigned long)pHVDCtx->_stHVDStream[u8Idx].u32PTSPreWptr);
2510 return E_HVD_RETURN_FAIL;
2511 }
2512
2513 // add one PTS entry
2514 PTSEntry.u32ByteCnt = pHVDCtx->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2515 PTSEntry.u32ID_L = pInfo->u32ID_L;
2516 PTSEntry.u32ID_H = pInfo->u32ID_H;
2517 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2518
2519 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDCtx->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2520
2521 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
2522
2523 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2524
2525 HAL_HVD_EX_FlushMemory();
2526
2527 // update Write ptr
2528 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2529
2530 pHVDCtx->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2531
2532 return E_HVD_RETURN_SUCCESS;
2533 }
2534
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2535 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2536 {
2537 //---------------------------------------------------
2538 // item format in nal table:
2539 // reserved |borken| u32NalOffset | u32NalLen
2540 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2541 //---------------------------------------------------
2542 MS_VIRT u32Adr = 0;
2543 MS_U32 u32BBUNewWptr = 0;
2544 MS_U8 item[8];
2545 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2546 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
2547 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2548 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2549 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2550
2551 #if HVD_ENABLE_MVC
2552 if(HAL_HVD_EX_CheckMVCID(u32Id))
2553 {
2554 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2555 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2556 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2557 {
2558 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2559 }
2560 }
2561 #endif /// HVD_ENABLE_MVC
2562
2563 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2564 {
2565 u32BBUNewWptr = pHVDCtx->u32VP8BBUWptr;
2566 }
2567 else
2568 {
2569 u32BBUNewWptr = pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr;
2570 }
2571 u32BBUNewWptr++;
2572 u32BBUNewWptr %= pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum;
2573
2574 // prepare nal entry
2575
2576 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2577 {
2578 // NAL len 22 bits , HEVC level5 constrain
2579 item[0] = u32NalLen & 0xff;
2580 item[1] = (u32NalLen >> 8) & 0xff;
2581 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2582 item[3] = (u32NalOffset >> 2) & 0xff;
2583 item[4] = (u32NalOffset >> 10) & 0xff;
2584 item[5] = (u32NalOffset >> 18) & 0xff;
2585 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2586 item[7] = 0;
2587 }
2588 else
2589 {
2590 item[0] = u32NalLen & 0xff;
2591 item[1] = (u32NalLen >> 8) & 0xff;
2592 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2593 item[3] = (u32NalOffset >> 3) & 0xff;
2594 item[4] = (u32NalOffset >> 11) & 0xff;
2595 item[5] = (u32NalOffset >> 19) & 0xff;
2596 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2597 item[7] = 0;
2598 }
2599
2600 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2601 {
2602 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDCtx->u32VP8BBUWptr << 3));
2603 }
2604 else
2605 {
2606 // add nal entry
2607 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr << 3));
2608 }
2609
2610 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2611
2612 HAL_HVD_EX_FlushMemory();
2613
2614 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr);
2615
2616 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2617 {
2618 pHVDCtx->u32VP8BBUWptr = u32BBUNewWptr;
2619 }
2620 else
2621 {
2622 pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2623 }
2624
2625 return E_HVD_RETURN_SUCCESS;
2626 }
2627
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2628 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2629 {
2630 MS_U8 item[8];
2631 MS_VIRT u32Adr = 0;
2632 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2633 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
2634 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2635 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2636 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2637
2638 /*
2639 HVD_PRINT("nal2 offset=0x%x, len=0x%x\n",
2640 u32NalOffset2, u32NalLen2);
2641 */
2642
2643 item[0] = u32NalLen2 & 0xff;
2644 item[1] = (u32NalLen2 >> 8) & 0xff;
2645 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2646 item[3] = (u32NalOffset2 >> 3) & 0xff;
2647 item[4] = (u32NalOffset2 >> 11) & 0xff;
2648 item[5] = (u32NalOffset2 >> 19) & 0xff;
2649 item[6] = (u32NalOffset2 >> 27) & 0x07;
2650 item[7] = 0;
2651
2652 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2653 {
2654 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDCtx->u32VP8BBUWptr << 3));
2655 }
2656 else
2657 {
2658 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr << 3));
2659 }
2660
2661 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2662
2663 HAL_HVD_EX_FlushMemory();
2664
2665 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2666 }
2667
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2668 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2669 {
2670 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2671 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
2672 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2673 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2674
2675 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2676 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
2677 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
2678 {
2679 MS_U16 i;
2680 MS_PHY u32VUIAddr;
2681 MS_U32 *pData = (MS_U32 *) &(pHVDCtx->g_hvd_VUIINFO);
2682
2683 HAL_HVD_EX_ReadMemory();
2684 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2685
2686 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2687 {
2688 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2689 {
2690 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2691 }
2692 else
2693 {
2694 //*pData = *((MS_VIRT *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2695 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2696 }
2697 pData++;
2698 }
2699 }
2700 else
2701 {
2702 memset(&(pHVDCtx->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2703 }
2704
2705 return (MS_VIRT) &(pHVDCtx->g_hvd_VUIINFO);
2706 }
2707
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2708 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2709 {
2710 MS_U32 u32ReadPtr = 0;
2711 MS_U32 eRet = 0;
2712 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2713 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
2714 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2715
2716 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2717 MS_U32 u32WritePtr = 0;
2718
2719 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2720 {
2721 u32WritePtr = pHVDCtx->u32VP8BBUWptr;
2722 }
2723 else
2724 {
2725 u32WritePtr = pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr;
2726 }
2727
2728 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
2729
2730 if (u32WritePtr >= u32ReadPtr)
2731 {
2732 eRet = u32WritePtr - u32ReadPtr;
2733 }
2734 else
2735 {
2736 eRet = pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2737 }
2738
2739 #if 0
2740 if (pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2741 {
2742 eRet = pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2743 }
2744 else
2745 {
2746 eRet = pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr);
2747 }
2748
2749 #endif
2750 return eRet;
2751 }
2752
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2753 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2754 {
2755 MS_U32 u32ReadPtr = 0;
2756 MS_U32 eRet = 0;
2757 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2758 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
2759
2760 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2761
2762 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2763 {
2764 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
2765 (MS_U32) MAX_PTS_TABLE_SIZE);
2766 return 0;
2767 }
2768
2769 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2770
2771 if (pHVDCtx->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2772 {
2773 eRet = pHVDCtx->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2774 }
2775 else
2776 {
2777 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDCtx->_stHVDStream[u8Idx].u32PTSPreWptr);
2778 }
2779
2780 return eRet;
2781 }
2782
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2783 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2784 {
2785 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2786 MS_U16 u16QNum = pShm->u16DispQNumb;
2787 MS_U16 u16QPtr = pShm->u16DispQPtr;
2788 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2789 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
2790
2791 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
2792 #if (HVD_ENABLE_MVC)
2793 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2794
2795 if(bMVC)
2796 {
2797 if (pHVDCtx->_stHVDStream[u8Idx].bDispOutSide)
2798 {
2799 MS_U16 u16RealQPtr = pHVDCtx->_stHVDStream[u8Idx].u32DispQIndex;
2800 MS_U16 u16UsedFrm = 0;
2801
2802 if (u16RealQPtr != u16QPtr)
2803 {
2804 if (u16RealQPtr > u16QPtr)
2805 {
2806 u16UsedFrm = u16RealQPtr - u16QPtr;
2807 }
2808 else
2809 {
2810 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2811 }
2812 }
2813
2814 if (u16QNum > u16UsedFrm)
2815 {
2816 volatile HVD_Frm_Information *pHvdFrm;
2817
2818 u16QNum -= u16UsedFrm;
2819 u16QPtr = u16RealQPtr;
2820 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2821
2822 if ((u16QPtr%2) == 0) //For MVC mode, we must check the pair of display entry is ready or not
2823 {
2824 volatile HVD_Frm_Information *pHvdFrmNext = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr+1];
2825
2826 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2827 {
2828 return NULL;
2829 }
2830 }
2831
2832 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2833 {
2834 pHVDCtx->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2835 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2836
2837 if ((u16QPtr%2) == 0)
2838 {
2839 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2840 pHVDCtx->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2841 }
2842 else
2843 {
2844 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDCtx->_stHVDStream[u8Idx].u32PrivateData);
2845 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDCtx->_stHVDStream[u8Idx].u32PrivateData;
2846 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2847 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDCtx->_stHVDStream[u8Idx].u32PrivateData);
2848 }
2849
2850 u16QPtr++;
2851 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2852 pHVDCtx->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2853
2854 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2855 }
2856 }
2857
2858 return NULL;
2859 }
2860
2861 /* Add for Mobile Platform by Ted Sun */
2862 #if 0
2863 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
2864 {
2865 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
2866 }
2867 #endif
2868
2869 //HVD_PRINT("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2870 //search the next frame to display
2871 while (u16QNum > 0)
2872 {
2873 //HVD_PRINT("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2874 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2875 pHVDCtx->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2876
2877 //HVD_PRINT("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2878 if (pHVDCtx->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2879 {
2880 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2881 /// Check the depned view was initial when Output the base view.
2882 if((u16QPtr%2) == 0)
2883 {
2884 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2885 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2886 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2887 {
2888 ///HVD_PRINT("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2889 ///HVD_PRINT("Return NULL.\n");
2890 return NULL;
2891 }
2892 }
2893
2894 //HVD_PRINT("V:%d.\n",u16QPtr);
2895 pHVDCtx->_u16DispQPtr = u16QPtr;
2896 pHVDCtx->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2897 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2898 (unsigned long) pHVDCtx->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2899 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDCtx->pHvdFrm->u32TimeStamp, (unsigned long) pHVDCtx->pHvdFrm->u32ID_H, u16QPtr); //STS output
2900 return (HVD_Frm_Information *)(MS_VIRT) pHVDCtx->pHvdFrm;
2901 }
2902
2903 u16QNum--;
2904 //go to next frame in the dispQ
2905 u16QPtr++;
2906
2907 if (u16QPtr >= pShm->u16DispQSize)
2908 {
2909 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2910 }
2911 }
2912 }
2913 else
2914 #endif ///HVD_ENABLE_MVC
2915 {
2916 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2917
2918 if (pHVDCtx->_stHVDStream[u8Idx].bDispOutSide)
2919 {
2920
2921 while (u16QNum != 0)
2922 {
2923 pHvdFrm = (volatile HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
2924
2925 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2926 {
2927 pHVDCtx->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2928 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2929 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2930 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2931 }
2932 u16QNum--;
2933 //go to next frame in the dispQ
2934 u16QPtr++;
2935
2936 if (u16QPtr == pShm->u16DispQSize)
2937 {
2938 u16QPtr = 0; //wrap to the begin
2939 }
2940 }
2941
2942 return NULL;
2943 }
2944 /* Add for Mobile Platform by Ted Sun */
2945 #if 0
2946 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
2947 {
2948 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
2949 }
2950 #endif
2951 //HVD_PRINT("Q: %d %d\n", u16QNum, u16QPtr);
2952 //search the next frame to display
2953 while (u16QNum != 0)
2954 {
2955 pHVDCtx->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2956
2957 //HVD_PRINT("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2958 if (pHVDCtx->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2959 {
2960 pHVDCtx->_u16DispQPtr = u16QPtr;
2961 pHVDCtx->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2962 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2963 (unsigned long) pHVDCtx->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2964 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDCtx->pHvdFrm->u32TimeStamp, pHVDCtx->pHvdFrm->u32ID_H, u16QPtr); //STS output
2965 return (HVD_Frm_Information *)(MS_VIRT) pHVDCtx->pHvdFrm;
2966 }
2967
2968 u16QNum--;
2969 //go to next frame in the dispQ
2970 u16QPtr++;
2971
2972 if (u16QPtr == pShm->u16DispQSize)
2973 {
2974 u16QPtr = 0; //wrap to the begin
2975 }
2976 }
2977 }
2978
2979 return NULL;
2980 }
2981
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2982 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2983 {
2984 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2985 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
2986 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2987
2988 if (pHVDCtx->_stHVDStream[u8Idx].bDispOutSide)
2989 {
2990 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2991 if(pVsyncBridgeExt != NULL)
2992 {
2993 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDCtx->_u16DispOutSideQPtr[u8Idx]]);
2994 }
2995 }
2996 return pFrmInfoExt;
2997 }
2998
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)2999 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
3000 {
3001 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3002 MS_U64 u64Ret = 0;
3003 #if SUPPORT_EVD
3004 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3005 #if SUPPORT_MSVP9
3006 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3007 #endif
3008 #endif
3009
3010 #if SUPPORT_EVD
3011 if (isEVD)
3012 {
3013 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
3014 }
3015 else
3016 #endif
3017 #if SUPPORT_G2VP9
3018 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3019 {
3020 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
3021 }
3022 else
3023 #endif
3024 {
3025 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
3026 }
3027
3028 return u64Ret;
3029 }
3030
3031 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)3032 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
3033 {
3034 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3035 MS_U16 u16QNum = pShm->u16DispQNumb;
3036 MS_U16 u16QPtr = pShm->u16DispQPtr;
3037 static volatile HVD_Frm_Information *pHvdFrm = NULL;
3038
3039 #if (HVD_ENABLE_MVC)
3040 if (HAL_HVD_EX_CheckMVCID(u32Id))
3041 {
3042 if (u16QNum == 1) return TRUE;
3043 }
3044 #endif
3045
3046 while (u16QNum != 0)
3047 {
3048 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3049 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3050 {
3051 return FALSE;
3052 }
3053 u16QNum--;
3054 u16QPtr++;
3055 if (u16QPtr == pShm->u16DispQSize)
3056 {
3057 u16QPtr = 0; //wrap to the begin
3058 }
3059 }
3060
3061 return TRUE;
3062 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)3063 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
3064 {
3065 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3066
3067 return &(_pHVDCtrls[u8DrvId]);
3068 }
3069
_HVD_EX_GetStreamIdx(MS_U32 u32Id)3070 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
3071 {
3072 MS_U8 u8OffsetIdx = 0;
3073 MS_U8 u8SidBaseMask = 0xF0;
3074 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
3075
3076 switch (eSidBase)
3077 {
3078 case E_HAL_HVD_MAIN_STREAM_BASE:
3079 {
3080 u8OffsetIdx = 0;
3081 break;
3082 }
3083 case E_HAL_HVD_SUB_STREAM_BASE:
3084 {
3085 u8OffsetIdx = 1;
3086 break;
3087 }
3088 case E_HAL_HVD_MVC_STREAM_BASE:
3089 {
3090 u8OffsetIdx = 0;
3091 break;
3092 }
3093 #ifdef VDEC3
3094 case E_HAL_HVD_N_STREAM_BASE:
3095 {
3096 u8OffsetIdx = (u32Id>>8) & 0xF;
3097 break;
3098 }
3099 #endif
3100 default:
3101 {
3102 u8OffsetIdx = 0;
3103 break;
3104 }
3105 }
3106
3107 return u8OffsetIdx;
3108 }
3109 /*
3110 static MS_BOOL _HAL_HVD_EX_HVDInUsed(MS_U32 u32Id)
3111 {
3112 MS_U32 i = 0;
3113 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3114 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
3115
3116 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3117 {
3118 if(TRUE == pHVDCtx->_stHVDStream[i].bUsed)
3119 {
3120 return TRUE;
3121 }
3122 }
3123 return FALSE;
3124 }
3125 */
3126
3127 #ifdef VDEC3
_HVD_EX_DecideCidx(MS_U8 u8Idx,MS_BOOL bIsEVD,MS_BOOL bIsNStreamMode)3128 static MS_U8 _HVD_EX_DecideCidx(MS_U8 u8Idx, MS_BOOL bIsEVD, MS_BOOL bIsNStreamMode)
3129 #else
3130 static MS_U8 _HVD_EX_DecideCidx(MS_U8 u8Idx, MS_BOOL bIsEVD)
3131 #endif
3132 {
3133 MS_U8 u8DecideCidx = 0;
3134
3135 #if (VPU_DISPATCH_POLICY == USE_FIRST_VPU_ONLY)
3136 {
3137 u8DecideCidx = 0;
3138 }
3139 #elif (VPU_DISPATCH_POLICY == USE_SECOND_VPU_ONLY)
3140 {
3141 u8DecideCidx = 1;
3142 }
3143 #elif (VPU_DISPATCH_POLICY == USE_KANO_RULE)
3144 {
3145 if (bIsEVD)
3146 {
3147 MS_U8 i = 0;
3148 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[0];
3149 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3150 {
3151 if ((E_HAL_HVD_HEVC == pHVDCtx->_stHVDStream[i].u32CodecType) || (E_HAL_HVD_VP9 == pHVDCtx->_stHVDStream[i].u32CodecType))
3152 {
3153 break;
3154 }
3155 }
3156
3157 if (i < HAL_HVD_EX_MAX_SUPPORT_STREAM)
3158 {
3159 u8DecideCidx = 1;
3160 }
3161 else
3162 {
3163 u8DecideCidx = 0;
3164 }
3165 }
3166 else
3167 {
3168 u8DecideCidx = 0;
3169 }
3170 }
3171 #elif (VPU_DISPATCH_POLICY == USE_KANO_INV_RULE)
3172 {
3173 if (bIsEVD)
3174 {
3175 MS_U8 i = 0;
3176 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[1];
3177 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3178 {
3179 if ((E_HAL_HVD_HEVC == pHVDCtx->_stHVDStream[i].u32CodecType) || (E_HAL_HVD_VP9 == pHVDCtx->_stHVDStream[i].u32CodecType))
3180 {
3181 break;
3182 }
3183 }
3184
3185 if (i < HAL_HVD_EX_MAX_SUPPORT_STREAM)
3186 {
3187 u8DecideCidx = 0;
3188 }
3189 else
3190 {
3191 u8DecideCidx = 1;
3192 }
3193 }
3194 else
3195 {
3196 u8DecideCidx = 0;
3197 }
3198 }
3199 #elif (VPU_DISPATCH_POLICY == USE_MAIN_EVD_IN_LITE)
3200 {
3201 if (bIsEVD && (u8Idx==0))
3202 {
3203 u8DecideCidx = 1;
3204 }
3205 else
3206 {
3207 u8DecideCidx = 0;
3208 }
3209 }
3210 #elif (VPU_DISPATCH_POLICY == USE_MAIN_EVD_IN_LITE_NDEC_IN_HICODEC)
3211 {
3212 if(bIsNStreamMode)
3213 {
3214 u8DecideCidx = 0;
3215 }
3216 else
3217 {
3218 if (bIsEVD && (u8Idx==0))
3219 {
3220 u8DecideCidx = 1;
3221 }
3222 else
3223 {
3224 u8DecideCidx = 0;
3225 }
3226 }
3227 }
3228 #endif
3229
3230 if(HAL_VPU_EX_GetSecurityMode() == TRUE)
3231 {
3232 u8DecideCidx = 0;
3233 HVD_PRINT("[VDEC][%s]Secure mode always use u8DecideCidx=%d\n",__FUNCTION__,u8DecideCidx);
3234 }
3235
3236 HVD_PRINT("[%s] policy=%d, u8Id=%d, bIsEVD=%d, u8DecideCidx=%d \n", __FUNCTION__, VPU_DISPATCH_POLICY, u8Idx, bIsEVD, u8DecideCidx);
3237 return u8DecideCidx;
3238 }
3239
HAL_HVD_EX_ExchangeCidx(MS_U32 u32Id)3240 void HAL_HVD_EX_ExchangeCidx(MS_U32 u32Id)
3241 {
3242 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3243
3244 #ifndef MSOS_TYPE_LINUX_KERNEL
3245 // The structure is too large to put it on the function stack, so we allocate it on the heap
3246 HVD_Unit_Ctx *p_stCtx = (HVD_Unit_Ctx*) malloc(sizeof(HVD_Unit_Ctx));
3247 if(p_stCtx == NULL)
3248 {
3249 HVD_PRINT("[error][%s] out of memory \n", __FUNCTION__);
3250 return;
3251 }
3252 #else
3253 HVD_Unit_Ctx stCtx;
3254 HVD_Unit_Ctx *p_stCtx = &stCtx;
3255 #endif
3256
3257 HVD_memcpy((volatile void *) p_stCtx , (void *) (&pHVDHalContext->_stCtx[0]), sizeof(HVD_Unit_Ctx));
3258 HVD_memcpy((volatile void *) (&pHVDHalContext->_stCtx[0]), (void *) (&pHVDHalContext->_stCtx[1]), sizeof(HVD_Unit_Ctx));
3259 HVD_memcpy((volatile void *) (&pHVDHalContext->_stCtx[1]), (void *) p_stCtx, sizeof(HVD_Unit_Ctx));
3260
3261 pHVDHalContext->u8Cidx[u8Idx] = 1 - pHVDHalContext->u8Cidx[u8Idx];
3262
3263 HVD_PRINT("[%s] u8Id=%d, cidx=%d \n", __FUNCTION__, u8Idx, pHVDHalContext->u8Cidx[u8Idx]);
3264
3265 #ifndef MSOS_TYPE_LINUX_KERNEL
3266 free((void*)p_stCtx);
3267 #endif
3268
3269 return;
3270 }
3271
3272 #ifdef VDEC3
HAL_HVD_EX_SetCidx(MS_U32 u32Id,MS_BOOL bIsEVD,MS_BOOL bIsNStreamMode)3273 void HAL_HVD_EX_SetCidx(MS_U32 u32Id, MS_BOOL bIsEVD, MS_BOOL bIsNStreamMode)
3274 {
3275 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3276 pHVDHalContext->u8Cidx[u8Idx] = _HVD_EX_DecideCidx(u8Idx, bIsEVD, bIsNStreamMode);
3277 return;
3278 }
3279 #else
HAL_HVD_EX_SetCidx(MS_U32 u32Id,MS_BOOL bIsEVD)3280 void HAL_HVD_EX_SetCidx(MS_U32 u32Id, MS_BOOL bIsEVD)
3281 {
3282 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3283 pHVDHalContext->u8Cidx[u8Idx] = _HVD_EX_DecideCidx(u8Idx, bIsEVD);
3284 return;
3285 }
3286 #endif
3287
HAL_HVD_EX_GetCidx(MS_U32 u32Id)3288 MS_U8 HAL_HVD_EX_GetCidx(MS_U32 u32Id)
3289 {
3290 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3291 return pHVDHalContext->u8Cidx[u8Idx];
3292 }
3293
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)3294 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
3295 {
3296 MS_PHY u32PhyAddr = 0x0;
3297 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3298
3299 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3300 {
3301 return 0;
3302 }
3303
3304 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3305
3306 if (u32PhyAddr == 0xFFFFFFFF) //boris
3307 {
3308 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3309 }
3310 else
3311 {
3312 // TEE, common + share_info
3313 u32PhyAddr += COMMON_AREA_SIZE;
3314 }
3315
3316 return MsOS_PA2KSEG1(u32PhyAddr);
3317 }
3318
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3319 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3320 {
3321 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3322 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3323
3324 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3325 {
3326 return 0;
3327 }
3328
3329 MS_PHY u32PhyAddr = 0x0;
3330 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3331
3332 if (u32PhyAddr == 0xFFFFFFFF)
3333 {
3334 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr; // + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3335 }
3336
3337 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR;
3338
3339 return MsOS_PA2KSEG1(u32PhyAddr);
3340 }
3341
_HVD_MIF_MiuClientSel(MS_U8 u8MiuSel)3342 void _HVD_MIF_MiuClientSel(MS_U8 u8MiuSel) //SW select
3343 {
3344 if (u8MiuSel == E_CHIP_MIU_0)
3345 {
3346 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF0);
3347 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3348 }
3349 else if (u8MiuSel == E_CHIP_MIU_1)
3350 {
3351 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF0, MIU0_CLIENT_SELECT_GP4_HVD_MIF0);
3352 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3353 }
3354 }
3355
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3356 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3357 {
3358
3359 if (u8MiuSel == E_CHIP_MIU_0)
3360 {
3361 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3362 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3363 }
3364 else if (u8MiuSel == E_CHIP_MIU_1)
3365 {
3366 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3367 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3368 }
3369 else // 2
3370 {
3371 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3372 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, MIU2_CLIENT_SELECT_GP4_HVD_MIF1, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3373 }
3374
3375 }
3376
3377 #if SUPPORT_G2VP9 && defined(VDEC3)
3378 #ifdef __ARM_NEON__
3379 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3380 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3381 {
3382 uint32x4x4_t data, data2;
3383 MS_U8* raster2 = raster + tile_w * 4;
3384
3385 data = vld4q_u32((const uint32_t *)tile);
3386 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3387
3388 vst1q_u32((uint32_t *)raster, data.val[0]);
3389 raster += stride;
3390 vst1q_u32((uint32_t *)raster, data.val[1]);
3391 raster += stride;
3392 vst1q_u32((uint32_t *)raster, data.val[2]);
3393 raster += stride;
3394 vst1q_u32((uint32_t *)raster, data.val[3]);
3395
3396
3397 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3398 raster2 += stride;
3399 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3400 raster2 += stride;
3401 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3402 raster2 += stride;
3403 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3404 }
3405 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3406 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3407 {
3408 MS_U8* tile0 = tile;
3409 MS_U8* tile1 = tile+16;
3410 MS_U8* tile2 = tile+32;
3411 MS_U8* tile3 = tile+48;
3412 int i;
3413
3414 for (i=0; i<4; i++) {
3415 raster[i] = tile0[i];
3416 raster[4+i] = tile1[i];
3417 raster[8+i] = tile2[i];
3418 raster[12+i] = tile3[i];
3419 }
3420
3421 for (i=0; i<4; i++) {
3422 raster[stride+i] = tile0[4+i];
3423 raster[stride+4+i] = tile1[4+i];
3424 raster[stride+8+i] = tile2[4+i];
3425 raster[stride+12+i] = tile3[4+i];
3426 }
3427
3428 for (i=0; i<4; i++) {
3429 raster[2*stride+i] = tile0[8+i];
3430 raster[2*stride+4+i] = tile1[8+i];
3431 raster[2*stride+8+i] = tile2[8+i];
3432 raster[2*stride+12+i] = tile3[8+i];
3433 }
3434
3435 for (i=0; i<4; i++) {
3436 raster[3*stride+i] = tile0[12+i];
3437 raster[3*stride+4+i] = tile1[12+i];
3438 raster[3*stride+8+i] = tile2[12+i];
3439 raster[3*stride+12+i] = tile3[12+i];
3440 }
3441 }
3442 #endif // #ifdef __ARM_NEON__
3443
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)3444 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
3445 {
3446 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
3447 u32Id,
3448 E_TASK_PRI_MEDIUM,
3449 TRUE,
3450 NULL,
3451 32, // stack size..
3452 "HVD_PostProcess_task");
3453
3454 if (s32HvdPpTaskId < 0)
3455 {
3456 HVD_EX_MSG_ERR("Pp Task create failed\n");
3457
3458 return FALSE;
3459 }
3460
3461 HVD_EX_MSG_DBG("Pp Task create success\n");
3462 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
3463
3464 return TRUE;
3465 }
3466
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3467 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3468 {
3469 return y * stride * h + x * w * h;
3470 }
3471
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3472 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3473 {
3474 return y * stride * h + x * w;
3475 }
3476
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3477 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3478 {
3479 raster[0] = tile[0];
3480 raster[1] = tile[1];
3481 raster[2] = tile[2];
3482 raster[3] = tile[3];
3483 raster[stride] = tile[4];
3484 raster[stride + 1] = tile[5];
3485 raster[stride + 2] = tile[6];
3486 raster[stride + 3] = tile[7];
3487 raster[2 * stride] = tile[8];
3488 raster[2 * stride + 1] = tile[9];
3489 raster[2 * stride + 2] = tile[10];
3490 raster[2 * stride + 3] = tile[11];
3491 raster[3 * stride] = tile[12];
3492 raster[3 * stride + 1] = tile[13];
3493 raster[3 * stride + 2] = tile[14];
3494 raster[3 * stride + 3] = tile[15];
3495 }
3496
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3497 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3498 {
3499 const MS_U32 tile_w = 4;
3500 const MS_U32 tile_h = 4;
3501 MS_U32 tile_stride = w;
3502 MS_U32 x, y;
3503 MS_U8 *dst1, *dst2;
3504 MS_U8 *src1, *src2;
3505
3506 #ifdef __ARM_NEON__
3507 // To overlap load and store, handle two blocks at the same time.
3508 dst1 = dst;
3509 src1 = src;
3510 for (y = 0; y < h / tile_h; y++)
3511 {
3512 dst2 = dst1;
3513 src2 = src1;
3514 for (x = 0; x <= (w/tile_w - 8); x+=8)
3515 {
3516 tile4x4_to_raster_8(
3517 dst2,
3518 src2,
3519 raster_stride, tile_w, tile_h);
3520 dst2 += tile_w * 8;
3521 src2 += tile_w * tile_h * 8;
3522 }
3523 dst1 += raster_stride * tile_h;
3524 src1 += tile_stride * tile_h;
3525 for (; x < w / tile_w; x++)
3526 {
3527 tile4x4_to_raster(
3528 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3529 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3530 raster_stride);
3531 }
3532 }
3533 #else
3534 dst1 = NULL;
3535 src1 = NULL;
3536 dst2 = NULL;
3537 src2 = NULL;
3538
3539 for (y = 0; y < h / tile_h; y++)
3540 {
3541 for (x = 0; x <= (w/tile_w - 4); x+=4)
3542 {
3543 tile4x4_to_raster_4(
3544 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3545 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3546 raster_stride);
3547 }
3548 for (; x < w / tile_w; x++)
3549 {
3550 tile4x4_to_raster(
3551 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3552 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3553 raster_stride);
3554 }
3555 }
3556 #endif
3557 }
3558
3559 #define FLUSH_CACHE_SIZE (256 * 1024)
3560
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3561 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3562 {
3563 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
3564 if (u32Size > FLUSH_CACHE_SIZE)
3565 u32Size = FLUSH_CACHE_SIZE;
3566
3567 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
3568 }
3569
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3570 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3571 {
3572 MS_U32 u32SkipSize = 0;
3573
3574 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3575 if (u32Size > FLUSH_CACHE_SIZE)
3576 {
3577 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3578 u32Size = FLUSH_CACHE_SIZE;
3579 }
3580
3581 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
3582 }
3583
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3584 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3585 {
3586 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3587 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
3588 HVD_EX_Stream *pstHVDStream = pHVDCtx->_stHVDStream + u8Idx;
3589 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3590 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3591 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3592
3593 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3594
3595 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3596
3597 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3598 {
3599 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3600 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3601
3602 HVD_Delay_ms(1); // FIXME
3603
3604 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3605 continue;
3606
3607 HAL_HVD_EX_ReadMemory();
3608
3609 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3610 {
3611 MS_U8 *pSrcVA, *pDstVA;
3612 MS_U32 u32SrcPA, u32DstPA;
3613 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3614 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3615
3616 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3617 {
3618 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3619
3620 u16Width = pFrmInfo->u16Width;
3621 u16Height = pFrmInfo->u16Height;
3622 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3623 }
3624
3625 // Luma
3626 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3627 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3628
3629 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3630 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3631
3632 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3633 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3634
3635 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3636
3637 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3638
3639 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3640
3641 // Chroma
3642 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3643 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3644
3645 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3646 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3647
3648 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3649 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3650
3651 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3652
3653 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3654
3655 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3656
3657 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3658 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3659 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3660
3661 HAL_HVD_EX_FlushMemory();
3662
3663 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3664 break;
3665
3666 HAL_HVD_EX_ReadMemory();
3667 }
3668 }
3669
3670 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3671
3672 return TRUE;
3673 }
3674 #endif
3675
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3676 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3677 {
3678 #ifndef VDEC3
3679 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3680 #endif
3681 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3682 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3683 MS_U8 u8EVD = pHVDHalContext->u8Cidx[u8Idx];
3684 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[u8EVD];
3685
3686 MS_U8 u8MiuSel;
3687 MS_U32 u32StartOffset;
3688 if(pCtrl == NULL)
3689 {
3690 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
3691 return FALSE;
3692 }
3693 MS_BOOL isHVD = (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) \
3694 || (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) \
3695 || (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) \
3696 || (E_HVD_INIT_HW_MVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) \
3697 || (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3698
3699 #if SUPPORT_EVD
3700 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3701 #if SUPPORT_MSVP9
3702 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3703 #endif
3704 #endif
3705 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3706 // re-setup clock.
3707 #if SUPPORT_G2VP9 && defined(VDEC3)
3708 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3709 #endif
3710
3711 if (!HAL_VPU_EX_HVDInUsed(u32Id))
3712 {
3713 HVD_PRINT("HVD power on\n");
3714 #ifdef CONFIG_MSTAR_CLKM
3715 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, TRUE);
3716
3717 if(isHVD)
3718 {
3719 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD_IDB, TRUE);
3720 }
3721
3722 if(E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3723 {
3724 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VP8, TRUE);
3725 }
3726 else if((E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
3727 (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) )
3728 {
3729 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD_AEC, TRUE);
3730 }
3731 #else
3732 HAL_HVD_EX_PowerCtrl(u32Id, TRUE);
3733 #endif
3734
3735 #ifdef CONFIG_MSTAR_SRAMPD
3736 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3737 HVD_Delay_ms(1);
3738 #endif
3739 }
3740
3741 #if SUPPORT_EVD
3742 if (isEVD)
3743 {
3744 #ifdef VDEC3
3745 if (!HAL_VPU_EX_EVDInUsed(u32Id))
3746 #endif
3747 {
3748 HVD_PRINT("EVD power on\n");
3749 HAL_EVD_EX_PowerCtrl(u32Id, TRUE);
3750 }
3751 }
3752 #endif
3753
3754 #if SUPPORT_G2VP9 && defined(VDEC3)
3755 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3756 {
3757 if (!HAL_VPU_EX_G2VP9InUsed(u32Id))
3758 {
3759 HVD_PRINT("G2 VP9 power on\n");
3760 HAL_VP9_EX_PowerCtrl(u32Id, TRUE);
3761 }
3762 }
3763 #endif
3764
3765 if (isHVD && (E_HVD_INIT_HW_MJPEG != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3766 {
3767 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
3768 //ALOGD("[HVD FB] addr=0x%x, size=0x%x, miu=%d \n", (MS_U32)(pCtrl->MemMap.u32FrameBufAddr), pCtrl->MemMap.u32FrameBufSize, u8MiuSel);
3769
3770 _HAL_HVD_Entry();
3771 _HVD_MIF_MiuClientSel(u8MiuSel);
3772 _HAL_HVD_Release();
3773 }
3774
3775 if ((!HAL_VPU_EX_HVDInUsed(u32Id)) )
3776 {
3777 pHVDCtx->_stHVDStream[0].u32BBUWptr = 0; //main
3778 pHVDCtx->_stHVDStream[1].u32BBUWptr = 0; //sub
3779 pHVDCtx->u32VP8BBUWptr = 0; //VP8
3780 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3781
3782 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3783
3784 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
3785 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
3786 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256);
3787 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256);
3788 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128);
3789 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128);
3790
3791 #if 0
3792 if((pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable) &&
3793 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3794 {
3795 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufAddr);
3796
3797 _HAL_HVD_Entry();
3798 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
3799 _HAL_HVD_Release();
3800
3801 }
3802 #endif
3803 }
3804
3805 #if SUPPORT_EVD
3806 if (isEVD)
3807 {
3808 #ifdef VDEC3
3809 if (!HAL_VPU_EX_EVDInUsed(u32Id))
3810 #endif
3811 _HVD_WriteWordMask(EVD_REG_RESET(u8EVD), EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3812 }
3813 #endif
3814
3815 #if SUPPORT_G2VP9 && defined(VDEC3)
3816 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3817 {
3818 if (!HAL_VPU_EX_G2VP9InUsed(u32Id))
3819 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3820 }
3821 #endif
3822
3823 #if SUPPORT_EVD
3824 if (isEVD)
3825 {
3826 #ifdef VDEC3
3827 if (!HAL_VPU_EX_EVDInUsed(u32Id))
3828 #endif
3829 {
3830 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3831 _HVD_WriteWordMask(EVD_REG_RESET(u8EVD), EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3832 }
3833
3834 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3835 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3836 {
3837 #ifdef VDEC3
3838 if (0 == pCtrl->u32BBUId)
3839 #else
3840 if (0 == u8TaskId)
3841 #endif
3842 {
3843 _HVD_WriteWordMask(EVD_REG_RESET(u8EVD), EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN);
3844 }
3845 else
3846 {
3847 _HVD_WriteWordMask(EVD_REG_RESET(u8EVD), EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN);
3848 }
3849 }
3850 goto RESET;
3851 }
3852 #endif
3853
3854 // HVD4, from JANUS and later chip
3855 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3856 {
3857 case E_HVD_INIT_HW_AVS:
3858 {
3859 #ifdef VDEC3
3860 if (0 == pCtrl->u32BBUId)
3861 #else
3862 if (0 == u8TaskId)
3863 #endif
3864 {
3865 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3866 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3867 }
3868 else
3869 {
3870 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3871 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3872 }
3873
3874 break;
3875 }
3876 case E_HVD_INIT_HW_RM:
3877 {
3878 #ifdef VDEC3
3879 if (0 == pCtrl->u32BBUId)
3880 #else
3881 if (0 == u8TaskId)
3882 #endif
3883 {
3884 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3885 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3886
3887 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3888 {
3889 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3890 }
3891 else // RV 8
3892 {
3893 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3894 }
3895 }
3896 else
3897 {
3898 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3899 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3900
3901 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3902 {
3903 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3904 }
3905 else // RV 8
3906 {
3907 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3908 }
3909
3910 }
3911
3912 break;
3913 }
3914 default:
3915 {
3916 #ifdef VDEC3
3917 if (0 == pCtrl->u32BBUId)
3918 #else
3919 if (0 == u8TaskId)
3920 #endif
3921 {
3922 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3923 }
3924 else
3925 {
3926 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3927 }
3928 break;
3929 }
3930 }
3931
3932 RESET:
3933
3934 #if 0 //Kano: use miu256bit
3935 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3936
3937 if (!HAL_VPU_EX_HVDInUsed(u32Id))
3938 {
3939 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3940 }
3941
3942 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3943 #endif
3944
3945 #if SUPPORT_EVD
3946 if (isEVD)
3947 {
3948 #ifdef VDEC3
3949 if (!HAL_VPU_EX_EVDInUsed(u32Id))
3950 #endif
3951 {
3952 HVD_PRINT("EVD miu 256 bits\n");
3953 _HVD_Write2Byte(EVD_REG_RESET(u8EVD), (_HVD_Read2Byte(EVD_REG_RESET(u8EVD)) & ~EVD_REG_RESET_MIU0_128 & ~EVD_REG_RESET_MIU1_128));
3954 _HVD_Write2Byte(EVD_REG_RESET(u8EVD), (_HVD_Read2Byte(EVD_REG_RESET(u8EVD)) | EVD_REG_RESET_MIU0_256 | EVD_REG_RESET_MIU1_256));
3955 // set EVD mif client to IP auto select
3956 _HVD_Write2Byte(EVD_REG_MIF_SOURCE_GROUP4, _HVD_Read2Byte(EVD_REG_MIF_SOURCE_GROUP4) | 0x0000008E );
3957 }
3958 }
3959 #endif
3960
3961 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3962 // Only ES buffer addrress needs to be set for VP8
3963 _HVD_EX_SetESBufferAddr(u32Id);
3964 #else
3965 if(DecoderType != E_VPU_EX_DECODER_MVD)
3966 {
3967 _HVD_EX_SetBufferAddr(u32Id);
3968 }
3969 #endif
3970
3971 if (!HAL_VPU_EX_HVDInUsed(u32Id))
3972 {
3973 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3974 }
3975
3976 #if SUPPORT_EVD
3977 if (isEVD)
3978 {
3979 #ifdef VDEC3
3980 if (!HAL_VPU_EX_EVDInUsed(u32Id))
3981 #endif
3982 _HVD_WriteWordMask(EVD_REG_RESET(u8EVD), 0, EVD_REG_RESET_SWRST);
3983 }
3984 #endif
3985
3986 #if SUPPORT_G2VP9 && defined(VDEC3)
3987 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3988 {
3989 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3990
3991 if (!HAL_VPU_EX_G2VP9InUsed(u32Id))
3992 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3993
3994 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3995 _HVD_EX_PpTask_Create(u32Id, &pHVDCtx->_stHVDStream[u8Idx]);
3996 }
3997 #endif
3998
3999 return TRUE;
4000 }
4001
HAL_HVD_EX_DeinitHW(MS_U32 u32Id)4002 MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id)
4003 {
4004 MS_U16 u16Timeout = 1000;
4005
4006 _HVD_EX_SetMIUProtectMask(u32Id, TRUE);
4007
4008 #if SUPPORT_EVD //EVD using HVD DIU, it should be turn off EVD first
4009 HAL_EVD_EX_DeinitHW(u32Id);
4010 #endif
4011
4012 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
4013
4014 while (u16Timeout)
4015 {
4016 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
4017 {
4018 break;
4019 }
4020 u16Timeout--;
4021 }
4022 #ifdef CONFIG_MSTAR_CLKM
4023 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD, FALSE);
4024 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD_IDB, FALSE);
4025 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD_AEC, FALSE);
4026 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_VP8, FALSE);
4027 #else
4028 HAL_HVD_EX_PowerCtrl(u32Id, FALSE);
4029 #endif
4030
4031 #ifdef CONFIG_MSTAR_SRAMPD
4032 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
4033 HVD_Delay_ms(1);
4034 #endif
4035
4036 _HVD_EX_SetMIUProtectMask(u32Id, FALSE);
4037
4038 return TRUE;
4039 }
4040
HAL_HVD_EX_FlushMemory(void)4041 void HAL_HVD_EX_FlushMemory(void)
4042 {
4043 MsOS_FlushMemory();
4044 }
4045
HAL_HVD_EX_ReadMemory(void)4046 void HAL_HVD_EX_ReadMemory(void)
4047 {
4048 MsOS_ReadMemory();
4049 }
4050
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)4051 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
4052 {
4053 _pHVDCtrls = pHVDCtrlsBase;
4054 }
4055
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)4056 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
4057 {
4058 return;
4059 }
4060
HAL_HVD_EX_GetHWVersionID(void)4061 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
4062 {
4063 return _HVD_Read2Byte(HVD_REG_REV_ID);
4064 }
4065
4066
HAL_HVD_EX_Init_Share_Mem(void)4067 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
4068 {
4069 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
4070 #if !defined(SUPPORT_X_MODEL_FEATURE)
4071 MS_U32 u32ShmId;
4072 MS_VIRT u32Addr;
4073 MS_U32 u32BufSize;
4074
4075
4076 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
4077 sizeof(HVD_Hal_CTX),
4078 &u32ShmId,
4079 &u32Addr,
4080 &u32BufSize,
4081 MSOS_SHM_QUERY))
4082 {
4083 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
4084 sizeof(HVD_Hal_CTX),
4085 &u32ShmId,
4086 &u32Addr,
4087 &u32BufSize,
4088 MSOS_SHM_CREATE))
4089 {
4090 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
4091 if(pHVDHalContext == NULL)
4092 {
4093 pHVDHalContext = &gHVDHalContext;
4094 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4095 _HVD_EX_Context_Init_HAL();
4096 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
4097 }
4098 else
4099 {
4100 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
4101 }
4102 //return FALSE;
4103 }
4104 else
4105 {
4106 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
4107 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
4108 _HVD_EX_Context_Init_HAL();
4109 }
4110 }
4111 else
4112 {
4113 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
4114 }
4115 #else
4116 if(pHVDHalContext == NULL)
4117 {
4118 pHVDHalContext = &gHVDHalContext;
4119 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4120 _HVD_EX_Context_Init_HAL();
4121 }
4122 #endif
4123 _HAL_HVD_MutexCreate();
4124 #else
4125 if(pHVDHalContext == NULL)
4126 {
4127 pHVDHalContext = &gHVDHalContext;
4128 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4129 _HVD_EX_Context_Init_HAL();
4130 }
4131 #endif
4132
4133 return TRUE;
4134 }
4135
4136 #ifdef VDEC3
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType,MS_BOOL bIsEVD,MS_BOOL bIsNStreamMode)4137 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType, MS_BOOL bIsEVD, MS_BOOL bIsNStreamMode)
4138 #else
4139 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType, MS_BOOL bIsEVD)
4140 #endif
4141 {
4142 MS_U32 i = 0;
4143 MS_U8 idx = 0;
4144 if (E_HAL_HVD_MVC_STREAM == eStreamType)
4145 {
4146 idx = 0;
4147 }
4148 else if (E_HAL_HVD_MAIN_STREAM == eStreamType)
4149 {
4150 idx = 0;
4151 }
4152 else if (E_HAL_HVD_SUB_STREAM == eStreamType)
4153 {
4154 idx = 1;
4155 }
4156 #ifdef VDEC3
4157 else if (eStreamType >= E_HAL_HVD_N_STREAM && eStreamType < (E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
4158 {
4159 idx = eStreamType - E_HAL_HVD_N_STREAM;
4160 }
4161 #endif
4162
4163 #ifdef VDEC3
4164 MS_U8 u8DecideCidx = _HVD_EX_DecideCidx(idx, bIsEVD, bIsNStreamMode);
4165 #else
4166 MS_U8 u8DecideCidx = _HVD_EX_DecideCidx(idx, bIsEVD);
4167 #endif
4168 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[u8DecideCidx];
4169
4170 if (eStreamType == E_HAL_HVD_MVC_STREAM)
4171 {
4172 if ((FALSE == pHVDCtx->_stHVDStream[0].bUsed) && (FALSE == pHVDCtx->_stHVDStream[1].bUsed))
4173 return pHVDCtx->_stHVDStream[0].eStreamId;
4174 }
4175 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
4176 {
4177 for (i = 0;
4178 i <
4179 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
4180 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
4181 {
4182 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDCtx->_stHVDStream[i].eStreamId) && (FALSE == pHVDCtx->_stHVDStream[i].bUsed))
4183 {
4184 return pHVDCtx->_stHVDStream[i].eStreamId;
4185 }
4186 }
4187 }
4188 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
4189 {
4190 for (i = 0;
4191 i <
4192 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
4193 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
4194 {
4195 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDCtx->_stHVDStream[i].eStreamId) && (FALSE == pHVDCtx->_stHVDStream[i].bUsed))
4196 {
4197 return pHVDCtx->_stHVDStream[i].eStreamId;
4198 }
4199 }
4200 }
4201 #ifdef VDEC3
4202 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
4203 {
4204 i = eStreamType - E_HAL_HVD_N_STREAM;
4205 if (!pHVDCtx->_stHVDStream[i].bUsed)
4206 return pHVDCtx->_stHVDStream[i].eStreamId;
4207 }
4208 #endif
4209
4210 return E_HAL_HVD_STREAM_NONE;
4211 }
4212
HAL_HVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)4213 void HAL_HVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
4214 {
4215 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4216 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
4217
4218 if (bEnable)
4219 {
4220 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4221 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4222 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
4223 }
4224 else
4225 {
4226 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4227 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4228 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
4229 }
4230
4231 // fix to not inverse
4232 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
4233
4234 switch (pHVDCtx->u32HVDClockType)
4235 {
4236 #if 0 //for overclocking
4237 case 432:
4238 {
4239 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
4240 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4241 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_320MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4242 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK);
4243 break;
4244 }
4245 #endif
4246 case 384:
4247 {
4248 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4249 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4250 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4251 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4252 break;
4253 }
4254 case 288:
4255 {
4256 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
4257 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4258 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4259 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
4260 break;
4261 }
4262 default:
4263 {
4264 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4265 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4266 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4267 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4268 break;
4269 }
4270 }
4271
4272 return;
4273 }
4274
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)4275 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
4276 {
4277 u32HVDRegOSBase = u32RegBase;
4278 HAL_VPU_EX_InitRegBase(u32RegBase);
4279 }
4280
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)4281 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
4282 {
4283 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
4284 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4285 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
4286 pHVDCtx->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
4287 }
4288
HAL_HVD_EX_InitVariables(MS_U32 u32Id)4289 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
4290 {
4291 MS_U8 i;
4292 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4293 HVD_ShareMem *pShm = NULL;
4294 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4295 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
4296 #if HVD_ENABLE_MVC
4297 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4298 #endif ///HVD_ENABLE_MVC
4299
4300 pHVDCtx->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4301 pHVDCtx->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4302 pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4303 pHVDCtx->_stHVDStream[u8Idx].u32DispQIndex = 0;
4304 pHVDCtx->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4305
4306 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
4307 pHVDCtx->_s32VDEC_BBU_TaskId[i] = -1;
4308
4309 #if HVD_ENABLE_MVC
4310 if (bMVC)
4311 {
4312 pHVDCtx->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
4313 pHVDCtx->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
4314 pHVDCtx->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
4315 pHVDCtx->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
4316 }
4317 #endif ///HVD_ENABLE_MVC
4318
4319 // set a local copy of FW code address; assuming there is only one copy of FW,
4320 // no matter how many task will be created.
4321
4322 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4323
4324 memset((void *) (pHVDCtx->g_hvd_nal_fill_pair), 0, 16);
4325
4326 // global variables
4327 pHVDCtx->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
4328 //pHVDCtx->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4329 //pHVDCtx->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4330
4331 // Create mutex
4332 //_HAL_HVD_MutexCreate();
4333
4334 // fill HVD init variables
4335 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4336 {
4337 pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
4338 pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
4339 }
4340 else
4341 #if HVD_ENABLE_RV_FEATURE
4342 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4343 {
4344 pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
4345 pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
4346 #ifdef VDEC3_FB
4347 pHVDCtx->u32RV_VLCTableAddr = 0;
4348 #else
4349 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
4350 {
4351 pHVDCtx->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
4352 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
4353 }
4354 else
4355 {
4356 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
4357 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
4358 return E_HVD_RETURN_INVALID_PARAMETER;
4359 }
4360 #endif
4361 }
4362 else
4363 #endif
4364 {
4365 pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
4366 pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
4367 #if HVD_ENABLE_MVC
4368 if (bMVC)
4369 {
4370 pHVDCtx->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
4371 pHVDCtx->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
4372 }
4373 #endif /// HVD_ENABLE_MVC
4374 pHVDCtx->u32RV_VLCTableAddr = 0;
4375 }
4376
4377 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
4378 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
4379 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
4380 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
4381 {
4382 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4383 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4384 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4385 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4386 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4387 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4388 #if HVD_ENABLE_MVC
4389 if (bMVC)
4390 {
4391 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
4392 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
4393 {
4394 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
4395 }
4396 }
4397 #endif /// HVD_ENABLE_MVC
4398
4399 return E_HVD_RETURN_SUCCESS;
4400 }
4401 else
4402 {
4403 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4404 (unsigned long)MS_PA2KSEG1((MS_VIRT) pShm),
4405 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4406 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4407 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4408 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4409 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4410 return E_HVD_RETURN_INVALID_PARAMETER;
4411 }
4412 }
4413
4414 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)4415 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
4416 #else
4417 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
4418 #endif
4419 {
4420 MS_U32 u32Addr = 0;
4421 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4422 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4423 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
4424 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4425
4426 MS_U32 u32TmpStartOffset;
4427 MS_U8 u8TmpMiuSel;
4428
4429 memset(pShm, 0, sizeof(HVD_ShareMem));
4430
4431 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
4432
4433 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
4434 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
4435 #ifdef VDEC3
4436 if (bFWdecideFB || bCMAUsed)
4437 {
4438 pShm->u32FrameBufAddr = 0;
4439 pShm->u32FrameBufSize = 0;
4440 }
4441 else
4442 #endif
4443 {
4444 pShm->u32FrameBufAddr = u32Addr;
4445 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
4446 }
4447
4448 pShm->DispInfo.u16DispWidth = 1;
4449 pShm->DispInfo.u16DispHeight = 1;
4450 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
4451 pShm->u32CPUClock = pHVDCtx->u32VPUClockType;
4452 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
4453 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4454 //Chip info
4455 pShm->u16ChipID = E_MSTAR_CHIP_KANO;
4456 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4457 // PreSetControl
4458 if (pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->bOnePendingBuffer)
4459 {
4460 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4461 }
4462
4463 if (pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->bCalFrameRate)
4464 {
4465 pShm->u32PreSetControl |= PRESET_CAL_FRAMERATE;
4466 }
4467
4468 pShm->bUseTSPInBBUMode = FALSE;
4469
4470 if(pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->eDisplayMode == E_HVD_DISPLAY_MODE_MCU)
4471 {
4472 pShm->bEnableDispQueue = TRUE;
4473 pShm->bEnableDispOutSide = TRUE;
4474 pHVDCtx->_stHVDStream[u8Idx].bDispOutSide = TRUE;
4475 }
4476 else if(pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->eDisplayMode == E_HVD_DISPLAY_MODE_HARDWIRE)
4477 {
4478 pShm->bEnableDispQueue = FALSE;
4479 pShm->bEnableDispOutSide = FALSE;
4480 pHVDCtx->_stHVDStream[u8Idx].bDispOutSide = FALSE;
4481 }
4482
4483 if ((pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable) &&
4484 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4485 {
4486 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4487
4488 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufAddr);
4489
4490 pShm->u32IapGnBufAddr = u32Addr;
4491 pShm->u32IapGnBufSize = pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufSize;
4492
4493 }
4494
4495 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
4496 switch(pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
4497 {
4498 case E_HVD_DEF_MFCODEC_DEFAULT:
4499 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4500 break;
4501 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
4502 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
4503 break;
4504 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
4505 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
4506 break;
4507 default:
4508 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4509 }
4510
4511 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4512 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4513 if (_stHVDPreSet[u8Idx].bColocateBBUMode)
4514 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4515 else
4516 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4517
4518 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4519 {
4520 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4521 {
4522 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4523 }
4524 else
4525 {
4526 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4527 }
4528 }
4529 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4530 {
4531 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4532 {
4533 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4534 }
4535 else
4536 {
4537 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4538 }
4539 }
4540 else
4541 {
4542 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4543 }
4544
4545 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4546 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4547 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4548 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4549 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4550 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4551 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4552 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4553 {
4554 pShm->bUseWbMvop = 1;
4555 }
4556
4557 /*
4558 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
4559 E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4560 {
4561 pShm->u8CodecFeature |= E_VDEC_TEMPORAL_SCALABILITY_MODE;
4562 }
4563 */
4564
4565 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4566 #if (VPU_FORCE_MIU_MODE)
4567 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4568
4569 pShm->u32FWBaseAddr = u32TmpStartOffset;
4570
4571 #else
4572 ///TODO:
4573 /*
4574 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4575
4576 if(u8TmpMiuSel == E_CHIP_MIU_0)
4577 {
4578 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4579 }
4580 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4581 {
4582 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4583 }
4584 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4585 {
4586 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4587 }
4588 */
4589 #endif
4590 //HVD_PRINT("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4591 #else
4592 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4593 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4594 {
4595 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4596 }
4597 pShm->u32FWBaseAddr = u32Addr;
4598 #endif
4599
4600 // RM only
4601 #if HVD_ENABLE_RV_FEATURE
4602 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4603 && (pCtrl->InitParams.pRVFileInfo != NULL))
4604 {
4605 MS_U32 i = 0;
4606
4607 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4608 {
4609 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4610 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4611 }
4612
4613 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4614 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4615 #ifdef VDEC3_FB
4616 pShm->u32RM_VLCTableAddr = 0;
4617 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4618 #else
4619 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDCtx->u32RV_VLCTableAddr;
4620
4621 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4622 u32Addr = u32TmpStartOffset;
4623
4624 pShm->u32RM_VLCTableAddr = u32Addr;
4625 #endif
4626 }
4627 #endif
4628
4629 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4630 && (pCtrl->InitParams.pRVFileInfo != NULL))
4631 {
4632 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4633 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4634 }
4635
4636 //if(pCtrl->InitParams.bColocateBBUMode)
4637 if (_stHVDPreSet[u8Idx].bColocateBBUMode)
4638 {
4639 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr;
4640 }
4641
4642 #if SUPPORT_G2VP9
4643 // Enable SW detile support for G2 VP9
4644 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4645 {
4646 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4647 }
4648 #endif
4649
4650 HAL_HVD_EX_FlushMemory();
4651
4652 return E_HVD_RETURN_SUCCESS;
4653 }
4654 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4655 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4656 #else
4657 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4658 #endif
4659 {
4660 MS_BOOL bInitRet = FALSE;
4661
4662 #if 0
4663 // check MVD power on
4664 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4665 {
4666 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4667 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4668 HVD_Delay_ms(1);
4669 }
4670 // Check VPU power on
4671 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4672 {
4673 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4674 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4675 HVD_Delay_ms(1);
4676 }
4677 // check HVD power on
4678 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4679 {
4680 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4681 HAL_HVD_EX_PowerCtrl(u32Id, TRUE);
4682 HVD_Delay_ms(1);
4683 }
4684 #endif
4685 #ifdef VDEC3
4686 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4687 #else
4688 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4689 #endif
4690 if (!bInitRet)
4691 {
4692 return E_HVD_RETURN_FAIL;
4693 }
4694
4695 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4696
4697 if (!bInitRet)
4698 {
4699 return E_HVD_RETURN_FAIL;
4700 }
4701
4702 return E_HVD_RETURN_SUCCESS;
4703 }
4704
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4705 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4706 {
4707 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4708
4709 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4710
4711 return E_HVD_RETURN_SUCCESS;
4712 }
4713
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)4714 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
4715 {
4716 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4717 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4718 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4719 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
4720 MS_BOOL bMVC = FALSE;
4721 #if HVD_ENABLE_MVC
4722 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4723 #endif
4724
4725 switch (u32type)
4726 {
4727 // share memory
4728 // switch
4729 case E_HVD_SDATA_FRAMEBUF_ADDR:
4730 {
4731 pShm->u32FrameBufAddr = u32Data;
4732 break;
4733 }
4734 case E_HVD_SDATA_FRAMEBUF_SIZE:
4735 {
4736 pShm->u32FrameBufSize = u32Data;
4737 break;
4738 }
4739 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4740 {
4741 pShm->u32FrameBuf2Addr = u32Data;
4742 break;
4743 }
4744 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4745 {
4746 pShm->u32FrameBuf2Size = u32Data;
4747 break;
4748 }
4749 case E_HVD_SDATA_CMA_USED:
4750 {
4751 pShm->bCMA_Use = u32Data;
4752 break;
4753 }
4754 case E_HVD_SDATA_CMA_ALLOC_DONE:
4755 {
4756 pShm->bCMA_AllocDone = u32Data;
4757 break;
4758 }
4759 case E_HVD_SDATA_CMA_TWO_MIU:
4760 {
4761 pShm->bCMA_TwoMIU = u32Data;
4762 break;
4763 }
4764 case E_HVD_SDATA_RM_PICTURE_SIZES:
4765 {
4766 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4767 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4768 break;
4769 }
4770 case E_HVD_SDATA_ERROR_CODE:
4771 {
4772 pShm->u16ErrCode = (MS_U16) u32Data;
4773 break;
4774 }
4775 case E_HVD_SDATA_DISP_INFO_TH:
4776 {
4777 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4778 sizeof(HVD_DISP_THRESHOLD));
4779 break;
4780 }
4781 case E_HVD_SDATA_FW_FLUSH_STATUS:
4782 {
4783 pShm->u8FlushStatus = (MS_U8)u32Data;
4784 break;
4785 }
4786 case E_HVD_SDATA_DMX_FRAMERATE:
4787 {
4788 pShm->u32DmxFrameRate = u32Data;
4789 break;
4790 }
4791 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4792 {
4793 pShm->u32DmxFrameRateBase = u32Data;
4794 break;
4795 }
4796 case E_HVD_SDATA_MIU_SEL:
4797 {
4798 pShm->u32VDEC_MIU_SEL = u32Data;
4799 break;
4800 }
4801 case E_HVD_SDATA_DV_XC_SHM_SIZE:
4802 {
4803 pShm->u32DolbyVisionXCShmSize = u32Data;
4804 break;
4805 }
4806 // SRAM
4807
4808 // Mailbox
4809 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4810 {
4811 if (u32Data != 0)
4812 {
4813 pShm->bEnableDispCtrl = TRUE;
4814 pShm->bIsTrigDisp = TRUE;
4815 }
4816 else
4817 {
4818 pShm->bEnableDispCtrl = FALSE;
4819 }
4820
4821 break;
4822 }
4823 case E_HVD_SDATA_GET_DISP_INFO_START:
4824 {
4825 pShm->bSpsChange = FALSE;
4826 break;
4827 }
4828 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4829 {
4830 pShm->u32VirtualBoxWidth = u32Data;
4831 break;
4832 }
4833 case E_HVD_SDATA_DV_INFO:
4834 {
4835 pShm->u8DVLevelFromDriverAPI = (MS_U8)(u32Data & 0xff);
4836 pShm->u8DVProfileFromDriverAPI = (MS_U8)((u32Data >> 8) & 0xff);
4837 pShm->u8DolbyMetaReorder = (MS_U8)((u32Data >> 16) & 0xff);
4838 }
4839 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4840 {
4841 pShm->u32VirtualBoxHeight = u32Data;
4842 break;
4843 }
4844 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4845 {
4846 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4847 {
4848 //HVD_PRINT("DispFrame DqPtr: %d\n", u32Data);
4849 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4850 }
4851 break;
4852 }
4853 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4854 {
4855 if (!(pHVDCtx->_stHVDStream[u8Idx].bDispOutSide))
4856 {
4857 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4858 {
4859 //HVD_PRINT("DispFrame DqPtr: %ld\n", u32Data);
4860 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4861 }
4862 }
4863 break;
4864 }
4865 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4866 {
4867 if (pHVDCtx->_stHVDStream[u8Idx].bDispOutSide)
4868 {
4869 if (bMVC)
4870 {
4871 if (pHVDCtx->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4872 {
4873 //ALOGE("R1: %x", u32Data);
4874 pHVDCtx->_stHVDStream[u8Idx].u32FreeData = u32Data;
4875 }
4876 else
4877 {
4878 //ALOGE("R2: %x", (u32Data << 16) | pHVDCtx->_stHVDStream[u8Idx].u32FreeData);
4879 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDCtx->_stHVDStream[u8Idx].u32FreeData);
4880 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDCtx->_stHVDStream[u8Idx].u32FreeData;
4881 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4882 pHVDCtx->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4883 }
4884 }
4885 else
4886 {
4887 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4888 }
4889 }
4890 else
4891 {
4892 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4893 {
4894 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4895 }
4896 }
4897 break;
4898 }
4899 #if (HVD_ENABLE_IQMEM)
4900 case E_HVD_SDATA_FW_IQMEM_CTRL:
4901 {
4902 pShm->u8IQmemCtrl= (MS_U8)u32Data;
4903 break;
4904
4905 }
4906 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
4907 {
4908 if (u32Data != 0)
4909 {
4910 pShm->bIQmemEnableIfSupport= TRUE;
4911 }
4912 else
4913 {
4914 pShm->bIQmemEnableIfSupport= FALSE;
4915 }
4916
4917
4918 break;
4919
4920 }
4921 #endif
4922
4923 default:
4924 break;
4925 }
4926
4927 HAL_HVD_EX_FlushMemory();
4928
4929 return eRet;
4930 }
4931
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4932 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4933 {
4934 MS_S64 s64Ret = 0;
4935 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4936
4937 HAL_HVD_EX_ReadMemory();
4938
4939 switch (eType)
4940 {
4941 case E_HVD_GDATA_PTS_STC_DIFF:
4942 s64Ret = pShm->s64PtsStcDiff;
4943 break;
4944 default:
4945 break;
4946 }
4947
4948 return s64Ret;
4949 }
4950
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4951 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4952 {
4953 MS_VIRT u32Ret = 0;
4954 //static MS_U64 u64pts_real = 0;
4955 MS_U64 u64pts_low = 0;
4956 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4957 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
4958 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4959
4960 HAL_HVD_EX_ReadMemory();
4961
4962 if(pShm == NULL)
4963 {
4964 HVD_PRINT("########## VDEC patch for Debug ###########\n");
4965 return 0x0;
4966 }
4967
4968 switch (eType)
4969 {
4970 // share memory
4971 // switch
4972 case E_HVD_GDATA_DISP_INFO_ADDR:
4973 {
4974 u32Ret = (MS_VIRT) (&pShm->DispInfo);
4975 break;
4976 }
4977 case E_HVD_GDATA_MIU_SEL:
4978 u32Ret = pShm->u32VDEC_MIU_SEL;
4979 break;
4980 case E_HVD_GDATA_FRAMEBUF_ADDR:
4981 u32Ret = pShm->u32FrameBufAddr;
4982 break;
4983 case E_HVD_GDATA_FRAMEBUF_SIZE:
4984 u32Ret = pShm->u32FrameBufSize;
4985 break;
4986 case E_HVD_GDATA_FRAMEBUF2_ADDR:
4987 u32Ret = pShm->u32FrameBuf2Addr;
4988 break;
4989 case E_HVD_GDATA_FRAMEBUF2_SIZE:
4990 u32Ret = pShm->u32FrameBuf2Size;
4991 break;
4992 case E_HVD_GDATA_CMA_ALLOC_DONE:
4993 u32Ret = pShm->bCMA_AllocDone;
4994 break;
4995 case E_HVD_GDATA_CMA_USED:
4996 u32Ret = pShm->bCMA_Use;
4997 break;
4998 // report
4999 case E_HVD_GDATA_PTS:
5000 {
5001 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
5002 break;
5003 }
5004 case E_HVD_GDATA_U64PTS:
5005 {
5006 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
5007 pHVDCtx->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
5008 pHVDCtx->u64pts_real = (pHVDCtx->u64pts_real<<32)|u64pts_low;
5009 u32Ret = (MS_VIRT)(&(pHVDCtx->u64pts_real));
5010 break;
5011 }
5012 case E_HVD_GDATA_U64PTS_PRE_PARSE:
5013 {
5014 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
5015 pHVDCtx->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
5016 pHVDCtx->u64pts_real = (pHVDCtx->u64pts_real<<32)|u64pts_low;
5017 u32Ret = (MS_VIRT)(&(pHVDCtx->u64pts_real));
5018 break;
5019 }
5020 case E_HVD_GDATA_DECODE_CNT:
5021 {
5022 u32Ret = pShm->u32DecodeCnt;
5023 break;
5024 }
5025 case E_HVD_GDATA_DATA_ERROR_CNT:
5026 {
5027 u32Ret = pShm->u32DataErrCnt;
5028 break;
5029 }
5030 case E_HVD_GDATA_DEC_ERROR_CNT:
5031 {
5032 u32Ret = pShm->u32DecErrCnt;
5033 break;
5034 }
5035 case E_HVD_GDATA_ERROR_CODE:
5036 {
5037 u32Ret = (MS_U32) (pShm->u16ErrCode);
5038 break;
5039 }
5040 case E_HVD_GDATA_VPU_IDLE_CNT:
5041 {
5042 u32Ret = pShm->u32VPUIdleCnt;
5043 break;
5044 }
5045 case E_HVD_GDATA_DISP_FRM_INFO:
5046 {
5047 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
5048 break;
5049 }
5050 case E_HVD_GDATA_DEC_FRM_INFO:
5051 {
5052 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
5053 break;
5054 }
5055 case E_HVD_GDATA_ES_LEVEL:
5056 {
5057 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
5058 break;
5059 }
5060 #if HVD_ENABLE_MVC
5061 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
5062 {
5063 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
5064 break;
5065 }
5066 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
5067 {
5068 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
5069 break;
5070 }
5071 #endif
5072
5073 // user data
5074 case E_HVD_GDATA_USERDATA_WPTR:
5075 {
5076 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
5077 break;
5078 }
5079 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
5080 {
5081 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
5082 break;
5083 }
5084 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
5085 {
5086 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
5087 break;
5088 }
5089 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
5090 {
5091 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
5092 break;
5093 }
5094 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
5095 {
5096 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
5097 break;
5098 }
5099 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
5100 {
5101 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
5102 break;
5103 }
5104 // report - modes
5105 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
5106 {
5107 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
5108 break;
5109 }
5110 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
5111 {
5112 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
5113 break;
5114 }
5115 case E_HVD_GDATA_IS_ERR_CONCEAL:
5116 {
5117 u32Ret = pShm->ModeStatus.bIsErrConceal;
5118 break;
5119 }
5120 case E_HVD_GDATA_IS_SYNC_ON:
5121 {
5122 u32Ret = pShm->ModeStatus.bIsSyncOn;
5123 break;
5124 }
5125 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
5126 {
5127 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
5128 break;
5129 }
5130 case E_HVD_GDATA_SYNC_MODE:
5131 {
5132 u32Ret = pShm->ModeStatus.u8SyncType;
5133 break;
5134 }
5135 case E_HVD_GDATA_SKIP_MODE:
5136 {
5137 u32Ret = pShm->ModeStatus.u8SkipMode;
5138 break;
5139 }
5140 case E_HVD_GDATA_DROP_MODE:
5141 {
5142 u32Ret = pShm->ModeStatus.u8DropMode;
5143 break;
5144 }
5145 case E_HVD_GDATA_DISPLAY_DURATION:
5146 {
5147 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
5148 break;
5149 }
5150 case E_HVD_GDATA_FRC_MODE:
5151 {
5152 u32Ret = pShm->ModeStatus.u8FrcMode;
5153 break;
5154 }
5155 case E_HVD_GDATA_NEXT_PTS:
5156 {
5157 u32Ret = pShm->u32NextPTS;
5158 break;
5159 }
5160 case E_HVD_GDATA_DISP_Q_SIZE:
5161 {
5162 u32Ret = pShm->u16DispQSize;
5163 break;
5164 }
5165 case E_HVD_GDATA_DISP_Q_PTR:
5166 {
5167 u32Ret = (MS_U32) pHVDCtx->_u16DispQPtr;
5168 break;
5169 }
5170 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
5171 {
5172 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
5173 break;
5174 }
5175 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
5176 {
5177 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
5178 break;
5179 }
5180 case E_HVD_GDATA_REAL_FRAMERATE:
5181 {
5182 // return VPS/VUI timing info framerate, and 0 if timing info not exist
5183 u32Ret = pShm->u32RealFrameRate;
5184 break;
5185 }
5186 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
5187 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
5188 break;
5189 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
5190 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
5191 break;
5192 case E_HVD_GDATA_DISPLAYCOLOURVOLUME_SEI_DATA:
5193 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
5194 break;
5195 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
5196 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
5197 break;
5198 case E_HVD_GDATA_FW_STATUS_FLAG:
5199 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
5200 break;
5201
5202 // internal control
5203 case E_HVD_GDATA_IS_1ST_FRM_RDY:
5204 {
5205 u32Ret = pShm->bIs1stFrameRdy;
5206 break;
5207 }
5208 case E_HVD_GDATA_IS_I_FRM_FOUND:
5209 {
5210 u32Ret = pShm->bIsIFrmFound;
5211 break;
5212 }
5213 case E_HVD_GDATA_IS_SYNC_START:
5214 {
5215 u32Ret = pShm->bIsSyncStart;
5216 break;
5217 }
5218 case E_HVD_GDATA_IS_SYNC_REACH:
5219 {
5220 u32Ret = pShm->bIsSyncReach;
5221 break;
5222 }
5223 case E_HVD_GDATA_FW_VERSION_ID:
5224 {
5225 u32Ret = pShm->u32FWVersionID;
5226 break;
5227 }
5228 case E_HVD_GDATA_FW_IF_VERSION_ID:
5229 {
5230 u32Ret = pShm->u32FWIfVersionID;
5231 break;
5232 }
5233 case E_HVD_GDATA_BBU_Q_NUMB:
5234 {
5235 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
5236 break;
5237 }
5238 case E_HVD_GDATA_DEC_Q_NUMB:
5239 {
5240 u32Ret = pShm->u16DecQNumb;
5241 break;
5242 }
5243 case E_HVD_GDATA_DISP_Q_NUMB:
5244 {
5245 u32Ret = pShm->u16DispQNumb;
5246 break;
5247 }
5248 case E_HVD_GDATA_PTS_Q_NUMB:
5249 {
5250 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
5251 break;
5252 }
5253 case E_HVD_GDATA_FW_INIT_DONE:
5254 {
5255 u32Ret = pShm->bInitDone;
5256 break;
5257 }
5258 // debug
5259 case E_HVD_GDATA_SKIP_CNT:
5260 {
5261 u32Ret = pShm->u32SkipCnt;
5262 break;
5263 }
5264 case E_HVD_GDATA_GOP_CNT:
5265 {
5266 u32Ret = pShm->u32DropCnt;
5267 break;
5268 }
5269 case E_HVD_GDATA_DISP_CNT:
5270 {
5271 u32Ret = pShm->u32DispCnt;
5272 break;
5273 }
5274 case E_HVD_GDATA_DROP_CNT:
5275 {
5276 u32Ret = pShm->u32DropCnt;
5277 break;
5278 }
5279 case E_HVD_GDATA_DISP_STC:
5280 {
5281 u32Ret = pShm->u32DispSTC;
5282 break;
5283 }
5284 case E_HVD_GDATA_VSYNC_CNT:
5285 {
5286 u32Ret = pShm->u32VsyncCnt;
5287 break;
5288 }
5289 case E_HVD_GDATA_MAIN_LOOP_CNT:
5290 {
5291 u32Ret = pShm->u32MainLoopCnt;
5292 break;
5293 }
5294
5295 // AVC
5296 case E_HVD_GDATA_AVC_LEVEL_IDC:
5297 {
5298 u32Ret = pShm->u16AVC_SPS_LevelIDC;
5299 break;
5300 }
5301 case E_HVD_GDATA_AVC_LOW_DELAY:
5302 {
5303 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
5304 break;
5305 }
5306 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
5307 {
5308 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
5309 break;
5310 }
5311 case E_HVD_GDATA_FW_FLUSH_STATUS:
5312 {
5313 u32Ret = (MS_U32) (pShm->u8FlushStatus);
5314 break;
5315 }
5316 case E_HVD_GDATA_FW_CODEC_TYPE:
5317 {
5318 u32Ret = pShm->u32CodecType;
5319 break;
5320 }
5321 case E_HVD_GDATA_FW_ES_BUF_STATUS:
5322 {
5323 u32Ret = (MS_U32)pShm->u8ESBufStatus;
5324 break;
5325 }
5326 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
5327 {
5328 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
5329 {
5330 u32Ret = 1;
5331 }
5332 else
5333 {
5334 u32Ret = 0;
5335 }
5336 break;
5337 }
5338
5339 // SRAM
5340
5341 // Mailbox
5342 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
5343 {
5344 u32Ret = pShm->u32FwState;
5345 break;
5346 }
5347 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
5348 {
5349 u32Ret = pShm->bSpsChange;
5350 break;
5351 }
5352 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
5353 {
5354 u32Ret = pShm->bSpsChange;
5355
5356 if (pShm->bSpsChange &&
5357 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
5358 IS_TASK_ALIVE(pHVDCtx->_stHVDStream[u8Idx].s32HvdPpTaskId))
5359 {
5360 _HVD_EX_PpTask_Delete(&pHVDCtx->_stHVDStream[u8Idx]);
5361 }
5362
5363 break;
5364 }
5365 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
5366 {
5367 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5368
5369 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
5370 {
5371 u32Ret = pShm->u32FwInfo;
5372 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
5373 }
5374 break;
5375 }
5376 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
5377 {
5378 if (pShm->bIsTrigDisp) // not clear yet
5379 {
5380 u32Ret = FALSE;
5381 }
5382 else
5383 {
5384 u32Ret = TRUE;
5385 }
5386 break;
5387 }
5388 case E_HVD_GDATA_ES_READ_PTR:
5389 {
5390 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5391 break;
5392 }
5393 case E_HVD_GDATA_ES_WRITE_PTR:
5394 {
5395 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
5396 break;
5397 }
5398 case E_HVD_GDATA_BBU_READ_PTR:
5399 {
5400 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
5401 break;
5402 }
5403 case E_HVD_GDATA_BBU_WRITE_PTR:
5404 {
5405 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5406 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5407 {
5408 u32Ret = pHVDCtx->u32VP8BBUWptr;
5409 }
5410 else
5411 {
5412 u32Ret = pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr;
5413 }
5414 break;
5415 }
5416 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
5417 {
5418 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5419
5420 u32Ret = pCtrl->u32BBUWptr_Fired;
5421
5422 break;
5423 }
5424 case E_HVD_GDATA_VPU_PC_CNT:
5425 {
5426 u32Ret = _HVD_EX_GetPC(u32Id);
5427 break;
5428 }
5429 case E_HVD_GDATA_ES_QUANTITY:
5430 {
5431 u32Ret=_HVD_EX_GetESQuantity(u32Id);
5432 break;
5433 }
5434
5435
5436 // FW def
5437 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
5438 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
5439 break;
5440
5441 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
5442 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
5443 break;
5444 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
5445 u32Ret = pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNumTH;
5446 break;
5447 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
5448 u32Ret = pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum;
5449 break;
5450 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
5451 u32Ret = MAX_PTS_TABLE_SIZE;
5452 break;
5453 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
5454 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
5455 break;
5456 case E_HVD_GDATA_FW_DS_BUF_ADDR:
5457 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
5458 break;
5459 case E_HVD_GDATA_FW_DS_BUF_SIZE:
5460 u32Ret = pShm->u32DSBuffSize; //3k or 6k
5461 break;
5462 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
5463 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
5464 break;
5465 case E_HVD_GDATA_FW_DS_INFO_ADDR:
5466 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
5467 break;
5468 case E_HVD_GDATA_FW_DS_IS_ENABLED:
5469 {
5470 if (pShm->bDSIsRunning)
5471 {
5472 u32Ret = TRUE;
5473 }
5474 else
5475 {
5476 u32Ret = FALSE;
5477 }
5478 break;
5479 }
5480 #if (HVD_ENABLE_IQMEM)
5481 case E_HVD_GDATA_FW_IQMEM_CTRL:
5482 {
5483
5484 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
5485
5486 break;
5487 }
5488 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
5489 {
5490 if(pShm->bIsIQMEMSupport){
5491 u32Ret = TRUE;
5492 }
5493 else{
5494
5495 u32Ret = FALSE;
5496 }
5497
5498 break;
5499 }
5500 #endif
5501 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
5502 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
5503 break;
5504 case E_HVD_GDATA_FIELD_PIC_FLAG:
5505 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
5506 break;
5507 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
5508 u32Ret = pShm->u32SeamlessTSStatus;
5509 break;
5510 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
5511 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
5512 break;
5513 #ifdef VDEC3
5514 case E_HVD_GDATA_FW_VBBU_ADDR:
5515 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
5516 break;
5517 #endif
5518 case E_HVD_GDATA_GET_NOT_SUPPORT_INFO:
5519 u32Ret = pShm->u32NotSupportInfo;
5520 break;
5521 case E_HVD_GDATA_GET_MIN_TSP_DATA_SIZE:
5522 u32Ret = pShm->u32CurMinTspDataSize;
5523 break;
5524 default:
5525 break;
5526 }
5527 return u32Ret;
5528 }
5529
HAL_HVD_EX_GetDVSupportProfiles(void)5530 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
5531 {
5532 #if 0 // wait avc finish DV dual job
5533 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5534 #else
5535 return E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5536 #endif
5537 }
5538
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)5539 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
5540 {
5541 switch (u32DV_Stream_Profile)
5542 {
5543 #if 0 // wait avc finish DV dual job
5544 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
5545 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
5546 #endif
5547
5548 #if 0 // unsupported profile
5549 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
5550 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5551 #endif
5552
5553 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
5554 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5555
5556 #if 0 // unsupported profile
5557 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
5558 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5559 #endif
5560
5561 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
5562 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5563
5564 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
5565 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5566
5567 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
5568 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5569
5570 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
5571 default:
5572 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5573 }
5574 }
5575
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)5576 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
5577 {
5578 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5579 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
5580 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5581 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
5582
5583 _HAL_HVD_Entry();
5584
5585 // check if old SVD cmds
5586 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5587 {
5588 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
5589
5590 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5591 }
5592
5593 if (u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5594 {
5595 pHVDCtx->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5596 }
5597
5598 #if HVD_ENABLE_MVC
5599 if (pHVDCtx->_stHVDStream[u8Idx].bDispOutSide)
5600 {
5601 if (HAL_HVD_EX_CheckMVCID(u32Id) && u32Cmd == E_HVD_CMD_FLUSH)
5602 {
5603 pHVDCtx->_stHVDStream[u8Idx].u32DispQIndex = 0;
5604 }
5605 }
5606 #endif
5607
5608 if (u32Cmd == E_HVD_CMD_FLUSH &&
5609 IS_TASK_ALIVE(pHVDCtx->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5610 pHVDCtx->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5611 {
5612 pHVDCtx->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5613 while (pHVDCtx->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5614 {
5615 _HAL_HVD_Release();
5616 HVD_Delay_ms(1);
5617 _HAL_HVD_Entry();
5618 }
5619 }
5620
5621 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
5622
5623 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5624
5625 _HAL_HVD_Return(eRet);
5626 }
5627
HAL_HVD_EX_DeInit(MS_U32 u32Id)5628 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5629 {
5630 HVD_Return eRet = E_HVD_RETURN_FAIL;
5631 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5632 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
5633 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5634 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5635 MS_U8 u8MiuSel;
5636 MS_U32 u32StartOffset;
5637 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5638
5639 #if HVD_ENABLE_TIME_MEASURE
5640 MS_U32 ExitTimeCnt = 0;
5641 ExitTimeCnt = HVD_GetSysTime_ms();
5642 #endif
5643
5644 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
5645
5646 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5647
5648 if (E_HVD_RETURN_SUCCESS != eRet)
5649 {
5650 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5651 }
5652
5653 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5654
5655 if (E_HVD_RETURN_SUCCESS != eRet)
5656 {
5657 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5658 }
5659
5660 // check FW state to make sure it's STOP DONE
5661 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5662 {
5663 if (HVD_GetSysTime_ms() > u32Timeout)
5664 {
5665 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt(u32Id));
5666
5667 //return E_HVD_RETURN_TIMEOUT;
5668 eRet = E_HVD_RETURN_TIMEOUT;
5669 break;
5670 }
5671 }
5672
5673 if (pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt)
5674 {
5675 HVD_EX_MSG_INF("VDEC PLUS: DropRatio %d, Drop:0.%d (%d), Dec:0.%d (%d), Disp:0.%d\n",
5676 pShm->u8VdecPlusDropRatio,
5677 100*pShm->u32VdecPlusDropCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5678 pShm->u32VdecPlusDropCnt,
5679 100*pShm->u32VdecPlusDecCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5680 pShm->u32VdecPlusDecCnt,
5681 100*pShm->u32VdecPlusDispPicCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt));
5682 }
5683 else
5684 {
5685 HVD_EX_MSG_INF("VDEC PLUS DISABLE: DropRatio %d, Drop: %d, Dec: %d, Disp: %d\n",
5686 pShm->u8VdecPlusDropRatio,
5687 pShm->u32VdecPlusDropCnt,
5688 pShm->u32VdecPlusDecCnt,
5689 pShm->u32VdecPlusDispPicCnt);
5690 }
5691
5692 VPU_EX_FWCodeCfg fwCfg;
5693 VPU_EX_TaskInfo taskInfo;
5694 VPU_EX_NDecInitPara nDecInitPara;
5695
5696 nDecInitPara.pFWCodeCfg = &fwCfg;
5697 nDecInitPara.pTaskInfo = &taskInfo;
5698
5699 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5700 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5701
5702 taskInfo.u32Id = u32Id;
5703 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5704 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5705
5706 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5707 {
5708 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5709 }
5710 else
5711 {
5712 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5713 }
5714
5715 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5716 {
5717 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5718 }
5719
5720 /* clear es buffer */
5721 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5722 {
5723 //HVD_PRINT("Clear ES buffer\n");
5724
5725 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5726 }
5727
5728 //_HAL_HVD_MutexDelete();
5729
5730 #if HVD_ENABLE_TIME_MEASURE
5731 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5732 #endif
5733
5734 pHVDCtx->_stHVDStream[u8Idx].bUsed = FALSE;
5735 pHVDCtx->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
5736
5737 #ifndef VDEC3
5738 // reset bbu wptr
5739 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5740 {
5741 if(TRUE == HAL_VPU_EX_HVDInUsed(u32Id))
5742 {
5743 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5744 {
5745 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5746 pHVDCtx->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5747 }
5748 else
5749 {
5750 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5751 {
5752 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5753 }
5754 pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5755 }
5756 }
5757 else
5758 {
5759 pHVDCtx->_stHVDStream[0].u32BBUWptr = 0; //main
5760 pHVDCtx->_stHVDStream[1].u32BBUWptr = 0; //sub
5761 pHVDCtx->u32VP8BBUWptr = 0; //VP8
5762 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5763 {
5764 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5765 {
5766 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5767 }
5768 }
5769 else
5770 {
5771 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5772 }
5773 }
5774 }
5775 #endif
5776
5777 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5778
5779 if (IS_TASK_ALIVE(pHVDCtx->_stHVDStream[u8Idx].s32HvdPpTaskId))
5780 {
5781 _HVD_EX_PpTask_Delete(&pHVDCtx->_stHVDStream[u8Idx]);
5782 }
5783
5784 if (pHVDCtx->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable)
5785 {
5786
5787 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
5788
5789 _HAL_HVD_Entry();
5790 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
5791 _HAL_HVD_Release();
5792
5793 }
5794
5795 pHVDCtx->_stHVDStream[u8Idx].u32RegBase = 0;
5796 pHVDHalContext->u8Cidx[u8Idx] = 0xFF;
5797 HVD_EX_MSG_DBG("success\n");
5798
5799 return eRet;
5800 }
5801
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5802 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5803 {
5804 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5805 MS_U32 u32Addr = 0;
5806 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5807 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5808 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
5809
5810 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5811
5812 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5813 {
5814 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5815
5816 if (E_HVD_RETURN_SUCCESS != eRet)
5817 {
5818 return eRet;
5819 }
5820 }
5821
5822 //HVD_PRINT(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5823
5824 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5825 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5826 {
5827 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5828
5829 if (E_HVD_RETURN_SUCCESS != eRet)
5830 {
5831 return eRet;
5832 }
5833 }
5834
5835 u32Addr = pInfo->u32Staddr;
5836
5837 if (pInfo->bRVBrokenPacket)
5838 {
5839 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5840 }
5841
5842 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5843 {
5844 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5845 }
5846 else
5847 {
5848 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5849 }
5850
5851 if (E_HVD_RETURN_SUCCESS != eRet)
5852 {
5853 return eRet;
5854 }
5855
5856 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5857 {
5858 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5859 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5860
5861 if (E_HVD_RETURN_SUCCESS != eRet)
5862 {
5863 return eRet;
5864 }
5865 }
5866
5867 pHVDCtx->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5868
5869 // do not add local pointer
5870 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5871 {
5872 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5873
5874 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5875 (u32PacketStAddr <
5876 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5877 {
5878 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5879 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5880 }
5881 else
5882 {
5883 //null packet
5884 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5885 pCtrl->LastNal.u32NalSize = 0;
5886 }
5887 }
5888 else
5889 {
5890 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5891 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5892 }
5893
5894 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5895 pCtrl->u32BBUPacketCnt++;
5896
5897 return eRet;
5898 }
5899
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5900 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5901 {
5902 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5903 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
5904 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
5905
5906 if (bEnable)
5907 {
5908 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5909 }
5910 else
5911 {
5912 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5913 }
5914 }
5915
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5916 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5917 {
5918 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5919 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
5920 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
5921
5922 if (bEnable)
5923 {
5924 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5925 }
5926 else
5927 {
5928 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5929 }
5930 }
5931
HAL_HVD_EX_SetClearISR(MS_U32 u32RB)5932 void HAL_HVD_EX_SetClearISR(MS_U32 u32RB)
5933 {
5934 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5935 }
5936
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5937 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5938 {
5939 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5940 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
5941 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
5942
5943 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5944 }
5945
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)5946 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
5947 {
5948 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5949 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
5950 MS_U32 u32RB = pHVDCtx->_stHVDStream[u8Idx].u32RegBase;
5951
5952 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
5953 {
5954 return FALSE;
5955 }
5956 else
5957 {
5958 return TRUE;
5959 }
5960 }
5961
HAL_HVD_EX_IsAlive(MS_U32 u32Id)5962 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
5963 {
5964 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5965
5966 if (pCtrl)
5967 {
5968 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
5969 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
5970 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
5971 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
5972 {
5973 return FALSE;
5974 }
5975 else
5976 {
5977 return TRUE;
5978 }
5979 }
5980 else
5981 {
5982 return FALSE;
5983 }
5984 }
5985
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)5986 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
5987 {
5988 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5989 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5990 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
5991 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5992
5993 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5994 {
5995 HAL_HVD_EX_ReadMemory();
5996
5997 pHVDCtx->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
5998 pHVDCtx->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
5999
6000 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
6001 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDCtx->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDCtx->_stHVDStream[u8Idx].u32PTSPreWptr);
6002 }
6003
6004 return TRUE;
6005 }
6006
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)6007 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
6008 {
6009 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6010 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6011 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
6012 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6013 MS_U32 u32Data;
6014
6015 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
6016
6017 HAL_HVD_EX_FlushMemory();
6018 if (pHVDCtx->_stHVDStream[u8Idx].bDispOutSide)
6019 {
6020 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
6021 pCtrl->LastNal.u32NalAddr = u32Data;
6022 pCtrl->LastNal.u32NalSize = 0;
6023 }
6024
6025 if (IS_TASK_ALIVE(pHVDCtx->_stHVDStream[u8Idx].s32HvdPpTaskId))
6026 pHVDCtx->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
6027
6028 return TRUE;
6029 }
6030
HAL_HVD_EX_UartSwitch2FW(MS_U32 u32Id,MS_BOOL bEnable)6031 void HAL_HVD_EX_UartSwitch2FW(MS_U32 u32Id, MS_BOOL bEnable)
6032 {
6033 if (bEnable)
6034 {
6035 if (HAL_VPU_EX_IsEVDR2(u32Id))
6036 {
6037 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
6038 }
6039 else
6040 {
6041 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_R2_LITE, REG_TOP_UART_SEL_0_MASK);
6042 }
6043 }
6044 else
6045 {
6046 #if defined (__aeon__)
6047 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6048 #else // defined (__mips__)
6049 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
6050 #endif
6051 }
6052 }
6053
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)6054 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
6055 {
6056 return 0;
6057 }
6058
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)6059 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
6060 {
6061 return;
6062 }
6063
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)6064 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
6065 {
6066 //if( u16Clock == 0 )
6067 return 216; //140;
6068 //if( )
6069 }
6070
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)6071 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
6072 {
6073 //MS_BOOL bBitMIU1 = FALSE;
6074 //MS_BOOL bCodeMIU1 = FALSE;
6075 MS_U8 u8BitMiuSel = 0;
6076 MS_U8 u8CodeMiuSel = 0;
6077 MS_U32 u32BitStartOffset;
6078 MS_U32 u32CodeStartOffset;
6079 //MS_U8 u8MiuSel;
6080 //MS_U32 u32StartOffset;
6081 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6082 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6083 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
6084 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6085 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
6086
6087 #if HVD_ENABLE_MVC
6088 if(HAL_HVD_EX_CheckMVCID(u32Id))
6089 {
6090 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
6091 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
6092 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
6093 {
6094 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
6095 }
6096 }
6097 #endif /// HVD_ENABLE_MVC
6098
6099 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6100 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6101
6102
6103
6104
6105 if (u8BitMiuSel != u8CodeMiuSel)
6106 {
6107 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
6108 BDMA_Result bdmaRlt;
6109 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6110
6111 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6112 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
6113 u32tabsize = pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6114
6115 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
6116
6117 if (E_BDMA_OK != bdmaRlt)
6118 {
6119 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
6120 }
6121 #else
6122 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6123
6124 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6125 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
6126 u32tabsize = pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6127
6128 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
6129 #endif
6130 }
6131
6132 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
6133
6134 HAL_HVD_EX_FlushMemory();
6135
6136 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6137 {
6138 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDCtx->u32VP8BBUWptr));
6139 pCtrl->u32BBUWptr_Fired = pHVDCtx->u32VP8BBUWptr;
6140 }
6141 else
6142 {
6143 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr));
6144 pCtrl->u32BBUWptr_Fired = pHVDCtx->_stHVDStream[u8Idx].u32BBUWptr;
6145 }
6146 }
6147
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)6148 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
6149 {
6150 if (bEnable)
6151 {
6152 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
6153 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
6154 }
6155 else
6156 {
6157 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
6158 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
6159 }
6160 }
6161
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)6162 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
6163 {
6164 MS_U32 tmp1 = 0;
6165 MS_U32 tmp2 = 0;
6166 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6167
6168 HAL_HVD_EX_ReadMemory();
6169
6170 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
6171 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
6172
6173 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6174 {
6175 MS_U32 u32Tmp = u32UartCtrl;
6176
6177 HVD_EX_MSG_DBG("\n");
6178 u32UartCtrl = 0; // turn off debug message to prevent other function prints
6179 HVD_PRINT("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
6180 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt(u32Id));
6181
6182 HVD_PRINT("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
6183 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
6184 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
6185 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
6186
6187 HVD_PRINT("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
6188 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
6189 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
6190
6191 HVD_PRINT("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
6192 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
6193 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
6194 _HVD_EX_GetESLevel(u32Id));
6195
6196 HVD_PRINT("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
6197 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
6198 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
6199 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
6200 HVD_PRINT
6201 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
6202 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
6203 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
6204 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
6205 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
6206 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
6207 pShm->ModeStatus.bShowOneField);
6208
6209 u32UartCtrl = u32Tmp; // recover debug level
6210 }
6211 }
6212
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)6213 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
6214 {
6215 MS_U8 *u32Addr = NULL;
6216 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6217 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
6218 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6219
6220 if (u32Idx >= pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum)
6221 {
6222 return;
6223 }
6224
6225 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
6226
6227 *u32NalSize = *(u32Addr + 2) & 0x1f;
6228 *u32NalSize <<= 8;
6229 *u32NalSize |= *(u32Addr + 1) & 0xff;
6230 *u32NalSize <<= 8;
6231 *u32NalSize |= *(u32Addr) & 0xff;
6232
6233 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
6234 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
6235 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
6236 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
6237 }
6238
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)6239 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
6240 {
6241 MS_U32 u32CurIdx = 0;
6242 MS_BOOL bFinished = FALSE;
6243 MS_U32 u32NalOffset = 0;
6244 MS_U32 u32NalSize = 0;
6245 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6246 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
6247
6248 if ((u32StartIdx >= pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum))
6249 {
6250 return;
6251 }
6252
6253 u32CurIdx = u32StartIdx;
6254
6255 do
6256 {
6257 if (u32CurIdx == u32EndIdx)
6258 {
6259 bFinished = TRUE;
6260 }
6261
6262 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
6263
6264 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
6265 {
6266 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
6267 }
6268
6269 u32CurIdx++;
6270
6271 if (u32CurIdx >= pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum)
6272 {
6273 u32CurIdx %= pHVDCtx->_stHVDStream[u8Idx].u32BBUEntryNum;
6274 }
6275 } while (bFinished == TRUE);
6276 }
6277
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)6278 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
6279 {
6280 MS_U32 i = 0;
6281 MS_U32 value = 0;
6282
6283 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6284 {
6285 HVD_EX_MSG_DBG("\n");
6286
6287 for (i = 0; i <= u32Num; i++)
6288 {
6289 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
6290 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
6291 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
6292
6293 if (value == 0)
6294 {
6295 break;
6296 }
6297
6298 HVD_PRINT(" %08x", value);
6299
6300 if (((i % 8) + 1) == 8)
6301 {
6302 HVD_PRINT(" |%u\n", i + 1);
6303 }
6304 }
6305
6306 HVD_PRINT("\nHVD Dump HW status End: total number:%u\n", i);
6307 }
6308 }
6309
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)6310 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
6311 {
6312 if (pDrvCtrl)
6313 {
6314 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
6315 }
6316 }
6317
6318 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)6319 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
6320 {
6321 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
6322 }
6323
HAL_HVD_EX_GetView(MS_U32 u32Id)6324 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
6325 {
6326 if( (0xFF & (u32Id >> 8)) == 0x10)
6327 return E_VDEC_EX_MAIN_VIEW;
6328 else
6329 return E_VDEC_EX_SUB_VIEW;
6330 }
6331 #endif ///HVD_ENABLE_MVC
6332
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)6333 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
6334 {
6335 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
6336 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
6337 return;
6338 }
6339
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)6340 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
6341 {
6342 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
6343 return;
6344 }
6345
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)6346 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
6347 {
6348 MS_U64 _hw_max_pixel = 0;
6349 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
6350
6351 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
6352 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
6353 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
6354 }
6355
6356
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)6357 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
6358 {
6359 #if 1
6360 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6361 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
6362 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6363 MS_U16 u16QNum = pShm->u16DispQNumb;
6364 MS_U16 u16QPtr = pShm->u16DispQPtr;
6365 // MS_U16 u16QSize = pShm->u16DispQSize;
6366 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
6367 MS_U32 u32DispQNum = 0;
6368 #if HVD_ENABLE_MVC
6369 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
6370
6371 if(bMVC)
6372 {
6373 #if 0
6374 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
6375 {
6376 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
6377 }
6378 #endif
6379
6380 //HVD_PRINT("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
6381 //search the next frame to display
6382 while (u16QNum > 0)
6383 {
6384 //HVD_PRINT("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
6385 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
6386 pHVDCtx->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6387
6388 //HVD_PRINT("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
6389 if (pHVDCtx->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6390 {
6391 /// For MVC. Output views after the pair of (base and depend) views were decoded.
6392 /// Check the depned view was initial when Output the base view.
6393 if((u16QPtr%2) == 0)
6394 {
6395 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
6396 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
6397 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
6398 {
6399 ///HVD_PRINT("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
6400 ///HVD_PRINT("Return NULL.\n");
6401 continue;
6402 }
6403 }
6404 u32DispQNum++;
6405 }
6406
6407 u16QNum--;
6408 //go to next frame in the dispQ
6409 u16QPtr++;
6410
6411 if (u16QPtr >= pShm->u16DispQSize)
6412 {
6413 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
6414 }
6415 }
6416 }
6417 else
6418 #endif ///HVD_ENABLE_MVC
6419 {
6420 #if 0
6421 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
6422 {
6423 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
6424 }
6425 #endif
6426 // HVD_PRINT("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
6427 //search the next frame to display
6428 while (u16QNum != 0)
6429 {
6430 pHVDCtx->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6431
6432 // HVD_PRINT("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
6433 if (pHVDCtx->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6434 {
6435 u32DispQNum++;
6436 }
6437
6438 u16QNum--;
6439 //go to next frame in the dispQ
6440 u16QPtr++;
6441
6442 if (u16QPtr == pShm->u16DispQSize)
6443 {
6444 u16QPtr = 0; //wrap to the begin
6445 }
6446 }
6447 }
6448
6449 //HVD_PRINT("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
6450 return u32DispQNum;
6451 #else
6452 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
6453 return pShm->u16DispQNumb;
6454 #endif
6455 }
6456
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)6457 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
6458 {
6459 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6460 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
6461
6462 if (pHVDHalContext->u8Cidx[u8Idx] == HWDEC_EVD_LITE)
6463 {
6464 pHVDCtx->_stHVDStream[u8Idx].u32RegBase = REG_EVD_LITE_BASE;
6465
6466 if (((u32ModeFlag & E_HVD_INIT_HW_MASK) != E_HVD_INIT_HW_HEVC) && ((u32ModeFlag & E_HVD_INIT_HW_MASK) != E_HVD_INIT_HW_VP9))
6467 {
6468 HVD_EX_MSG_ERR("Not HEVC nor VP9 using HWDEC_EVD_LITE 0x%x, 0x%x \033[0m\n", u32Id, u32ModeFlag);
6469 }
6470 }
6471 else
6472 {
6473 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
6474 {
6475 pHVDCtx->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6476 }
6477 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
6478 {
6479 #if SUPPORT_G2VP9 && defined(VDEC3)
6480 pHVDCtx->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
6481 #else // Not using G2 VP9 implies using Mstar EVD VP9
6482 pHVDCtx->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6483 #endif
6484 }
6485 else
6486 {
6487 pHVDCtx->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
6488 }
6489 }
6490
6491 HVD_PRINT("%s 0x%x, %d, %d, 0x%x \033[0m\n", __FUNCTION__, u32Id, u8Idx, pHVDHalContext->u8Cidx[u8Idx], pHVDCtx->_stHVDStream[u8Idx].u32RegBase);
6492 }
6493
6494 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)6495 void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
6496 {
6497 MS_U8 i,j;
6498 MS_U8 u8EVDTaskCnt = 0;
6499 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6500 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
6501
6502 for (j = 0; j < MAX_HVD_EVD_NUM; j++) //may refer to _HAL_EX_BBU_EVD_InUsed
6503 {
6504 HVD_Unit_Ctx *pCheckHVDCtx = &pHVDHalContext->_stCtx[j];
6505
6506 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
6507 {
6508 if ((pCheckHVDCtx->_stHVDStream[i].bUsed) &&
6509 ((pCheckHVDCtx->_stHVDStream[i].u32CodecType == E_HAL_HVD_HEVC)
6510 #if SUPPORT_MSVP9
6511 ||(pCheckHVDCtx->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP9)
6512 #endif
6513 ))
6514 {
6515 u8EVDTaskCnt++;
6516 break;
6517 }
6518 }
6519 }
6520
6521 if (bEnable)
6522 {
6523 if (u8EVDTaskCnt == 0)
6524 {
6525 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6526 }
6527 }
6528 else
6529 {
6530 if (u8EVDTaskCnt == 1)
6531 {
6532 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6533 }
6534 }
6535
6536 HVD_EX_MSG_DBG("EVD clk=%d\n", pHVDCtx->u32EVDClockType);
6537
6538 if (pHVDHalContext->u8Cidx[u8Idx] == HWDEC_EVD_LITE)
6539 {
6540 #ifdef CONFIG_MSTAR_CLKM
6541 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_LITE, bEnable);
6542 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_PPU_LITE, bEnable);
6543 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_HVD_AEC_LITE, bEnable);
6544 #else
6545 if (bEnable)
6546 {
6547 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, ~TOP_CKG_EVD_PPU_LITE_DIS, TOP_CKG_EVD_PPU_LITE_DIS);
6548 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, ~TOP_CKG_EVD_LITE_DIS, TOP_CKG_EVD_LITE_DIS);
6549 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, ~TOP_CKG_HVD_AEC_LITE_DIS, TOP_CKG_HVD_AEC_LITE_DIS);
6550 }
6551 else
6552 {
6553 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, TOP_CKG_EVD_PPU_LITE_DIS, TOP_CKG_EVD_PPU_LITE_DIS);
6554 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, TOP_CKG_EVD_LITE_DIS, TOP_CKG_EVD_LITE_DIS);
6555 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, TOP_CKG_HVD_AEC_LITE_DIS, TOP_CKG_HVD_AEC_LITE_DIS);
6556 }
6557
6558 switch (pHVDCtx->u32EVDClockType)
6559 {
6560 case 576:
6561 {
6562 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, TOP_CKG_EVD_PPU_LITE_PLL_BUF, TOP_CKG_EVD_PPU_LITE_MASK);
6563 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, TOP_CKG_EVD_LITE_480MHZ, TOP_CKG_EVD_LITE_MASK);
6564 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, TOP_CKG_HVD_AEC_LITE_288MHZ, TOP_CKG_HVD_AEC_LITE_CLK_MASK);
6565 break;
6566 }
6567 case 532:
6568 {
6569 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, TOP_CKG_EVD_PPU_LITE_MIU128PLL, TOP_CKG_EVD_PPU_LITE_MASK);
6570 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, TOP_CKG_EVD_LITE_MIU128PLL, TOP_CKG_EVD_LITE_MASK);
6571 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, TOP_CKG_HVD_AEC_LITE_288MHZ, TOP_CKG_HVD_AEC_LITE_CLK_MASK);
6572 break;
6573 }
6574 case 466:
6575 {
6576 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, TOP_CKG_EVD_PPU_LITE_MIU256PLL, TOP_CKG_EVD_PPU_LITE_MASK);
6577 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, TOP_CKG_EVD_LITE_MIU256PLL, TOP_CKG_EVD_LITE_MASK);
6578 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, TOP_CKG_HVD_AEC_LITE_288MHZ, TOP_CKG_HVD_AEC_LITE_CLK_MASK);
6579 break;
6580 }
6581 case 480:
6582 {
6583 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, TOP_CKG_EVD_PPU_LITE_480MHZ, TOP_CKG_EVD_PPU_LITE_MASK);
6584 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, TOP_CKG_EVD_LITE_480MHZ, TOP_CKG_EVD_LITE_MASK);
6585 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, TOP_CKG_HVD_AEC_LITE_288MHZ, TOP_CKG_HVD_AEC_LITE_CLK_MASK);
6586 break;
6587 }
6588 case 384:
6589 {
6590 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, TOP_CKG_EVD_PPU_LITE_384MHZ, TOP_CKG_EVD_PPU_LITE_MASK);
6591 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, TOP_CKG_EVD_LITE_384MHZ, TOP_CKG_EVD_LITE_MASK);
6592 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, TOP_CKG_HVD_AEC_LITE_288MHZ, TOP_CKG_HVD_AEC_LITE_CLK_MASK);
6593 break;
6594 }
6595 case 320:
6596 {
6597 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, TOP_CKG_EVD_PPU_LITE_320MHZ, TOP_CKG_EVD_PPU_LITE_MASK);
6598 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, TOP_CKG_EVD_LITE_320MHZ, TOP_CKG_EVD_LITE_MASK);
6599 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, TOP_CKG_HVD_AEC_LITE_288MHZ, TOP_CKG_HVD_AEC_LITE_CLK_MASK);
6600 break;
6601 }
6602 case 240:
6603 {
6604 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, TOP_CKG_EVD_PPU_LITE_240MHZ, TOP_CKG_EVD_PPU_LITE_MASK);
6605 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, TOP_CKG_EVD_LITE_240MHZ, TOP_CKG_EVD_LITE_MASK);
6606 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, TOP_CKG_HVD_AEC_LITE_240MHZ, TOP_CKG_HVD_AEC_LITE_CLK_MASK);
6607 break;
6608 }
6609 case 192:
6610 {
6611 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, TOP_CKG_EVD_PPU_LITE_192MHZ, TOP_CKG_EVD_PPU_LITE_MASK);
6612 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, TOP_CKG_EVD_LITE_192MHZ, TOP_CKG_EVD_LITE_MASK);
6613 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, TOP_CKG_HVD_AEC_LITE_216MHZ, TOP_CKG_HVD_AEC_LITE_CLK_MASK);
6614 break;
6615 }
6616 default:
6617 {
6618 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU_LITE, TOP_CKG_EVD_PPU_LITE_PLL_BUF, TOP_CKG_EVD_PPU_LITE_MASK);
6619 _HVD_WriteWordMask(REG_TOP_CKG_EVD_LITE, TOP_CKG_EVD_LITE_480MHZ, TOP_CKG_EVD_LITE_MASK);
6620 _HVD_WriteWordMask(REG_TOP_HVD_AEC_LITE, TOP_CKG_HVD_AEC_LITE_288MHZ, TOP_CKG_HVD_AEC_LITE_CLK_MASK);
6621 break;
6622 }
6623 }
6624 #endif
6625 #ifdef CONFIG_MSTAR_SRAMPD
6626 if (bEnable)
6627 {
6628 _HVD_WriteByteMask(REG_HICODEC_LITE_SRAM_SD_EN, HICODEC_LITE_SRAM_HICODEC0, HICODEC_LITE_SRAM_HICODEC0);
6629 HVD_Delay_ms(1);
6630 }
6631 else
6632 {
6633 _HVD_WriteByteMask(REG_HICODEC_LITE_SRAM_SD_EN, ~HICODEC_LITE_SRAM_HICODEC0, HICODEC_LITE_SRAM_HICODEC0);
6634 HVD_Delay_ms(1);
6635 }
6636 #endif
6637 }
6638 else
6639 {
6640 #ifdef CONFIG_MSTAR_CLKM
6641 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD, bEnable);
6642 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_PPU, bEnable);
6643 #else
6644 if (bEnable)
6645 {
6646 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6647 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6648 }
6649 else
6650 {
6651 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6652 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6653 }
6654
6655 switch (pHVDCtx->u32EVDClockType)
6656 {
6657 case 576:
6658 {
6659 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6660 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6661 break;
6662 }
6663 case 532:
6664 {
6665 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
6666 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
6667 break;
6668 }
6669 case 466:
6670 {
6671 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6672 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
6673 break;
6674 }
6675 case 480:
6676 {
6677 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
6678 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6679 break;
6680 }
6681 case 384:
6682 {
6683 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
6684 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
6685 break;
6686 }
6687 case 320:
6688 {
6689 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
6690 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
6691 break;
6692 }
6693 case 240:
6694 {
6695 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
6696 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6697 break;
6698 }
6699 case 192:
6700 {
6701 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
6702 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
6703 break;
6704 }
6705 default:
6706 {
6707 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6708 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6709 break;
6710 }
6711 }
6712 #endif
6713 #ifdef CONFIG_MSTAR_SRAMPD
6714 if (bEnable)
6715 {
6716 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6717 HVD_Delay_ms(1);
6718 }
6719 else
6720 {
6721 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6722 HVD_Delay_ms(1);
6723 }
6724 #endif
6725 }
6726 return;
6727 }
6728
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)6729 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
6730 {
6731 #ifndef VDEC3
6732 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6733 #endif
6734 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6735 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6736 MS_U8 u8EVD = pHVDHalContext->u8Cidx[u8Idx];
6737
6738 #ifdef VDEC3
6739 if (0 == pCtrl->u32BBUId)
6740 #else
6741 if (0 == u8TaskId)
6742 #endif
6743 {
6744 _HVD_Write2Byte(EVD_REG_RESET(u8EVD), (_HVD_Read2Byte(EVD_REG_RESET(u8EVD)) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
6745 }
6746 else
6747 {
6748 _HVD_Write2Byte(EVD_REG_RESET(u8EVD), (_HVD_Read2Byte(EVD_REG_RESET(u8EVD)) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
6749 }
6750
6751 return;
6752 }
6753
HAL_EVD_EX_DeinitHW(MS_U32 u32Id)6754 static MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id)
6755 {
6756 MS_U16 u16Timeout = 1000;
6757 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6758 MS_U8 u8EVD = pHVDHalContext->u8Cidx[u8Idx];
6759
6760 _HVD_WriteWordMask(EVD_REG_RESET(u8EVD), EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
6761
6762 while (u16Timeout)
6763 {
6764 if ((_HVD_Read2Byte(EVD_REG_RESET(u8EVD)) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
6765 {
6766 break;
6767 }
6768 u16Timeout--;
6769 }
6770
6771 HAL_EVD_EX_PowerCtrl(u32Id, FALSE);
6772
6773 return TRUE;
6774 }
6775 #endif
6776
6777 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)6778 static void HAL_VP9_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
6779 {
6780 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6781 HVD_Unit_Ctx *pHVDCtx = &pHVDHalContext->_stCtx[pHVDHalContext->u8Cidx[u8Idx]];
6782
6783 if (bEnable)
6784 {
6785 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6786 }
6787 else
6788 {
6789 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6790 }
6791
6792 switch (pHVDCtx->u32VP9ClockType)
6793 {
6794 case 432:
6795 {
6796 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6797 break;
6798 }
6799 case 384:
6800 {
6801 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6802 break;
6803 }
6804 case 345:
6805 {
6806 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6807 break;
6808 }
6809 case 320:
6810 {
6811 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6812 break;
6813 }
6814 case 288:
6815 {
6816 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6817 break;
6818 }
6819 case 240:
6820 {
6821 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6822 break;
6823 }
6824 case 216:
6825 {
6826 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6827 break;
6828 }
6829 case 172:
6830 {
6831 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
6832 break;
6833 }
6834 default:
6835 {
6836 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6837 break;
6838 }
6839 }
6840
6841 return;
6842 }
6843
HAL_VP9_EX_DeinitHW(MS_U32 u32Id)6844 MS_BOOL HAL_VP9_EX_DeinitHW(MS_U32 u32Id)
6845 {
6846 MS_U16 u16Timeout = 1000;
6847
6848 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6849
6850 while (u16Timeout)
6851 {
6852 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6853 {
6854 break;
6855 }
6856 u16Timeout--;
6857 }
6858
6859 HAL_VP9_EX_PowerCtrl(u32Id);
6860
6861 return TRUE;
6862 }
6863 #endif
6864
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6865 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6866 {
6867 return TRUE;
6868 }
HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)6869 void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)
6870 {
6871 _HVD_EX_SetBufferAddr(u32Id);
6872 }
6873
6874
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)6875 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6876 {
6877 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6878
6879 if(pCtrl->InitParams.u16ChipECONum == 0)
6880 return FALSE;
6881 else
6882 return TRUE;
6883
6884 }
6885
6886
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6887 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6888 {
6889
6890 }
6891
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6892 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6893 {
6894
6895 }
6896
HAL_HVD_EX_GetEVDHWBuffer(void)6897 MS_U32 HAL_HVD_EX_GetEVDHWBuffer(void)
6898 {
6899 return EVD_HW_BUFFER;
6900 }
6901
6902 #else
6903 #include "drvMMIO.h"
6904 #include "regHVD_EX.h"
6905 #include "halCHIP.h"
6906 #include "halHVD_EX.h"
6907
6908 #if defined(MSOS_TYPE_OPTEE)
6909 #define PRINTF printf
6910 MS_U32 u32HVDRegOSBase;
6911 #define HVD_LWORD(x) (MS_U16)((x)&0xffff)
6912 #define HVD_HWORD(x) (MS_U16)(((x)>>16)&0xffff)
6913
HAL_HVD_EX_SetLockDownOpteeRegister(void * param)6914 MS_BOOL HAL_HVD_EX_SetLockDownOpteeRegister(void* param)
6915 {
6916 MS_PHY u32StAddr;
6917 MS_PHY u32StartOffset;
6918 MS_U8 u8MiuSel;
6919 MS_U32 u32NonPMBankSize = 0;
6920 MS_U32 u32RegBase;
6921 Lock_Register_Info* Lock_info;
6922
6923 if(param == NULL)
6924 {
6925 return FALSE;
6926 }
6927
6928 Lock_info = (Lock_Register_Info*)param;
6929
6930 MDrv_MMIO_GetBASE(&u32HVDRegOSBase, &u32NonPMBankSize, MS_MODULE_HW);
6931
6932 _phy_to_miu_offset(u8MiuSel, u32StartOffset, Lock_info->BSBufAddr);
6933 u32StAddr = u32StartOffset;
6934
6935 if(Lock_info->Decoder== E_Decode_HVD || Lock_info->Decoder == E_Decode_VP8)
6936 {
6937 u32RegBase = REG_HVD_BASE;
6938 printf("[VDEC][OPTEE]Dec=%d,RegBase=%x\n",Lock_info->Decoder,u32RegBase);
6939 }
6940 else if(Lock_info->Decoder == E_Decode_EVD)
6941 {
6942 //u32RegBase = REG_EVD_LITE_BASE;
6943 u32RegBase = REG_EVD_BASE;
6944 printf("[VDEC][OPTEE]Dec=%d,RegBase=%x\n",Lock_info->Decoder,u32RegBase);
6945 }
6946
6947 if(Lock_info->stream_ID == 0)
6948 {
6949 if(Lock_info->Decoder == E_Decode_HVD || Lock_info->Decoder == E_Decode_EVD)
6950 {
6951 printf("[VDEC][OPTEE]%d:set HVD/EVD register\n",Lock_info->stream_ID);
6952 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RegBase), HVD_LWORD(u32StAddr >> 3));
6953 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RegBase), HVD_HWORD(u32StAddr >> 3));
6954 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RegBase), HVD_LWORD(Lock_info->BSBufSize>>3));
6955 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RegBase), HVD_HWORD(Lock_info->BSBufSize>>3));
6956 }
6957 else if(Lock_info->Decoder == E_Decode_VP8)
6958 {
6959 printf("[VDEC][OPTEE]%d:set VP8 register\n",Lock_info->stream_ID);
6960 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
6961 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
6962 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(Lock_info->BSBufSize>>3));
6963 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(Lock_info->BSBufSize>>3));
6964 }
6965 }
6966 else if(Lock_info->stream_ID == 1)
6967 {
6968 if(Lock_info->Decoder == E_Decode_HVD || Lock_info->Decoder == E_Decode_EVD)
6969 {
6970 printf("[VDEC][OPTEE]%d:set HVD/EVD register\n",Lock_info->stream_ID);
6971 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RegBase), HVD_LWORD(u32StAddr >> 3));
6972 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RegBase), HVD_HWORD(u32StAddr >> 3));
6973 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RegBase), HVD_LWORD(Lock_info->BSBufSize >> 3));
6974 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RegBase), HVD_HWORD(Lock_info->BSBufSize >> 3));
6975 }
6976 else if(Lock_info->Decoder == E_Decode_VP8)
6977 {
6978 printf("[VDEC][OPTEE]%d:set VP8 register\n",Lock_info->stream_ID);
6979 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
6980 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
6981 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(Lock_info->BSBufSize>>3));
6982 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(Lock_info->BSBufSize>>3));
6983 }
6984 }
6985
6986 return TRUE;
6987 }
6988 #endif
6989 #endif
6990