1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
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11 //
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15 //
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20 //
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32 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
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89 // reverse engineering and compiling of the contents of MStar Confidential
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126 #define RV_VLC_TABLE_SIZE 0x20000
127 /* Add for Mobile Platform by Ted Sun */
128 //#define HVD_DISPQ_PREFETCH_COUNT 2
129 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
130 #define VPU_QMEM_BASE 0x20000000UL
131
132 //max support pixel(by chip capacity)
133 #define HVD_HW_MAX_PIXEL (3840*2160*31000ULL) // 4kx2k@30p
134 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
135 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
136
137 #if 0
138 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
139 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
140 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
141 static MS_U16 _u16DispQPtr = 0;
142 #endif
143
144 #define IS_TASK_ALIVE(id) ((id) != -1)
145 #ifndef UNUSED
146 #define UNUSED(x) (void)(x)
147 #endif
148
149
150 //---------------------------------- Mutex settings -----------------------------------------
151 #if HAL_HVD_ENABLE_MUTEX_PROTECT
152 #define _HAL_HVD_MutexCreate() \
153 do \
154 { \
155 if (s32HVDMutexID < 0) \
156 { \
157 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
158 } \
159 } while (0)
160
161 #define _HAL_HVD_MutexDelete() \
162 do \
163 { \
164 if (s32HVDMutexID >= 0) \
165 { \
166 OSAL_HVD_MutexDelete(s32HVDMutexID); \
167 s32HVDMutexID = -1; \
168 } \
169 } while (0)
170
171 #define _HAL_HVD_Entry() \
172 do \
173 { \
174 if (s32HVDMutexID >= 0) \
175 { \
176 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
177 { \
178 HVD_PRINT("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
179 } \
180 } \
181 } while (0)
182
183 #define _HAL_HVD_Return(_ret_) \
184 do \
185 { \
186 if (s32HVDMutexID >= 0) \
187 { \
188 OSAL_HVD_MutexRelease(s32HVDMutexID); \
189 } \
190 return _ret_; \
191 } while(0)
192
193 #define _HAL_HVD_Release() \
194 do \
195 { \
196 if (s32HVDMutexID >= 0) \
197 { \
198 OSAL_HVD_MutexRelease(s32HVDMutexID); \
199 } \
200 } while (0)
201 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
202
203 #define _HAL_HVD_MutexCreate()
204 #define _HAL_HVD_MutexDelete()
205 #define _HAL_HVD_Entry()
206 #define _HAL_HVD_Return(_ret) {return _ret;}
207 #define _HAL_HVD_Release()
208
209 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
210
211 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
212 #define IS_TASK_ALIVE(id) ((id) != -1)
213 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
214
215 //------------------------------ MIU SETTINGS ----------------------------------
216 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(6))
217 //#define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
218 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(2))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(5))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(3))
222
223 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(6))
224 //#define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
225 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(2))
226 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(4))
227 #define _MaskMiu1Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(5))
228 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK+1, m, BIT(3))
229
230
231 #define HVD_MVD_RW_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == 0))
232 #define HVD_MVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == 0))
233 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0))
234 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == 0))
235 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == 0))
236
237 #define HVD_MVD_RW_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == BIT(6)))
238 #define HVD_MVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == BIT(10)))
239 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4)))
240 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == BIT(5)))
241 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == BIT(11)))
242
243
244
245 #if SUPPORT_EVD
246 #define _MaskMiuReq_EVD_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
247 #define _MaskMiuReq_EVD_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(1))
248 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(2))
249
250 #define _MaskMiu1Req_EVD_RW1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
251 #define _MaskMiu1Req_EVD_RW2( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(1))
252 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK+1, m, BIT(2))
253
254
255
256
257 #define HVD_EVD_RW1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0))
258 #define HVD_EVD_RW2_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == 0))
259 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == 0))
260
261 #define HVD_EVD_RW1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)))
262 #define HVD_EVD_RW2_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == BIT(1)))
263 #define HVD_EVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == BIT(10)))
264
265 #endif
266
267 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
268 do \
269 { \
270 if (HVD_##miu_clients##_ON_MIU0 == 1) \
271 { \
272 _MaskMiuReq_##miu_clients(mask); \
273 } \
274 else \
275 { \
276 if (HVD_##miu_clients##_ON_MIU1 == 1) \
277 { \
278 _MaskMiu1Req_##miu_clients(mask); \
279 } \
280 } \
281 } while (0)
282
283 // check RM is supported or not
284 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
285 #ifdef VDEC3
286 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
287 #else
288 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
289 #endif
290
291 #define DIFF(a, b) (a > b ? (a-b) : (b-a)) // abs diff
292
293 //-------------------------------------------------------------------------------------------------
294 // Local Structures
295 //-------------------------------------------------------------------------------------------------
296
297 //-------------------------------------------------------------------------------------------------
298 // Local Functions Prototype
299 //-------------------------------------------------------------------------------------------------
300 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
301 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
302 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
303 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
304 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
305 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
306 static MS_U32 _HVD_EX_GetPC(void);
307 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
308 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
309 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
310 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
311 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
312 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
313 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
314 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
315 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
316 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
317 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
318 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
319 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
320 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
321 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
322 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
323 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
324 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed, MS_BOOL *isAVCUsed);
325 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable);
326 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable);
327 #if SUPPORT_EVD
328 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable);
329 #endif
330 #ifdef CONFIG_MSTAR_CLKM
331 static void HAL_EVD_EX_PowerCtrl_CLKM(MS_U32 u32Id, MS_BOOL bEnable);
332 #endif
333 #if SUPPORT_G2VP9 && defined(VDEC3)
334 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
335 #endif
336 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
337 #if SUPPORT_G2VP9 && defined(VDEC3)
338 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
339 #endif
340
341 //-------------------------------------------------------------------------------------------------
342 // Global Variables
343 //-------------------------------------------------------------------------------------------------
344 #if defined (__aeon__)
345 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
346 #else
347 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
348 #endif
349 #if HAL_HVD_ENABLE_MUTEX_PROTECT
350 MS_S32 s32HVDMutexID = -1;
351 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
352 #endif
353
354
355 #define HVD_EX_STACK_SIZE 4096
356 //-------------------------------------------------------------------------------------------------
357 // Local Variables
358 //-------------------------------------------------------------------------------------------------
359 typedef struct
360 {
361
362 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
363 MS_U8 g_hvd_nal_fill_pair[2][8];
364 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
365 MS_U16 _u16DispQPtr;
366 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
367
368 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
369 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
370 MS_U32 u32VPUClockType;
371 MS_U32 u32HVDClockType;//160
372 #if SUPPORT_EVD
373 MS_U32 u32EVDClockType;
374 #endif
375 #if SUPPORT_G2VP9 && defined(VDEC3)
376 MS_U32 u32VP9ClockType;
377 #endif
378 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
379
380 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
381 MS_BOOL g_RstFlag;
382 MS_U64 u64pts_real;
383 MS_PHY u32VP8BBUWptr;
384 MS_PHY u32EVDBBUWptr;
385 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
386 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
387 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
388 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
389 //pre_set
390 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
391 } HVD_Hal_CTX;
392
393 HVD_Hal_CTX* pHVDHalContext = NULL;
394 HVD_Hal_CTX gHVDHalContext;
395 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
396
397 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
398 {
399 {FALSE},
400 {FALSE},
401 {FALSE},
402 #ifdef VDEC3
403 {FALSE},
404 #endif
405 };
406
407 //-------------------------------------------------------------------------------------------------
408 // Debug Functions
409 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)410 void HVD_EX_SetRstFlag(MS_BOOL bRst)
411 {
412 pHVDHalContext->g_RstFlag = bRst;
413 }
HVD_EX_GetRstFlag(void)414 MS_BOOL HVD_EX_GetRstFlag(void)
415 {
416 return pHVDHalContext->g_RstFlag;
417 }
418
419 //-------------------------------------------------------------------------------------------------
420 // Local Functions
421 //-------------------------------------------------------------------------------------------------
422 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)423 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
424 {
425 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
426
427 if (u32CodecType == E_HVD_INIT_HW_HEVC || u32CodecType == E_HVD_INIT_HW_HEVC_DV
428 #if SUPPORT_MSVP9
429 || u32CodecType == E_HVD_INIT_HW_VP9
430 #endif
431 )
432 return TRUE;
433
434 return FALSE;
435 }
436
_HAL_EX_BBU_VP8_InUsed(void)437 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
438 {
439 if (!pHVDHalContext)
440 return FALSE;
441
442 MS_U32 i;
443 MS_BOOL bRet = FALSE;
444
445 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
446 {
447 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
448 {
449 bRet = TRUE;
450 break;
451 }
452 }
453
454 return bRet;
455 }
456
457 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
458 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)459 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
460 {
461
462 MS_U32 ret = TRUE;
463 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
464
465 if(pCtrl == NULL || pstTaskInfo == NULL)
466 return FALSE;
467
468 pstTaskInfo->u32Id = u32Id;
469
470 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
471 {
472 case E_HVD_INIT_HW_RM:
473 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
474 break;
475 case E_HVD_INIT_HW_VP8:
476 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
477 break;
478 case E_HVD_INIT_HW_MVC:
479 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
480 break;
481 case E_HVD_INIT_HW_HEVC:
482 case E_HVD_INIT_HW_HEVC_DV:
483 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
484 break;
485 #if SUPPORT_MSVP9
486 case E_HVD_INIT_HW_VP9:
487 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
488 break;
489 #endif
490 #if SUPPORT_G2VP9
491 case E_HVD_INIT_HW_VP9:
492 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
493 break;
494 #endif
495 default:
496 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
497 break;
498 }
499
500 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
501
502 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
503 {
504 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
505 }
506 else
507 {
508 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
509 }
510
511 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
512
513 #ifdef SUPPORT_EVD
514 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
515 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
516 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
517 #endif
518 return ret;
519
520 }
521
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)522 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
523 {
524 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
525 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
526 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
527 _HAL_HVD_Entry();
528
529 if(pCtrl == NULL)
530 _HAL_HVD_Return(ret);
531
532 VPU_EX_TaskInfo taskInfo;
533 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
534
535 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
536
537 taskInfo.u8HalId = u8Idx;
538 ret = HAL_VPU_EX_GetBBUId(u32Id, &taskInfo, pCtrl->bShareBBU);
539
540 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
541 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
542
543 _HAL_HVD_Return(ret);
544 }
545
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)546 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
547 {
548 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
549 MS_BOOL ret = FALSE;
550 _HAL_HVD_Entry();
551
552 if(pCtrl == NULL)
553 _HAL_HVD_Return(ret);
554 VPU_EX_TaskInfo taskInfo;
555 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
556
557 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
558
559 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
560
561 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
562 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
563
564 _HAL_HVD_Return(ret);
565 }
566
HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId)567 MS_BOOL HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId)
568 {
569 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
570 MS_BOOL ret = FALSE;
571 _HAL_HVD_Entry();
572
573 if(pCtrl == NULL)
574 _HAL_HVD_Return(ret);
575 VPU_EX_TaskInfo taskInfo;
576 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
577
578 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
579
580 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, taskInfo.eDecType);
581
582 _HAL_HVD_Return(TRUE);
583 }
584 #endif
585
586 #if SUPPORT_G2VP9 && defined(VDEC3)
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)587 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
588 {
589 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
590 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
591 pstHVDStream->s32HvdPpTaskId = -1;
592 }
593 #endif
594
_HVD_EX_Context_Init_HAL(void)595 static void _HVD_EX_Context_Init_HAL(void)
596 {
597 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
598 pHVDHalContext->u32VPUClockType = 480;
599 pHVDHalContext->u32HVDClockType = 384;
600 #if SUPPORT_EVD
601 pHVDHalContext->u32EVDClockType = 576;
602 #endif
603 #if SUPPORT_G2VP9 && defined(VDEC3)
604 pHVDHalContext->u32VP9ClockType = 384;
605 #endif
606 #ifdef VDEC3
607 MS_U8 i;
608
609 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
610 {
611 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
612 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
613 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
614 }
615 #else
616 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
617 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
618 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
619 #endif
620 }
621
622
_HVD_EX_Get_REG_NAL_RPTR_HI(MS_U32 u32Id)623 static MS_U32 _HVD_EX_Get_REG_NAL_RPTR_HI(MS_U32 u32Id)
624 {
625 #if (HVD_ENABLE_MVC || (!VDEC3))
626 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
627 #endif
628 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
629 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
630 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
631 //HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
632
633 #if HVD_ENABLE_MVC
634 if(HAL_HVD_EX_CheckMVCID(u32Id))
635 {
636 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
637 }
638 #endif /// HVD_ENABLE_MVC
639
640
641 MS_U32 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI(u32RB);
642
643 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
644
645
646 #ifdef VDEC3
647 if ((0 == pCtrl->u32BBUId))
648 #else
649 if ((0 == u8TaskId))
650 #endif
651 {
652 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI(u32RB);
653
654 }
655 #ifdef VDEC3
656 else if (1 == pCtrl->u32BBUId)
657 #else
658 else if (1 == u8TaskId)
659 #endif
660 {
661 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI_BS2(u32RB);
662 }
663 #ifdef VDEC3
664 else if (2 == pCtrl->u32BBUId)
665 #else
666 else if (2 == u8TaskId)
667 #endif
668 {
669 if(isEVD)
670 u32RegNalRptrHi = EVD_REG_NAL_RPTR_HI_BS3;
671 else
672 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI_BS5;
673 }
674 #ifdef VDEC3
675 else if (3 == pCtrl->u32BBUId)
676 #else
677 else if (3 == u8TaskId)
678 #endif
679 {
680 if(isEVD)
681 u32RegNalRptrHi = EVD_REG_NAL_RPTR_HI_BS4;
682 else
683 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI_BS6;
684 }
685 else
686 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
687
688
689 return u32RegNalRptrHi;
690
691 }
692
693
_HVD_EX_Get_REG_NAL_WPTR_HI(MS_U32 u32Id)694 static MS_U32 _HVD_EX_Get_REG_NAL_WPTR_HI(MS_U32 u32Id)
695 {
696 #if (HVD_ENABLE_MVC || (!VDEC3))
697 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
698 #endif
699 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
700 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
701 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
702 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
703
704 #if HVD_ENABLE_MVC
705 if(HAL_HVD_EX_CheckMVCID(u32Id))
706 {
707 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
708 }
709 #endif /// HVD_ENABLE_MVC
710
711
712 MS_U32 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI(u32RB);
713
714 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
715
716
717
718 #ifdef VDEC3
719 if ((0 == pCtrl->u32BBUId))
720 #else
721 if ((0 == u8TaskId))
722 #endif
723 {
724 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI(u32RB);
725
726 }
727 #ifdef VDEC3
728 else if (1 == pCtrl->u32BBUId)
729 #else
730 else if (1 == u8TaskId)
731 #endif
732 {
733 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI_BS2(u32RB);
734 }
735 #ifdef VDEC3
736 else if (2 == pCtrl->u32BBUId)
737 #else
738 else if (2 == u8TaskId)
739 #endif
740 {
741 if(isEVD)
742 u32RegNalWptrHi = EVD_REG_NAL_WPTR_HI_BS3;
743 else
744 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI_BS5;
745 }
746 #ifdef VDEC3
747 else if (3 == pCtrl->u32BBUId)
748 #else
749 else if (3 == u8TaskId)
750 #endif
751 {
752 if(isEVD)
753 u32RegNalWptrHi = EVD_REG_NAL_WPTR_HI_BS4;
754 else
755 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI_BS6;
756 }
757 else
758 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
759
760
761 return u32RegNalWptrHi;
762
763 }
764
765
766
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)767 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
768 {
769 MS_U16 u16Ret = 0;
770 #if (HVD_ENABLE_MVC || (!VDEC3))
771 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
772 #endif
773 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
774 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
775 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
776 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
777
778 #if HVD_ENABLE_MVC
779 if(HAL_HVD_EX_CheckMVCID(u32Id))
780 {
781 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
782 }
783 #endif /// HVD_ENABLE_MVC
784
785 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
786 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
787
788 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
789 {
790 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
791 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
792 }
793 else
794 {
795 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
796 u16Ret = pShm->u32ColocateBBUReadPtr;
797 else
798 u16Ret = _HVD_Read2Byte(_HVD_EX_Get_REG_NAL_RPTR_HI(u32Id));
799 }
800
801 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
802 if(isEVD)
803 {
804 HVD_EX_MSG_DBG("isEVD: %d, Task0=%d, Task1=%d, Task2=%d, Task4=%d\n",
805 isEVD, _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)), _HVD_Read2Byte(EVD_REG_NAL_RPTR_HI_BS3), _HVD_Read2Byte(EVD_REG_NAL_RPTR_HI_BS4));
806 }
807 else
808 {
809 HVD_EX_MSG_DBG("isEVD:%d, Task0=%d, Task1=%d, Task2=%d, Task4=%d\n",
810 isEVD, _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS5), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS6));
811
812 }
813
814 return u16Ret;
815 }
816
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)817 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
818 {
819 MS_U16 u16Ret = 0;
820 #if (HVD_ENABLE_MVC || (!VDEC3))
821 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
822 #endif
823 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
824 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
825 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
826 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
827
828 #if HVD_ENABLE_MVC
829 if (HAL_HVD_EX_CheckMVCID(u32Id))
830 {
831 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
832 }
833 #endif /// HVD_ENABLE_MVC
834 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
835 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
836
837 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
838 {
839 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
840 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
841 }
842 else
843 {
844 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
845 u16Ret = pShm->u32ColocateBBUWritePtr;
846 else
847 u16Ret = _HVD_Read2Byte(_HVD_EX_Get_REG_NAL_WPTR_HI(u32Id));
848
849 }
850
851 return u16Ret;
852 }
853
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)854 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
855 {
856 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
857 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
858
859 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
860 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
861 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
862 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
863 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
864 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
865 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
866 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
867
868
869
870 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS5, 0);
871 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
872 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS6, 0);
873 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
874 _HVD_Write2Byte(EVD_REG_NAL_RPTR_HI_BS3, 0);
875 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
876 _HVD_Write2Byte(EVD_REG_NAL_RPTR_HI_BS4, 0);
877 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
878
879 }
880
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)881 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
882 {
883 #if (HVD_ENABLE_MVC || (!VDEC3))
884 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
885 #endif
886 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
887 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
888 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
889 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
890
891 #if HVD_ENABLE_MVC
892 if (HAL_HVD_EX_CheckMVCID(u32Id))
893 {
894 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
895 }
896 #endif /// HVD_ENABLE_MVC
897
898 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
899 {
900 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
901 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
902 }
903 else
904 {
905 _HVD_Write2Byte(_HVD_EX_Get_REG_NAL_WPTR_HI(u32Id), u16BBUNewWptr);
906 //if(pCtrl->InitParams.bColocateBBUMode)
907 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
908 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
909
910 }
911
912
913
914 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
915
916 if(isEVD)
917 {
918 HVD_EX_MSG_DBG("isEVD:%d, Task0=%d, Task1=%d, Task2=%d, Task3=%d\n",
919 isEVD, _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)), _HVD_Read2Byte(EVD_REG_NAL_WPTR_HI_BS3), _HVD_Read2Byte(EVD_REG_NAL_WPTR_HI_BS4));
920 }
921 else
922 {
923 HVD_EX_MSG_DBG("isEVD:%d, Task0=%d, Task1=%d, Task2=%d, Task3=%d\n",
924 isEVD, _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS5), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS6));
925 }
926
927 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
928 }
929
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)930 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
931 {
932 MS_BOOL bResult = TRUE;
933 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
934 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
935
936 switch (u8MBox)
937 {
938 case E_HVD_HI_0:
939 {
940 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
941 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
942 break;
943 }
944 case E_HVD_HI_1:
945 {
946 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
947 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
948 break;
949 }
950 case E_HVD_VPU_HI_0:
951 {
952 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
953 break;
954 }
955 case E_HVD_VPU_HI_1:
956 {
957 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
958 break;
959 }
960 default:
961 {
962 bResult = FALSE;
963 break;
964 }
965 }
966
967 return bResult;
968 }
969
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)970 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
971 {
972 MS_BOOL bResult = TRUE;
973 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
974 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
975
976 switch (u8MBox)
977 {
978 case E_HVD_HI_0:
979 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
980 break;
981 case E_HVD_HI_1:
982 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
983 break;
984 case E_HVD_RISC_0:
985 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
986 break;
987 case E_HVD_RISC_1:
988 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
989 break;
990 case E_HVD_VPU_HI_0:
991 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
992 break;
993 case E_HVD_VPU_HI_1:
994 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
995 break;
996 case E_HVD_VPU_RISC_0:
997 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
998 break;
999 case E_HVD_VPU_RISC_1:
1000 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
1001 break;
1002 default:
1003 break;
1004 }
1005
1006 return bResult;
1007 }
1008
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)1009 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
1010 {
1011 MS_BOOL bResult = TRUE;
1012 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1013 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1014
1015 switch (u8MBox)
1016 {
1017 case E_HVD_HI_0:
1018 {
1019 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
1020 break;
1021 }
1022 case E_HVD_HI_1:
1023 {
1024 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
1025 break;
1026 }
1027 case E_HVD_RISC_0:
1028 {
1029 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
1030 break;
1031 }
1032 case E_HVD_RISC_1:
1033 {
1034 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
1035 break;
1036 }
1037 case E_HVD_VPU_RISC_0:
1038 {
1039 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
1040 break;
1041 }
1042 case E_HVD_VPU_RISC_1:
1043 {
1044 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
1045 break;
1046 }
1047 default:
1048 {
1049 bResult = FALSE;
1050 break;
1051 }
1052 }
1053
1054 return bResult;
1055 }
1056
1057 #if 0
1058 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
1059 {
1060 switch (u8MBox)
1061 {
1062 case E_HVD_RISC_0:
1063 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
1064 break;
1065 case E_HVD_RISC_1:
1066 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
1067 break;
1068 case E_HVD_VPU_RISC_0:
1069 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
1070 break;
1071 case E_HVD_VPU_RISC_1:
1072 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
1073 break;
1074 default:
1075 break;
1076 }
1077 }
1078 #endif
1079
_HVD_EX_GetPC(void)1080 static MS_U32 _HVD_EX_GetPC(void)
1081 {
1082 MS_U32 u32PC = 0;
1083 u32PC = HAL_VPU_EX_GetProgCnt();
1084 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
1085 return u32PC;
1086 }
1087
_HVD_EX_Get_REG_ES_RPTR_L(MS_U32 u32Id)1088 static MS_U32 _HVD_EX_Get_REG_ES_RPTR_L(MS_U32 u32Id)
1089 {
1090 #if (HVD_ENABLE_MVC || (!VDEC3))
1091 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1092 #endif
1093 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1094 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1095 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1096 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1097
1098 #if HVD_ENABLE_MVC
1099 if(HAL_HVD_EX_CheckMVCID(u32Id))
1100 {
1101 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1102 }
1103 #endif /// HVD_ENABLE_MVC
1104
1105
1106 MS_U32 u32RegESRptrLow = HVD_REG_ESB_RPTR(u32RB);
1107
1108 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1109
1110
1111
1112 #ifdef VDEC3
1113 if ((0 == pCtrl->u32BBUId))
1114 #else
1115 if ((0 == u8TaskId))
1116 #endif
1117 {
1118 u32RegESRptrLow = HVD_REG_ESB_RPTR(u32RB);
1119
1120 }
1121 #ifdef VDEC3
1122 else if (1 == pCtrl->u32BBUId)
1123 #else
1124 else if (1 == u8TaskId)
1125 #endif
1126 {
1127 u32RegESRptrLow = HVD_REG_ESB_RPTR_L_BS2(u32RB);
1128 }
1129 #ifdef VDEC3
1130 else if (2 == pCtrl->u32BBUId)
1131 #else
1132 else if (2 == u8TaskId)
1133 #endif
1134 {
1135 if(isEVD)
1136 u32RegESRptrLow = EVD_REG_ESB_RPTR_L_BS3;
1137 else
1138 u32RegESRptrLow = HVD_REG_ESB_RPTR_L_BS5;
1139 }
1140 #ifdef VDEC3
1141 else if (3 == pCtrl->u32BBUId)
1142 #else
1143 else if (3 == u8TaskId)
1144 #endif
1145 {
1146 if(isEVD)
1147 u32RegESRptrLow = EVD_REG_ESB_RPTR_L_BS4;
1148 else
1149 u32RegESRptrLow = HVD_REG_ESB_RPTR_L_BS6;
1150 }
1151 else
1152 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1153
1154
1155 return u32RegESRptrLow;
1156
1157 }
1158
_HVD_EX_Get_REG_ES_RPTR_H(MS_U32 u32Id)1159 static MS_U32 _HVD_EX_Get_REG_ES_RPTR_H(MS_U32 u32Id)
1160 {
1161 #if (HVD_ENABLE_MVC || (!VDEC3))
1162 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1163 #endif
1164 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1165 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1166 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1167 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1168
1169 #if HVD_ENABLE_MVC
1170 if(HAL_HVD_EX_CheckMVCID(u32Id))
1171 {
1172 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1173 }
1174 #endif /// HVD_ENABLE_MVC
1175
1176
1177 MS_U32 u32RegESRptrHi = HVD_REG_ESB_RPTR_H(u32RB);
1178
1179 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1180
1181
1182
1183 #ifdef VDEC3
1184 if ((0 == pCtrl->u32BBUId))
1185 #else
1186 if ((0 == u8TaskId))
1187 #endif
1188 {
1189 u32RegESRptrHi = HVD_REG_ESB_RPTR_H(u32RB);
1190
1191 }
1192 #ifdef VDEC3
1193 else if (1 == pCtrl->u32BBUId)
1194 #else
1195 else if (1 == u8TaskId)
1196 #endif
1197 {
1198 u32RegESRptrHi = HVD_REG_ESB_RPTR_H_BS2(u32RB);
1199 }
1200 #ifdef VDEC3
1201 else if (2 == pCtrl->u32BBUId)
1202 #else
1203 else if (2 == u8TaskId)
1204 #endif
1205 {
1206 if(isEVD)
1207 u32RegESRptrHi = EVD_REG_ESB_RPTR_H_BS3;
1208 else
1209 u32RegESRptrHi = HVD_REG_ESB_RPTR_H_BS5;
1210 }
1211 #ifdef VDEC3
1212 else if (3 == pCtrl->u32BBUId)
1213 #else
1214 else if (3 == u8TaskId)
1215 #endif
1216 {
1217 if(isEVD)
1218 u32RegESRptrHi = EVD_REG_ESB_RPTR_H_BS4;
1219 else
1220 u32RegESRptrHi = HVD_REG_ESB_RPTR_H_BS6;
1221 }
1222 else
1223 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1224
1225
1226 return u32RegESRptrHi;
1227
1228 }
1229
1230
1231
1232
_HVD_EX_Get_NAL_TBL_ST_ADDR_L(MS_U32 u32Id)1233 static MS_U32 _HVD_EX_Get_NAL_TBL_ST_ADDR_L(MS_U32 u32Id)
1234 {
1235 #if (HVD_ENABLE_MVC || (!VDEC3))
1236 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1237 #endif
1238 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1239 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1240 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1241 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1242
1243 #if HVD_ENABLE_MVC
1244 if(HAL_HVD_EX_CheckMVCID(u32Id))
1245 {
1246 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1247 }
1248 #endif /// HVD_ENABLE_MVC
1249
1250
1251 MS_U32 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L(u32RB);
1252
1253 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1254
1255
1256
1257 #ifdef VDEC3
1258 if ((0 == pCtrl->u32BBUId))
1259 #else
1260 if ((0 == u8TaskId))
1261 #endif
1262 {
1263 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L(u32RB);
1264
1265 }
1266 #ifdef VDEC3
1267 else if (1 == pCtrl->u32BBUId)
1268 #else
1269 else if (1 == u8TaskId)
1270 #endif
1271 {
1272 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB);
1273 }
1274 #ifdef VDEC3
1275 else if (2 == pCtrl->u32BBUId)
1276 #else
1277 else if (2 == u8TaskId)
1278 #endif
1279 {
1280 if(isEVD)
1281 u32RegNalTblAddrLo = EVD_REG_NAL_TBL_ST_ADDR_L_BS3;
1282 else
1283 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L_BS5;
1284 }
1285 #ifdef VDEC3
1286 else if (3 == pCtrl->u32BBUId)
1287 #else
1288 else if (3 == u8TaskId)
1289 #endif
1290 {
1291 if(isEVD)
1292 u32RegNalTblAddrLo = EVD_REG_NAL_TBL_ST_ADDR_L_BS4;
1293 else
1294 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L_BS6;
1295 }
1296 else
1297 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1298
1299
1300 return u32RegNalTblAddrLo;
1301
1302 }
1303
1304
_HVD_EX_Get_NAL_TBL_ST_ADDR_H(MS_U32 u32Id)1305 static MS_U32 _HVD_EX_Get_NAL_TBL_ST_ADDR_H(MS_U32 u32Id)
1306 {
1307 #if (HVD_ENABLE_MVC || (!VDEC3))
1308 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1309 #endif
1310 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1311 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1312 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1313 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1314
1315 #if HVD_ENABLE_MVC
1316 if(HAL_HVD_EX_CheckMVCID(u32Id))
1317 {
1318 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1319 }
1320 #endif /// HVD_ENABLE_MVC
1321
1322
1323 MS_U32 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H(u32RB);
1324
1325 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1326
1327
1328
1329 #ifdef VDEC3
1330 if ((0 == pCtrl->u32BBUId))
1331 #else
1332 if ((0 == u8TaskId))
1333 #endif
1334 {
1335 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H(u32RB);
1336
1337 }
1338 #ifdef VDEC3
1339 else if (1 == pCtrl->u32BBUId)
1340 #else
1341 else if (1 == u8TaskId)
1342 #endif
1343 {
1344 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB);
1345 }
1346 #ifdef VDEC3
1347 else if (2 == pCtrl->u32BBUId)
1348 #else
1349 else if (2 == u8TaskId)
1350 #endif
1351 {
1352 if(isEVD)
1353 u32RegNalTblAddrHi = EVD_REG_NAL_TBL_ST_ADDR_H_BS3;
1354 else
1355 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H_BS5;
1356 }
1357 #ifdef VDEC3
1358 else if (3 == pCtrl->u32BBUId)
1359 #else
1360 else if (3 == u8TaskId)
1361 #endif
1362 {
1363 if(isEVD)
1364 u32RegNalTblAddrHi = EVD_REG_NAL_TBL_ST_ADDR_H_BS4;
1365 else
1366 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H_BS6;
1367 }
1368 else
1369 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1370
1371
1372 return u32RegNalTblAddrHi;
1373
1374 }
1375
_HVD_EX_Get_NAL_TAB_LEN(MS_U32 u32Id)1376 static MS_U32 _HVD_EX_Get_NAL_TAB_LEN(MS_U32 u32Id)
1377 {
1378 #if (HVD_ENABLE_MVC || (!VDEC3))
1379 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1380 #endif
1381 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1382 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1383 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1384 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1385
1386 #if HVD_ENABLE_MVC
1387 if(HAL_HVD_EX_CheckMVCID(u32Id))
1388 {
1389 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1390 }
1391 #endif /// HVD_ENABLE_MVC
1392
1393
1394 MS_U32 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN(u32RB);
1395
1396 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1397
1398
1399
1400 #ifdef VDEC3
1401 if ((0 == pCtrl->u32BBUId))
1402 #else
1403 if ((0 == u8TaskId))
1404 #endif
1405 {
1406 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN(u32RB);
1407
1408 }
1409 #ifdef VDEC3
1410 else if (1 == pCtrl->u32BBUId)
1411 #else
1412 else if (1 == u8TaskId)
1413 #endif
1414 {
1415 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN_BS2(u32RB);
1416 }
1417 #ifdef VDEC3
1418 else if (2 == pCtrl->u32BBUId)
1419 #else
1420 else if (2 == u8TaskId)
1421 #endif
1422 {
1423 if(isEVD)
1424 u32RegNalTblLen = EVD_REG_NAL_TAB_LEN_BS3;
1425 else
1426 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN_BS5;
1427 }
1428 #ifdef VDEC3
1429 else if (3 == pCtrl->u32BBUId)
1430 #else
1431 else if (3 == u8TaskId)
1432 #endif
1433 {
1434 if(isEVD)
1435 u32RegNalTblLen = EVD_REG_NAL_TAB_LEN_BS4;
1436 else
1437 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN_BS6;
1438 }
1439 else
1440 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1441
1442
1443 return u32RegNalTblLen;
1444
1445 }
1446
1447
1448
_HVD_EX_Get_ESB_ST_ADDR_L(MS_U32 u32Id)1449 static MS_U32 _HVD_EX_Get_ESB_ST_ADDR_L(MS_U32 u32Id)
1450 {
1451 #if (HVD_ENABLE_MVC || (!VDEC3))
1452 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1453 #endif
1454 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1455 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1456 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1457 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1458
1459 #if HVD_ENABLE_MVC
1460 if(HAL_HVD_EX_CheckMVCID(u32Id))
1461 {
1462 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1463 }
1464 #endif /// HVD_ENABLE_MVC
1465
1466
1467 MS_U32 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L(u32RB);
1468
1469 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1470
1471
1472
1473 #ifdef VDEC3
1474 if ((0 == pCtrl->u32BBUId))
1475 #else
1476 if ((0 == u8TaskId))
1477 #endif
1478 {
1479 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L(u32RB);
1480
1481 }
1482 #ifdef VDEC3
1483 else if (1 == pCtrl->u32BBUId)
1484 #else
1485 else if (1 == u8TaskId)
1486 #endif
1487 {
1488 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L_BS2(u32RB);
1489 }
1490 #ifdef VDEC3
1491 else if (2 == pCtrl->u32BBUId)
1492 #else
1493 else if (2 == u8TaskId)
1494 #endif
1495 {
1496 if(isEVD)
1497 u32RegEsbAddrLo = EVD_REG_ESB_ST_ADDR_L_BS3;
1498 else
1499 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L_BS5;
1500 }
1501 #ifdef VDEC3
1502 else if (3 == pCtrl->u32BBUId)
1503 #else
1504 else if (3 == u8TaskId)
1505 #endif
1506 {
1507 if(isEVD)
1508 u32RegEsbAddrLo = EVD_REG_ESB_ST_ADDR_L_BS4;
1509 else
1510 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L_BS6;
1511 }
1512 else
1513 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1514
1515
1516 return u32RegEsbAddrLo;
1517
1518 }
1519
1520
_HVD_EX_Get_ESB_ST_ADDR_H(MS_U32 u32Id)1521 static MS_U32 _HVD_EX_Get_ESB_ST_ADDR_H(MS_U32 u32Id)
1522 {
1523 #if (HVD_ENABLE_MVC || (!VDEC3))
1524 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1525 #endif
1526 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1527 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1528 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1529 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1530
1531 #if HVD_ENABLE_MVC
1532 if(HAL_HVD_EX_CheckMVCID(u32Id))
1533 {
1534 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1535 }
1536 #endif /// HVD_ENABLE_MVC
1537
1538
1539 MS_U32 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H(u32RB);
1540
1541 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1542
1543
1544
1545 #ifdef VDEC3
1546 if ((0 == pCtrl->u32BBUId))
1547 #else
1548 if ((0 == u8TaskId))
1549 #endif
1550 {
1551 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H(u32RB);
1552
1553 }
1554 #ifdef VDEC3
1555 else if (1 == pCtrl->u32BBUId)
1556 #else
1557 else if (1 == u8TaskId)
1558 #endif
1559 {
1560 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H_BS2(u32RB);
1561 }
1562 #ifdef VDEC3
1563 else if (2 == pCtrl->u32BBUId)
1564 #else
1565 else if (2 == u8TaskId)
1566 #endif
1567 {
1568 if(isEVD)
1569 u32RegEsbAddrHi = EVD_REG_ESB_ST_ADDR_H_BS3;
1570 else
1571 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H_BS5;
1572 }
1573 #ifdef VDEC3
1574 else if (3 == pCtrl->u32BBUId)
1575 #else
1576 else if (3 == u8TaskId)
1577 #endif
1578 {
1579 if(isEVD)
1580 u32RegEsbAddrHi = EVD_REG_ESB_ST_ADDR_H_BS4;
1581 else
1582 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H_BS6;
1583 }
1584 else
1585 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1586
1587
1588 return u32RegEsbAddrHi;
1589
1590 }
1591
1592
1593
_HVD_EX_Get_ESB_LENGTH_L(MS_U32 u32Id)1594 static MS_U32 _HVD_EX_Get_ESB_LENGTH_L(MS_U32 u32Id)
1595 {
1596 #if (HVD_ENABLE_MVC || (!VDEC3))
1597 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1598 #endif
1599 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1600 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1601 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1602 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1603
1604 #if HVD_ENABLE_MVC
1605 if(HAL_HVD_EX_CheckMVCID(u32Id))
1606 {
1607 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1608 }
1609 #endif /// HVD_ENABLE_MVC
1610
1611
1612 MS_U32 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L(u32RB);
1613
1614 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1615
1616
1617
1618 #ifdef VDEC3
1619 if ((0 == pCtrl->u32BBUId))
1620 #else
1621 if ((0 == u8TaskId))
1622 #endif
1623 {
1624 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L(u32RB);
1625
1626 }
1627 #ifdef VDEC3
1628 else if (1 == pCtrl->u32BBUId)
1629 #else
1630 else if (1 == u8TaskId)
1631 #endif
1632 {
1633 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L_BS2(u32RB);
1634 }
1635 #ifdef VDEC3
1636 else if (2 == pCtrl->u32BBUId)
1637 #else
1638 else if (2 == u8TaskId)
1639 #endif
1640 {
1641 if(isEVD)
1642 u32RegEsbLenLo = EVD_REG_ESB_LENGTH_L_BS3;
1643 else
1644 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L_BS5;
1645 }
1646 #ifdef VDEC3
1647 else if (3 == pCtrl->u32BBUId)
1648 #else
1649 else if (3 == u8TaskId)
1650 #endif
1651 {
1652 if(isEVD)
1653 u32RegEsbLenLo = EVD_REG_ESB_LENGTH_L_BS4;
1654 else
1655 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L_BS6;
1656 }
1657 else
1658 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1659
1660
1661 return u32RegEsbLenLo;
1662
1663 }
1664
1665
_HVD_EX_Get_ESB_LENGTH_H(MS_U32 u32Id)1666 static MS_U32 _HVD_EX_Get_ESB_LENGTH_H(MS_U32 u32Id)
1667 {
1668 #if (HVD_ENABLE_MVC || (!VDEC3))
1669 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1670 #endif
1671 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1672 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1673 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1674 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1675
1676 #if HVD_ENABLE_MVC
1677 if(HAL_HVD_EX_CheckMVCID(u32Id))
1678 {
1679 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1680 }
1681 #endif /// HVD_ENABLE_MVC
1682
1683
1684 MS_U32 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H(u32RB);
1685
1686 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1687
1688
1689
1690 #ifdef VDEC3
1691 if ((0 == pCtrl->u32BBUId))
1692 #else
1693 if ((0 == u8TaskId))
1694 #endif
1695 {
1696 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H(u32RB);
1697
1698 }
1699 #ifdef VDEC3
1700 else if (1 == pCtrl->u32BBUId)
1701 #else
1702 else if (1 == u8TaskId)
1703 #endif
1704 {
1705 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H_BS2(u32RB);
1706 }
1707 #ifdef VDEC3
1708 else if (2 == pCtrl->u32BBUId)
1709 #else
1710 else if (2 == u8TaskId)
1711 #endif
1712 {
1713 if(isEVD)
1714 u32RegEsbLenHi = EVD_REG_ESB_LENGTH_H_BS3;
1715 else
1716 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H_BS5;
1717 }
1718 #ifdef VDEC3
1719 else if (3 == pCtrl->u32BBUId)
1720 #else
1721 else if (3 == u8TaskId)
1722 #endif
1723 {
1724 if(isEVD)
1725 u32RegEsbLenHi = EVD_REG_ESB_LENGTH_H_BS4;
1726 else
1727 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H_BS6;
1728 }
1729 else
1730 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1731
1732
1733 return u32RegEsbLenHi;
1734
1735 }
1736
1737
_HVD_EX_Get_MIF_BBU(MS_U32 u32Id)1738 static MS_U32 _HVD_EX_Get_MIF_BBU(MS_U32 u32Id)
1739 {
1740 #if (HVD_ENABLE_MVC || (!VDEC3))
1741 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1742 #endif
1743 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1744 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1745 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1746 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1747
1748 #if HVD_ENABLE_MVC
1749 if(HAL_HVD_EX_CheckMVCID(u32Id))
1750 {
1751 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1752 }
1753 #endif /// HVD_ENABLE_MVC
1754
1755
1756 MS_U32 u32RegMIFBBU = HVD_REG_MIF_BBU(u32RB);
1757
1758 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1759
1760
1761
1762 #ifdef VDEC3
1763 if ((0 == pCtrl->u32BBUId))
1764 #else
1765 if ((0 == u8TaskId))
1766 #endif
1767 {
1768 u32RegMIFBBU = HVD_REG_MIF_BBU(u32RB);
1769
1770 }
1771 #ifdef VDEC3
1772 else if (1 == pCtrl->u32BBUId)
1773 #else
1774 else if (1 == u8TaskId)
1775 #endif
1776 {
1777 u32RegMIFBBU = HVD_REG_MIF_BBU_BS2(u32RB);
1778 }
1779 #ifdef VDEC3
1780 else if (2 == pCtrl->u32BBUId)
1781 #else
1782 else if (2 == u8TaskId)
1783 #endif
1784 {
1785 if(isEVD)
1786 u32RegMIFBBU = EVD_REG_MIF_BBU_BS3;
1787 else
1788 u32RegMIFBBU = HVD_REG_MIF_BBU_BS5;
1789 }
1790 #ifdef VDEC3
1791 else if (3 == pCtrl->u32BBUId)
1792 #else
1793 else if (3 == u8TaskId)
1794 #endif
1795 {
1796 if(isEVD)
1797 u32RegMIFBBU = EVD_REG_MIF_BBU_BS4;
1798 else
1799 u32RegMIFBBU = HVD_REG_MIF_BBU_BS6;
1800 }
1801 else
1802 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1803
1804
1805 return u32RegMIFBBU;
1806
1807 }
1808
1809
1810
_HVD_EX_GetESWritePtr(MS_U32 u32Id)1811 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
1812 {
1813 MS_U32 u32Data = 0;
1814 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1815 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1816
1817 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1818 {
1819 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
1820
1821 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
1822 {
1823 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
1824
1825 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
1826 }
1827 }
1828 else
1829 {
1830 #if HVD_ENABLE_MVC
1831 MS_U8 u8ViewIdx = 0;
1832 if(HAL_HVD_EX_CheckMVCID(u32Id))
1833 {
1834 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1835 }
1836 if(u8ViewIdx != 0) /// 2nd ES ptr.
1837 {
1838 u32Data = pShm->u32ES2WritePtr;
1839 }
1840 else
1841 {
1842 u32Data = pShm->u32ESWritePtr;
1843 }
1844 #else
1845 u32Data = pShm->u32ESWritePtr;
1846 #endif
1847 }
1848
1849 return u32Data;
1850 }
1851
1852 #define NAL_UNIT_LEN_BITS 21
1853 #define NAL_UNIT_OFT_BITS 30
1854 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
1855 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
1856 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
1857
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)1858 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
1859 {
1860 MS_U32 u32Data = 0;
1861 MS_U8 u8TaskId = 0;
1862 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1863 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1864 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1865 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1866 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
1867
1868 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1869 #if HVD_ENABLE_MVC
1870 if(HAL_HVD_EX_CheckMVCID(u32Id))
1871 {
1872 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1873 }
1874 #endif /// HVD_ENABLE_MVC
1875
1876 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
1877 {
1878 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
1879 {
1880 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1881 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
1882 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
1883 MS_U32 *u32Adr;
1884 MS_U32 u32Tmp;
1885
1886 if (u16ReadPtr == u16WritePtr)
1887 {
1888 u32Data = _HVD_EX_GetESWritePtr(u32Id);
1889 }
1890 else
1891 {
1892 if (u16ReadPtr)
1893 u16ReadPtr--;
1894 else
1895 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
1896
1897 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
1898
1899 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
1900 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
1901 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
1902 u32Data = u32Data | u32Tmp;
1903
1904 //HVD_PRINT("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
1905 //while(1);
1906 }
1907 goto EXIT;
1908 }
1909 // set reg_poll_nal_rptr 0
1910 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
1911 // set reg_poll_nal_rptr 1
1912 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
1913
1914
1915
1916
1917
1918 // read reg_nal_rptr_hi
1919
1920 u32Data = _HVD_Read2Byte(_HVD_EX_Get_REG_ES_RPTR_L(u32Id)) & 0xFFC0;
1921 u32Data >>= 6;
1922 u32Data |= _HVD_Read2Byte(_HVD_EX_Get_REG_ES_RPTR_H(u32Id)) << 10;
1923
1924 u32Data <<= 3; // unit
1925
1926 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1927 {
1928 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1929
1930 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1931 {
1932 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1933 u32Data = u32ESWptr;
1934 }
1935 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1936 {
1937 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1938 u32Data = u32ESWptr;
1939 }
1940 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1941 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1942 {
1943 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1944 u32Data = u32ESWptr;
1945 }
1946 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1947 && ((u32Data - u32ESWptr) < 32)
1948 && (pCtrl->u32FlushRstPtr == 1))
1949 {
1950 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1951 u32Data = u32ESWptr;
1952 }
1953 }
1954
1955 // remove illegal pointer
1956 #if 1
1957 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1958 {
1959 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1960
1961 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1962 (u32PacketStaddr <
1963 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1964 {
1965 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1966 u32Data = pCtrl->u32LastESRptr;
1967 }
1968 }
1969 #endif
1970 }
1971 else
1972 {
1973 #if HVD_ENABLE_MVC
1974 MS_U8 u8ViewIdx = 0;
1975 if(HAL_HVD_EX_CheckMVCID(u32Id))
1976 {
1977 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1978 }
1979 if(u8ViewIdx != 0) /// 2nd ES ptr.
1980 {
1981 u32Data = pShm->u32ES2ReadPtr;
1982 }
1983 else
1984 {
1985 u32Data = pShm->u32ESReadPtr;
1986 }
1987 #else
1988 u32Data = pShm->u32ESReadPtr;
1989 #endif
1990 }
1991
1992 EXIT:
1993
1994 pCtrl->u32LastESRptr = u32Data;
1995
1996 return u32Data;
1997 }
1998
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1999 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
2000 {
2001 MS_U16 u16TimeOut = 0xFFFF;
2002 MS_BOOL bResult = FALSE;
2003
2004 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
2005
2006 while (--u16TimeOut)
2007 {
2008 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
2009 {
2010 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
2011 break;
2012 }
2013 }
2014
2015 return bResult;
2016 }
2017
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)2018 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
2019 {
2020 MS_U16 u16TimeOut = 0xFFFF;
2021 MS_BOOL bResult = FALSE;
2022 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2023
2024 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
2025
2026 #if HVD_ENABLE_MVC
2027 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
2028 {
2029 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
2030 }
2031 #endif /// HVD_ENABLE_MVC
2032
2033 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
2034
2035 while (--u16TimeOut)
2036 {
2037 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
2038 {
2039 u32Cmd |= (u8TaskId << 24);
2040 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
2041 break;
2042 }
2043 }
2044 return bResult;
2045 }
2046
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)2047 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
2048 {
2049 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2050 #ifdef VDEC3
2051 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
2052 MS_BOOL IsSent = FALSE;
2053 MS_BOOL IsMailBox = FALSE;
2054 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2055
2056 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
2057 {
2058 do {
2059 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
2060 if (!SentRet)
2061 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2062 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2063 break;
2064 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
2065 IsSent = TRUE;
2066 break;
2067 }
2068 else if (HVD_GetSysTime_ms() > u32timeout)
2069 {
2070 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2071 break;
2072 }
2073 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2074 }
2075 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
2076 {
2077 do {
2078 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
2079 if (!SentRet)
2080 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2081 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2082 break;
2083 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
2084 IsSent = TRUE;
2085 break;
2086 }
2087 else if (HVD_GetSysTime_ms() > u32timeout)
2088 {
2089 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2090 break;
2091 }
2092 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2093 }
2094 if (!IsSent) {
2095 IsMailBox = TRUE;
2096 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2097 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
2098 #else
2099 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
2100 #endif
2101 {
2102 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2103 if (HVD_GetSysTime_ms() > u32timeout)
2104 {
2105 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2106 return E_HVD_RETURN_TIMEOUT;
2107 }
2108 #endif
2109
2110 #if 0
2111 if (u32Cmd == E_HVD_CMD_STOP)
2112 {
2113 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2114 #if HVD_ENABLE_MVC
2115 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
2116 {
2117 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
2118 }
2119 #endif /// HVD_ENABLE_MVC
2120 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
2121
2122 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
2123 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
2124
2125 return E_HVD_RETURN_SUCCESS;
2126 }
2127 #endif
2128
2129 if(u32Cmd < E_DUAL_CMD_BASE)
2130 {
2131 //_HVD_EX_GetPC();
2132 HAL_HVD_EX_Dump_FW_Status(u32Id);
2133 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
2134 }
2135 }
2136
2137 #ifdef VDEC3
2138 }
2139 IsSent = FALSE;
2140 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2141 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
2142 {
2143 do {
2144 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
2145 if (!SentRet)
2146 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2147 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2148 break;
2149 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
2150 IsSent = TRUE;
2151 break;
2152 }
2153 else if (HVD_GetSysTime_ms() > u32timeout)
2154 {
2155 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2156 break;
2157 }
2158 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2159 }
2160 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
2161 {
2162 do {
2163 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
2164 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
2165 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2166 }
2167 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2168 break;
2169 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
2170 IsSent = TRUE;
2171 break;
2172 }
2173 else if (HVD_GetSysTime_ms() > u32timeout)
2174 {
2175 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2176 break;
2177 }
2178 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2179 }
2180 if (!IsSent)
2181 {
2182 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2183 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
2184 #else
2185 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2186
2187 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
2188 #endif
2189 {
2190 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2191 if (HVD_GetSysTime_ms() > u32timeout)
2192 {
2193 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
2194 return E_HVD_RETURN_TIMEOUT;
2195 }
2196 #endif
2197 if(u32Cmd < E_DUAL_CMD_BASE)
2198 {
2199 //_HVD_EX_GetPC();
2200 HAL_HVD_EX_Dump_FW_Status(u32Id);
2201 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
2202 }
2203 }
2204 #ifdef VDEC3
2205 }
2206 else
2207 {
2208 HAL_HVD_EX_FlushMemory();
2209 }
2210 #endif
2211 return E_HVD_RETURN_SUCCESS;
2212 }
2213
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)2214 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
2215 {
2216 #if HAL_HVD_ENABLE_MIU_PROTECT
2217 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
2218 //_HVD_MIU_SetReqMask(MVD_RW_1, bEnable);
2219 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
2220 #if SUPPORT_EVD
2221 _HVD_MIU_SetReqMask(EVD_RW1, bEnable);
2222 _HVD_MIU_SetReqMask(EVD_RW2, bEnable);
2223 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
2224 #endif
2225 _HVD_MIU_SetReqMask(HVD_RW_MIF0, bEnable);
2226 _HVD_MIU_SetReqMask(HVD_RW_MIF1, bEnable);
2227 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
2228 HAL_VPU_EX_MIU_RW_Protect(bEnable);
2229 //HVD_Delay_ms(1);
2230 #endif
2231 return;
2232 }
2233
_HVD_EX_SetBufferAddr(MS_U32 u32Id)2234 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
2235 {
2236 MS_U16 u16Reg = 0;
2237 MS_VIRT u32StAddr = 0;
2238 #ifdef VDEC3
2239 MS_U32 u32Length = 0;
2240 #endif
2241 MS_U8 u8BitMiuSel = 0;
2242 MS_U8 u8CodeMiuSel = 0;
2243 MS_U8 u8FBMiuSel = 0;
2244 MS_U8 u8TmpMiuSel = 0;
2245
2246 MS_U32 u32BitStartOffset;
2247 MS_U32 u32CodeStartOffset;
2248 MS_U32 u32FBStartOffset;
2249
2250 #ifndef VDEC3
2251 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2252 #endif
2253 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2254 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2255 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
2256
2257 _HAL_HVD_Entry();
2258
2259 if (pCtrl == NULL)
2260 {
2261 _HAL_HVD_Return();
2262 }
2263
2264 MS_BOOL bIsEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
2265 MS_BOOL bESBufferAlreadySet = FALSE;
2266 VPU_EX_TaskInfo taskInfo;
2267 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2268
2269 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
2270
2271 bESBufferAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
2272
2273
2274
2275 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
2276 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
2277 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
2278
2279 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
2280 (u8BitMiuSel << VDEC_BS_MIUSEL) |
2281 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
2282 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
2283 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
2284 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
2285 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
2286 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
2287 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
2288 (u8FBMiuSel << VDEC_PPIN_MIUSEL) |
2289 (u8FBMiuSel << VDEC_XCSHM_MIUSEL));
2290
2291 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2292 {
2293 // ES buffer
2294 #ifdef VDEC3
2295 if(pCtrl->bShareBBU)
2296 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
2297 else
2298 #endif
2299 u32StAddr = u32BitStartOffset;
2300
2301 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
2302
2303 #ifdef VDEC3
2304 if (!_HAL_EX_BBU_VP8_InUsed())
2305 #endif
2306 {
2307 HVD_EX_MSG_ERR("ESB start addr=%lx\n", (unsigned long)u32StAddr);
2308
2309 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
2310 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
2311
2312 #ifdef VDEC3
2313 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
2314 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
2315 #else
2316 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2317 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2318 #endif
2319
2320 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
2321 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
2322 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
2323 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
2324 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
2325 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
2326 }
2327
2328 _HAL_HVD_Return();
2329 }
2330
2331 // ES buffer
2332 #ifdef VDEC3
2333 if(!pCtrl->bShareBBU || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
2334 {
2335 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2336 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
2337 }
2338 else
2339 {
2340 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
2341 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
2342 }
2343 #else
2344 u32StAddr = u32BitStartOffset;
2345 #endif
2346
2347 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
2348
2349 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
2350
2351 #ifdef VDEC3
2352 if (!bESBufferAlreadySet)
2353 {
2354 _HVD_Write2Byte(_HVD_EX_Get_ESB_ST_ADDR_L(u32Id), HVD_LWORD(u32StAddr >> 3));
2355 _HVD_Write2Byte(_HVD_EX_Get_ESB_ST_ADDR_H(u32Id), HVD_HWORD(u32StAddr >> 3));
2356
2357 _HVD_Write2Byte(_HVD_EX_Get_ESB_LENGTH_L(u32Id), HVD_LWORD(u32Length));
2358 _HVD_Write2Byte(_HVD_EX_Get_ESB_LENGTH_H(u32Id), HVD_HWORD(u32Length));
2359 }
2360 #else
2361 if (0 == u8TaskId)
2362 {
2363 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
2364 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
2365
2366 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2367 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2368 }
2369 else
2370 {
2371 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
2372 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
2373
2374 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2375 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2376 }
2377 #endif
2378
2379 // others
2380 #ifdef VDEC3
2381 if (!bESBufferAlreadySet)
2382 {
2383 u16Reg = _HVD_Read2Byte(_HVD_EX_Get_MIF_BBU(u32Id));
2384
2385 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2386 {
2387 if (pCtrl->u32BBUId == 0)
2388 u16Reg |= HVD_REG_BBU_TSP_INPUT;
2389 else if (pCtrl->u32BBUId == 1)
2390 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
2391 else if (pCtrl->u32BBUId == 2)
2392 {
2393 if(bIsEVD)
2394 u16Reg |= EVD_REG_BBU_TSP_INPUT_BS3;
2395 else
2396 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS5;
2397 }
2398 else
2399 {
2400 if(bIsEVD)
2401 u16Reg |= EVD_REG_BBU_TSP_INPUT_BS4;
2402 else
2403 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS6;
2404 }
2405 }
2406 else
2407 {
2408 if (pCtrl->u32BBUId == 0)
2409 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
2410 else if (pCtrl->u32BBUId == 1)
2411 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
2412 else if (pCtrl->u32BBUId == 2)
2413 {
2414 if(bIsEVD)
2415 u16Reg &= ~EVD_REG_BBU_TSP_INPUT_BS3;
2416 else
2417 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS5;
2418 }
2419 else
2420 {
2421 if(bIsEVD)
2422 u16Reg &= ~EVD_REG_BBU_TSP_INPUT_BS4;
2423 else
2424 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS6;
2425 }
2426 }
2427
2428 // do not set parsing setting in DRV, and we set it in FW (hvd_switch_bbu)
2429 if (pCtrl->u32BBUId == 0)
2430 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
2431 else if(pCtrl->u32BBUId == 1)
2432 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
2433 else if(pCtrl->u32BBUId == 2)
2434 {
2435 if(bIsEVD)
2436 u16Reg &= ~EVD_REG_BBU_PASER_MASK_BS3;
2437 else
2438 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS5;
2439 }
2440 else
2441 {
2442 if(bIsEVD)
2443 u16Reg &= ~EVD_REG_BBU_PASER_MASK_BS4;
2444 else
2445 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS6;
2446 }
2447
2448 if (pCtrl->u32BBUId == 0)
2449 {
2450 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
2451 }
2452 else if (pCtrl->u32BBUId == 1)
2453 {
2454 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
2455 }
2456 else if (pCtrl->u32BBUId == 2)
2457 {
2458 if(bIsEVD)
2459 u16Reg |= EVD_REG_BBU_AUTO_NAL_TAB_BS3;
2460 else
2461 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS5;
2462 }
2463 else
2464 {
2465 if(bIsEVD)
2466 u16Reg |= EVD_REG_BBU_AUTO_NAL_TAB_BS4;
2467 else
2468 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS6;
2469 }
2470
2471 _HVD_Write2Byte(_HVD_EX_Get_MIF_BBU(u32Id), u16Reg);
2472 }
2473 #else
2474 if (0 == u8TaskId)
2475 {
2476 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
2477
2478 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2479 {
2480 u16Reg |= HVD_REG_BBU_TSP_INPUT;
2481 }
2482 else
2483 {
2484 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
2485 }
2486
2487 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
2488
2489 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
2490 {
2491 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
2492 }
2493 else // AVS or AVC
2494 {
2495 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
2496 {
2497 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
2498 }
2499 else // start code remained
2500 {
2501 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
2502 }
2503 }
2504
2505 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
2506
2507 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
2508 }
2509 else
2510 {
2511 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
2512
2513 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2514 {
2515 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
2516 }
2517 else
2518 {
2519 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
2520 }
2521
2522 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
2523
2524 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
2525 {
2526 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
2527 }
2528 else // AVS or AVC
2529 {
2530 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
2531 {
2532 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
2533 }
2534 else // start code remained
2535 {
2536 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
2537 }
2538 }
2539
2540 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
2541
2542 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
2543 }
2544 #endif
2545
2546 #if (HVD_ENABLE_MVC)
2547 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2548 {
2549 /// Used sub stream to record sub view data.
2550 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
2551 //HVD_PRINT("**************** Buffer setting for MVC dual-BBU *************\n");
2552
2553 // ES buffer
2554 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
2555
2556 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
2557 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
2558 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
2559
2560 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
2561 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
2562
2563 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
2564 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2565 {
2566 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
2567 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
2568 }
2569 else
2570 {
2571 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
2572 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
2573 }
2574 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
2575 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
2576 {
2577 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
2578 }
2579 else // AVS or AVC
2580 {
2581 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
2582 {
2583 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
2584 }
2585 else // start code remained
2586 {
2587 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
2588 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
2589 }
2590 }
2591 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
2592 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
2593 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
2594 }
2595 #endif
2596
2597 // MIF offset
2598 #if 0
2599 {
2600 MS_U16 offaddr = 0;
2601 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
2602 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2603 {
2604 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2605 }
2606 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
2607 offaddr = (MS_U16) ((u32StAddr) >> 20);
2608 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
2609 //0x1FF; // 9 bits(L + H)
2610 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
2611 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
2612 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
2613 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
2614 {
2615 u16Reg |= HVD_REG_MIF_OFFSET_H;
2616 }
2617 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
2618 }
2619 #endif
2620
2621 if (!bESBufferAlreadySet)
2622 {
2623 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
2624 }
2625
2626 _HAL_HVD_Return();
2627 }
2628
2629 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
2630 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
2631 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
2632 {
2633 MS_U16 u16Reg = 0;
2634 MS_U32 u32StAddr = 0;
2635 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2636 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2637 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
2638
2639 if(pCtrl == NULL) return;
2640
2641 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2642 {
2643 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
2644
2645 // ES buffer
2646 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2647
2648 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2649 {
2650 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2651 }
2652
2653 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
2654 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
2655
2656 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2657 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2658
2659 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
2660 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
2661 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
2662 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
2663 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
2664 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
2665
2666 return;
2667 }
2668
2669 // ES buffer
2670 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2671
2672 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2673 {
2674 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2675 }
2676
2677 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
2678
2679 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
2680 {
2681 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
2682 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
2683
2684 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2685 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2686 }
2687 else
2688 {
2689 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
2690 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
2691
2692 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2693 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2694 }
2695 }
2696 #endif
2697
_HVD_EX_GetESLevel(MS_U32 u32Id)2698 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
2699 {
2700 MS_U32 u32Wptr = 0;
2701 MS_U32 u32Rptr = 0;
2702 MS_U32 u32CurMBX = 0;
2703 MS_U32 u32ESsize = 0;
2704 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
2705 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2706
2707 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
2708 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
2709 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
2710
2711 if (u32Rptr >= u32Wptr)
2712 {
2713 u32CurMBX = u32Rptr - u32Wptr;
2714 }
2715 else
2716 {
2717 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
2718 }
2719
2720 if (u32CurMBX == 0)
2721 {
2722 u32Ret = E_HVD_ESB_LEVEL_UNDER;
2723 }
2724 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
2725 {
2726 u32Ret = E_HVD_ESB_LEVEL_OVER;
2727 }
2728 else
2729 {
2730 u32CurMBX = u32ESsize - u32CurMBX;
2731 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
2732 {
2733 u32Ret = E_HVD_ESB_LEVEL_UNDER;
2734 }
2735 }
2736
2737 return u32Ret;
2738 }
2739
_HVD_EX_GetESQuantity(MS_U32 u32Id)2740 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
2741 {
2742 MS_U32 u32Wptr = 0;
2743 MS_U32 u32Rptr = 0;
2744 MS_U32 u32ESsize = 0;
2745 MS_U32 u32Ret = 0;
2746 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2747
2748 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
2749 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
2750 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
2751
2752
2753 if(u32Wptr >= u32Rptr)
2754 {
2755 u32Ret = u32Wptr - u32Rptr;
2756 }
2757 else
2758 {
2759 u32Ret = u32ESsize - u32Rptr + u32Wptr;
2760 }
2761 //HVD_PRINT("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
2762 return u32Ret;
2763 }
2764
2765 #if 0//(HVD_ENABLE_IQMEM)
2766 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
2767 {
2768
2769 MS_U32 u32Timeout = 20000;
2770
2771 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
2772 {
2773
2774 HAL_VPU_EX_IQMemSetDAMode(TRUE);
2775
2776 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
2777
2778
2779 while (u32Timeout)
2780 {
2781
2782 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
2783 {
2784 break;
2785 }
2786 u32Timeout--;
2787 HVD_Delay_ms(1);
2788 }
2789
2790 HAL_VPU_EX_IQMemSetDAMode(FALSE);
2791
2792 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
2793
2794 if (u32Timeout==0)
2795 {
2796 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
2797 return FALSE;
2798 }
2799
2800
2801 }
2802 return TRUE;
2803 }
2804
2805 #endif
2806
2807 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)2808 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
2809 #else
2810 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
2811 #endif
2812 {
2813 MS_U32 u32FirmVer = 0;
2814 MS_U32 u32Timeout = 20000;
2815 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2816
2817 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
2818
2819 #if HVD_ENABLE_TIME_MEASURE
2820 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2821 #endif
2822
2823 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
2824
2825 VPU_EX_FWCodeCfg fwCfg;
2826 VPU_EX_TaskInfo taskInfo;
2827 VPU_EX_VLCTblCfg vlcCfg;
2828 #ifdef VDEC3
2829 VPU_EX_FBCfg fbCfg;
2830 #endif
2831 VPU_EX_NDecInitPara nDecInitPara;
2832
2833 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
2834 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2835 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
2836 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
2837 #ifdef VDEC3_FB
2838 nDecInitPara.pVLCCfg = NULL;
2839 #else
2840 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2841 {
2842 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
2843 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2844 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2845 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
2846 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
2847 nDecInitPara.pVLCCfg = &vlcCfg;
2848 }
2849 #endif
2850 nDecInitPara.pFWCodeCfg = &fwCfg;
2851 nDecInitPara.pTaskInfo = &taskInfo;
2852 #ifdef VDEC3
2853 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
2854 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2855
2856 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2857 {
2858 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2859 }
2860
2861 nDecInitPara.pFBCfg = &fbCfg;
2862 #endif
2863
2864 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
2865 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
2866 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
2867 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
2868 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
2869
2870 taskInfo.u32Id = u32Id;
2871
2872 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2873 {
2874 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
2875 }
2876 #ifdef VDEC3
2877 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2878 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
2879 {
2880 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2881 }
2882 #if SUPPORT_MSVP9
2883 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2884 {
2885 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2886 }
2887 #endif
2888 #if SUPPORT_G2VP9
2889 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2890 {
2891 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2892 }
2893 #endif
2894 #endif
2895 else
2896 {
2897 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2898 }
2899
2900 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2901
2902 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2903 {
2904 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2905 }
2906 else
2907 {
2908 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2909 }
2910 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2911
2912 #ifdef SUPPORT_EVD
2913 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2914 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2915 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2916 #endif
2917
2918 if(TRUE == HVD_EX_GetRstFlag())
2919 {
2920 //Delete task for Rst
2921 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2922 {
2923 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2924 }
2925 HVD_EX_SetRstFlag(FALSE);
2926 }
2927
2928 #if 0//(HVD_ENABLE_IQMEM)
2929 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2930 #endif
2931
2932 #ifdef VDEC3
2933 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2934 #else
2935 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2936 #endif
2937 {
2938 HVD_EX_MSG_ERR("Task create fail!\n");
2939
2940 return FALSE;
2941 }
2942
2943 while (u32Timeout)
2944 {
2945 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2946
2947 if (u32FirmVer != 0)
2948 {
2949 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2950 break;
2951 }
2952 u32Timeout--;
2953 HVD_Delay_ms(1);
2954 }
2955
2956 #ifdef VDEC3_FB
2957 #if HVD_ENABLE_RV_FEATURE
2958 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2959
2960 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2961 {
2962 if(pShm->u32RM_VLCTableAddr == 0) {
2963 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2964 }
2965 else
2966 {
2967 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2968 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2969 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2970 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2971 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2972 nDecInitPara.pVLCCfg = &vlcCfg;
2973 }
2974 }
2975
2976 if (nDecInitPara.pVLCCfg)
2977 {
2978 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2979 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2980 {
2981 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2982 return FALSE;
2983 }
2984 }
2985 #endif
2986 #endif
2987 if (u32Timeout > 0)
2988 {
2989 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2990
2991 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2992
2993 #ifdef VDEC3
2994 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2995 {
2996 case E_HVD_INIT_HW_AVC:
2997 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2998 break;
2999 case E_HVD_INIT_HW_AVS:
3000 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
3001 break;
3002 case E_HVD_INIT_HW_RM:
3003 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
3004 break;
3005 case E_HVD_INIT_HW_MVC:
3006 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
3007 break;
3008 case E_HVD_INIT_HW_VP8:
3009 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
3010 break;
3011 case E_HVD_INIT_HW_MJPEG:
3012 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
3013 break;
3014 case E_HVD_INIT_HW_VP6:
3015 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
3016 break;
3017 case E_HVD_INIT_HW_HEVC:
3018 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
3019 break;
3020 case E_HVD_INIT_HW_VP9:
3021 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
3022 break;
3023 case E_HVD_INIT_HW_HEVC_DV:
3024 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC_DV;
3025 break;
3026 default:
3027 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
3028 break;
3029 }
3030 #endif
3031
3032 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
3033 }
3034 else
3035 {
3036 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
3037 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
3038
3039 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
3040 {
3041 HVD_EX_MSG_ERR("Task delete fail!\n");
3042 }
3043
3044 return FALSE;
3045 }
3046
3047
3048
3049 #if 0//(HVD_ENABLE_IQMEM)
3050
3051 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
3052 {
3053
3054 HAL_HVD_EX_IQMem_Init(u32Id);
3055 }
3056 else{
3057 HVD_EX_MSG_DBG("not support IQMEM\n");
3058 }
3059 #endif
3060
3061
3062
3063
3064
3065
3066 #if HVD_ENABLE_TIME_MEASURE
3067 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
3068 #endif
3069
3070 return TRUE;
3071 }
3072
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)3073 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
3074 {
3075 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3076 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3077 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
3078 {
3079 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
3080 }
3081 else
3082 {
3083 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3084 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3085 }
3086 }
3087
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)3088 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
3089 {
3090 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3091 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3092
3093 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
3094 {
3095 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
3096 }
3097 else
3098 {
3099 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3100 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3101 }
3102 }
3103
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)3104 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
3105 {
3106 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3107 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3108
3109 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
3110 {
3111 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
3112 {
3113 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
3114 }
3115 }
3116 else
3117 {
3118 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
3119 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
3120 }
3121 }
3122
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)3123 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
3124 {
3125 MS_VIRT u32PTSWptr = HVD_U32_MAX;
3126 MS_VIRT u32PTSRptr = HVD_U32_MAX;
3127 MS_VIRT u32DestAddr = 0;
3128 HVD_PTS_Entry PTSEntry;
3129 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3130 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3131 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3132
3133 // update R & W ptr
3134 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
3135
3136 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
3137
3138 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
3139 {
3140 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
3141 (MS_U32) MAX_PTS_TABLE_SIZE);
3142 return E_HVD_RETURN_FAIL;
3143 }
3144
3145 // check queue is full or not
3146 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
3147 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
3148
3149 if (u32PTSWptr == u32PTSRptr)
3150 {
3151 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
3152 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
3153 return E_HVD_RETURN_FAIL;
3154 }
3155
3156 // add one PTS entry
3157 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
3158 PTSEntry.u32ID_L = pInfo->u32ID_L;
3159 PTSEntry.u32ID_H = pInfo->u32ID_H;
3160 PTSEntry.u32PTS = pInfo->u32TimeStamp;
3161
3162 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
3163
3164 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
3165
3166 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
3167
3168 HAL_HVD_EX_FlushMemory();
3169
3170 // update Write ptr
3171 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
3172
3173 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
3174
3175 return E_HVD_RETURN_SUCCESS;
3176 }
3177
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)3178 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
3179 {
3180 //---------------------------------------------------
3181 // item format in nal table:
3182 // reserved |borken| u32NalOffset | u32NalLen
3183 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
3184 //---------------------------------------------------
3185 MS_VIRT u32Adr = 0;
3186 MS_U32 u32BBUNewWptr = 0;
3187 MS_U8 item[8];
3188 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3189 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3190 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3191 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
3192
3193 #if HVD_ENABLE_MVC
3194 if(HAL_HVD_EX_CheckMVCID(u32Id))
3195 {
3196 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
3197 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
3198 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
3199 {
3200 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
3201 }
3202 }
3203 #endif /// HVD_ENABLE_MVC
3204
3205 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3206 {
3207 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
3208 }
3209 else
3210 {
3211 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
3212 }
3213 u32BBUNewWptr++;
3214 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
3215
3216 // prepare nal entry
3217
3218 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
3219 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3220 {
3221 // NAL len 22 bits , HEVC level5 constrain
3222 item[0] = u32NalLen & 0xff;
3223 item[1] = (u32NalLen >> 8) & 0xff;
3224 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
3225 item[3] = (u32NalOffset >> 2) & 0xff;
3226 item[4] = (u32NalOffset >> 10) & 0xff;
3227 item[5] = (u32NalOffset >> 18) & 0xff;
3228 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
3229 item[7] = 0;
3230 }
3231 else
3232 {
3233 item[0] = u32NalLen & 0xff;
3234 item[1] = (u32NalLen >> 8) & 0xff;
3235 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
3236 item[3] = (u32NalOffset >> 3) & 0xff;
3237 item[4] = (u32NalOffset >> 11) & 0xff;
3238 item[5] = (u32NalOffset >> 19) & 0xff;
3239 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
3240 item[7] = 0;
3241 }
3242
3243 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3244 {
3245 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
3246 }
3247 else
3248 {
3249 // add nal entry
3250 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
3251 }
3252
3253 HVD_memcpy((void *) u32Adr, (void *) item, 8);
3254
3255 HAL_HVD_EX_FlushMemory();
3256
3257 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
3258
3259 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3260 {
3261 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
3262 }
3263 else
3264 {
3265 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
3266 }
3267
3268 return E_HVD_RETURN_SUCCESS;
3269 }
3270
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)3271 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
3272 {
3273 MS_U8 item[8];
3274 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3275 MS_VIRT u32Adr = 0;
3276 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3277 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3278 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
3279
3280 /*
3281 HVD_PRINT("nal2 offset=0x%x, len=0x%x\n",
3282 u32NalOffset2, u32NalLen2);
3283 */
3284
3285 item[0] = u32NalLen2 & 0xff;
3286 item[1] = (u32NalLen2 >> 8) & 0xff;
3287 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
3288 item[3] = (u32NalOffset2 >> 3) & 0xff;
3289 item[4] = (u32NalOffset2 >> 11) & 0xff;
3290 item[5] = (u32NalOffset2 >> 19) & 0xff;
3291 item[6] = (u32NalOffset2 >> 27) & 0x07;
3292 item[7] = 0;
3293
3294 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3295 {
3296 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
3297 }
3298 else
3299 {
3300 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
3301 }
3302
3303 HVD_memcpy((void *) u32Adr, (void *) item, 8);
3304
3305 HAL_HVD_EX_FlushMemory();
3306
3307 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
3308 }
3309
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)3310 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
3311 {
3312 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3313 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3314
3315 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
3316 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
3317 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
3318 {
3319 MS_U16 i;
3320 MS_PHY u32VUIAddr;
3321 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
3322
3323 HAL_HVD_EX_ReadMemory();
3324 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
3325
3326 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
3327 {
3328 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
3329 {
3330 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
3331 }
3332 else
3333 {
3334 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
3335 }
3336 pData++;
3337 }
3338 }
3339 else
3340 {
3341 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
3342 }
3343
3344 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
3345 }
3346
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)3347 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
3348 {
3349 MS_U32 u32ReadPtr = 0;
3350 MS_U32 eRet = 0;
3351 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3352 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3353
3354 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
3355 MS_U32 u32WritePtr = 0;
3356
3357 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3358 {
3359 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
3360 }
3361 else
3362 {
3363 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
3364 }
3365
3366 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
3367
3368 if (u32WritePtr >= u32ReadPtr)
3369 {
3370 eRet = u32WritePtr - u32ReadPtr;
3371 }
3372 else
3373 {
3374 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
3375 }
3376
3377 #if 0
3378 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
3379 {
3380 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
3381 }
3382 else
3383 {
3384 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
3385 }
3386
3387 #endif
3388 return eRet;
3389 }
3390
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)3391 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
3392 {
3393 MS_U32 u32ReadPtr = 0;
3394 MS_U32 eRet = 0;
3395 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3396
3397 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
3398
3399 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
3400 {
3401 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
3402 (MS_U32) MAX_PTS_TABLE_SIZE);
3403 return 0;
3404 }
3405
3406 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3407
3408 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
3409 {
3410 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
3411 }
3412 else
3413 {
3414 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
3415 }
3416
3417 return eRet;
3418 }
3419
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)3420 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
3421 {
3422 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3423
3424 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
3425 }
3426
hevc_get_paired(HEVC_PIC_STRUCT pic_struct,int first_field)3427 static HEVC_PIC_STRUCT hevc_get_paired(HEVC_PIC_STRUCT pic_struct, int first_field)
3428 {
3429 if (pic_struct == EVD_TOP_FIELD)
3430 return EVD_BOTTOM_FIELD;
3431 else if (pic_struct == EVD_BOTTOM_FIELD)
3432 return EVD_TOP_FIELD;
3433
3434 if (first_field)
3435 {
3436 // pic_struct is the first field and must pair with the next one
3437 if (pic_struct == EVD_TOP_WITH_NEXT)
3438 return EVD_BOTTOM_WITH_PREV;
3439 else if (pic_struct == EVD_BOTTOM_WITH_NEXT)
3440 return EVD_TOP_WITH_PREV;
3441 }
3442 else
3443 {
3444 // pic_struct is the second field and must pair with the previous one
3445 if (pic_struct == EVD_TOP_WITH_PREV)
3446 return EVD_BOTTOM_WITH_NEXT;
3447 else if (pic_struct == EVD_BOTTOM_WITH_PREV)
3448 return EVD_TOP_WITH_NEXT;
3449 }
3450
3451 return EVD_UNKNOWN_TYPE;
3452 }
3453
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)3454 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
3455 {
3456 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3457 MS_U16 u16QNum = pShm->u16DispQNumb;
3458 MS_U16 u16QPtr = pShm->u16DispQPtr;
3459 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3460
3461 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3462 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3463
3464 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
3465 static MS_BOOL bfirstTime = TRUE;
3466 if (bDolbyVision)
3467 {
3468 if (bfirstTime && u16QNum < 4) // first time we need to wait 4 pic to ensure we got the correct layer type
3469 {
3470 return NULL;
3471 }
3472 else
3473 {
3474 bfirstTime = FALSE;
3475 }
3476 }
3477
3478 #if (HVD_ENABLE_MVC)
3479 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3480 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
3481 {
3482 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3483 {
3484 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
3485 MS_U16 u16UsedFrm = 0;
3486
3487 if (u16RealQPtr != u16QPtr)
3488 {
3489 if (u16RealQPtr > u16QPtr)
3490 {
3491 u16UsedFrm = u16RealQPtr - u16QPtr;
3492 }
3493 else
3494 {
3495 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
3496 }
3497 }
3498
3499 if (u16QNum > u16UsedFrm)
3500 {
3501 u16QNum -= u16UsedFrm;
3502 u16QPtr = u16RealQPtr;
3503 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
3504
3505 if ((u16QPtr%2) == 0) //For MVC mode, we must check the pair of display entry is ready or not
3506 {
3507 volatile HVD_Frm_Information *pHvdFrmNext = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr+1];
3508
3509 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
3510 {
3511 return NULL;
3512 }
3513 }
3514
3515 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
3516 {
3517 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
3518 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3519
3520 if ((u16QPtr%2) == 0)
3521 {
3522 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
3523 if(bDolbyVision)
3524 HVD_PRINT("BL pts: %d, u16QPtr: %d, u16QNum:%d, u32PrivateData:%d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData);
3525 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
3526 }
3527 else
3528 {
3529 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
3530 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
3531 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
3532 if(bDolbyVision)
3533 {
3534 HVD_PRINT("EL pts: %d, u16QPtr: %d, u16QNum:%d, u32PrivateData:%d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData);
3535
3536 volatile HVD_Frm_Information *pPrevHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr-1];//BL
3537 if(DIFF(pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp) > 1000)
3538 HVD_EX_MSG_ERR("BL pts: %d, EL pts: %d matched failed!!\n",pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp);
3539 }
3540 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
3541 }
3542
3543 u16QPtr++;
3544 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
3545 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
3546
3547 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
3548 }
3549 }
3550
3551 return NULL;
3552 }
3553
3554 //HVD_PRINT("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
3555 //search the next frame to display
3556 while (u16QNum > 0)
3557 {
3558 //HVD_PRINT("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
3559 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
3560 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3561
3562 //HVD_PRINT("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
3563 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3564 {
3565 /// For MVC. Output views after the pair of (base and depend) views were decoded.
3566 /// Check the depned view was initial when Output the base view.
3567 if((u16QPtr%2) == 0)
3568 {
3569 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
3570 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
3571 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
3572 {
3573 ///HVD_PRINT("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
3574 ///HVD_PRINT("Return NULL.\n");
3575 return NULL;
3576 }
3577 }
3578
3579 //HVD_PRINT("V:%d.\n",u16QPtr);
3580 pHVDHalContext->_u16DispQPtr = u16QPtr;
3581 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
3582 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
3583 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
3584 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
3585 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
3586 }
3587
3588 u16QNum--;
3589 //go to next frame in the dispQ
3590 u16QPtr++;
3591
3592 if (u16QPtr >= pShm->u16DispQSize)
3593 {
3594 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
3595 }
3596 }
3597 }
3598 else
3599 #endif ///HVD_ENABLE_MVC
3600 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
3601 if (_HVD_EX_IsHevcInterlaceField(u32Id))
3602 {
3603 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
3604 volatile HVD_Frm_Information *pHvdFrm_first = NULL;
3605
3606 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
3607 return NULL;
3608 }
3609
3610 while (u16QNum != 0)
3611 {
3612 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3613 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
3614 {
3615 if (!first_field) // second get frame, we will check at least one paired in disp queue.
3616 {
3617 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3618 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
3619 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
3620
3621 if(pHvdFrm->u8FieldType == EVD_TOP_FIELD || pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
3622 pHvdFrm->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
3623 else
3624 pHvdFrm->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
3625 return (HVD_Frm_Information *)pHvdFrm;
3626 }
3627 else // first get frame, we will check at least one paired in disp queue.
3628 {
3629 if (pHvdFrm_first == NULL)
3630 {
3631 pHvdFrm_first = pHvdFrm;
3632 }
3633 else
3634 {
3635 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3636 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
3637
3638 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV)
3639 {
3640 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV && pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_NEXT)
3641 {
3642 pHvdFrm_first->u32ID_L |= (1 << 16);
3643 pHvdFrm->u32ID_L |= (1 << 16);
3644 }
3645 else if (pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV && pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
3646 {
3647 pHvdFrm_first->u32ID_L &= (~(1 << 16));
3648 pHvdFrm->u32ID_L &= (~(1 << 16));
3649 }
3650 else
3651 {
3652 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
3653 return NULL;
3654 }
3655 }
3656 else
3657 {
3658 if (hevc_get_paired(pHvdFrm->u8FieldType, 0) != pHvdFrm_first->u8FieldType)
3659 {
3660 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
3661 return NULL;
3662 }
3663 }
3664
3665 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
3666 if (pHvdFrm_first->u8FieldType == EVD_TOP_FIELD || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_NEXT)
3667 pHvdFrm_first->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
3668 else
3669 pHvdFrm_first->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
3670 return (HVD_Frm_Information *)pHvdFrm_first;
3671 }
3672 }
3673 }
3674 u16QNum--;
3675 //go to next frame in the dispQ
3676 u16QPtr++;
3677
3678 if (u16QPtr == pShm->u16DispQSize)
3679 {
3680 u16QPtr = 0; //wrap to the begin
3681 }
3682
3683 }
3684 return NULL;
3685 }
3686 else
3687 {
3688 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3689 {
3690
3691 while (u16QNum != 0)
3692 {
3693 pHvdFrm = (volatile HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
3694
3695 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
3696 {
3697 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
3698 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3699 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
3700 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
3701 }
3702 u16QNum--;
3703 //go to next frame in the dispQ
3704 if (bDolbyVision)
3705 u16QPtr += 2; // single layer must in even ptr
3706 else
3707 u16QPtr++;
3708
3709 if (u16QPtr >= pShm->u16DispQSize)
3710 {
3711 u16QPtr = 0; //wrap to the begin
3712 }
3713 }
3714
3715 return NULL;
3716 }
3717
3718 //HVD_PRINT("Q: %d %d\n", u16QNum, u16QPtr);
3719 //search the next frame to display
3720 while (u16QNum != 0)
3721 {
3722 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3723
3724 //HVD_PRINT("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
3725 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3726 {
3727 pHVDHalContext->_u16DispQPtr = u16QPtr;
3728 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
3729 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
3730 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
3731 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
3732 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
3733 }
3734
3735 u16QNum--;
3736 //go to next frame in the dispQ
3737 u16QPtr++;
3738
3739 if (u16QPtr == pShm->u16DispQSize)
3740 {
3741 u16QPtr = 0; //wrap to the begin
3742 }
3743 }
3744 }
3745
3746 return NULL;
3747 }
3748
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)3749 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
3750 {
3751 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3752 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
3753 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3754 {
3755 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
3756 if(pVsyncBridgeExt != NULL)
3757 {
3758 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
3759 }
3760 }
3761 return pFrmInfoExt;
3762 }
3763
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)3764 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
3765 {
3766 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3767 MS_U64 u64Ret = 0;
3768
3769 #if SUPPORT_EVD
3770 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
3771 if (isEVD)
3772 {
3773 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
3774 }
3775 else
3776 #endif
3777 #if SUPPORT_G2VP9
3778 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3779 {
3780 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
3781 }
3782 else
3783 #endif
3784 {
3785 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
3786 }
3787
3788 return u64Ret;
3789 }
3790
3791 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)3792 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
3793 {
3794 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3795 MS_U16 u16QNum = pShm->u16DispQNumb;
3796 MS_U16 u16QPtr = pShm->u16DispQPtr;
3797 static volatile HVD_Frm_Information *pHvdFrm = NULL;
3798 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3799 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3800 MS_BOOL bMVC = FALSE;
3801 #if HVD_ENABLE_MVC
3802 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3803 #endif
3804
3805
3806 if (bMVC || (bDolbyVision && !pShm->bSingleLayer) || _HVD_EX_IsHevcInterlaceField(u32Id))
3807 {
3808 if (u16QNum == 1) return TRUE;
3809 }
3810
3811 while (u16QNum != 0)
3812 {
3813 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3814 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3815 {
3816 return FALSE;
3817 }
3818 u16QNum--;
3819
3820 if (bDolbyVision)
3821 u16QPtr += 2; // single layer must in even ptr
3822 else
3823 u16QPtr++;
3824
3825 if (u16QPtr >= pShm->u16DispQSize)
3826 {
3827 u16QPtr = 0; //wrap to the begin
3828 }
3829 }
3830
3831 return TRUE;
3832 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)3833 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
3834 {
3835 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3836
3837 return &(_pHVDCtrls[u8DrvId]);
3838 }
3839
_HVD_EX_GetStreamIdx(MS_U32 u32Id)3840 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
3841 {
3842 MS_U8 u8OffsetIdx = 0;
3843 MS_U8 u8SidBaseMask = 0xF0;
3844 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
3845
3846 switch (eSidBase)
3847 {
3848 case E_HAL_HVD_MAIN_STREAM_BASE:
3849 {
3850 u8OffsetIdx = 0;
3851 break;
3852 }
3853 case E_HAL_VPU_SUB_STREAM_BASE:
3854 {
3855 u8OffsetIdx = 1;
3856 break;
3857 }
3858 case E_HAL_VPU_MVC_STREAM_BASE:
3859 {
3860 u8OffsetIdx = 0;
3861 break;
3862 }
3863 #ifdef VDEC3
3864 case E_HAL_VPU_N_STREAM_BASE:
3865 {
3866 u8OffsetIdx = (u32Id>>8) & 0xF;
3867 break;
3868 }
3869 #endif
3870 default:
3871 {
3872 u8OffsetIdx = 0;
3873 break;
3874 }
3875 }
3876
3877 return u8OffsetIdx;
3878 }
3879 /*
3880 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
3881 {
3882 MS_U32 i = 0;
3883 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3884 {
3885 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
3886 {
3887 return TRUE;
3888 }
3889 }
3890 return FALSE;
3891 }
3892 */
3893
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)3894 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
3895 {
3896 MS_PHY u32PhyAddr = 0x0;
3897 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3898
3899 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3900 {
3901 return 0;
3902 }
3903
3904 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3905
3906 if (u32PhyAddr == 0xFFFFFFFF) //boris
3907 {
3908 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3909 }
3910 else
3911 {
3912 // TEE, common + share_info
3913 u32PhyAddr += COMMON_AREA_SIZE;
3914 }
3915
3916 return MsOS_PA2KSEG1(u32PhyAddr);
3917 }
3918
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3919 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3920 {
3921 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3922 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3923
3924 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3925 {
3926 return 0;
3927 }
3928
3929 MS_PHY u32PhyAddr = 0x0;
3930 #if 0
3931 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3932
3933 if (u32PhyAddr == 0xFFFFFFFF)
3934 {
3935 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3936 }
3937 #endif
3938 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3939 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3940
3941 return MsOS_PA2KSEG1(u32PhyAddr);
3942 }
3943
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3944 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3945 {
3946
3947 if (u8MiuSel == E_CHIP_MIU_0)
3948 {
3949 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3950 //_HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3951 }
3952 else if (u8MiuSel == E_CHIP_MIU_1)
3953 {
3954 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3955 //_HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3956 }
3957 /*
3958 else // 2
3959 {
3960 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3961 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, MIU2_CLIENT_SELECT_GP4_HVD_MIF1, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3962 }*/
3963
3964 }
3965
3966 #if SUPPORT_G2VP9 && defined(VDEC3)
3967 #ifdef __ARM_NEON__
3968 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3969 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3970 {
3971 uint32x4x4_t data, data2;
3972 MS_U8* raster2 = raster + tile_w * 4;
3973
3974 data = vld4q_u32((const uint32_t *)tile);
3975 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3976
3977 vst1q_u32((uint32_t *)raster, data.val[0]);
3978 raster += stride;
3979 vst1q_u32((uint32_t *)raster, data.val[1]);
3980 raster += stride;
3981 vst1q_u32((uint32_t *)raster, data.val[2]);
3982 raster += stride;
3983 vst1q_u32((uint32_t *)raster, data.val[3]);
3984
3985
3986 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3987 raster2 += stride;
3988 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3989 raster2 += stride;
3990 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3991 raster2 += stride;
3992 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3993 }
3994 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3995 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3996 {
3997 MS_U8* tile0 = tile;
3998 MS_U8* tile1 = tile+16;
3999 MS_U8* tile2 = tile+32;
4000 MS_U8* tile3 = tile+48;
4001 int i;
4002
4003 for (i=0; i<4; i++) {
4004 raster[i] = tile0[i];
4005 raster[4+i] = tile1[i];
4006 raster[8+i] = tile2[i];
4007 raster[12+i] = tile3[i];
4008 }
4009
4010 for (i=0; i<4; i++) {
4011 raster[stride+i] = tile0[4+i];
4012 raster[stride+4+i] = tile1[4+i];
4013 raster[stride+8+i] = tile2[4+i];
4014 raster[stride+12+i] = tile3[4+i];
4015 }
4016
4017 for (i=0; i<4; i++) {
4018 raster[2*stride+i] = tile0[8+i];
4019 raster[2*stride+4+i] = tile1[8+i];
4020 raster[2*stride+8+i] = tile2[8+i];
4021 raster[2*stride+12+i] = tile3[8+i];
4022 }
4023
4024 for (i=0; i<4; i++) {
4025 raster[3*stride+i] = tile0[12+i];
4026 raster[3*stride+4+i] = tile1[12+i];
4027 raster[3*stride+8+i] = tile2[12+i];
4028 raster[3*stride+12+i] = tile3[12+i];
4029 }
4030 }
4031 #endif // #ifdef __ARM_NEON__
4032
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)4033 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
4034 {
4035 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
4036 u32Id,
4037 E_TASK_PRI_MEDIUM,
4038 TRUE,
4039 NULL,
4040 32, // stack size..
4041 "HVD_PostProcess_task");
4042
4043 if (s32HvdPpTaskId < 0)
4044 {
4045 HVD_EX_MSG_ERR("Pp Task create failed\n");
4046
4047 return FALSE;
4048 }
4049
4050 HVD_EX_MSG_DBG("Pp Task create success\n");
4051 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
4052
4053 return TRUE;
4054 }
4055
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)4056 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
4057 {
4058 return y * stride * h + x * w * h;
4059 }
4060
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)4061 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
4062 {
4063 return y * stride * h + x * w;
4064 }
4065
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)4066 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
4067 {
4068 raster[0] = tile[0];
4069 raster[1] = tile[1];
4070 raster[2] = tile[2];
4071 raster[3] = tile[3];
4072 raster[stride] = tile[4];
4073 raster[stride + 1] = tile[5];
4074 raster[stride + 2] = tile[6];
4075 raster[stride + 3] = tile[7];
4076 raster[2 * stride] = tile[8];
4077 raster[2 * stride + 1] = tile[9];
4078 raster[2 * stride + 2] = tile[10];
4079 raster[2 * stride + 3] = tile[11];
4080 raster[3 * stride] = tile[12];
4081 raster[3 * stride + 1] = tile[13];
4082 raster[3 * stride + 2] = tile[14];
4083 raster[3 * stride + 3] = tile[15];
4084 }
4085
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)4086 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
4087 {
4088 const MS_U32 tile_w = 4;
4089 const MS_U32 tile_h = 4;
4090 MS_U32 tile_stride = w;
4091 MS_U32 x, y;
4092 MS_U8 *dst1, *dst2;
4093 MS_U8 *src1, *src2;
4094
4095 #ifdef __ARM_NEON__
4096 // To overlap load and store, handle two blocks at the same time.
4097 dst1 = dst;
4098 src1 = src;
4099 for (y = 0; y < h / tile_h; y++)
4100 {
4101 dst2 = dst1;
4102 src2 = src1;
4103 for (x = 0; x <= (w/tile_w - 8); x+=8)
4104 {
4105 tile4x4_to_raster_8(
4106 dst2,
4107 src2,
4108 raster_stride, tile_w, tile_h);
4109 dst2 += tile_w * 8;
4110 src2 += tile_w * tile_h * 8;
4111 }
4112 dst1 += raster_stride * tile_h;
4113 src1 += tile_stride * tile_h;
4114 for (; x < w / tile_w; x++)
4115 {
4116 tile4x4_to_raster(
4117 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
4118 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
4119 raster_stride);
4120 }
4121 }
4122 #else
4123 dst1 = NULL;
4124 src1 = NULL;
4125 dst2 = NULL;
4126 src2 = NULL;
4127
4128 for (y = 0; y < h / tile_h; y++)
4129 {
4130 for (x = 0; x <= (w/tile_w - 4); x+=4)
4131 {
4132 tile4x4_to_raster_4(
4133 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
4134 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
4135 raster_stride);
4136 }
4137 for (; x < w / tile_w; x++)
4138 {
4139 tile4x4_to_raster(
4140 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
4141 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
4142 raster_stride);
4143 }
4144 }
4145 #endif
4146 }
4147
4148 #define FLUSH_CACHE_SIZE (256 * 1024)
4149
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)4150 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
4151 {
4152 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
4153 if (u32Size > FLUSH_CACHE_SIZE)
4154 u32Size = FLUSH_CACHE_SIZE;
4155
4156 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
4157 }
4158
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)4159 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
4160 {
4161 MS_U32 u32SkipSize = 0;
4162
4163 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
4164 if (u32Size > FLUSH_CACHE_SIZE)
4165 {
4166 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
4167 u32Size = FLUSH_CACHE_SIZE;
4168 }
4169
4170 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
4171 }
4172
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)4173 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
4174 {
4175 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
4176 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4177 MS_U32 u32SrcMiuSel, u32DstMiuSel;
4178 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
4179
4180 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
4181
4182 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
4183
4184 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
4185 {
4186 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
4187 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
4188
4189 HVD_Delay_ms(1); // FIXME
4190
4191 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
4192 continue;
4193
4194 HAL_HVD_EX_ReadMemory();
4195
4196 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
4197 {
4198 MS_U8 *pSrcVA, *pDstVA;
4199 MS_U32 u32SrcPA, u32DstPA;
4200 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
4201 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
4202
4203 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
4204 {
4205 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
4206
4207 u16Width = pFrmInfo->u16Width;
4208 u16Height = pFrmInfo->u16Height;
4209 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
4210 }
4211
4212 // Luma
4213 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
4214 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
4215
4216 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
4217 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
4218
4219 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
4220 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
4221
4222 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
4223
4224 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
4225
4226 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
4227
4228 // Chroma
4229 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
4230 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
4231
4232 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
4233 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
4234
4235 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
4236 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
4237
4238 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
4239
4240 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
4241
4242 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
4243
4244 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
4245 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
4246 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
4247
4248 HAL_HVD_EX_FlushMemory();
4249
4250 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
4251 break;
4252
4253 HAL_HVD_EX_ReadMemory();
4254 }
4255 }
4256
4257 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
4258
4259 return TRUE;
4260 }
4261 #endif
4262
HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id,MS_BOOL * isVP8Used,MS_BOOL * isAECUsed,MS_BOOL * isAVCUsed)4263 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed , MS_BOOL *isAVCUsed)
4264 {
4265 MS_U8 i ;
4266 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
4267
4268 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM ; i++)
4269 {
4270 if( _pHVDCtrls[i].bUsed && (i != u8DrvId))
4271 {
4272 MS_U32 u32TempModeFlag = (_pHVDCtrls[i].InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ;
4273 if((E_HVD_INIT_HW_VP8 == u32TempModeFlag))
4274 {
4275 *isVP8Used = TRUE ;
4276 }
4277 else if((E_HVD_INIT_HW_VP9 == u32TempModeFlag) || (E_HVD_INIT_HW_AVS == u32TempModeFlag))
4278 {
4279 *isAECUsed = TRUE ;
4280 }
4281 else if((E_HVD_INIT_HW_AVC == u32TempModeFlag))
4282 {
4283 *isAVCUsed = TRUE ;
4284 }
4285 }
4286 }
4287 }
4288
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)4289 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
4290 {
4291 #ifndef VDEC3
4292 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
4293 #endif
4294 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4295 MS_BOOL isVP8Used = FALSE;
4296 MS_BOOL isAECUsed = FALSE;
4297 MS_BOOL isAVCUsed = FALSE;
4298 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
4299 // MS_U8 u8MiuSel;
4300 // MS_U32 u32StartOffset;
4301
4302 #if SUPPORT_EVD
4303 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
4304 #else
4305 MS_BOOL isEVD = FALSE;
4306 #endif
4307 MS_BOOL isHVD = !isEVD;
4308
4309 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
4310 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
4311
4312 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
4313 // re-setup clock.
4314 #if SUPPORT_G2VP9 && defined(VDEC3)
4315 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4316 #endif
4317
4318 if(isHVD)
4319 {
4320 if(!HAL_VPU_EX_HVDInUsed())
4321 {
4322 HVD_PRINT("HVD power on\n");
4323 #ifdef CONFIG_MSTAR_CLKM
4324 HAL_HVD_EX_PowerCtrl_CLKM(u32Id, TRUE);
4325 #else
4326 HAL_HVD_EX_PowerCtrl(u32Id, TRUE);
4327 #endif
4328 }
4329
4330 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4331 {
4332 HAL_VP8_PowerCtrl(TRUE);
4333 }
4334 else if(!isAECUsed &&( E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4335 {
4336 HAL_AEC_PowerCtrl(TRUE);
4337 }
4338
4339 #ifdef CONFIG_MSTAR_SRAMPD
4340 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
4341 HVD_Delay_ms(1);
4342 #endif
4343 }
4344
4345 #if SUPPORT_EVD
4346 #ifdef VDEC3
4347 if (isEVD)
4348 {
4349 if(!HAL_VPU_EX_EVDInUsed())
4350 {
4351 HVD_PRINT("EVD power on\n");
4352 #ifdef CONFIG_MSTAR_CLKM
4353 HAL_EVD_EX_PowerCtrl_CLKM(u32Id, TRUE);
4354 #else
4355 HAL_EVD_EX_PowerCtrl(u32Id, TRUE);
4356 #endif
4357 }
4358 if(!isAECUsed && (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4359 {
4360 HAL_AEC_PowerCtrl(TRUE);
4361 }
4362 }
4363 #endif
4364 #endif
4365
4366
4367
4368
4369 #if SUPPORT_G2VP9 && defined(VDEC3)
4370 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4371 {
4372 if (!HAL_VPU_EX_G2VP9InUsed())
4373 {
4374 HVD_PRINT("G2 VP9 power on\n");
4375 HAL_VP9_EX_PowerCtrl(TRUE);
4376 }
4377 }
4378 #endif
4379
4380 if ((!HAL_VPU_EX_HVDInUsed()) )
4381 {
4382 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
4383 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
4384 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
4385 _HVD_EX_ResetMainSubBBUWptr(u32Id);
4386
4387 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
4388
4389 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
4390 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
4391 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_128 , HVD_REG_RESET_MIU_128);
4392 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_128 , HVD_REG_RESET_MIU1_128 );
4393 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_256 );
4394 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_256);
4395 //BWA
4396 _HVD_Write2Byte(HVD_REG_BWA_CLK, ((_HVD_Read2Byte(HVD_REG_BWA_CLK))&((~HVD_REG_CLK_HVD_SW_OV_EN & ~HVD_REG_CLK_HVD_IDB_SW_OV_EN))));
4397
4398 #if 0
4399 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
4400 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4401 {
4402 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
4403
4404 _HAL_HVD_Entry();
4405 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
4406 _HAL_HVD_Release();
4407
4408 }
4409 #endif
4410 }
4411
4412 #if SUPPORT_EVD
4413 if (isEVD)
4414 {
4415 #ifdef VDEC3
4416 if (!HAL_VPU_EX_EVDInUsed())
4417 #endif
4418 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
4419 }
4420 #endif
4421
4422 #if SUPPORT_G2VP9 && defined(VDEC3)
4423 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4424 {
4425 if (!HAL_VPU_EX_G2VP9InUsed())
4426 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
4427 }
4428 #endif
4429
4430
4431 if(pCtrl == NULL)
4432 {
4433 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
4434 //return FALSE;
4435 goto RESET;
4436 }
4437
4438 #if SUPPORT_EVD
4439 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
4440 {
4441 #ifdef VDEC3
4442 if (!HAL_VPU_EX_EVDInUsed())
4443 #endif
4444 {
4445 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4446 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
4447 }
4448
4449 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
4450 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
4451 {
4452 #ifdef VDEC3
4453 if (0 == pCtrl->u32BBUId)
4454 #else
4455 if (0 == u8TaskId)
4456 #endif
4457 {
4458 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
4459 }
4460 #ifdef VDEC3
4461 else if (1 == pCtrl->u32BBUId)
4462 #else
4463 else if (1 == u8TaskId)
4464 #endif
4465 {
4466 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
4467 }
4468 #ifdef VDEC3
4469 else if (2 == pCtrl->u32BBUId)
4470 #else
4471 else if (2 == u8TaskId)
4472 #endif
4473 {
4474 _HVD_WriteWordMask(EVD_BBU23_SETTING, REG_TSP2EVD_EN_BS3, REG_TSP2EVD_EN_BS3);
4475 }
4476 else
4477 {
4478 #ifdef VDEC3
4479 if (pCtrl->u32BBUId > 3)
4480 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
4481 #else
4482 if (u8TaskId > 3)
4483 HVD_PRINT("Error u8TaskId = %d , %s:%d\n",u8TaskId,__FUNCTION__,__LINE__);
4484 #endif
4485
4486 _HVD_WriteWordMask(EVD_BBU23_SETTING, REG_TSP2EVD_EN_BS4, REG_TSP2EVD_EN_BS4);
4487 }
4488 }
4489 goto RESET;
4490 }
4491 #endif
4492
4493 // HVD4, from JANUS and later chip
4494 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
4495 {
4496 case E_HVD_INIT_HW_AVS:
4497 {
4498 #ifdef VDEC3
4499 if (0 == pCtrl->u32BBUId)
4500 #else
4501 if (0 == u8TaskId)
4502 #endif
4503 {
4504 _HVD_WriteWordMask(HVD_REG_RESET, 0,
4505 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
4506 }
4507 else
4508 {
4509 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
4510 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
4511 }
4512
4513 break;
4514 }
4515 case E_HVD_INIT_HW_RM:
4516 {
4517 #ifdef VDEC3
4518 if (0 == pCtrl->u32BBUId)
4519 #else
4520 if (0 == u8TaskId)
4521 #endif
4522 {
4523 _HVD_WriteWordMask(HVD_REG_RESET, 0,
4524 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
4525
4526 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
4527 {
4528 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
4529 }
4530 else // RV 8
4531 {
4532 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
4533 }
4534 }
4535 else
4536 {
4537 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
4538 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
4539
4540 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
4541 {
4542 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
4543 }
4544 else // RV 8
4545 {
4546 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
4547 }
4548
4549 }
4550
4551 break;
4552 }
4553 default:
4554 {
4555 #ifdef VDEC3
4556 if (0 == pCtrl->u32BBUId)
4557 #else
4558 if (0 == u8TaskId)
4559 #endif
4560 {
4561 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
4562 }
4563 else
4564 {
4565 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
4566 }
4567 break;
4568 }
4569 }
4570
4571 RESET:
4572
4573 #if 0 //use miu256bit
4574 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
4575
4576 if (!HAL_VPU_EX_HVDInUsed())
4577 {
4578 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
4579 }
4580
4581 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
4582 #endif
4583
4584 #if SUPPORT_EVD
4585 if (isEVD)
4586 {
4587 #ifdef VDEC3
4588 if (!HAL_VPU_EX_EVDInUsed())
4589 #endif
4590 {
4591 HVD_PRINT("EVD miu 128 bits\n");
4592 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_256 & ~EVD_REG_RESET_MIU1_256));
4593 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_128 | EVD_REG_RESET_MIU1_128));
4594 HVD_PRINT("EVD BBU 128 bits\n");
4595 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) & ~REG_BBU_MIU_256));
4596 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) | REG_BBU_MIU_128));
4597 _HVD_Write2Byte(REG_CLK_EVD, (_HVD_Read2Byte(REG_CLK_EVD) & ~REG_CLK_EVD_SW_OV_EN & ~REG_CLK_EVD_PPU_SW_OV_EN));//set 0 firmware
4598 }
4599 }
4600 #endif
4601 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
4602 // Only ES buffer addrress needs to be set for VP8
4603 _HVD_EX_SetESBufferAddr(u32Id);
4604 #else
4605 if(DecoderType != E_VPU_EX_DECODER_MVD)
4606 {
4607 _HVD_EX_SetBufferAddr(u32Id);
4608 }
4609 #endif
4610 if (!HAL_VPU_EX_HVDInUsed())
4611 {
4612 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
4613 }
4614
4615 #if SUPPORT_EVD
4616 if (isEVD)
4617 {
4618 #ifdef VDEC3
4619 if (!HAL_VPU_EX_EVDInUsed())
4620 #endif
4621 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
4622 }
4623 #endif
4624
4625 #if SUPPORT_G2VP9 && defined(VDEC3)
4626 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4627 {
4628 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4629
4630 if (!HAL_VPU_EX_G2VP9InUsed())
4631 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
4632
4633 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
4634 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
4635 }
4636 #endif
4637
4638 return TRUE;
4639 }
4640
HAL_HVD_EX_DeinitHW(MS_U32 u32Id)4641 MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id)
4642 {
4643 MS_U16 u16Timeout = 1000;
4644 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4645 MS_BOOL isVP8Used = FALSE;
4646 MS_BOOL isAECUsed = FALSE;
4647 MS_BOOL isAVCUsed = FALSE;
4648 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed , &isAVCUsed);
4649
4650 #if SUPPORT_EVD
4651 if(!isAVCUsed && E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) && !HAL_VPU_EX_EVDInUsed())
4652 {
4653 HAL_EVD_EX_DeinitHW(u32Id);//no AVC/EVD use , close EVD power
4654 }
4655 #endif
4656
4657 if(TRUE == HAL_VPU_EX_HVDInUsed())
4658 {
4659 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4660 {
4661 HAL_VP8_PowerCtrl(FALSE);
4662 }
4663 else if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4664 {
4665 HAL_AEC_PowerCtrl(FALSE);
4666 }
4667 return FALSE;
4668 }
4669 else
4670 {
4671 _HVD_EX_SetMIUProtectMask(TRUE);
4672
4673 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
4674
4675 while (u16Timeout)
4676 {
4677 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
4678 {
4679 break;
4680 }
4681 u16Timeout--;
4682 }
4683
4684 #ifdef CONFIG_MSTAR_CLKM
4685 HAL_HVD_EX_PowerCtrl_CLKM(u32Id, FALSE);
4686 #else
4687 HAL_HVD_EX_PowerCtrl(u32Id, FALSE);
4688 #endif
4689
4690 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4691 {
4692 HAL_VP8_PowerCtrl(FALSE);
4693 }
4694 else if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4695 {
4696 HAL_AEC_PowerCtrl(FALSE);
4697 }
4698
4699 #ifdef CONFIG_MSTAR_SRAMPD
4700 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
4701 HVD_Delay_ms(1);
4702 #endif
4703
4704 _HVD_EX_SetMIUProtectMask(FALSE);
4705
4706 return TRUE;
4707 }
4708
4709 return FALSE;
4710 }
4711
HAL_HVD_EX_FlushMemory(void)4712 void HAL_HVD_EX_FlushMemory(void)
4713 {
4714 MsOS_FlushMemory();
4715 }
4716
HAL_HVD_EX_ReadMemory(void)4717 void HAL_HVD_EX_ReadMemory(void)
4718 {
4719 MsOS_ReadMemory();
4720 }
4721
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)4722 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
4723 {
4724 _pHVDCtrls = pHVDCtrlsBase;
4725 }
4726
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)4727 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
4728 {
4729 return;
4730 }
4731
HAL_HVD_EX_GetHWVersionID(void)4732 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
4733 {
4734 return _HVD_Read2Byte(HVD_REG_REV_ID);
4735 }
4736
4737
HAL_HVD_EX_Init_Share_Mem(void)4738 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
4739 {
4740 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
4741 #if !defined(SUPPORT_X_MODEL_FEATURE)
4742 MS_U32 u32ShmId;
4743 MS_VIRT u32Addr;
4744 MS_U32 u32BufSize;
4745
4746
4747 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
4748 sizeof(HVD_Hal_CTX),
4749 &u32ShmId,
4750 &u32Addr,
4751 &u32BufSize,
4752 MSOS_SHM_QUERY))
4753 {
4754 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
4755 sizeof(HVD_Hal_CTX),
4756 &u32ShmId,
4757 &u32Addr,
4758 &u32BufSize,
4759 MSOS_SHM_CREATE))
4760 {
4761 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
4762 if(pHVDHalContext == NULL)
4763 {
4764 pHVDHalContext = &gHVDHalContext;
4765 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4766 _HVD_EX_Context_Init_HAL();
4767 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
4768 }
4769 else
4770 {
4771 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
4772 }
4773 //return FALSE;
4774 }
4775 else
4776 {
4777 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
4778 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
4779 _HVD_EX_Context_Init_HAL();
4780 }
4781 }
4782 else
4783 {
4784 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
4785 }
4786 #else
4787 if(pHVDHalContext == NULL)
4788 {
4789 pHVDHalContext = &gHVDHalContext;
4790 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4791 _HVD_EX_Context_Init_HAL();
4792 }
4793 #endif
4794 _HAL_HVD_MutexCreate();
4795 #else
4796 if(pHVDHalContext == NULL)
4797 {
4798 pHVDHalContext = &gHVDHalContext;
4799 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4800 _HVD_EX_Context_Init_HAL();
4801 }
4802 #endif
4803
4804 return TRUE;
4805 }
4806
4807
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)4808 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
4809 {
4810 MS_U32 i = 0;
4811
4812 if (eStreamType == E_HAL_HVD_MVC_STREAM)
4813 {
4814 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
4815 return pHVDHalContext->_stHVDStream[0].eStreamId;
4816 }
4817 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
4818 {
4819 for (i = 0;
4820 i <
4821 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
4822 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
4823 {
4824 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
4825 {
4826 return pHVDHalContext->_stHVDStream[i].eStreamId;
4827 }
4828 }
4829 }
4830 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
4831 {
4832 for (i = 0;
4833 i <
4834 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
4835 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
4836 {
4837 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
4838 {
4839 return pHVDHalContext->_stHVDStream[i].eStreamId;
4840 }
4841 }
4842 }
4843 #ifdef VDEC3
4844 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
4845 {
4846 i = eStreamType - E_HAL_HVD_N_STREAM;
4847 if (!pHVDHalContext->_stHVDStream[i].bUsed)
4848 return pHVDHalContext->_stHVDStream[i].eStreamId;
4849 }
4850 #endif
4851
4852 return E_HAL_HVD_STREAM_NONE;
4853 }
4854
HAL_VP8_PowerCtrl(MS_BOOL bEnable)4855 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable)
4856 {
4857 if (bEnable)
4858 {
4859 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
4860
4861 switch (pHVDHalContext->u32HVDClockType)
4862 {
4863 case 384:
4864 {
4865 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
4866 break;
4867 }
4868 case 288:
4869 {
4870 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
4871 break;
4872 }
4873 default:
4874 {
4875 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
4876 break;
4877 }
4878 }
4879 }
4880 else
4881 {
4882 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
4883 }
4884
4885 }
4886
HAL_AEC_PowerCtrl(MS_BOOL bEnable)4887 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable)
4888 {
4889 if (bEnable)
4890 {
4891 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4892
4893 switch (pHVDHalContext->u32HVDClockType)
4894 {
4895 case 384:
4896 {
4897 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4898 break;
4899 }
4900 case 288:
4901 {
4902 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4903 break;
4904 }
4905 default:
4906 {
4907 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4908 break;
4909 }
4910 }
4911 }
4912 else
4913 {
4914 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4915 }
4916
4917 }
4918
4919
HAL_HVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)4920 void HAL_HVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
4921 {
4922
4923 if (bEnable)
4924 {
4925 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4926 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4927 }
4928 else
4929 {
4930 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4931 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4932 }
4933
4934 // fix to not inverse
4935 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
4936
4937 switch (pHVDHalContext->u32HVDClockType)
4938 {
4939 #if 0 //for overclocking
4940 case 432:
4941 {
4942 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
4943 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4944 break;
4945 }
4946 #endif
4947 case 384:
4948 {
4949 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4950 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4951 break;
4952 }
4953 case 288:
4954 {
4955 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
4956 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4957 break;
4958 }
4959 default:
4960 {
4961 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4962 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4963 break;
4964 }
4965 }
4966 }
4967
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)4968 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
4969 {
4970 u32HVDRegOSBase = u32RegBase;
4971 HAL_VPU_EX_InitRegBase(u32RegBase);
4972 }
4973
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)4974 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
4975 {
4976 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
4977 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4978 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
4979 }
4980
HAL_HVD_EX_InitVariables(MS_U32 u32Id)4981 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
4982 {
4983 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4984 HVD_ShareMem *pShm = NULL;
4985 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4986 #if HVD_ENABLE_MVC
4987 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4988 #endif ///HVD_ENABLE_MVC
4989
4990 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4991 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4992 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4993 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
4994 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4995 int i;
4996 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
4997 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
4998 #if HVD_ENABLE_MVC
4999 if(bMVC)
5000 {
5001 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
5002 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
5003 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
5004 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
5005 }
5006 #endif ///HVD_ENABLE_MVC
5007
5008 // set a local copy of FW code address; assuming there is only one copy of FW,
5009 // no matter how many task will be created.
5010
5011 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5012
5013 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
5014
5015 // global variables
5016 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
5017
5018
5019 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
5020 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
5021 // Create mutex
5022 //_HAL_HVD_MutexCreate();
5023
5024 // fill HVD init variables
5025 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5026 {
5027 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
5028 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
5029 }
5030 else
5031 #if HVD_ENABLE_RV_FEATURE
5032 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
5033 {
5034 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
5035 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
5036 #ifdef VDEC3_FB
5037 pHVDHalContext->u32RV_VLCTableAddr = 0;
5038 #else
5039 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
5040 {
5041 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
5042 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
5043 }
5044 else
5045 {
5046 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
5047 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
5048 return E_HVD_RETURN_INVALID_PARAMETER;
5049 }
5050 #endif
5051 }
5052 else
5053 #endif
5054 {
5055 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
5056 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
5057 #if HVD_ENABLE_MVC
5058 if(bMVC)
5059 {
5060 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
5061 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
5062 }
5063 #endif /// HVD_ENABLE_MVC
5064 pHVDHalContext->u32RV_VLCTableAddr = 0;
5065 }
5066
5067 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
5068 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
5069 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
5070 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
5071 {
5072 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
5073 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
5074 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
5075 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
5076 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
5077 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
5078 #if HVD_ENABLE_MVC
5079 if(bMVC)
5080 {
5081 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
5082 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
5083 {
5084 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
5085 }
5086 }
5087 #endif /// HVD_ENABLE_MVC
5088
5089 return E_HVD_RETURN_SUCCESS;
5090 }
5091 else
5092 {
5093 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
5094 (unsigned long)MS_VA2PA((MS_VIRT)pShm),
5095 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
5096 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
5097 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
5098 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
5099 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
5100 return E_HVD_RETURN_INVALID_PARAMETER;
5101 }
5102 }
5103
5104 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)5105 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
5106 #else
5107 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
5108 #endif
5109 {
5110 MS_U32 u32Addr = 0;
5111 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5112 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5113 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5114
5115 MS_U32 u32TmpStartOffset;
5116 MS_U8 u8TmpMiuSel;
5117
5118
5119 memset(pShm, 0, sizeof(HVD_ShareMem));
5120
5121 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
5122
5123 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
5124 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
5125 #ifdef VDEC3
5126 if (bFWdecideFB || bCMAUsed)
5127 {
5128 pShm->u32FrameBufAddr = 0;
5129 pShm->u32FrameBufSize = 0;
5130 }
5131 else
5132 #endif
5133 {
5134 pShm->u32FrameBufAddr = u32Addr;
5135 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
5136 }
5137
5138 // FIXME: need to use the avaliable task resource instead of using next task resource
5139 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
5140 pShm->u8ExternalHeapIdx = u8Idx + 1;
5141 else
5142 pShm->u8ExternalHeapIdx = 0xFF;
5143 pShm->DispInfo.u16DispWidth = 1;
5144 pShm->DispInfo.u16DispHeight = 1;
5145 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
5146 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
5147 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
5148 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
5149 //Chip info
5150 pShm->u16ChipID = E_MSTAR_CHIP_K6;
5151 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
5152 // PreSetControl
5153 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bOnePendingBuffer)
5154 {
5155 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
5156 }
5157
5158 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bCalFrameRate)
5159 {
5160 pShm->u32PreSetControl |= PRESET_CAL_FRAMERATE;
5161 }
5162
5163
5164 pShm->bUseTSPInBBUMode = FALSE;
5165
5166
5167 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable) &&
5168 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
5169 {
5170 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
5171
5172 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufAddr);
5173
5174 pShm->u32IapGnBufAddr = u32Addr;
5175 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufSize;
5176
5177 }
5178
5179 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
5180 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
5181 {
5182 case E_HVD_DEF_MFCODEC_DEFAULT:
5183 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
5184 break;
5185 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
5186 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
5187 break;
5188 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
5189 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
5190 break;
5191 default:
5192 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
5193 }
5194
5195 pShm->u8CodecFeature &= ~E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
5196 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bDVSingleLayerMode)
5197 pShm->u8CodecFeature |= E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
5198
5199 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
5200 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
5201 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
5202 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
5203 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
5204 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
5205
5206 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.bEnable))
5207 {
5208 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
5209
5210 pShm->stDynmcDispPath.u8Connect = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.bConnect;
5211 pShm->stDynmcDispPath.u8DispPath = (MS_U8)(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.eMvopPath);
5212 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
5213
5214 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, pShm->stDynmcDispPath.u8DispPath);
5215 }
5216 else
5217 {
5218 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
5219
5220 MS_U8 u8Connect = FALSE;
5221 MS_U8 u8Path = E_CTL_DISPLAY_PATH_NONE;
5222 switch (pCtrl->eStream)
5223 {
5224 case E_HVD_ORIGINAL_MAIN_STREAM:
5225 u8Connect = TRUE;
5226 u8Path = E_CTL_DISPLAY_PATH_MVOP_0;
5227 break;
5228 case E_HVD_ORIGINAL_SUB_STREAM:
5229 u8Connect = TRUE;
5230 u8Path = E_CTL_DISPLAY_PATH_MVOP_1;
5231 break;
5232 case E_HVD_ORIGINAL_N_STREAM:
5233 default:
5234 u8Connect = FALSE;
5235 u8Path = E_CTL_DISPLAY_PATH_NONE;
5236 break;
5237 }
5238
5239 pShm->stDynmcDispPath.u8Connect = u8Connect;
5240 pShm->stDynmcDispPath.u8DispPath = u8Path;
5241 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
5242
5243 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, u8Path);
5244 }
5245
5246 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5247 {
5248 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.bEnable))
5249 {
5250 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
5251 pShm->u8InputTSP = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.u8InputTsp;
5252
5253 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
5254 }
5255 else
5256 {
5257 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
5258
5259 MS_U8 u8Input = E_CTL_INPUT_TSP_NONE;
5260 switch (pCtrl->eStream)
5261 {
5262 case E_HVD_ORIGINAL_MAIN_STREAM:
5263 u8Input = E_CTL_INPUT_TSP_0;
5264 break;
5265 case E_HVD_ORIGINAL_SUB_STREAM:
5266 u8Input = E_CTL_INPUT_TSP_1;
5267 break;
5268 case E_HVD_ORIGINAL_N_STREAM:
5269 default:
5270 u8Input = E_CTL_INPUT_TSP_NONE;
5271 break;
5272 }
5273
5274 pShm->u8InputTSP = u8Input;
5275
5276 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
5277 }
5278 }
5279 else
5280 {
5281 HVD_EX_MSG_DBG("[NDec][0x%x][%d] not TSP input, ignore PRESET_CONNECT_INPUT_TSP \n", u32Id, u8Idx);
5282 }
5283
5284 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
5285 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
5286 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
5287 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
5288 else
5289 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
5290 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
5291 {
5292 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
5293 {
5294 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
5295 }
5296 else
5297 {
5298 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
5299 }
5300 }
5301 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
5302 {
5303 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
5304 {
5305 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
5306 }
5307 else
5308 {
5309 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
5310 }
5311 }
5312 else
5313 {
5314 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
5315 }
5316
5317 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5318 {
5319 pShm->bHVDIMIEnable = TRUE;
5320 }
5321
5322 #if 0
5323 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bEnableDynamicCMA)
5324 {
5325 pShm->u8CodecFeature |= E_VDEC_DYNAMIC_CMA_MODE;
5326 }
5327 #endif
5328
5329 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5330 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5331 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5332 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5333 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5334 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5335 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5336 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5337 (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
5338 {
5339 pShm->bUseWbMvop = 1;
5340 }
5341
5342
5343 // disable AVC fluidplay temporarily
5344 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
5345 || E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5346 {
5347 pShm->u8CodecFeature |= E_VDEC_TEMPORAL_SCALABILITY_MODE;
5348 }
5349
5350 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
5351
5352 #if (VPU_FORCE_MIU_MODE)
5353 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5354
5355 pShm->u32FWBaseAddr = u32TmpStartOffset;
5356
5357 #else
5358 ///TODO:
5359 /*
5360 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5361
5362 if(u8TmpMiuSel == E_CHIP_MIU_0)
5363 {
5364 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
5365 }
5366 else if(u8TmpMiuSel == E_CHIP_MIU_1)
5367 {
5368 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
5369 }
5370 else if(u8TmpMiuSel == E_CHIP_MIU_2)
5371 {
5372 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
5373 }
5374 */
5375 #endif
5376 //HVD_PRINT("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
5377 #else
5378 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
5379 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
5380 {
5381 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
5382 }
5383 pShm->u32FWBaseAddr = u32Addr;
5384 #endif
5385
5386 // RM only
5387 #if HVD_ENABLE_RV_FEATURE
5388 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
5389 && (pCtrl->InitParams.pRVFileInfo != NULL))
5390 {
5391 MS_U32 i = 0;
5392
5393 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
5394 {
5395 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
5396 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
5397 }
5398
5399 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
5400 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
5401 #ifdef VDEC3_FB
5402 pShm->u32RM_VLCTableAddr = 0;
5403 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
5404 #else
5405 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
5406
5407 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
5408 u32Addr = u32TmpStartOffset;
5409
5410 pShm->u32RM_VLCTableAddr = u32Addr;
5411 #endif
5412 }
5413 #endif
5414
5415 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5416 && (pCtrl->InitParams.pRVFileInfo != NULL))
5417 {
5418 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
5419 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
5420 }
5421
5422 //if(pCtrl->InitParams.bColocateBBUMode)
5423 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
5424 {
5425 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5426 }
5427
5428 #if SUPPORT_G2VP9
5429 // Enable SW detile support for G2 VP9
5430 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5431 {
5432 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
5433 }
5434 #endif
5435
5436 HAL_HVD_EX_FlushMemory();
5437
5438 return E_HVD_RETURN_SUCCESS;
5439 }
5440 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)5441 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
5442 #else
5443 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
5444 #endif
5445 {
5446 MS_BOOL bInitRet = FALSE;
5447
5448 #if 0
5449 // check MVD power on
5450 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
5451 {
5452 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
5453 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
5454 HVD_Delay_ms(1);
5455 }
5456 // Check VPU power on
5457 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
5458 {
5459 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
5460 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
5461 HVD_Delay_ms(1);
5462 }
5463 // check HVD power on
5464 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
5465 {
5466 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
5467 HAL_HVD_EX_PowerCtrl(TRUE);
5468 HVD_Delay_ms(1);
5469 }
5470 #endif
5471 #ifdef VDEC3
5472 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
5473 #else
5474 bInitRet = _HVD_EX_SetRegCPU(u32Id);
5475 #endif
5476 if (!bInitRet)
5477 {
5478 return E_HVD_RETURN_FAIL;
5479 }
5480
5481 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
5482
5483 if (!bInitRet)
5484 {
5485 return E_HVD_RETURN_FAIL;
5486 }
5487
5488 return E_HVD_RETURN_SUCCESS;
5489 }
5490
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)5491 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
5492 {
5493 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5494
5495 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
5496
5497 return E_HVD_RETURN_SUCCESS;
5498 }
5499
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)5500 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
5501 {
5502 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5503 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5504 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5505 MS_BOOL bMVC = FALSE;
5506 #if HVD_ENABLE_MVC
5507 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
5508 #endif
5509
5510 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5511 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
5512
5513 switch (u32type)
5514 {
5515 // share memory
5516 // switch
5517 case E_HVD_SDATA_FRAMEBUF_ADDR:
5518 {
5519 pShm->u32FrameBufAddr = u32Data;
5520 break;
5521 }
5522 case E_HVD_SDATA_FRAMEBUF_SIZE:
5523 {
5524 pShm->u32FrameBufSize = u32Data;
5525 break;
5526 }
5527 case E_HVD_SDATA_FRAMEBUF2_ADDR:
5528 {
5529 pShm->u32FrameBuf2Addr = u32Data;
5530 break;
5531 }
5532 case E_HVD_SDATA_FRAMEBUF2_SIZE:
5533 {
5534 pShm->u32FrameBuf2Size = u32Data;
5535 break;
5536 }
5537 case E_HVD_SDATA_MAX_CMA_SIZE:
5538 {
5539 pShm->u32MaxCMAFrameBufSize = u32Data;
5540 break;
5541 }
5542 case E_HVD_SDATA_MAX_CMA_SIZE2:
5543 {
5544 pShm->u32MaxCMAFrameBuf2Size = u32Data;
5545 break;
5546 }
5547 case E_HVD_SDATA_CMA_USED:
5548 {
5549 pShm->bCMA_Use = u32Data;
5550 break;
5551 }
5552 case E_HVD_SDATA_CMA_ALLOC_DONE:
5553 {
5554 pShm->bCMA_AllocDone = u32Data;
5555 break;
5556 }
5557 case E_HVD_SDATA_CMA_TWO_MIU:
5558 {
5559 pShm->bCMA_TwoMIU = u32Data;
5560 break;
5561 }
5562 case E_HVD_SDATA_RM_PICTURE_SIZES:
5563 {
5564 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
5565 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
5566 break;
5567 }
5568 case E_HVD_SDATA_ERROR_CODE:
5569 {
5570 pShm->u16ErrCode = (MS_U16) u32Data;
5571 break;
5572 }
5573 case E_HVD_SDATA_DISP_INFO_TH:
5574 {
5575 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
5576 sizeof(HVD_DISP_THRESHOLD));
5577 break;
5578 }
5579 case E_HVD_SDATA_FW_FLUSH_STATUS:
5580 {
5581 pShm->u8FlushStatus = (MS_U8)u32Data;
5582 break;
5583 }
5584 case E_HVD_SDATA_DMX_FRAMERATE:
5585 {
5586 pShm->u32DmxFrameRate = u32Data;
5587 break;
5588 }
5589 case E_HVD_SDATA_DMX_FRAMERATEBASE:
5590 {
5591 pShm->u32DmxFrameRateBase = u32Data;
5592 break;
5593 }
5594 case E_HVD_SDATA_MIU_SEL:
5595 {
5596 pShm->u32VDEC_MIU_SEL = u32Data;
5597 break;
5598 }
5599 case E_HVD_SDATA_DV_XC_SHM_SIZE:
5600 {
5601 pShm->u32DolbyVisionXCShmSize = u32Data;
5602 break;
5603 }
5604 // SRAM
5605
5606 // Mailbox
5607 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
5608 {
5609 if (u32Data != 0)
5610 {
5611 pShm->bEnableDispCtrl = TRUE;
5612 pShm->bIsTrigDisp = TRUE;
5613 }
5614 else
5615 {
5616 pShm->bEnableDispCtrl = FALSE;
5617 }
5618
5619 break;
5620 }
5621 case E_HVD_SDATA_GET_DISP_INFO_START:
5622 {
5623 pShm->bSpsChange = FALSE;
5624 break;
5625 }
5626 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
5627 {
5628 pShm->u32VirtualBoxWidth = u32Data;
5629 break;
5630 }
5631 case E_HVD_SDATA_DV_INFO:
5632 {
5633 MS_U8 u8DVLevel = u32Data & 0x00ff;
5634 MS_U8 u8DVProfile = (u32Data >> 8) & 0x00ff;
5635
5636 pShm->u8DVLevelFromDriverAPI = u8DVLevel;
5637 pShm->u8DVProfileFromDriverAPI = u8DVProfile;
5638 }
5639 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
5640 {
5641 pShm->u32VirtualBoxHeight = u32Data;
5642 break;
5643 }
5644 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
5645 {
5646 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
5647 {
5648 //HVD_PRINT("DispFrame DqPtr: %d\n", u32Data);
5649 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
5650 }
5651 break;
5652 }
5653 case E_HVD_SDATA_DISPQ_STATUS_DISP:
5654 {
5655 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
5656 {
5657 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
5658 {
5659 //HVD_PRINT("DispFrame DqPtr: %ld\n", u32Data);
5660 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
5661 }
5662 }
5663 break;
5664 }
5665 case E_HVD_SDATA_DISPQ_STATUS_FREE:
5666 {
5667 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5668 {
5669 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
5670 {
5671 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
5672 {
5673 //ALOGE("R1: %x", u32Data);
5674 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
5675 }
5676 else
5677 {
5678 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
5679 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
5680 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
5681 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
5682 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
5683 }
5684 }
5685 else
5686 {
5687 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
5688 }
5689 }
5690 else
5691 {
5692 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
5693 {
5694 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
5695 }
5696 }
5697 break;
5698 }
5699 #if 0//(HVD_ENABLE_IQMEM)
5700 case E_HVD_SDATA_FW_IQMEM_CTRL:
5701 {
5702 pShm->u8IQmemCtrl= (MS_U8)u32Data;
5703 break;
5704
5705 }
5706 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
5707 {
5708 if (u32Data != 0)
5709 {
5710 pShm->bIQmemEnableIfSupport= TRUE;
5711 }
5712 else
5713 {
5714 pShm->bIQmemEnableIfSupport= FALSE;
5715 }
5716
5717
5718 break;
5719
5720 }
5721 #endif
5722 case E_HVD_SDATA_DYNMC_DISP_PATH_STATUS:
5723 {
5724 pShm->stDynmcDispPath.u8ConnectStatus = u32Data;
5725 break;
5726 }
5727 case E_HVD_SDATA_VP9HDR10INFO:
5728 {
5729 int i,j;
5730 HVD_Config_VP9HDR10* stVP9HDR10Info = (HVD_Config_VP9HDR10*) u32Data;
5731
5732 pShm->VP9HDR10Info.u32Version = stVP9HDR10Info->u32Version;
5733 pShm->VP9HDR10Info.u8MatrixCoefficients = stVP9HDR10Info->u8MatrixCoefficients;
5734 pShm->VP9HDR10Info.u8BitsPerChannel = stVP9HDR10Info->u8BitsPerChannel;
5735 pShm->VP9HDR10Info.u8ChromaSubsamplingHorz = stVP9HDR10Info->u8ChromaSubsamplingHorz;
5736 pShm->VP9HDR10Info.u8ChromaSubsamplingVert = stVP9HDR10Info->u8ChromaSubsamplingVert;
5737 pShm->VP9HDR10Info.u8CbSubsamplingHorz = stVP9HDR10Info->u8CbSubsamplingHorz;
5738 pShm->VP9HDR10Info.u8CbSubsamplingVert = stVP9HDR10Info->u8CbSubsamplingVert;
5739 pShm->VP9HDR10Info.u8ChromaSitingHorz = stVP9HDR10Info->u8ChromaSitingHorz;
5740 pShm->VP9HDR10Info.u8ChromaSitingVert = stVP9HDR10Info->u8ChromaSitingVert;
5741 pShm->VP9HDR10Info.u8ColorRange = stVP9HDR10Info->u8ColorRange;
5742 pShm->VP9HDR10Info.u8TransferCharacteristics = stVP9HDR10Info->u8TransferCharacteristics;
5743 pShm->VP9HDR10Info.u8ColourPrimaries = stVP9HDR10Info->u8ColourPrimaries;
5744 pShm->VP9HDR10Info.u16MaxCLL = stVP9HDR10Info->u16MaxCLL;
5745 pShm->VP9HDR10Info.u16MaxFALL = stVP9HDR10Info->u16MaxFALL;
5746 pShm->VP9HDR10Info.u32MaxLuminance = stVP9HDR10Info->u32MaxLuminance;
5747 pShm->VP9HDR10Info.u32MinLuminance = stVP9HDR10Info->u32MinLuminance;
5748
5749 for(i=0;i<2;i++)
5750 {
5751 pShm->VP9HDR10Info.u16WhitePoint[i] = stVP9HDR10Info->u16WhitePoint[i];
5752 }
5753
5754 for(i=0;i<3;i++)
5755 {
5756 for(j=0;j<2;j++)
5757 {
5758 pShm->VP9HDR10Info.u16Primaries[i][j] = stVP9HDR10Info->u16Primaries[i][j];
5759 }
5760 }
5761 pShm->u8VP9HDR10InfoVaild = TRUE;
5762 break;
5763 }
5764 default:
5765 break;
5766 }
5767
5768 HAL_HVD_EX_FlushMemory();
5769
5770 return eRet;
5771 }
5772
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)5773 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
5774 {
5775 MS_S64 s64Ret = 0;
5776 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5777
5778 HAL_HVD_EX_ReadMemory();
5779
5780 switch (eType)
5781 {
5782 case E_HVD_GDATA_PTS_STC_DIFF:
5783 s64Ret = pShm->s64PtsStcDiff;
5784 break;
5785 case E_HVD_GDATA_TS_SEAMLESS_TARGET_PTS:
5786 s64Ret = (MS_S64)(pShm->u64SeamlessTargetPTS); //33bit PTS is compatible in S64
5787 break;
5788 default:
5789 break;
5790 }
5791
5792 return s64Ret;
5793 }
5794
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)5795 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
5796 {
5797 MS_VIRT u32Ret = 0;
5798 //static MS_U64 u64pts_real = 0;
5799 MS_U64 u64pts_low = 0;
5800 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5801 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5802
5803 HAL_HVD_EX_ReadMemory();
5804
5805 if(pShm == NULL)
5806 {
5807 HVD_PRINT("########## VDEC patch for Debug ###########\n");
5808 return 0x0;
5809 }
5810
5811 switch (eType)
5812 {
5813 // share memory
5814 // switch
5815 case E_HVD_GDATA_DISP_INFO_ADDR:
5816 {
5817 u32Ret = (MS_VIRT) (&pShm->DispInfo);
5818 break;
5819 }
5820 case E_HVD_GDATA_MIU_SEL:
5821 u32Ret = pShm->u32VDEC_MIU_SEL;
5822 break;
5823 case E_HVD_GDATA_FRAMEBUF_ADDR:
5824 u32Ret = pShm->u32FrameBufAddr;
5825 break;
5826 case E_HVD_GDATA_FRAMEBUF_SIZE:
5827 u32Ret = pShm->u32FrameBufSize;
5828 break;
5829 case E_HVD_GDATA_FRAMEBUF2_ADDR:
5830 u32Ret = pShm->u32FrameBuf2Addr;
5831 break;
5832 case E_HVD_GDATA_FRAMEBUF2_SIZE:
5833 u32Ret = pShm->u32FrameBuf2Size;
5834 break;
5835 case E_HVD_GDATA_CMA_ALLOC_DONE:
5836 u32Ret = pShm->bCMA_AllocDone;
5837 break;
5838 case E_HVD_GDATA_CMA_USED:
5839 u32Ret = pShm->bCMA_Use;
5840 break;
5841 case E_HVD_GDATA_DYNMC_DISP_PATH_STATUS:
5842 u32Ret = pShm->stDynmcDispPath.u8ConnectStatus;//pShm->u8SetDynmcDispPathStatus;
5843 break;
5844 // report
5845 case E_HVD_GDATA_PTS:
5846 {
5847 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
5848 break;
5849 }
5850 case E_HVD_GDATA_U64PTS:
5851 {
5852 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
5853 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
5854 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
5855 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
5856 break;
5857 }
5858 case E_HVD_GDATA_U64PTS_PRE_PARSE:
5859 {
5860 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
5861 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
5862 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
5863 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
5864 break;
5865 }
5866 case E_HVD_GDATA_DECODE_CNT:
5867 {
5868 u32Ret = pShm->u32DecodeCnt;
5869 break;
5870 }
5871 case E_HVD_GDATA_DATA_ERROR_CNT:
5872 {
5873 u32Ret = pShm->u32DataErrCnt;
5874 break;
5875 }
5876 case E_HVD_GDATA_DEC_ERROR_CNT:
5877 {
5878 u32Ret = pShm->u32DecErrCnt;
5879 break;
5880 }
5881 case E_HVD_GDATA_ERROR_CODE:
5882 {
5883 u32Ret = (MS_U32) (pShm->u16ErrCode);
5884 break;
5885 }
5886 case E_HVD_GDATA_VPU_IDLE_CNT:
5887 {
5888 u32Ret = pShm->u32VPUIdleCnt;
5889 break;
5890 }
5891 case E_HVD_GDATA_DISP_FRM_INFO:
5892 {
5893 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
5894 break;
5895 }
5896 case E_HVD_GDATA_DEC_FRM_INFO:
5897 {
5898 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
5899 break;
5900 }
5901 case E_HVD_GDATA_ES_LEVEL:
5902 {
5903 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
5904 break;
5905 }
5906 #if HVD_ENABLE_MVC
5907 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
5908 {
5909 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
5910 break;
5911 }
5912 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
5913 {
5914 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
5915 break;
5916 }
5917 #endif
5918
5919 // user data
5920 case E_HVD_GDATA_USERDATA_WPTR:
5921 {
5922 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
5923 break;
5924 }
5925 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
5926 {
5927 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
5928 break;
5929 }
5930 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
5931 {
5932 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
5933 break;
5934 }
5935 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
5936 {
5937 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
5938 break;
5939 }
5940 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
5941 {
5942 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
5943 break;
5944 }
5945 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
5946 {
5947 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
5948 break;
5949 }
5950 // report - modes
5951 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
5952 {
5953 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
5954 break;
5955 }
5956 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
5957 {
5958 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
5959 break;
5960 }
5961 case E_HVD_GDATA_IS_ERR_CONCEAL:
5962 {
5963 u32Ret = pShm->ModeStatus.bIsErrConceal;
5964 break;
5965 }
5966 case E_HVD_GDATA_IS_SYNC_ON:
5967 {
5968 u32Ret = pShm->ModeStatus.bIsSyncOn;
5969 break;
5970 }
5971 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
5972 {
5973 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
5974 break;
5975 }
5976 case E_HVD_GDATA_SYNC_MODE:
5977 {
5978 u32Ret = pShm->ModeStatus.u8SyncType;
5979 break;
5980 }
5981 case E_HVD_GDATA_SKIP_MODE:
5982 {
5983 u32Ret = pShm->ModeStatus.u8SkipMode;
5984 break;
5985 }
5986 case E_HVD_GDATA_DROP_MODE:
5987 {
5988 u32Ret = pShm->ModeStatus.u8DropMode;
5989 break;
5990 }
5991 case E_HVD_GDATA_DISPLAY_DURATION:
5992 {
5993 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
5994 break;
5995 }
5996 case E_HVD_GDATA_FRC_MODE:
5997 {
5998 u32Ret = pShm->ModeStatus.u8FrcMode;
5999 break;
6000 }
6001 case E_HVD_GDATA_NEXT_PTS:
6002 {
6003 u32Ret = pShm->u32NextPTS;
6004 break;
6005 }
6006 case E_HVD_GDATA_DISP_Q_SIZE:
6007 {
6008 u32Ret = pShm->u16DispQSize;
6009 break;
6010 }
6011 case E_HVD_GDATA_DISP_Q_PTR:
6012 {
6013 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
6014 break;
6015 }
6016 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
6017 {
6018 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
6019 break;
6020 }
6021 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
6022 {
6023 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
6024 break;
6025 }
6026 case E_HVD_GDATA_REAL_FRAMERATE:
6027 {
6028 // return VPS/VUI timing info framerate, and 0 if timing info not exist
6029 u32Ret = pShm->u32RealFrameRate;
6030 break;
6031 }
6032 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
6033 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
6034 break;
6035 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
6036 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
6037 break;
6038 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
6039 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
6040 break;
6041 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
6042 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
6043 break;
6044 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
6045 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
6046 break;
6047 case E_HVD_GDATA_FW_STATUS_FLAG:
6048 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
6049 break;
6050
6051 // internal control
6052 case E_HVD_GDATA_IS_1ST_FRM_RDY:
6053 {
6054 u32Ret = pShm->bIs1stFrameRdy;
6055 break;
6056 }
6057 case E_HVD_GDATA_IS_I_FRM_FOUND:
6058 {
6059 u32Ret = pShm->bIsIFrmFound;
6060 break;
6061 }
6062 case E_HVD_GDATA_IS_SYNC_START:
6063 {
6064 u32Ret = pShm->bIsSyncStart;
6065 break;
6066 }
6067 case E_HVD_GDATA_IS_SYNC_REACH:
6068 {
6069 u32Ret = pShm->bIsSyncReach;
6070 break;
6071 }
6072 case E_HVD_GDATA_FW_VERSION_ID:
6073 {
6074 u32Ret = pShm->u32FWVersionID;
6075 break;
6076 }
6077 case E_HVD_GDATA_FW_IF_VERSION_ID:
6078 {
6079 u32Ret = pShm->u32FWIfVersionID;
6080 break;
6081 }
6082 case E_HVD_GDATA_BBU_Q_NUMB:
6083 {
6084 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
6085 break;
6086 }
6087 case E_HVD_GDATA_DEC_Q_NUMB:
6088 {
6089 u32Ret = pShm->u16DecQNumb;
6090 break;
6091 }
6092 case E_HVD_GDATA_DISP_Q_NUMB:
6093 {
6094 u32Ret = pShm->u16DispQNumb;
6095 break;
6096 }
6097 case E_HVD_GDATA_PTS_Q_NUMB:
6098 {
6099 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
6100 break;
6101 }
6102 case E_HVD_GDATA_FW_INIT_DONE:
6103 {
6104 u32Ret = pShm->bInitDone;
6105 break;
6106 }
6107 // debug
6108 case E_HVD_GDATA_SKIP_CNT:
6109 {
6110 u32Ret = pShm->u32SkipCnt;
6111 break;
6112 }
6113 case E_HVD_GDATA_GOP_CNT:
6114 {
6115 u32Ret = pShm->u32DropCnt;
6116 break;
6117 }
6118 case E_HVD_GDATA_DISP_CNT:
6119 {
6120 u32Ret = pShm->u32DispCnt;
6121 break;
6122 }
6123 case E_HVD_GDATA_DROP_CNT:
6124 {
6125 u32Ret = pShm->u32DropCnt;
6126 break;
6127 }
6128 case E_HVD_GDATA_DISP_STC:
6129 {
6130 u32Ret = pShm->u32DispSTC;
6131 break;
6132 }
6133 case E_HVD_GDATA_VSYNC_CNT:
6134 {
6135 u32Ret = pShm->u32VsyncCnt;
6136 break;
6137 }
6138 case E_HVD_GDATA_MAIN_LOOP_CNT:
6139 {
6140 u32Ret = pShm->u32MainLoopCnt;
6141 break;
6142 }
6143
6144 // AVC
6145 case E_HVD_GDATA_AVC_LEVEL_IDC:
6146 {
6147 u32Ret = pShm->u16AVC_SPS_LevelIDC;
6148 break;
6149 }
6150 case E_HVD_GDATA_AVC_LOW_DELAY:
6151 {
6152 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
6153 break;
6154 }
6155 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
6156 {
6157 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
6158 break;
6159 }
6160 case E_HVD_GDATA_FW_FLUSH_STATUS:
6161 {
6162 u32Ret = (MS_U32) (pShm->u8FlushStatus);
6163 break;
6164 }
6165 case E_HVD_GDATA_FW_CODEC_TYPE:
6166 {
6167 u32Ret = pShm->u32CodecType;
6168 break;
6169 }
6170 case E_HVD_GDATA_FW_ES_BUF_STATUS:
6171 {
6172 u32Ret = (MS_U32)pShm->u8ESBufStatus;
6173 break;
6174 }
6175 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
6176 {
6177 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
6178 {
6179 u32Ret = 1;
6180 }
6181 else
6182 {
6183 u32Ret = 0;
6184 }
6185 break;
6186 }
6187
6188 // SRAM
6189
6190 // Mailbox
6191 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
6192 {
6193 u32Ret = pShm->u32FwState;
6194 break;
6195 }
6196 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
6197 {
6198 u32Ret = pShm->bSpsChange;
6199 break;
6200 }
6201 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
6202 {
6203 u32Ret = pShm->bSpsChange;
6204 #if SUPPORT_G2VP9 && defined(VDEC3)
6205 if (pShm->bSpsChange &&
6206 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
6207 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
6208 {
6209 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
6210 }
6211 #endif
6212 break;
6213 }
6214 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
6215 {
6216 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6217
6218 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
6219 {
6220 u32Ret = pShm->u32FwInfo;
6221 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
6222 }
6223 break;
6224 }
6225 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
6226 {
6227 if (pShm->bIsTrigDisp) // not clear yet
6228 {
6229 u32Ret = FALSE;
6230 }
6231 else
6232 {
6233 u32Ret = TRUE;
6234 }
6235 break;
6236 }
6237 case E_HVD_GDATA_ES_READ_PTR:
6238 {
6239 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
6240 break;
6241 }
6242 case E_HVD_GDATA_ES_WRITE_PTR:
6243 {
6244 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
6245 break;
6246 }
6247 case E_HVD_GDATA_BBU_READ_PTR:
6248 {
6249 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
6250 break;
6251 }
6252 case E_HVD_GDATA_BBU_WRITE_PTR:
6253 {
6254 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6255 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6256 {
6257 u32Ret = pHVDHalContext->u32VP8BBUWptr;
6258 }
6259 else
6260 {
6261 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
6262 }
6263 break;
6264 }
6265 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
6266 {
6267 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6268
6269 u32Ret = pCtrl->u32BBUWptr_Fired;
6270
6271 break;
6272 }
6273 case E_HVD_GDATA_VPU_PC_CNT:
6274 {
6275 u32Ret = _HVD_EX_GetPC();
6276 break;
6277 }
6278 case E_HVD_GDATA_ES_QUANTITY:
6279 {
6280 u32Ret=_HVD_EX_GetESQuantity(u32Id);
6281 break;
6282 }
6283
6284
6285 // FW def
6286 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
6287 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
6288 break;
6289
6290 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
6291 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
6292 break;
6293 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
6294 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
6295 break;
6296 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
6297 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
6298 break;
6299 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
6300 u32Ret = MAX_PTS_TABLE_SIZE;
6301 break;
6302 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
6303 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
6304 break;
6305 case E_HVD_GDATA_FW_DS_BUF_ADDR:
6306 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
6307 break;
6308 case E_HVD_GDATA_FW_DS_BUF_SIZE:
6309 u32Ret = pShm->u32DSBuffSize; //3k or 6k
6310 break;
6311 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
6312 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
6313 break;
6314 case E_HVD_GDATA_FW_DS_INFO_ADDR:
6315 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
6316 break;
6317 case E_HVD_GDATA_FW_DS_IS_ENABLED:
6318 {
6319 if (pShm->bDSIsRunning)
6320 {
6321 u32Ret = TRUE;
6322 }
6323 else
6324 {
6325 u32Ret = FALSE;
6326 }
6327 break;
6328 }
6329 #if 0//(HVD_ENABLE_IQMEM)
6330 case E_HVD_GDATA_FW_IQMEM_CTRL:
6331 {
6332
6333 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
6334
6335 break;
6336 }
6337 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
6338 {
6339 if(pShm->bIsIQMEMSupport){
6340 u32Ret = TRUE;
6341 }
6342 else{
6343
6344 u32Ret = FALSE;
6345 }
6346
6347 break;
6348 }
6349 #endif
6350 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
6351 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
6352 break;
6353 case E_HVD_GDATA_FIELD_PIC_FLAG:
6354 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
6355 break;
6356 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
6357 u32Ret = pShm->u32SeamlessTSStatus;
6358 break;
6359 case E_HVD_GDATA_TS_SEAMLESS_TARGET_POC:
6360 u32Ret = pShm->u32SeamlessTargetPOC;
6361 break;
6362 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
6363 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
6364 break;
6365 #ifdef VDEC3
6366 case E_HVD_GDATA_FW_VBBU_ADDR:
6367 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
6368 break;
6369 #endif
6370 case E_HVD_GDATA_SEQ_CHANGE_INFO:
6371 u32Ret = (MS_U32)pShm->u32SeqChangeInfo;
6372 break;
6373 case E_HVD_GDATA_GET_NOT_SUPPORT_INFO:
6374 u32Ret = pShm->u32NotSupportInfo;
6375 break;
6376 case E_HVD_GDATA_GET_MIN_TSP_DATA_SIZE:
6377 u32Ret = pShm->u32CurMinTspDataSize;
6378 break;
6379 default:
6380 break;
6381 }
6382 return u32Ret;
6383 }
6384
HAL_HVD_EX_Get_DV_Support_Profiles(void)6385 MS_U32 HAL_HVD_EX_Get_DV_Support_Profiles(void)
6386 {
6387 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
6388 }
6389
HAL_HVD_EX_Get_DV_Support_Highest_Level(DV_Stream_Profile pDV_Stream_Profile)6390 DV_Stream_Level HAL_HVD_EX_Get_DV_Support_Highest_Level(DV_Stream_Profile pDV_Stream_Profile)
6391 {
6392 switch (pDV_Stream_Profile)
6393 {
6394 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
6395 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
6396
6397 #if 0// unsupported profile
6398 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
6399 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
6400 #endif
6401
6402 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
6403 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
6404
6405 #if 0// unsupported profile
6406 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
6407 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
6408 #endif
6409
6410 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
6411 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
6412
6413 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
6414 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
6415
6416 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
6417 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
6418
6419 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
6420 default:
6421 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
6422 }
6423 }
6424
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)6425 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
6426 {
6427 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
6428 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
6429 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6430
6431 _HAL_HVD_Entry();
6432
6433 // check if old SVD cmds
6434 if (u32Cmd < E_HVD_CMD_SVD_BASE)
6435 {
6436 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
6437
6438 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
6439 }
6440
6441 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
6442 {
6443 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
6444 }
6445
6446 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
6447 {
6448 if (u32Cmd == E_HVD_CMD_FLUSH)
6449 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
6450 }
6451
6452 if (u32Cmd == E_HVD_CMD_FLUSH &&
6453 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
6454 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
6455 {
6456 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
6457 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
6458 {
6459 _HAL_HVD_Release();
6460 HVD_Delay_ms(1);
6461 _HAL_HVD_Entry();
6462 }
6463 }
6464
6465 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
6466
6467 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
6468
6469 _HAL_HVD_Return(eRet);
6470 }
6471
HAL_HVD_EX_DeInit(MS_U32 u32Id)6472 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
6473 {
6474 HVD_Return eRet = E_HVD_RETURN_FAIL;
6475 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6476 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6477 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
6478 MS_U8 u8MiuSel;
6479 MS_U32 u32StartOffset;
6480 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6481
6482 #if HVD_ENABLE_TIME_MEASURE
6483 MS_U32 ExitTimeCnt = 0;
6484 ExitTimeCnt = HVD_GetSysTime_ms();
6485 #endif
6486
6487 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
6488
6489 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
6490
6491 if (E_HVD_RETURN_SUCCESS != eRet)
6492 {
6493 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
6494 }
6495
6496 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
6497
6498 if (E_HVD_RETURN_SUCCESS != eRet)
6499 {
6500 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
6501 }
6502
6503 // check FW state to make sure it's STOP DONE
6504 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
6505 {
6506 if (HVD_GetSysTime_ms() > u32Timeout)
6507 {
6508 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
6509
6510 //return E_HVD_RETURN_TIMEOUT;
6511 eRet = E_HVD_RETURN_TIMEOUT;
6512 break;
6513 }
6514 }
6515
6516 if (pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt)
6517 {
6518 HVD_EX_MSG_INF("VDEC PLUS: DropRatio %d, Drop:0.%d (%d), Dec:0.%d (%d), Disp:0.%d\n",
6519 pShm->u8VdecPlusDropRatio,
6520 100*pShm->u32VdecPlusDropCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
6521 pShm->u32VdecPlusDropCnt,
6522 100*pShm->u32VdecPlusDecCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
6523 pShm->u32VdecPlusDecCnt,
6524 100*pShm->u32VdecPlusDispPicCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt));
6525 }
6526 else
6527 {
6528 HVD_EX_MSG_INF("VDEC PLUS DISABLE: DropRatio %d, Drop: %d, Dec: %d, Disp: %d\n",
6529 pShm->u8VdecPlusDropRatio,
6530 pShm->u32VdecPlusDropCnt,
6531 pShm->u32VdecPlusDecCnt,
6532 pShm->u32VdecPlusDispPicCnt);
6533 }
6534
6535 VPU_EX_FWCodeCfg fwCfg;
6536 VPU_EX_TaskInfo taskInfo;
6537 VPU_EX_NDecInitPara nDecInitPara;
6538
6539 nDecInitPara.pFWCodeCfg = &fwCfg;
6540 nDecInitPara.pTaskInfo = &taskInfo;
6541
6542 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
6543 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
6544
6545 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);//power control
6546 #if 0
6547 taskInfo.u32Id = u32Id;
6548 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
6549 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
6550 #endif
6551
6552 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6553 {
6554 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
6555 }
6556 else
6557 {
6558 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
6559 }
6560
6561 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
6562 {
6563 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
6564 }
6565
6566 /* clear es buffer */
6567 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
6568 {
6569 //HVD_PRINT("Clear ES buffer\n");
6570
6571 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
6572 }
6573
6574 //_HAL_HVD_MutexDelete();
6575
6576 #if HVD_ENABLE_TIME_MEASURE
6577 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
6578 #endif
6579
6580 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
6581 #ifndef VDEC3
6582 // reset bbu wptr
6583 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6584 {
6585 if(TRUE == HAL_VPU_EX_HVDInUsed())
6586 {
6587 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
6588 {
6589 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
6590 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
6591 }
6592 else
6593 {
6594 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
6595 {
6596 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
6597 }
6598 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
6599 }
6600 }
6601 else
6602 {
6603 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
6604 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
6605 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
6606 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6607 {
6608 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
6609 {
6610 _HVD_EX_ResetMainSubBBUWptr(u32Id);
6611 }
6612 }
6613 else
6614 {
6615 _HVD_EX_ResetMainSubBBUWptr(u32Id);
6616 }
6617 }
6618 }
6619 #endif
6620 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
6621
6622 #if SUPPORT_G2VP9 && defined(VDEC3)
6623 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
6624 {
6625 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
6626 }
6627 #endif
6628
6629 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
6630 {
6631
6632 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
6633
6634 _HAL_HVD_Entry();
6635 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
6636 _HAL_HVD_Release();
6637
6638 }
6639
6640 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
6641 HVD_EX_MSG_DBG("success\n");
6642
6643 return eRet;
6644 }
6645
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)6646 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
6647 {
6648 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
6649 MS_U32 u32Addr = 0;
6650 HVD_EX_Drv_Ctrl *pCtrl = NULL;
6651 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6652
6653 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6654
6655 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
6656 {
6657 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
6658
6659 if (E_HVD_RETURN_SUCCESS != eRet)
6660 {
6661 return eRet;
6662 }
6663 }
6664
6665 //HVD_PRINT(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
6666
6667 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
6668 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6669 {
6670 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
6671
6672 if (E_HVD_RETURN_SUCCESS != eRet)
6673 {
6674 return eRet;
6675 }
6676 }
6677
6678 u32Addr = pInfo->u32Staddr;
6679
6680 if (pInfo->bRVBrokenPacket)
6681 {
6682 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
6683 }
6684
6685 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
6686 {
6687 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
6688 }
6689 else
6690 {
6691 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
6692 }
6693
6694 if (E_HVD_RETURN_SUCCESS != eRet)
6695 {
6696 return eRet;
6697 }
6698
6699 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6700 {
6701 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
6702 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
6703
6704 if (E_HVD_RETURN_SUCCESS != eRet)
6705 {
6706 return eRet;
6707 }
6708 }
6709
6710 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
6711
6712 // do not add local pointer
6713 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
6714 {
6715 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
6716
6717 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
6718 (u32PacketStAddr <
6719 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
6720 {
6721 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
6722 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
6723 }
6724 else
6725 {
6726 //null packet
6727 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
6728 pCtrl->LastNal.u32NalSize = 0;
6729 }
6730 }
6731 else
6732 {
6733 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
6734 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
6735 }
6736
6737 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
6738 pCtrl->u32BBUPacketCnt++;
6739
6740 return eRet;
6741 }
6742
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)6743 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
6744 {
6745 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6746 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6747 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
6748 if(bCurrentStatus == bEnable)
6749 return;
6750
6751 if (bEnable)
6752 {
6753 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
6754 }
6755 else
6756 {
6757 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
6758 }
6759 }
6760
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)6761 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
6762 {
6763 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6764 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6765
6766 if (bEnable)
6767 {
6768 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
6769 }
6770 else
6771 {
6772 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
6773 }
6774 }
6775
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)6776 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
6777 {
6778 MS_U32 u32RB = 0;
6779 switch(eISRType)
6780 {
6781 case E_HWDEC_ISR_HVD:
6782 u32RB = REG_HVD_BASE;
6783 break;
6784 #if SUPPORT_EVD
6785 case E_HWDEC_ISR_EVD:
6786 u32RB = REG_EVD_BASE;
6787 break;
6788 #endif
6789 #if SUPPORT_G2VP9
6790 case E_HWDEC_ISR_G2VP9:
6791 break;
6792 #endif
6793 default:
6794 break;
6795 }
6796 if(u32RB)
6797 {
6798 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
6799 }
6800 }
6801
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)6802 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
6803 {
6804 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6805 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6806
6807 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
6808 }
6809
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)6810 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
6811 {
6812 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6813 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6814
6815 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
6816 {
6817 return FALSE;
6818 }
6819 else
6820 {
6821 return TRUE;
6822 }
6823 }
6824
HAL_HVD_EX_IsAlive(MS_U32 u32Id)6825 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
6826 {
6827 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6828
6829 if (pCtrl)
6830 {
6831 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
6832 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
6833 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
6834 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
6835 {
6836 return FALSE;
6837 }
6838 else
6839 {
6840 return TRUE;
6841 }
6842 }
6843 else
6844 {
6845 return FALSE;
6846 }
6847 }
6848
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)6849 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
6850 {
6851 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6852 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6853 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6854
6855 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6856 {
6857 HAL_HVD_EX_ReadMemory();
6858
6859 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
6860 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
6861
6862 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
6863 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
6864 }
6865
6866 return TRUE;
6867 }
6868
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)6869 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
6870 {
6871 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6872 HVD_EX_Drv_Ctrl *pCtrl = NULL;
6873 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6874 MS_U32 u32Data;
6875 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6876
6877 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
6878
6879 HAL_HVD_EX_FlushMemory();
6880 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
6881 {
6882 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
6883 pCtrl->LastNal.u32NalAddr = u32Data;
6884 pCtrl->LastNal.u32NalSize = 0;
6885 }
6886
6887 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
6888 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
6889
6890 return TRUE;
6891 }
6892
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)6893 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
6894 {
6895 if (bEnable)
6896 {
6897 if (HAL_VPU_EX_IsEVDR2())
6898 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6899 else
6900 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
6901 }
6902 else
6903 {
6904 #if defined (__aeon__)
6905 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6906 #else // defined (__mips__)
6907 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
6908 #endif
6909 }
6910 }
6911
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)6912 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
6913 {
6914 return 0;
6915 }
6916
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)6917 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
6918 {
6919 return;
6920 }
6921
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)6922 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
6923 {
6924 //if( u16Clock == 0 )
6925 return 216; //140;
6926 //if( )
6927 }
6928
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)6929 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
6930 {
6931 //MS_BOOL bBitMIU1 = FALSE;
6932 //MS_BOOL bCodeMIU1 = FALSE;
6933 MS_U8 u8BitMiuSel = 0;
6934 MS_U8 u8CodeMiuSel = 0;
6935 MS_U32 u32BitStartOffset;
6936 MS_U32 u32CodeStartOffset;
6937 //MS_U8 u8MiuSel;
6938 //MS_U32 u32StartOffset;
6939 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6940 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6941 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6942 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
6943
6944 #if HVD_ENABLE_MVC
6945 if(HAL_HVD_EX_CheckMVCID(u32Id))
6946 {
6947 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
6948 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
6949 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
6950 {
6951 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
6952 }
6953 }
6954 #endif /// HVD_ENABLE_MVC
6955
6956 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6957 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6958
6959
6960
6961
6962 if (u8BitMiuSel != u8CodeMiuSel)
6963 {
6964 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
6965 BDMA_Result bdmaRlt;
6966 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6967
6968 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6969 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
6970 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6971
6972 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
6973
6974 if (E_BDMA_OK != bdmaRlt)
6975 {
6976 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
6977 }
6978 #else
6979 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6980
6981 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6982 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
6983 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6984
6985 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
6986 #endif
6987 }
6988
6989 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
6990
6991 HAL_HVD_EX_FlushMemory();
6992
6993 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6994 {
6995 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
6996 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
6997 }
6998 else
6999 {
7000 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
7001
7002 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
7003 }
7004 }
7005
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)7006 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
7007 {
7008 if (bEnable)
7009 {
7010 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
7011 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
7012 }
7013 else
7014 {
7015 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
7016 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
7017 }
7018 }
7019
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)7020 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
7021 {
7022 MS_U32 tmp1 = 0;
7023 MS_U32 tmp2 = 0;
7024 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7025
7026 HAL_HVD_EX_ReadMemory();
7027
7028 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
7029 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
7030
7031 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
7032 {
7033 MS_U32 u32Tmp = u32UartCtrl;
7034
7035 HVD_EX_MSG_DBG("\n");
7036 u32UartCtrl = 0; // turn off debug message to prevent other function prints
7037 HVD_PRINT("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
7038 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
7039
7040 HVD_PRINT("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
7041 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
7042 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
7043 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
7044
7045 HVD_PRINT("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
7046 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
7047 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
7048
7049 HVD_PRINT("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
7050 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
7051 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
7052 _HVD_EX_GetESLevel(u32Id));
7053
7054 HVD_PRINT("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
7055 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
7056 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
7057 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
7058 HVD_PRINT
7059 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
7060 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
7061 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
7062 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
7063 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
7064 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
7065 pShm->ModeStatus.bShowOneField);
7066
7067 u32UartCtrl = u32Tmp; // recover debug level
7068 }
7069 }
7070
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)7071 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
7072 {
7073 MS_U8 *u32Addr = NULL;
7074 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7075 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7076
7077 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
7078 {
7079 return;
7080 }
7081
7082 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
7083
7084 *u32NalSize = *(u32Addr + 2) & 0x1f;
7085 *u32NalSize <<= 8;
7086 *u32NalSize |= *(u32Addr + 1) & 0xff;
7087 *u32NalSize <<= 8;
7088 *u32NalSize |= *(u32Addr) & 0xff;
7089
7090 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
7091 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
7092 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
7093 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
7094 }
7095
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)7096 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
7097 {
7098 MS_U32 u32CurIdx = 0;
7099 MS_BOOL bFinished = FALSE;
7100 MS_U32 u32NalOffset = 0;
7101 MS_U32 u32NalSize = 0;
7102 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7103
7104 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
7105 {
7106 return;
7107 }
7108
7109 u32CurIdx = u32StartIdx;
7110
7111 do
7112 {
7113 if (u32CurIdx == u32EndIdx)
7114 {
7115 bFinished = TRUE;
7116 }
7117
7118 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
7119
7120 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
7121 {
7122 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
7123 }
7124
7125 u32CurIdx++;
7126
7127 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
7128 {
7129 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
7130 }
7131 } while (bFinished == TRUE);
7132 }
7133
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)7134 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
7135 {
7136 MS_U32 i = 0;
7137 MS_U32 value = 0;
7138
7139 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
7140 {
7141 HVD_EX_MSG_DBG("\n");
7142
7143 for (i = 0; i <= u32Num; i++)
7144 {
7145 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
7146 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
7147 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
7148
7149 if (value == 0)
7150 {
7151 break;
7152 }
7153
7154 HVD_PRINT(" %08x", value);
7155
7156 if (((i % 8) + 1) == 8)
7157 {
7158 HVD_PRINT(" |%u\n", i + 1);
7159 }
7160 }
7161
7162 HVD_PRINT("\nHVD Dump HW status End: total number:%u\n", i);
7163 }
7164 }
7165
HAL_HVD_EX_GetDVSupportProfiles(void)7166 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
7167 {
7168 #if 0 // wait avc finish DV dual job
7169 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
7170 #else
7171 return E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
7172 #endif
7173 }
7174
7175
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)7176 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
7177 {
7178 switch (u32DV_Stream_Profile)
7179 {
7180 #if 0 // wait avc finish DV dual job
7181 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
7182 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
7183 #endif
7184
7185 #if 0 // unsupported profile
7186 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
7187 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
7188 #endif
7189
7190 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
7191 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
7192
7193 #if 0 // unsupported profile
7194 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
7195 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
7196 #endif
7197
7198 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
7199 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
7200
7201 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
7202 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
7203
7204 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
7205 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
7206
7207 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
7208 default:
7209 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
7210 }
7211 }
7212
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)7213 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
7214 {
7215 if (pDrvCtrl)
7216 {
7217 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
7218 }
7219 }
7220
7221 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)7222 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
7223 {
7224 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
7225 }
7226
HAL_HVD_EX_GetView(MS_U32 u32Id)7227 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
7228 {
7229 if( (0xFF & (u32Id >> 8)) == 0x10)
7230 return E_VDEC_EX_MAIN_VIEW;
7231 else
7232 return E_VDEC_EX_SUB_VIEW;
7233 }
7234 #endif ///HVD_ENABLE_MVC
7235
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)7236 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
7237 {
7238 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
7239 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
7240 return;
7241 }
7242
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)7243 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
7244 {
7245 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
7246 return;
7247 }
7248
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)7249 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
7250 {
7251 MS_U64 _hw_max_pixel = 0;
7252 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
7253
7254 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
7255 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
7256 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
7257 }
7258
7259
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)7260 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
7261 {
7262 #if 1
7263 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7264 MS_U16 u16QNum = pShm->u16DispQNumb;
7265 MS_U16 u16QPtr = pShm->u16DispQPtr;
7266 // MS_U16 u16QSize = pShm->u16DispQSize;
7267 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
7268 MS_U32 u32DispQNum = 0;
7269 #if HVD_ENABLE_MVC
7270 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
7271
7272 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7273 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
7274
7275 if(bMVC || bDolbyVision)
7276 {
7277 #if 0
7278 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
7279 {
7280 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
7281 }
7282 #endif
7283
7284 //HVD_PRINT("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
7285 //search the next frame to display
7286 while (u16QNum > 0)
7287 {
7288 //HVD_PRINT("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
7289 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
7290 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
7291
7292 //HVD_PRINT("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
7293 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
7294 {
7295 /// For MVC. Output views after the pair of (base and depend) views were decoded.
7296 /// Check the depned view was initial when Output the base view.
7297 if((u16QPtr%2) == 0)
7298 {
7299 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
7300 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
7301 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
7302 {
7303 ///HVD_PRINT("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
7304 ///HVD_PRINT("Return NULL.\n");
7305 continue;
7306 }
7307 }
7308 u32DispQNum++;
7309 }
7310
7311 u16QNum--;
7312 //go to next frame in the dispQ
7313 u16QPtr++;
7314
7315 if (u16QPtr >= pShm->u16DispQSize)
7316 {
7317 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
7318 }
7319 }
7320 }
7321 else
7322 #endif ///HVD_ENABLE_MVC
7323 {
7324 #if 0
7325 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
7326 {
7327 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
7328 }
7329 #endif
7330 // HVD_PRINT("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
7331 //search the next frame to display
7332 while (u16QNum != 0)
7333 {
7334 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
7335
7336 // HVD_PRINT("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
7337 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
7338 {
7339 u32DispQNum++;
7340 }
7341
7342 u16QNum--;
7343 //go to next frame in the dispQ
7344 u16QPtr++;
7345
7346 if (u16QPtr == pShm->u16DispQSize)
7347 {
7348 u16QPtr = 0; //wrap to the begin
7349 }
7350 }
7351 }
7352
7353 //HVD_PRINT("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
7354 return u32DispQNum;
7355 #else
7356 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
7357 return pShm->u16DispQNumb;
7358 #endif
7359 }
7360
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)7361 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
7362 {
7363 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7364 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
7365 (u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
7366 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
7367 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
7368 #if SUPPORT_G2VP9 && defined(VDEC3)
7369 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
7370 #else // Not using G2 VP9 implies using Mstar EVD VP9
7371 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
7372 #endif
7373 else
7374 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
7375 }
7376
7377 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)7378 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
7379 {
7380 #ifdef CONFIG_MSTAR_CLKM
7381 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD, bEnable);
7382 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_PPU, bEnable);
7383 #else
7384 if (bEnable)
7385 {
7386 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
7387 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
7388 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
7389 }
7390 else
7391 {
7392 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
7393 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
7394 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
7395 }
7396
7397 switch (pHVDHalContext->u32EVDClockType)
7398 {
7399 case 576:
7400 {
7401 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
7402 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
7403 break;
7404 }
7405 case 532:
7406 {
7407 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
7408 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
7409 break;
7410 }
7411 case 456:
7412 {
7413 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
7414 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
7415 _HVD_WriteWordMask(REG_EVDPLL_LOOP_DIV_SECOND, REG_EVDPLL_LOOP_DIV_SECOND_456MHZ, REG_EVDPLL_LOOP_DIV_SECOND_MASK);
7416 }
7417 case 466:
7418 {
7419 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
7420 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
7421 break;
7422 }
7423 case 480:
7424 {
7425 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
7426 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
7427 break;
7428 }
7429 case 384:
7430 {
7431 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
7432 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
7433 break;
7434 }
7435 case 320:
7436 {
7437 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
7438 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
7439 break;
7440 }
7441 case 240:
7442 {
7443 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
7444 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
7445 break;
7446 }
7447 case 192:
7448 {
7449 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
7450 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
7451 break;
7452 }
7453 default:
7454 {
7455 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
7456 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
7457 break;
7458 }
7459 }
7460 #endif
7461 #ifdef CONFIG_MSTAR_SRAMPD
7462 if (bEnable)
7463 {
7464 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
7465 HVD_Delay_ms(1);
7466 }
7467 else
7468 {
7469 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
7470 HVD_Delay_ms(1);
7471 }
7472 #endif
7473 return;
7474 }
7475
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)7476 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
7477 {
7478 #ifndef VDEC3
7479 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
7480 #endif
7481 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7482
7483 #ifdef VDEC3
7484 if (0 == pCtrl->u32BBUId)
7485 #else
7486 if (0 == u8TaskId)
7487 #endif
7488 {
7489 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
7490 }
7491 #ifdef VDEC3
7492 else if (1 == pCtrl->u32BBUId)
7493 #else
7494 else if (1 == u8TaskId)
7495 #endif
7496 {
7497 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
7498 }
7499 #ifdef VDEC3
7500 else if (2 == pCtrl->u32BBUId)
7501 #else
7502 else if (2 == u8TaskId)
7503 #endif
7504 {
7505 _HVD_Write2Byte(EVD_BBU23_SETTING, (_HVD_Read2Byte(EVD_BBU23_SETTING) & ~REG_TSP2EVD_EN_BS3)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for bbu3-DTV mode
7506 }
7507 else
7508 {
7509 #ifdef VDEC3
7510 if (pCtrl->u32BBUId > 3)
7511 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
7512 #else
7513 if (u8TaskId > 3)
7514 HVD_PRINT("Error u8TaskId = %d , %s:%d\n",u8TaskId,__FUNCTION__,__LINE__);
7515 #endif
7516 _HVD_Write2Byte(EVD_BBU23_SETTING, (_HVD_Read2Byte(EVD_BBU23_SETTING) & ~REG_TSP2EVD_EN_BS4)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for bbu4-DTV mode
7517 }
7518 return;
7519 }
7520
HAL_EVD_EX_DeinitHW(MS_U32 u32Id)7521 MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id)
7522 {
7523 MS_U16 u16Timeout = 1000;
7524 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7525 MS_BOOL isVP8Used = FALSE;
7526 MS_BOOL isAECUsed = FALSE;
7527 MS_BOOL isAVCUsed = FALSE;
7528 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
7529
7530 if(TRUE == HAL_VPU_EX_EVDInUsed())
7531 {
7532 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
7533 {
7534 HAL_AEC_PowerCtrl(FALSE);
7535 }
7536 return FALSE;
7537 }
7538 else if(!isAVCUsed)
7539 {
7540 _HVD_EX_SetMIUProtectMask(TRUE);
7541 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
7542
7543 while (u16Timeout)
7544 {
7545 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
7546 {
7547 break;
7548 }
7549 u16Timeout--;
7550 }
7551 #ifdef CONFIG_MSTAR_CLKM
7552 HAL_EVD_EX_PowerCtrl_CLKM(u32Id, FALSE);
7553 #else
7554 HAL_EVD_EX_PowerCtrl(u32Id, FALSE);
7555 #endif
7556
7557 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
7558 {
7559 HAL_AEC_PowerCtrl(FALSE);
7560 }
7561
7562 _HVD_EX_SetMIUProtectMask(FALSE);
7563 return TRUE;
7564 }
7565
7566 return FALSE;
7567 }
7568 #endif
7569
7570 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)7571 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
7572 {
7573 if (bEnable)
7574 {
7575 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
7576 }
7577 else
7578 {
7579 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
7580 }
7581
7582 switch (pHVDHalContext->u32VP9ClockType)
7583 {
7584 case 432:
7585 {
7586 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
7587 break;
7588 }
7589 case 384:
7590 {
7591 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
7592 break;
7593 }
7594 case 345:
7595 {
7596 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
7597 break;
7598 }
7599 case 320:
7600 {
7601 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
7602 break;
7603 }
7604 case 288:
7605 {
7606 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
7607 break;
7608 }
7609 case 240:
7610 {
7611 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
7612 break;
7613 }
7614 case 216:
7615 {
7616 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
7617 break;
7618 }
7619 case 172:
7620 {
7621 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
7622 break;
7623 }
7624 default:
7625 {
7626 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
7627 break;
7628 }
7629 }
7630
7631 return;
7632 }
7633
HAL_VP9_EX_DeinitHW(void)7634 MS_BOOL HAL_VP9_EX_DeinitHW(void)
7635 {
7636 MS_U16 u16Timeout = 1000;
7637
7638 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
7639
7640 while (u16Timeout)
7641 {
7642 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
7643 {
7644 break;
7645 }
7646 u16Timeout--;
7647 }
7648
7649 HAL_VP9_EX_PowerCtrl(FALSE);
7650
7651 return TRUE;
7652 }
7653 #endif
7654
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)7655 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
7656 {
7657 return TRUE;
7658 }
7659
HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)7660 void HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)
7661 {
7662 MS_VIRT u32StAddr = 0;
7663 MS_U8 u8BitMiuSel = 0;
7664 MS_U8 u8CodeMiuSel = 0;
7665 MS_U8 u8TmpMiuSel = 0;
7666 MS_U32 u32BitStartOffset;
7667 MS_U32 u32CodeStartOffset;
7668
7669 #ifndef VDEC3
7670 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
7671 #endif
7672 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7673 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7674 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
7675 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7676
7677 _HAL_HVD_Entry();
7678
7679 if (pCtrl == NULL)
7680 {
7681 _HAL_HVD_Return();
7682 }
7683
7684 MS_BOOL bNalTblAlreadySet = FALSE;
7685 VPU_EX_TaskInfo taskInfo;
7686 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
7687 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
7688
7689 bNalTblAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
7690
7691
7692
7693 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
7694 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
7695
7696 if (u8BitMiuSel != u8CodeMiuSel)
7697 {
7698 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
7699 }
7700 else
7701 {
7702 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
7703 }
7704
7705 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
7706 {
7707 #ifdef VDEC3
7708 if (!_HAL_EX_BBU_VP8_InUsed())
7709 #endif
7710 {
7711 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
7712
7713 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
7714 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
7715 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7716
7717 u32StAddr += VP8_BBU_TBL_SIZE;
7718
7719 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
7720 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
7721 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7722 }
7723
7724 _HAL_HVD_Return();
7725 }
7726
7727 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
7728
7729 #ifdef VDEC3
7730 if (!bNalTblAlreadySet)
7731 {
7732 _HVD_Write2Byte(_HVD_EX_Get_NAL_TBL_ST_ADDR_L(u32Id), (MS_U16) (u32StAddr >> 3));
7733 _HVD_Write2Byte(_HVD_EX_Get_NAL_TBL_ST_ADDR_H(u32Id), (MS_U16) (u32StAddr >> 19));
7734 // -1 is for NAL_TAB_LEN counts from zero.
7735 _HVD_Write2Byte(_HVD_EX_Get_NAL_TAB_LEN(u32Id), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7736 }
7737 #else
7738 if (0 == u8TaskId)
7739 {
7740 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
7741 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
7742 // -1 is for NAL_TAB_LEN counts from zero.
7743 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7744 }
7745 else
7746 {
7747 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
7748 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
7749 // -1 is for NAL_TAB_LEN counts from zero.
7750 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7751 }
7752 #endif
7753
7754
7755 #if (HVD_ENABLE_MVC)
7756 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
7757 {
7758 /// Used sub stream to record sub view data.
7759 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
7760 //HVD_PRINT("**************** Buffer setting for MVC dual-BBU *************\n");
7761
7762 if (u8BitMiuSel != u8CodeMiuSel)
7763 {
7764 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
7765 }
7766 else
7767 {
7768 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
7769 }
7770
7771 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
7772 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
7773 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
7774 // -1 is for NAL_TAB_LEN counts from zero.
7775 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
7776 }
7777 #endif
7778
7779 if (!bNalTblAlreadySet)
7780 {
7781 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
7782 }
7783
7784 _HAL_HVD_Return();
7785 }
7786
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)7787 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
7788 {
7789 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7790
7791 if(pCtrl->InitParams.u16ChipECONum == 0)
7792 return FALSE;
7793 else
7794 return TRUE;
7795 }
7796
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)7797 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
7798 {
7799
7800 }
7801
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)7802 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
7803 {
7804
7805 }
7806 #endif
7807