1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126 #define RV_VLC_TABLE_SIZE 0x20000
127 /* Add for Mobile Platform by Ted Sun */
128 //#define HVD_DISPQ_PREFETCH_COUNT 2
129 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
130 #define VPU_QMEM_BASE 0x20000000UL
131
132 //max support pixel(by chip capacity)
133 #define HVD_HW_MAX_PIXEL (3840*2160*31000ULL) // 4kx2k@30p
134 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
135 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
136
137 #if 0
138 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
139 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
140 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
141 static MS_U16 _u16DispQPtr = 0;
142 #endif
143
144 #define IS_TASK_ALIVE(id) ((id) != -1)
145 #ifndef UNUSED
146 #define UNUSED(x) (void)(x)
147 #endif
148
149
150 //---------------------------------- Mutex settings -----------------------------------------
151 #if HAL_HVD_ENABLE_MUTEX_PROTECT
152 #define _HAL_HVD_MutexCreate() \
153 do \
154 { \
155 if (s32HVDMutexID < 0) \
156 { \
157 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
158 } \
159 } while (0)
160
161 #define _HAL_HVD_MutexDelete() \
162 do \
163 { \
164 if (s32HVDMutexID >= 0) \
165 { \
166 OSAL_HVD_MutexDelete(s32HVDMutexID); \
167 s32HVDMutexID = -1; \
168 } \
169 } while (0)
170
171 #define _HAL_HVD_Entry() \
172 do \
173 { \
174 if (s32HVDMutexID >= 0) \
175 { \
176 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
177 { \
178 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
179 } \
180 } \
181 } while (0)
182
183 #define _HAL_HVD_Return(_ret_) \
184 do \
185 { \
186 if (s32HVDMutexID >= 0) \
187 { \
188 OSAL_HVD_MutexRelease(s32HVDMutexID); \
189 } \
190 return _ret_; \
191 } while(0)
192
193 #define _HAL_HVD_Release() \
194 do \
195 { \
196 if (s32HVDMutexID >= 0) \
197 { \
198 OSAL_HVD_MutexRelease(s32HVDMutexID); \
199 } \
200 } while (0)
201 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
202
203 #define _HAL_HVD_MutexCreate()
204 #define _HAL_HVD_MutexDelete()
205 #define _HAL_HVD_Entry()
206 #define _HAL_HVD_Return(_ret) {return _ret;}
207 #define _HAL_HVD_Release()
208
209 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
210
211 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
212 #define IS_TASK_ALIVE(id) ((id) != -1)
213 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
214
215 //------------------------------ MIU SETTINGS ----------------------------------
216 #define _MaskMiuReq_MVD_RW_0( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
217 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
218 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
222
223 #define _MaskMiu1Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
224 #define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
225 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
226 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
227 #define _MaskMiu1Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(3))
228 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(0))
229
230 #define _MaskMiu2Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU2_REG_RQ2_MASK, m, BIT(4))
231 #define _MaskMiu2Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(6))
232 #define _MaskMiu2Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(4))
233 #define _MaskMiu2Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(2))
234 #define _MaskMiu2Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(3))
235 #define _MaskMiu2Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(0))
236
237
238 #define HVD_MVD_RW_0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == 0))
239 #define HVD_MVD_RW_1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == 0))
240 #define HVD_MVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == 0))
241 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == 0))
242 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == 0))
243 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == 0))
244
245 #define HVD_MVD_RW_0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == BIT(4)) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == 0))
246 #define HVD_MVD_RW_1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == 0))
247 #define HVD_MVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12)) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == 0))
248 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == 0))
249 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == 0))
250 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == 0))
251
252 #define HVD_MVD_RW_0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == BIT(4)))
253 #define HVD_MVD_RW_1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == BIT(6)))
254 #define HVD_MVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == BIT(12)))
255 #define HVD_HVD_RW_MIF0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == BIT(2)))
256 #define HVD_HVD_RW_MIF1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == BIT(3)))
257 #define HVD_HVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == BIT(0)))
258
259
260 #if SUPPORT_EVD
261 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
262 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
263 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
264 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
265 #define _MaskMiu2Req_EVD_RW( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
266 #define _MaskMiu2Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
267
268
269
270
271 #define HVD_EVD_RW_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
272 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
273 #define HVD_EVD_RW_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
274 #define HVD_EVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
275 #define HVD_EVD_RW_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == BIT(7)))
276 #define HVD_EVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == BIT(7)))
277 #endif
278
279 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
280 do \
281 { \
282 if (HVD_##miu_clients##_ON_MIU0 == 1) \
283 { \
284 _MaskMiuReq_##miu_clients(mask); \
285 } \
286 else \
287 { \
288 if (HVD_##miu_clients##_ON_MIU1 == 1) \
289 { \
290 _MaskMiu1Req_##miu_clients(mask); \
291 } \
292 else if (HVD_##miu_clients##_ON_MIU2 == 1) \
293 { \
294 _MaskMiu2Req_##miu_clients(mask); \
295 } \
296 } \
297 } while (0)
298
299 // check RM is supported or not
300 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
301 #ifdef VDEC3
302 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
303 #else
304 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
305 #endif
306
307 #define DIFF(a, b) (a > b ? (a-b) : (b-a)) // abs diff
308
309 //-------------------------------------------------------------------------------------------------
310 // Local Structures
311 //-------------------------------------------------------------------------------------------------
312
313 //-------------------------------------------------------------------------------------------------
314 // Local Functions Prototype
315 //-------------------------------------------------------------------------------------------------
316 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
317 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
318 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
319 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
320 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
321 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
322 static MS_U32 _HVD_EX_GetPC(void);
323 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
324 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
325 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
326 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
327 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
328 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
329 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
330 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
331 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
332 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
333 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
334 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
335 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
336 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
337 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
338 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
339 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
340 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed, MS_BOOL *isAVCUsed);
341 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable);
342 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable);
343 #if SUPPORT_EVD
344 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable);
345 #endif
346 #if SUPPORT_G2VP9 && defined(VDEC3)
347 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
348 #endif
349 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
350 #if SUPPORT_G2VP9 && defined(VDEC3)
351 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
352 #endif
353
354 //-------------------------------------------------------------------------------------------------
355 // Global Variables
356 //-------------------------------------------------------------------------------------------------
357 #if defined (__aeon__)
358 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
359 #else
360 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
361 #endif
362 #if HAL_HVD_ENABLE_MUTEX_PROTECT
363 MS_S32 s32HVDMutexID = -1;
364 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
365 #endif
366
367
368 #define HVD_EX_STACK_SIZE 4096
369 //-------------------------------------------------------------------------------------------------
370 // Local Variables
371 //-------------------------------------------------------------------------------------------------
372 typedef struct
373 {
374
375 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
376 MS_U8 g_hvd_nal_fill_pair[2][8];
377 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
378 MS_U16 _u16DispQPtr;
379 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
380
381 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
382 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
383 MS_U32 u32VPUClockType;
384 MS_U32 u32HVDClockType;//160
385 #if SUPPORT_EVD
386 MS_U32 u32EVDClockType;
387 #endif
388 #if SUPPORT_G2VP9 && defined(VDEC3)
389 MS_U32 u32VP9ClockType;
390 #endif
391 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
392
393 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
394 MS_BOOL g_RstFlag;
395 MS_U64 u64pts_real;
396 MS_PHY u32VP8BBUWptr;
397 MS_PHY u32EVDBBUWptr;
398 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
399 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
400 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
401 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
402 //pre_set
403 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
404 } HVD_Hal_CTX;
405
406 HVD_Hal_CTX* pHVDHalContext = NULL;
407 HVD_Hal_CTX gHVDHalContext;
408 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
409
410 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
411 {
412 {FALSE},
413 {FALSE},
414 {FALSE},
415 #ifdef VDEC3
416 {FALSE},
417 #endif
418 };
419
420 //-------------------------------------------------------------------------------------------------
421 // Debug Functions
422 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)423 void HVD_EX_SetRstFlag(MS_BOOL bRst)
424 {
425 pHVDHalContext->g_RstFlag = bRst;
426 }
HVD_EX_GetRstFlag(void)427 MS_BOOL HVD_EX_GetRstFlag(void)
428 {
429 return pHVDHalContext->g_RstFlag;
430 }
431
432 //-------------------------------------------------------------------------------------------------
433 // Local Functions
434 //-------------------------------------------------------------------------------------------------
435 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)436 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
437 {
438 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
439
440 if (u32CodecType == E_HVD_INIT_HW_HEVC || u32CodecType == E_HVD_INIT_HW_HEVC_DV
441 #if SUPPORT_MSVP9
442 || u32CodecType == E_HVD_INIT_HW_VP9
443 #endif
444 )
445 return TRUE;
446
447 return FALSE;
448 }
449
_HAL_EX_BBU_VP8_InUsed(void)450 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
451 {
452 if (!pHVDHalContext)
453 return FALSE;
454
455 MS_U32 i;
456 MS_BOOL bRet = FALSE;
457
458 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
459 {
460 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
461 {
462 bRet = TRUE;
463 break;
464 }
465 }
466
467 return bRet;
468 }
469
470 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
471 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)472 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
473 {
474
475 MS_U32 ret = TRUE;
476 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
477
478 if(pCtrl == NULL || pstTaskInfo == NULL)
479 return FALSE;
480
481 pstTaskInfo->u32Id = u32Id;
482
483 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
484 {
485 case E_HVD_INIT_HW_RM:
486 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
487 break;
488 case E_HVD_INIT_HW_VP8:
489 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
490 break;
491 case E_HVD_INIT_HW_MVC:
492 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
493 break;
494 case E_HVD_INIT_HW_HEVC:
495 case E_HVD_INIT_HW_HEVC_DV:
496 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
497 break;
498 #if SUPPORT_MSVP9
499 case E_HVD_INIT_HW_VP9:
500 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
501 break;
502 #endif
503 #if SUPPORT_G2VP9
504 case E_HVD_INIT_HW_VP9:
505 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
506 break;
507 #endif
508 default:
509 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
510 break;
511 }
512
513 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
514
515 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
516 {
517 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
518 }
519 else
520 {
521 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
522 }
523
524 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
525
526 #ifdef SUPPORT_EVD
527 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
528 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
529 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
530 #endif
531 return ret;
532
533 }
534
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)535 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
536 {
537 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
538 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
539 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
540 _HAL_HVD_Entry();
541
542 if(pCtrl == NULL)
543 _HAL_HVD_Return(ret);
544
545 VPU_EX_TaskInfo taskInfo;
546 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
547
548 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
549
550 taskInfo.u8HalId = u8Idx;
551 ret = HAL_VPU_EX_GetBBUId(u32Id, &taskInfo, pCtrl->bShareBBU);
552
553 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
554 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
555
556 _HAL_HVD_Return(ret);
557 }
558
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)559 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
560 {
561 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
562 MS_BOOL ret = FALSE;
563 _HAL_HVD_Entry();
564
565 if(pCtrl == NULL)
566 _HAL_HVD_Return(ret);
567 VPU_EX_TaskInfo taskInfo;
568 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
569
570 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
571
572 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
573
574 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
575 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
576
577 _HAL_HVD_Return(ret);
578 }
579
HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId)580 MS_BOOL HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId)
581 {
582 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
583 MS_BOOL ret = FALSE;
584 _HAL_HVD_Entry();
585
586 if(pCtrl == NULL)
587 _HAL_HVD_Return(ret);
588 VPU_EX_TaskInfo taskInfo;
589 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
590
591 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
592
593 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, taskInfo.eDecType);
594
595 _HAL_HVD_Return(TRUE);
596 }
597 #endif
598
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)599 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
600 {
601 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
602 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
603 pstHVDStream->s32HvdPpTaskId = -1;
604 }
605
_HVD_EX_Context_Init_HAL(void)606 static void _HVD_EX_Context_Init_HAL(void)
607 {
608 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
609 pHVDHalContext->u32VPUClockType = 432;
610 pHVDHalContext->u32HVDClockType = 384;
611 #if SUPPORT_EVD
612 pHVDHalContext->u32EVDClockType = 480;
613 #endif
614 #if SUPPORT_G2VP9 && defined(VDEC3)
615 pHVDHalContext->u32VP9ClockType = 384;
616 #endif
617 #ifdef VDEC3
618 MS_U8 i;
619
620 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
621 {
622 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
623 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
624 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
625 }
626 #else
627 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
628 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
629 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
630 #endif
631 }
632
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)633 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
634 {
635 MS_U16 u16Ret = 0;
636 #if (HVD_ENABLE_MVC || (!VDEC3))
637 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
638 #endif
639 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
640 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
641 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
642 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
643
644 #if HVD_ENABLE_MVC
645 if(HAL_HVD_EX_CheckMVCID(u32Id))
646 {
647 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
648 }
649 #endif /// HVD_ENABLE_MVC
650
651 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
652 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
653
654 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
655 {
656 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
657 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
658 }
659 else
660 #ifdef VDEC3
661 if (0 == pCtrl->u32BBUId)
662 #else
663 if (0 == u8TaskId)
664 #endif
665 {
666 //if(pCtrl->InitParams.bColocateBBUMode)
667 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
668 u16Ret = pShm->u32ColocateBBUReadPtr;
669 else
670 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
671 }
672 else
673 {
674 //if(pCtrl->InitParams.bColocateBBUMode)
675 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
676 u16Ret = pShm->u32ColocateBBUReadPtr;
677 else
678 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
679 }
680
681 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
682 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
683
684 return u16Ret;
685 }
686
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)687 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
688 {
689 MS_U16 u16Ret = 0;
690 #if (HVD_ENABLE_MVC || (!VDEC3))
691 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
692 #endif
693 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
694 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
695 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
696 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
697
698 #if HVD_ENABLE_MVC
699 if (HAL_HVD_EX_CheckMVCID(u32Id))
700 {
701 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
702 }
703 #endif /// HVD_ENABLE_MVC
704 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
705 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
706
707 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
708 {
709 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
710 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
711 }
712 else
713 #ifdef VDEC3
714 if (0 == pDrvCtrl->u32BBUId)
715 #else
716 if (0 == u8TaskId)
717 #endif
718 {
719 //if(pDrvCtrl->InitParams.bColocateBBUMode)
720 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
721 u16Ret = pShm->u32ColocateBBUWritePtr;
722 else
723 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
724 }
725 else
726 {
727 //if(pDrvCtrl->InitParams.bColocateBBUMode)
728 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
729 u16Ret = pShm->u32ColocateBBUWritePtr;
730 else
731 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
732 }
733
734 return u16Ret;
735 }
736
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)737 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
738 {
739 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
740 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
741
742 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
743 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
744 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
745 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
746 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
747 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
748 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
749 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
750 }
751
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)752 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
753 {
754 #if (HVD_ENABLE_MVC || (!VDEC3))
755 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
756 #endif
757 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
758 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
759 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
760 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
761
762 #if HVD_ENABLE_MVC
763 if (HAL_HVD_EX_CheckMVCID(u32Id))
764 {
765 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
766 }
767 #endif /// HVD_ENABLE_MVC
768
769 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
770 {
771 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
772 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
773 }
774 else
775 #ifdef VDEC3
776 if (0 == pCtrl->u32BBUId)
777 #else
778 if (0 == u8TaskId)
779 #endif
780 {
781 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
782 //if(pCtrl->InitParams.bColocateBBUMode)
783 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
784 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
785 }
786 else
787 {
788 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
789 //if(pCtrl->InitParams.bColocateBBUMode)
790 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
791 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
792 }
793
794 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
795 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
796
797 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
798 }
799
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)800 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
801 {
802 MS_BOOL bResult = TRUE;
803 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
804 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
805
806 switch (u8MBox)
807 {
808 case E_HVD_HI_0:
809 {
810 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
811 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
812 break;
813 }
814 case E_HVD_HI_1:
815 {
816 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
817 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
818 break;
819 }
820 case E_HVD_VPU_HI_0:
821 {
822 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
823 break;
824 }
825 case E_HVD_VPU_HI_1:
826 {
827 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
828 break;
829 }
830 default:
831 {
832 bResult = FALSE;
833 break;
834 }
835 }
836
837 return bResult;
838 }
839
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)840 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
841 {
842 MS_BOOL bResult = TRUE;
843 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
844 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
845
846 switch (u8MBox)
847 {
848 case E_HVD_HI_0:
849 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
850 break;
851 case E_HVD_HI_1:
852 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
853 break;
854 case E_HVD_RISC_0:
855 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
856 break;
857 case E_HVD_RISC_1:
858 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
859 break;
860 case E_HVD_VPU_HI_0:
861 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
862 break;
863 case E_HVD_VPU_HI_1:
864 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
865 break;
866 case E_HVD_VPU_RISC_0:
867 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
868 break;
869 case E_HVD_VPU_RISC_1:
870 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
871 break;
872 default:
873 break;
874 }
875
876 return bResult;
877 }
878
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)879 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
880 {
881 MS_BOOL bResult = TRUE;
882 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
883 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
884
885 switch (u8MBox)
886 {
887 case E_HVD_HI_0:
888 {
889 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
890 break;
891 }
892 case E_HVD_HI_1:
893 {
894 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
895 break;
896 }
897 case E_HVD_RISC_0:
898 {
899 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
900 break;
901 }
902 case E_HVD_RISC_1:
903 {
904 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
905 break;
906 }
907 case E_HVD_VPU_RISC_0:
908 {
909 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
910 break;
911 }
912 case E_HVD_VPU_RISC_1:
913 {
914 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
915 break;
916 }
917 default:
918 {
919 bResult = FALSE;
920 break;
921 }
922 }
923
924 return bResult;
925 }
926
927 #if 0
928 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
929 {
930 switch (u8MBox)
931 {
932 case E_HVD_RISC_0:
933 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
934 break;
935 case E_HVD_RISC_1:
936 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
937 break;
938 case E_HVD_VPU_RISC_0:
939 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
940 break;
941 case E_HVD_VPU_RISC_1:
942 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
943 break;
944 default:
945 break;
946 }
947 }
948 #endif
949
_HVD_EX_GetPC(void)950 static MS_U32 _HVD_EX_GetPC(void)
951 {
952 MS_U32 u32PC = 0;
953 u32PC = HAL_VPU_EX_GetProgCnt();
954 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
955 return u32PC;
956 }
957
_HVD_EX_GetESWritePtr(MS_U32 u32Id)958 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
959 {
960 MS_U32 u32Data = 0;
961 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
962 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
963
964 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
965 {
966 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
967
968 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
969 {
970 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
971
972 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
973 }
974 }
975 else
976 {
977 #if HVD_ENABLE_MVC
978 MS_U8 u8ViewIdx = 0;
979 if(HAL_HVD_EX_CheckMVCID(u32Id))
980 {
981 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
982 }
983 if(u8ViewIdx != 0) /// 2nd ES ptr.
984 {
985 u32Data = pShm->u32ES2WritePtr;
986 }
987 else
988 {
989 u32Data = pShm->u32ESWritePtr;
990 }
991 #else
992 u32Data = pShm->u32ESWritePtr;
993 #endif
994 }
995
996 return u32Data;
997 }
998
999 #define NAL_UNIT_LEN_BITS 21
1000 #define NAL_UNIT_OFT_BITS 30
1001 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
1002 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
1003 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
1004
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)1005 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
1006 {
1007 MS_U32 u32Data = 0;
1008 MS_U8 u8TaskId = 0;
1009 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1010 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1011 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1012 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1013 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
1014
1015 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1016 #if HVD_ENABLE_MVC
1017 if(HAL_HVD_EX_CheckMVCID(u32Id))
1018 {
1019 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1020 }
1021 #endif /// HVD_ENABLE_MVC
1022
1023 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
1024 {
1025 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
1026 {
1027 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1028 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
1029 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
1030 MS_U32 *u32Adr;
1031 MS_U32 u32Tmp;
1032
1033 if (u16ReadPtr == u16WritePtr)
1034 {
1035 u32Data = _HVD_EX_GetESWritePtr(u32Id);
1036 }
1037 else
1038 {
1039 if (u16ReadPtr)
1040 u16ReadPtr--;
1041 else
1042 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
1043
1044 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
1045
1046 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
1047 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
1048 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
1049 u32Data = u32Data | u32Tmp;
1050
1051 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
1052 //while(1);
1053 }
1054 goto EXIT;
1055 }
1056 // set reg_poll_nal_rptr 0
1057 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
1058 // set reg_poll_nal_rptr 1
1059 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
1060
1061 // read reg_nal_rptr_hi
1062 #ifdef VDEC3
1063 if (0 == pCtrl->u32BBUId)
1064 #else
1065 if (0 == u8TaskId)
1066 #endif
1067 {
1068 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
1069 u32Data >>= 6;
1070 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
1071 }
1072 else
1073 {
1074 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
1075 u32Data >>= 6;
1076 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
1077 }
1078
1079 u32Data <<= 3; // unit
1080
1081 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1082 {
1083 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1084
1085 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1086 {
1087 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1088 u32Data = u32ESWptr;
1089 }
1090 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1091 {
1092 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1093 u32Data = u32ESWptr;
1094 }
1095 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1096 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1097 {
1098 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1099 u32Data = u32ESWptr;
1100 }
1101 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1102 && ((u32Data - u32ESWptr) < 32)
1103 && (pCtrl->u32FlushRstPtr == 1))
1104 {
1105 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1106 u32Data = u32ESWptr;
1107 }
1108 }
1109
1110 // remove illegal pointer
1111 #if 1
1112 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1113 {
1114 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1115
1116 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1117 (u32PacketStaddr <
1118 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1119 {
1120 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1121 u32Data = pCtrl->u32LastESRptr;
1122 }
1123 }
1124 #endif
1125 }
1126 else
1127 {
1128 #if HVD_ENABLE_MVC
1129 MS_U8 u8ViewIdx = 0;
1130 if(HAL_HVD_EX_CheckMVCID(u32Id))
1131 {
1132 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1133 }
1134 if(u8ViewIdx != 0) /// 2nd ES ptr.
1135 {
1136 u32Data = pShm->u32ES2ReadPtr;
1137 }
1138 else
1139 {
1140 u32Data = pShm->u32ESReadPtr;
1141 }
1142 #else
1143 u32Data = pShm->u32ESReadPtr;
1144 #endif
1145 }
1146
1147 EXIT:
1148
1149 pCtrl->u32LastESRptr = u32Data;
1150
1151 return u32Data;
1152 }
1153
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1154 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1155 {
1156 MS_U16 u16TimeOut = 0xFFFF;
1157 MS_BOOL bResult = FALSE;
1158
1159 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
1160
1161 while (--u16TimeOut)
1162 {
1163 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1164 {
1165 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1166 break;
1167 }
1168 }
1169
1170 return bResult;
1171 }
1172
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1173 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1174 {
1175 MS_U16 u16TimeOut = 0xFFFF;
1176 MS_BOOL bResult = FALSE;
1177 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1178
1179 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
1180
1181 #if HVD_ENABLE_MVC
1182 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1183 {
1184 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1185 }
1186 #endif /// HVD_ENABLE_MVC
1187
1188 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1189
1190 while (--u16TimeOut)
1191 {
1192 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1193 {
1194 u32Cmd |= (u8TaskId << 24);
1195 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1196 break;
1197 }
1198 }
1199 return bResult;
1200 }
1201
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)1202 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
1203 {
1204 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1205 #ifdef VDEC3
1206 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1207 MS_BOOL IsSent = FALSE;
1208 MS_BOOL IsMailBox = FALSE;
1209 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1210
1211 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
1212 {
1213 do {
1214 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1215 if (!SentRet)
1216 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1217 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1218 break;
1219 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1220 IsSent = TRUE;
1221 break;
1222 }
1223 else if (HVD_GetSysTime_ms() > u32timeout)
1224 {
1225 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1226 break;
1227 }
1228 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1229 }
1230 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
1231 {
1232 do {
1233 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1234 if (!SentRet)
1235 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1236 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1237 break;
1238 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1239 IsSent = TRUE;
1240 break;
1241 }
1242 else if (HVD_GetSysTime_ms() > u32timeout)
1243 {
1244 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1245 break;
1246 }
1247 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1248 }
1249 if (!IsSent)
1250 {
1251 IsMailBox = TRUE;
1252 u32timeout = HVD_GetSysTime_ms() + HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT;//pHVDHalContext->u32HVDCmdTimeout;
1253 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1254 #else
1255 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1256 #endif
1257 {
1258 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1259 if (HVD_GetSysTime_ms() > u32timeout)
1260 {
1261 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1262 return E_HVD_RETURN_TIMEOUT;
1263 }
1264 //#endif
1265
1266 #if 0
1267 if (u32Cmd == E_HVD_CMD_STOP)
1268 {
1269 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1270 #if HVD_ENABLE_MVC
1271 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1272 {
1273 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1274 }
1275 #endif /// HVD_ENABLE_MVC
1276 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1277
1278 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1279 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1280
1281 return E_HVD_RETURN_SUCCESS;
1282 }
1283 #endif
1284
1285 if(u32Cmd < E_DUAL_CMD_BASE)
1286 {
1287 //_HVD_EX_GetPC();
1288 HAL_HVD_EX_Dump_FW_Status(u32Id);
1289 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1290 }
1291 }
1292
1293 #ifdef VDEC3
1294 }
1295 IsSent = FALSE;
1296 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1297 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
1298 {
1299 do {
1300 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1301 if (!SentRet)
1302 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1303 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1304 break;
1305 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1306 IsSent = TRUE;
1307 break;
1308 }
1309 else if (HVD_GetSysTime_ms() > u32timeout)
1310 {
1311 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1312 break;
1313 }
1314 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1315 }
1316 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
1317 {
1318 do {
1319 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1320 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1321 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1322 }
1323 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1324 break;
1325 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1326 IsSent = TRUE;
1327 break;
1328 }
1329 else if (HVD_GetSysTime_ms() > u32timeout)
1330 {
1331 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1332 break;
1333 }
1334 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1335 }
1336 if (!IsSent)
1337 {
1338 u32timeout = HVD_GetSysTime_ms() + HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT;//pHVDHalContext->u32HVDCmdTimeout;
1339 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1340 #else
1341 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1342
1343 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1344 #endif
1345 {
1346 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1347 if (HVD_GetSysTime_ms() > u32timeout)
1348 {
1349 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
1350 return E_HVD_RETURN_TIMEOUT;
1351 }
1352 //#endif
1353 if(u32Cmd < E_DUAL_CMD_BASE)
1354 {
1355 //_HVD_EX_GetPC();
1356 HAL_HVD_EX_Dump_FW_Status(u32Id);
1357 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1358 }
1359 }
1360 #ifdef VDEC3
1361 }
1362 else
1363 {
1364 HAL_HVD_EX_FlushMemory();
1365 }
1366 #endif
1367 return E_HVD_RETURN_SUCCESS;
1368 }
1369
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)1370 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
1371 {
1372 #if HAL_HVD_ENABLE_MIU_PROTECT
1373 _HVD_MIU_SetReqMask(MVD_RW_0, bEnable);
1374 _HVD_MIU_SetReqMask(MVD_RW_1, bEnable);
1375 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1376 #if SUPPORT_EVD
1377 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
1378 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1379 #endif
1380 _HVD_MIU_SetReqMask(HVD_RW_MIF0, bEnable);
1381 _HVD_MIU_SetReqMask(HVD_RW_MIF1, bEnable);
1382 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1383 HAL_VPU_EX_MIU_RW_Protect(bEnable);
1384 //HVD_Delay_ms(1);
1385 #endif
1386 return;
1387 }
1388
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1389 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1390 {
1391 MS_U16 u16Reg = 0;
1392 MS_VIRT u32StAddr = 0;
1393 #ifdef VDEC3
1394 MS_U32 u32Length = 0;
1395 #endif
1396 MS_U8 u8BitMiuSel = 0;
1397 MS_U8 u8CodeMiuSel = 0;
1398 MS_U8 u8FBMiuSel = 0;
1399 MS_U8 u8TmpMiuSel = 0;
1400 MS_U32 u32BitStartOffset;
1401 MS_U32 u32CodeStartOffset;
1402 MS_U32 u32FBStartOffset;
1403
1404 #ifndef VDEC3
1405 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1406 #endif
1407 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1408 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1409 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1410
1411 _HAL_HVD_Entry();
1412
1413 if (pCtrl == NULL)
1414 {
1415 _HAL_HVD_Return();
1416 }
1417
1418 MS_BOOL bESBufferAlreadySet = FALSE;
1419 VPU_EX_TaskInfo taskInfo;
1420 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1421
1422 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
1423
1424 bESBufferAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
1425
1426
1427
1428 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1429 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1430 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1431
1432 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1433 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1434 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1435 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1436 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1437 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1438 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1439 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1440 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1441 (u8FBMiuSel << VDEC_PPIN_MIUSEL) |
1442 (u8FBMiuSel << VDEC_XCSHM_MIUSEL));
1443
1444 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1445 {
1446 // ES buffer
1447 #ifdef VDEC3
1448 if(pCtrl->bShareBBU)
1449 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1450 else
1451 #endif
1452 u32StAddr = u32BitStartOffset;
1453
1454 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1455
1456 #ifdef VDEC3
1457 if (!_HAL_EX_BBU_VP8_InUsed())
1458 #endif
1459 {
1460 HVD_EX_MSG_ERR("ESB start addr=%lx\n", (unsigned long)u32StAddr);
1461
1462 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1463 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1464
1465 #ifdef VDEC3
1466 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1467 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1468 #else
1469 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1470 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1471 #endif
1472
1473 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1474 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1475 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1476 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1477 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1478 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1479 }
1480
1481 _HAL_HVD_Return();
1482 }
1483
1484 // ES buffer
1485 #ifdef VDEC3
1486 if(!pCtrl->bShareBBU || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1487 {
1488 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1489 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1490 }
1491 else
1492 {
1493 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1494 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1495 }
1496 #else
1497 u32StAddr = u32BitStartOffset;
1498 #endif
1499
1500 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1501
1502 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1503
1504 #ifdef VDEC3
1505 if (!bESBufferAlreadySet)
1506 {
1507 if (pCtrl->u32BBUId == 0)
1508 {
1509 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1510 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1511
1512 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1513 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1514 }
1515 else
1516 {
1517 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1518 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1519
1520 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1521 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1522 }
1523 }
1524 #else
1525 if (0 == u8TaskId)
1526 {
1527 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1528 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1529
1530 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1531 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1532 }
1533 else
1534 {
1535 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1536 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1537
1538 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1539 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1540 }
1541 #endif
1542
1543 // others
1544 #ifdef VDEC3
1545 if (!bESBufferAlreadySet)
1546 {
1547 if (pCtrl->u32BBUId == 0)
1548 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1549 else
1550 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1551
1552 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1553 {
1554 if (pCtrl->u32BBUId == 0)
1555 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1556 else
1557 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1558 }
1559 else
1560 {
1561 if (pCtrl->u32BBUId == 0)
1562 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1563 else
1564 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1565 }
1566
1567 // do not set parsing setting in DRV, and we set it in FW (hvd_switch_bbu)
1568 if (pCtrl->u32BBUId == 0)
1569 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1570 else
1571 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1572
1573 if (pCtrl->u32BBUId == 0)
1574 {
1575 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1576 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1577 }
1578 else
1579 {
1580 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1581 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1582 }
1583 }
1584 #else
1585 if (0 == u8TaskId)
1586 {
1587 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1588
1589 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1590 {
1591 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1592 }
1593 else
1594 {
1595 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1596 }
1597
1598 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1599
1600 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1601 {
1602 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1603 }
1604 else // AVS or AVC
1605 {
1606 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1607 {
1608 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1609 }
1610 else // start code remained
1611 {
1612 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1613 }
1614 }
1615
1616 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1617
1618 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1619 }
1620 else
1621 {
1622 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1623
1624 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1625 {
1626 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1627 }
1628 else
1629 {
1630 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1631 }
1632
1633 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1634
1635 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1636 {
1637 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1638 }
1639 else // AVS or AVC
1640 {
1641 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1642 {
1643 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1644 }
1645 else // start code remained
1646 {
1647 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1648 }
1649 }
1650
1651 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1652
1653 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1654 }
1655 #endif
1656
1657 #if (HVD_ENABLE_MVC)
1658 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1659 {
1660 /// Used sub stream to record sub view data.
1661 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1662 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1663
1664 // ES buffer
1665 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1666
1667 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1668 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1669 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1670
1671 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1672 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1673
1674 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1675 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1676 {
1677 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1678 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1679 }
1680 else
1681 {
1682 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1683 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1684 }
1685 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1686 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1687 {
1688 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1689 }
1690 else // AVS or AVC
1691 {
1692 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1693 {
1694 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1695 }
1696 else // start code remained
1697 {
1698 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1699 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1700 }
1701 }
1702 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1703 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1704 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1705 }
1706 #endif
1707
1708 // MIF offset
1709 #if 0
1710 {
1711 MS_U16 offaddr = 0;
1712 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1713 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1714 {
1715 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1716 }
1717 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1718 offaddr = (MS_U16) ((u32StAddr) >> 20);
1719 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1720 //0x1FF; // 9 bits(L + H)
1721 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1722 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1723 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1724 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1725 {
1726 u16Reg |= HVD_REG_MIF_OFFSET_H;
1727 }
1728 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1729 }
1730 #endif
1731
1732 if (!bESBufferAlreadySet)
1733 {
1734 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
1735 }
1736
1737 _HAL_HVD_Return();
1738 }
1739
1740 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1741 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1742 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1743 {
1744 MS_U16 u16Reg = 0;
1745 MS_U32 u32StAddr = 0;
1746 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1747 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1748 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1749
1750 if(pCtrl == NULL) return;
1751
1752 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1753 {
1754 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1755
1756 // ES buffer
1757 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1758
1759 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1760 {
1761 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1762 }
1763
1764 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1765 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1766
1767 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1768 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1769
1770 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1771 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1772 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1773 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1774 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1775 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1776
1777 return;
1778 }
1779
1780 // ES buffer
1781 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1782
1783 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1784 {
1785 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1786 }
1787
1788 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1789
1790 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1791 {
1792 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1793 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1794
1795 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1796 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1797 }
1798 else
1799 {
1800 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1801 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1802
1803 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1804 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1805 }
1806 }
1807 #endif
1808
_HVD_EX_GetESLevel(MS_U32 u32Id)1809 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1810 {
1811 MS_U32 u32Wptr = 0;
1812 MS_U32 u32Rptr = 0;
1813 MS_U32 u32CurMBX = 0;
1814 MS_U32 u32ESsize = 0;
1815 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1816 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1817
1818 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1819 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1820 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1821
1822 if (u32Rptr >= u32Wptr)
1823 {
1824 u32CurMBX = u32Rptr - u32Wptr;
1825 }
1826 else
1827 {
1828 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1829 }
1830
1831 if (u32CurMBX == 0)
1832 {
1833 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1834 }
1835 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1836 {
1837 u32Ret = E_HVD_ESB_LEVEL_OVER;
1838 }
1839 else
1840 {
1841 u32CurMBX = u32ESsize - u32CurMBX;
1842 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1843 {
1844 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1845 }
1846 }
1847
1848 return u32Ret;
1849 }
1850
_HVD_EX_GetESQuantity(MS_U32 u32Id)1851 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1852 {
1853 MS_U32 u32Wptr = 0;
1854 MS_U32 u32Rptr = 0;
1855 MS_U32 u32ESsize = 0;
1856 MS_U32 u32Ret = 0;
1857 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1858
1859 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1860 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1861 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1862
1863
1864 if(u32Wptr >= u32Rptr)
1865 {
1866 u32Ret = u32Wptr - u32Rptr;
1867 }
1868 else
1869 {
1870 u32Ret = u32ESsize - u32Rptr + u32Wptr;
1871 }
1872 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
1873 return u32Ret;
1874 }
1875
1876 #if (HVD_ENABLE_IQMEM)
HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)1877 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
1878 {
1879
1880 MS_U32 u32Timeout = 20000;
1881
1882 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
1883 {
1884
1885 HAL_VPU_EX_IQMemSetDAMode(TRUE);
1886
1887 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
1888
1889
1890 while (u32Timeout)
1891 {
1892
1893 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
1894 {
1895 break;
1896 }
1897 u32Timeout--;
1898 HVD_Delay_ms(1);
1899 }
1900
1901 HAL_VPU_EX_IQMemSetDAMode(FALSE);
1902
1903 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
1904
1905 if (u32Timeout==0)
1906 {
1907 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
1908 return FALSE;
1909 }
1910
1911
1912 }
1913 return TRUE;
1914 }
1915
1916 #endif
1917
1918 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)1919 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
1920 #else
1921 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
1922 #endif
1923 {
1924 MS_U32 u32FirmVer = 0;
1925 MS_U32 u32Timeout = 20000;
1926 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1927
1928 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
1929
1930 #if HVD_ENABLE_TIME_MEASURE
1931 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
1932 #endif
1933
1934 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
1935
1936 VPU_EX_FWCodeCfg fwCfg;
1937 VPU_EX_TaskInfo taskInfo;
1938 VPU_EX_VLCTblCfg vlcCfg;
1939 #ifdef VDEC3
1940 VPU_EX_FBCfg fbCfg;
1941 #endif
1942 VPU_EX_NDecInitPara nDecInitPara;
1943
1944 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
1945 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1946 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
1947 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
1948 #ifdef VDEC3_FB
1949 nDecInitPara.pVLCCfg = NULL;
1950 #else
1951 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
1952 {
1953 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
1954 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
1955 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
1956 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
1957 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
1958 nDecInitPara.pVLCCfg = &vlcCfg;
1959 }
1960 #endif
1961 nDecInitPara.pFWCodeCfg = &fwCfg;
1962 nDecInitPara.pTaskInfo = &taskInfo;
1963 #ifdef VDEC3
1964 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
1965 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
1966
1967 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1968 {
1969 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1970 }
1971
1972 nDecInitPara.pFBCfg = &fbCfg;
1973 #endif
1974
1975 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
1976 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
1977 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
1978 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
1979 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
1980
1981 taskInfo.u32Id = u32Id;
1982
1983 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1984 {
1985 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
1986 }
1987 #ifdef VDEC3
1988 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
1989 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
1990 {
1991 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
1992 }
1993 #if SUPPORT_MSVP9
1994 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
1995 {
1996 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
1997 }
1998 #endif
1999 #if SUPPORT_G2VP9
2000 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2001 {
2002 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2003 }
2004 #endif
2005 #endif
2006 else
2007 {
2008 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2009 }
2010
2011 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2012
2013 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2014 {
2015 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2016 }
2017 else
2018 {
2019 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2020 }
2021 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2022
2023 #ifdef SUPPORT_EVD
2024 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2025 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2026 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2027 #endif
2028
2029 if(TRUE == HVD_EX_GetRstFlag())
2030 {
2031 //Delete task for Rst
2032 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2033 {
2034 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2035 }
2036 HVD_EX_SetRstFlag(FALSE);
2037 }
2038
2039 #if (HVD_ENABLE_IQMEM)
2040 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2041 #endif
2042
2043 #ifdef VDEC3
2044 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2045 #else
2046 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2047 #endif
2048 {
2049 HVD_EX_MSG_ERR("Task create fail!\n");
2050
2051 return FALSE;
2052 }
2053
2054 while (u32Timeout)
2055 {
2056 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2057
2058 if (u32FirmVer != 0)
2059 {
2060 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2061 break;
2062 }
2063 u32Timeout--;
2064 HVD_Delay_ms(1);
2065 }
2066
2067 #ifdef VDEC3_FB
2068 #if HVD_ENABLE_RV_FEATURE
2069 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2070
2071 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2072 {
2073 if(pShm->u32RM_VLCTableAddr == 0) {
2074 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2075 }
2076 else
2077 {
2078 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2079 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2080 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2081 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2082 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2083 nDecInitPara.pVLCCfg = &vlcCfg;
2084 }
2085 }
2086
2087 if (nDecInitPara.pVLCCfg)
2088 {
2089 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2090 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2091 {
2092 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2093 return FALSE;
2094 }
2095 }
2096 #endif
2097 #endif
2098 if (u32Timeout > 0)
2099 {
2100 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2101
2102 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2103
2104 #ifdef VDEC3
2105 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2106 {
2107 case E_HVD_INIT_HW_AVC:
2108 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2109 break;
2110 case E_HVD_INIT_HW_AVS:
2111 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2112 break;
2113 case E_HVD_INIT_HW_RM:
2114 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2115 break;
2116 case E_HVD_INIT_HW_MVC:
2117 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2118 break;
2119 case E_HVD_INIT_HW_VP8:
2120 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2121 break;
2122 case E_HVD_INIT_HW_MJPEG:
2123 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2124 break;
2125 case E_HVD_INIT_HW_VP6:
2126 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2127 break;
2128 case E_HVD_INIT_HW_HEVC:
2129 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2130 break;
2131 case E_HVD_INIT_HW_VP9:
2132 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2133 break;
2134 case E_HVD_INIT_HW_HEVC_DV:
2135 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC_DV;
2136 break;
2137 default:
2138 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2139 break;
2140 }
2141 #endif
2142
2143 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2144 }
2145 else
2146 {
2147 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2148 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2149
2150 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2151 {
2152 HVD_EX_MSG_ERR("Task delete fail!\n");
2153 }
2154
2155 return FALSE;
2156 }
2157
2158
2159
2160 #if (HVD_ENABLE_IQMEM)
2161
2162 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
2163 {
2164
2165 HAL_HVD_EX_IQMem_Init(u32Id);
2166 }
2167 else{
2168 HVD_EX_MSG_DBG("not support IQMEM\n");
2169 }
2170 #endif
2171
2172
2173
2174
2175
2176
2177 #if HVD_ENABLE_TIME_MEASURE
2178 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2179 #endif
2180
2181 return TRUE;
2182 }
2183
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2184 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2185 {
2186 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2187 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2188 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2189 {
2190 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2191 }
2192 else
2193 {
2194 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2195 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2196 }
2197 }
2198
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2199 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2200 {
2201 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2202 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2203
2204 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2205 {
2206 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2207 }
2208 else
2209 {
2210 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2211 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2212 }
2213 }
2214
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2215 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2216 {
2217 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2218 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2219
2220 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2221 {
2222 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2223 {
2224 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2225 }
2226 }
2227 else
2228 {
2229 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2230 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2231 }
2232 }
2233
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2234 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2235 {
2236 MS_VIRT u32PTSWptr = HVD_U32_MAX;
2237 MS_VIRT u32PTSRptr = HVD_U32_MAX;
2238 MS_VIRT u32DestAddr = 0;
2239 HVD_PTS_Entry PTSEntry;
2240 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2241 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2242 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2243
2244 // update R & W ptr
2245 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2246
2247 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
2248
2249 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2250 {
2251 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
2252 (MS_U32) MAX_PTS_TABLE_SIZE);
2253 return E_HVD_RETURN_FAIL;
2254 }
2255
2256 // check queue is full or not
2257 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2258 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2259
2260 if (u32PTSWptr == u32PTSRptr)
2261 {
2262 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
2263 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2264 return E_HVD_RETURN_FAIL;
2265 }
2266
2267 // add one PTS entry
2268 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2269 PTSEntry.u32ID_L = pInfo->u32ID_L;
2270 PTSEntry.u32ID_H = pInfo->u32ID_H;
2271 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2272
2273 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2274
2275 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
2276
2277 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2278
2279 HAL_HVD_EX_FlushMemory();
2280
2281 // update Write ptr
2282 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2283
2284 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2285
2286 return E_HVD_RETURN_SUCCESS;
2287 }
2288
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2289 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2290 {
2291 //---------------------------------------------------
2292 // item format in nal table:
2293 // reserved |borken| u32NalOffset | u32NalLen
2294 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2295 //---------------------------------------------------
2296 MS_VIRT u32Adr = 0;
2297 MS_U32 u32BBUNewWptr = 0;
2298 MS_U8 item[8];
2299 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2300 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2301 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2302 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2303
2304 #if HVD_ENABLE_MVC
2305 if(HAL_HVD_EX_CheckMVCID(u32Id))
2306 {
2307 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2308 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2309 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2310 {
2311 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2312 }
2313 }
2314 #endif /// HVD_ENABLE_MVC
2315
2316 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2317 {
2318 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
2319 }
2320 else
2321 {
2322 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2323 }
2324 u32BBUNewWptr++;
2325 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
2326
2327 // prepare nal entry
2328
2329 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
2330 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2331 {
2332 // NAL len 22 bits , HEVC level5 constrain
2333 item[0] = u32NalLen & 0xff;
2334 item[1] = (u32NalLen >> 8) & 0xff;
2335 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2336 item[3] = (u32NalOffset >> 2) & 0xff;
2337 item[4] = (u32NalOffset >> 10) & 0xff;
2338 item[5] = (u32NalOffset >> 18) & 0xff;
2339 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2340 item[7] = 0;
2341 }
2342 else
2343 {
2344 item[0] = u32NalLen & 0xff;
2345 item[1] = (u32NalLen >> 8) & 0xff;
2346 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2347 item[3] = (u32NalOffset >> 3) & 0xff;
2348 item[4] = (u32NalOffset >> 11) & 0xff;
2349 item[5] = (u32NalOffset >> 19) & 0xff;
2350 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2351 item[7] = 0;
2352 }
2353
2354 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2355 {
2356 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
2357 }
2358 else
2359 {
2360 // add nal entry
2361 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2362 }
2363
2364 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2365
2366 HAL_HVD_EX_FlushMemory();
2367
2368 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2369
2370 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2371 {
2372 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
2373 }
2374 else
2375 {
2376 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2377 }
2378
2379 return E_HVD_RETURN_SUCCESS;
2380 }
2381
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2382 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2383 {
2384 MS_U8 item[8];
2385 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2386 MS_VIRT u32Adr = 0;
2387 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2388 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2389 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2390
2391 /*
2392 printf("nal2 offset=0x%x, len=0x%x\n",
2393 u32NalOffset2, u32NalLen2);
2394 */
2395
2396 item[0] = u32NalLen2 & 0xff;
2397 item[1] = (u32NalLen2 >> 8) & 0xff;
2398 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2399 item[3] = (u32NalOffset2 >> 3) & 0xff;
2400 item[4] = (u32NalOffset2 >> 11) & 0xff;
2401 item[5] = (u32NalOffset2 >> 19) & 0xff;
2402 item[6] = (u32NalOffset2 >> 27) & 0x07;
2403 item[7] = 0;
2404
2405 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2406 {
2407 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
2408 }
2409 else
2410 {
2411 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2412 }
2413
2414 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2415
2416 HAL_HVD_EX_FlushMemory();
2417
2418 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2419 }
2420
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2421 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2422 {
2423 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2424 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2425
2426 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2427 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
2428 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
2429 {
2430 MS_U16 i;
2431 MS_PHY u32VUIAddr;
2432 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
2433
2434 HAL_HVD_EX_ReadMemory();
2435 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2436
2437 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2438 {
2439 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2440 {
2441 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2442 }
2443 else
2444 {
2445 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2446 }
2447 pData++;
2448 }
2449 }
2450 else
2451 {
2452 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2453 }
2454
2455 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
2456 }
2457
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2458 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2459 {
2460 MS_U32 u32ReadPtr = 0;
2461 MS_U32 eRet = 0;
2462 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2463 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2464
2465 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2466 MS_U32 u32WritePtr = 0;
2467
2468 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2469 {
2470 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
2471 }
2472 else
2473 {
2474 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2475 }
2476
2477 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
2478
2479 if (u32WritePtr >= u32ReadPtr)
2480 {
2481 eRet = u32WritePtr - u32ReadPtr;
2482 }
2483 else
2484 {
2485 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2486 }
2487
2488 #if 0
2489 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2490 {
2491 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2492 }
2493 else
2494 {
2495 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2496 }
2497
2498 #endif
2499 return eRet;
2500 }
2501
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2502 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2503 {
2504 MS_U32 u32ReadPtr = 0;
2505 MS_U32 eRet = 0;
2506 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2507
2508 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2509
2510 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2511 {
2512 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
2513 (MS_U32) MAX_PTS_TABLE_SIZE);
2514 return 0;
2515 }
2516
2517 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2518
2519 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2520 {
2521 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2522 }
2523 else
2524 {
2525 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2526 }
2527
2528 return eRet;
2529 }
2530
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)2531 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
2532 {
2533 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2534
2535 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
2536 }
2537
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2538 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2539 {
2540 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2541 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2542 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2543 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2544 HAL_HVD_EX_ReadMemory();
2545 MS_U16 u16QNum = pShm->u16DispQNumb;
2546 MS_U16 u16QPtr = pShm->u16DispQPtr;
2547
2548 HVD_Frm_Information *pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2549 if (bDolbyVision)
2550 {
2551 if (pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone && u16QNum < 4) // first time we need to wait 4 pic to ensure we got the correct layer type
2552 {
2553 return NULL;
2554 }
2555 else
2556 {
2557 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = FALSE;
2558 }
2559 }
2560
2561 #if (HVD_ENABLE_MVC)
2562 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2563 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
2564 {
2565 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2566 {
2567 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
2568 MS_U16 u16UsedFrm = 0;
2569 MS_U16 u16ResvFrmNum = ((u16RealQPtr % 2) == 0) ? 1 : 0; // need to check the next frame num is exist when get first frame.
2570 if (u16RealQPtr != u16QPtr)
2571 {
2572 if (u16RealQPtr > u16QPtr)
2573 {
2574 u16UsedFrm = u16RealQPtr - u16QPtr;
2575 }
2576 else
2577 {
2578 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2579 }
2580 }
2581
2582 if (u16QNum > (u16UsedFrm + u16ResvFrmNum))
2583 {
2584 u16QNum -= u16UsedFrm;
2585 u16QPtr = u16RealQPtr;
2586 pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2587
2588 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2589 {
2590 if ((u16QPtr % 2) == 0)
2591 {
2592 HVD_Frm_Information *pHvdFrmNext = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr + 1];
2593
2594 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2595 {
2596 return NULL;
2597 }
2598
2599 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2600 if(bDolbyVision)
2601 {
2602 HVD_PRINT("BL pts: %d, u16QPtr: %d, u16QNum:%d, uid:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2603 }
2604 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2605 }
2606 else
2607 {
2608 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2609 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
2610 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2611 HVD_Frm_Information *pHvdFrmPrv = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr - 1]; // must be odd
2612
2613 if(bDolbyVision)
2614 {
2615 HVD_PRINT("EL pts: %d, u16QPtr: %d, u16QNum:%d, uid:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2616 #if 0 // dump dolby metadata calculated by FW
2617 unsigned char *dump_addr = (unsigned char *)((void *)pShm + pShm->u32HVD_DBG_DUMP_ADDR - (u8Idx * 0x100000 + HVD_SHARE_MEM_ST_OFFSET));
2618 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2619 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2620 unsigned int i = 0;
2621 unsigned char arr[33] = {0};
2622 if(pVsyncBridgeExt != NULL)
2623 {
2624 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[u16QPtr]);
2625 }
2626 dump_addr += 32 * pFrmInfoExt->u8CurrentIndex;
2627 for (i = 0; i < 32; i++)
2628 {
2629 arr[i] = *(dump_addr + i);
2630 }
2631 HVD_PRINT("[md5]%02d=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x %02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x", (unsigned int)pFrmInfoExt->u8CurrentIndex, arr[0], arr[1], arr[2], arr[3], arr[4], arr[5], arr[6], arr[7], arr[8], arr[9], arr[10], arr[11], arr[12], arr[13], arr[14], arr[15], arr[16], arr[17], arr[18], arr[19], arr[20], arr[21], arr[22], arr[23], arr[24], arr[25], arr[26], arr[27], arr[28], arr[29], arr[30], arr[31]);
2632 #endif
2633 if(DIFF(pHvdFrmPrv->u32TimeStamp, pHvdFrm->u32TimeStamp) > 1000)
2634 HVD_EX_MSG_ERR("BL pts: %d, EL pts: %d matched failed!!\n",pHvdFrmPrv->u32TimeStamp, pHvdFrm->u32TimeStamp);
2635 }
2636 pHvdFrmPrv->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2637 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2638 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2639 }
2640 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2641 u16QPtr++;
2642 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2643 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2644
2645 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2646 }
2647 }
2648
2649 return NULL;
2650 }
2651
2652 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2653 //search the next frame to display
2654 while (u16QNum > 0)
2655 {
2656 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2657 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2658 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2659
2660 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2661 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2662 {
2663 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2664 /// Check the depned view was initial when Output the base view.
2665 if((u16QPtr%2) == 0)
2666 {
2667 HVD_Frm_Information *pHvdFrm_sub = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2668 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2669 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2670 {
2671 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2672 ///printf("Return NULL.\n");
2673 return NULL;
2674 }
2675 }
2676
2677 //printf("V:%d.\n",u16QPtr);
2678 pHVDHalContext->_u16DispQPtr = u16QPtr;
2679 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2680 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2681 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2682 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2683 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2684 }
2685
2686 u16QNum--;
2687 //go to next frame in the dispQ
2688 u16QPtr++;
2689
2690 if (u16QPtr >= pShm->u16DispQSize)
2691 {
2692 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2693 }
2694 }
2695 }
2696 else
2697 #endif ///HVD_ENABLE_MVC
2698 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
2699 if (_HVD_EX_IsHevcInterlaceField(u32Id))
2700 {
2701 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
2702 HVD_Frm_Information *pHvdFrm_first = NULL;
2703
2704 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
2705 return NULL;
2706 }
2707
2708 while (u16QNum != 0)
2709 {
2710 pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2711 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2712 {
2713 if (!first_field) // second get frame, we will check at least one paired in disp queue.
2714 {
2715 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2716 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2717 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
2718
2719 if(pHvdFrm->u8FieldType == EVD_TOP_FIELD || pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
2720 pHvdFrm->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
2721 else
2722 pHvdFrm->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
2723 return pHvdFrm;
2724 }
2725 else // first get frame, we will check at least one paired in disp queue.
2726 {
2727 if (pHvdFrm_first == NULL)
2728 {
2729 pHvdFrm_first = pHvdFrm;
2730 }
2731 else
2732 {
2733 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2734 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
2735
2736 //After flush, we cannot get the correct field type of first field from sei, so we use second field type to decide first field type.
2737 if (pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 0xff)
2738 {
2739 if (pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV)
2740 pHvdFrm_first->u8FieldType = EVD_BOTTOM_WITH_NEXT;
2741 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_PREV)
2742 pHvdFrm_first->u8FieldType = EVD_TOP_WITH_NEXT;
2743 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_PREV)
2744 pHvdFrm_first->u8FieldType = EVD_TOP_WITH_NEXT;
2745 else if (pHvdFrm->u8FieldType == EVD_TOP_FIELD)
2746 pHvdFrm_first->u8FieldType = EVD_BOTTOM_FIELD;
2747 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_FIELD)
2748 pHvdFrm_first->u8FieldType = EVD_TOP_FIELD;
2749 else
2750 {
2751 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2752 return NULL;
2753 }
2754 if ((pHvdFrm_first->u32ID_L >> 16) & 0x1)
2755 pHvdFrm_first->u32ID_L |= (1 << 16);
2756 else
2757 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2758 }
2759 else if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV)
2760 {
2761 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV && pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_NEXT)
2762 {
2763 pHvdFrm_first->u32ID_L |= (1 << 16);
2764 pHvdFrm->u32ID_L |= (1 << 16);
2765 }
2766 else if (pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV && pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
2767 {
2768 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2769 pHvdFrm->u32ID_L &= (~(1 << 16));
2770 }
2771 else
2772 {
2773 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2774 return NULL;
2775 }
2776 }
2777 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
2778 if (pHvdFrm_first->u8FieldType == EVD_TOP_FIELD || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_NEXT)
2779 pHvdFrm_first->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
2780 else
2781 pHvdFrm_first->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
2782 return pHvdFrm_first;
2783 }
2784 }
2785 }
2786 u16QNum--;
2787 //go to next frame in the dispQ
2788 u16QPtr++;
2789
2790 if (u16QPtr == pShm->u16DispQSize)
2791 {
2792 u16QPtr = 0; //wrap to the begin
2793 }
2794
2795 }
2796 return NULL;
2797 }
2798 else
2799 {
2800 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2801 {
2802
2803 while (u16QNum != 0)
2804 {
2805 pHvdFrm = (HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
2806
2807 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2808 {
2809 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2810 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2811 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2812 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2813 }
2814 u16QNum--;
2815 //go to next frame in the dispQ
2816 if (bDolbyVision)
2817 u16QPtr += 2; // single layer must in even ptr
2818 else
2819 u16QPtr++;
2820
2821 if (u16QPtr >= pShm->u16DispQSize)
2822 {
2823 u16QPtr = 0; //wrap to the begin
2824 }
2825 }
2826
2827 return NULL;
2828 }
2829
2830 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2831 //search the next frame to display
2832 while (u16QNum != 0)
2833 {
2834 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2835
2836 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2837 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2838 {
2839 pHVDHalContext->_u16DispQPtr = u16QPtr;
2840 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2841 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2842 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2843 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2844 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2845 }
2846
2847 u16QNum--;
2848 //go to next frame in the dispQ
2849 u16QPtr++;
2850
2851 if (u16QPtr == pShm->u16DispQSize)
2852 {
2853 u16QPtr = 0; //wrap to the begin
2854 }
2855 }
2856 }
2857
2858 return NULL;
2859 }
2860
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2861 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2862 {
2863 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2864 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2865 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2866 {
2867 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2868 if(pVsyncBridgeExt != NULL)
2869 {
2870 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
2871 }
2872 }
2873 return pFrmInfoExt;
2874 }
2875
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)2876 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
2877 {
2878 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2879 MS_U64 u64Ret = 0;
2880
2881 #if SUPPORT_EVD
2882 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
2883 if (isEVD)
2884 {
2885 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
2886 }
2887 else
2888 #endif
2889 #if SUPPORT_G2VP9
2890 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2891 {
2892 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
2893 }
2894 else
2895 #endif
2896 {
2897 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
2898 }
2899
2900 return u64Ret;
2901 }
2902
2903 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)2904 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
2905 {
2906 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2907 MS_U16 u16QNum = pShm->u16DispQNumb;
2908 MS_U16 u16QPtr = pShm->u16DispQPtr;
2909 static volatile HVD_Frm_Information *pHvdFrm = NULL;
2910 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2911 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2912 MS_BOOL bMVC = FALSE;
2913 #if HVD_ENABLE_MVC
2914 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2915 #endif
2916
2917
2918 if (bMVC || (bDolbyVision && !pShm->bSingleLayer) || _HVD_EX_IsHevcInterlaceField(u32Id))
2919 {
2920 if (u16QNum == 1) return TRUE;
2921 }
2922
2923 while (u16QNum != 0)
2924 {
2925 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2926 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2927 {
2928 return FALSE;
2929 }
2930 u16QNum--;
2931
2932 if (bDolbyVision)
2933 u16QPtr += 2; // single layer must in even ptr
2934 else
2935 u16QPtr++;
2936
2937 if (u16QPtr >= pShm->u16DispQSize)
2938 {
2939 u16QPtr = 0; //wrap to the begin
2940 }
2941 }
2942
2943 return TRUE;
2944 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)2945 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
2946 {
2947 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
2948
2949 return &(_pHVDCtrls[u8DrvId]);
2950 }
2951
_HVD_EX_GetStreamIdx(MS_U32 u32Id)2952 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
2953 {
2954 MS_U8 u8OffsetIdx = 0;
2955 MS_U8 u8SidBaseMask = 0xF0;
2956 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
2957
2958 switch (eSidBase)
2959 {
2960 case E_HAL_HVD_MAIN_STREAM_BASE:
2961 {
2962 u8OffsetIdx = 0;
2963 break;
2964 }
2965 case E_HAL_VPU_SUB_STREAM_BASE:
2966 {
2967 u8OffsetIdx = 1;
2968 break;
2969 }
2970 case E_HAL_VPU_MVC_STREAM_BASE:
2971 {
2972 u8OffsetIdx = 0;
2973 break;
2974 }
2975 #ifdef VDEC3
2976 case E_HAL_VPU_N_STREAM_BASE:
2977 {
2978 u8OffsetIdx = (u32Id>>8) & 0xF;
2979 break;
2980 }
2981 #endif
2982 default:
2983 {
2984 u8OffsetIdx = 0;
2985 break;
2986 }
2987 }
2988
2989 return u8OffsetIdx;
2990 }
2991 /*
2992 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
2993 {
2994 MS_U32 i = 0;
2995 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
2996 {
2997 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
2998 {
2999 return TRUE;
3000 }
3001 }
3002 return FALSE;
3003 }
3004 */
3005
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)3006 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
3007 {
3008 MS_PHY u32PhyAddr = 0x0;
3009 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3010
3011 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3012 {
3013 return 0;
3014 }
3015
3016 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3017
3018 if (u32PhyAddr == 0xFFFFFFFF) //boris
3019 {
3020 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3021 }
3022 else
3023 {
3024 // TEE, common + share_info
3025 u32PhyAddr += COMMON_AREA_SIZE;
3026 }
3027
3028 return MsOS_PA2KSEG1(u32PhyAddr);
3029 }
3030
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3031 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3032 {
3033 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3034 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3035
3036 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3037 {
3038 return 0;
3039 }
3040
3041 MS_PHY u32PhyAddr = 0x0;
3042 #if 0
3043 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3044
3045 if (u32PhyAddr == 0xFFFFFFFF)
3046 {
3047 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3048 }
3049 #endif
3050 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3051 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3052
3053 return MsOS_PA2KSEG1(u32PhyAddr);
3054 }
3055
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3056 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3057 {
3058
3059 if (u8MiuSel == E_CHIP_MIU_0)
3060 {
3061 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3062 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3063 }
3064 else if (u8MiuSel == E_CHIP_MIU_1)
3065 {
3066 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3067 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3068 }
3069 else // 2
3070 {
3071 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3072 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, MIU2_CLIENT_SELECT_GP4_HVD_MIF1, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3073 }
3074
3075 }
3076
3077 #if SUPPORT_G2VP9 && defined(VDEC3)
3078 #ifdef __ARM_NEON__
3079 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3080 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3081 {
3082 uint32x4x4_t data, data2;
3083 MS_U8* raster2 = raster + tile_w * 4;
3084
3085 data = vld4q_u32((const uint32_t *)tile);
3086 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3087
3088 vst1q_u32((uint32_t *)raster, data.val[0]);
3089 raster += stride;
3090 vst1q_u32((uint32_t *)raster, data.val[1]);
3091 raster += stride;
3092 vst1q_u32((uint32_t *)raster, data.val[2]);
3093 raster += stride;
3094 vst1q_u32((uint32_t *)raster, data.val[3]);
3095
3096
3097 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3098 raster2 += stride;
3099 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3100 raster2 += stride;
3101 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3102 raster2 += stride;
3103 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3104 }
3105 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3106 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3107 {
3108 MS_U8* tile0 = tile;
3109 MS_U8* tile1 = tile+16;
3110 MS_U8* tile2 = tile+32;
3111 MS_U8* tile3 = tile+48;
3112 int i;
3113
3114 for (i=0; i<4; i++) {
3115 raster[i] = tile0[i];
3116 raster[4+i] = tile1[i];
3117 raster[8+i] = tile2[i];
3118 raster[12+i] = tile3[i];
3119 }
3120
3121 for (i=0; i<4; i++) {
3122 raster[stride+i] = tile0[4+i];
3123 raster[stride+4+i] = tile1[4+i];
3124 raster[stride+8+i] = tile2[4+i];
3125 raster[stride+12+i] = tile3[4+i];
3126 }
3127
3128 for (i=0; i<4; i++) {
3129 raster[2*stride+i] = tile0[8+i];
3130 raster[2*stride+4+i] = tile1[8+i];
3131 raster[2*stride+8+i] = tile2[8+i];
3132 raster[2*stride+12+i] = tile3[8+i];
3133 }
3134
3135 for (i=0; i<4; i++) {
3136 raster[3*stride+i] = tile0[12+i];
3137 raster[3*stride+4+i] = tile1[12+i];
3138 raster[3*stride+8+i] = tile2[12+i];
3139 raster[3*stride+12+i] = tile3[12+i];
3140 }
3141 }
3142 #endif // #ifdef __ARM_NEON__
3143
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)3144 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
3145 {
3146 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
3147 u32Id,
3148 E_TASK_PRI_MEDIUM,
3149 TRUE,
3150 NULL,
3151 32, // stack size..
3152 "HVD_PostProcess_task");
3153
3154 if (s32HvdPpTaskId < 0)
3155 {
3156 HVD_EX_MSG_ERR("Pp Task create failed\n");
3157
3158 return FALSE;
3159 }
3160
3161 HVD_EX_MSG_DBG("Pp Task create success\n");
3162 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
3163
3164 return TRUE;
3165 }
3166
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3167 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3168 {
3169 return y * stride * h + x * w * h;
3170 }
3171
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3172 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3173 {
3174 return y * stride * h + x * w;
3175 }
3176
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3177 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3178 {
3179 raster[0] = tile[0];
3180 raster[1] = tile[1];
3181 raster[2] = tile[2];
3182 raster[3] = tile[3];
3183 raster[stride] = tile[4];
3184 raster[stride + 1] = tile[5];
3185 raster[stride + 2] = tile[6];
3186 raster[stride + 3] = tile[7];
3187 raster[2 * stride] = tile[8];
3188 raster[2 * stride + 1] = tile[9];
3189 raster[2 * stride + 2] = tile[10];
3190 raster[2 * stride + 3] = tile[11];
3191 raster[3 * stride] = tile[12];
3192 raster[3 * stride + 1] = tile[13];
3193 raster[3 * stride + 2] = tile[14];
3194 raster[3 * stride + 3] = tile[15];
3195 }
3196
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3197 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3198 {
3199 const MS_U32 tile_w = 4;
3200 const MS_U32 tile_h = 4;
3201 MS_U32 tile_stride = w;
3202 MS_U32 x, y;
3203 MS_U8 *dst1, *dst2;
3204 MS_U8 *src1, *src2;
3205
3206 #ifdef __ARM_NEON__
3207 // To overlap load and store, handle two blocks at the same time.
3208 dst1 = dst;
3209 src1 = src;
3210 for (y = 0; y < h / tile_h; y++)
3211 {
3212 dst2 = dst1;
3213 src2 = src1;
3214 for (x = 0; x <= (w/tile_w - 8); x+=8)
3215 {
3216 tile4x4_to_raster_8(
3217 dst2,
3218 src2,
3219 raster_stride, tile_w, tile_h);
3220 dst2 += tile_w * 8;
3221 src2 += tile_w * tile_h * 8;
3222 }
3223 dst1 += raster_stride * tile_h;
3224 src1 += tile_stride * tile_h;
3225 for (; x < w / tile_w; x++)
3226 {
3227 tile4x4_to_raster(
3228 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3229 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3230 raster_stride);
3231 }
3232 }
3233 #else
3234 dst1 = NULL;
3235 src1 = NULL;
3236 dst2 = NULL;
3237 src2 = NULL;
3238
3239 for (y = 0; y < h / tile_h; y++)
3240 {
3241 for (x = 0; x <= (w/tile_w - 4); x+=4)
3242 {
3243 tile4x4_to_raster_4(
3244 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3245 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3246 raster_stride);
3247 }
3248 for (; x < w / tile_w; x++)
3249 {
3250 tile4x4_to_raster(
3251 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3252 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3253 raster_stride);
3254 }
3255 }
3256 #endif
3257 }
3258
3259 #define FLUSH_CACHE_SIZE (256 * 1024)
3260
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3261 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3262 {
3263 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
3264 if (u32Size > FLUSH_CACHE_SIZE)
3265 u32Size = FLUSH_CACHE_SIZE;
3266
3267 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
3268 }
3269
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3270 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3271 {
3272 MS_U32 u32SkipSize = 0;
3273
3274 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3275 if (u32Size > FLUSH_CACHE_SIZE)
3276 {
3277 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3278 u32Size = FLUSH_CACHE_SIZE;
3279 }
3280
3281 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
3282 }
3283
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3284 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3285 {
3286 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
3287 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3288 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3289 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3290
3291 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3292
3293 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3294
3295 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3296 {
3297 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3298 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3299
3300 HVD_Delay_ms(1); // FIXME
3301
3302 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3303 continue;
3304
3305 HAL_HVD_EX_ReadMemory();
3306
3307 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3308 {
3309 MS_U8 *pSrcVA, *pDstVA;
3310 MS_U32 u32SrcPA, u32DstPA;
3311 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3312 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3313
3314 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3315 {
3316 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3317
3318 u16Width = pFrmInfo->u16Width;
3319 u16Height = pFrmInfo->u16Height;
3320 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3321 }
3322
3323 // Luma
3324 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3325 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3326
3327 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3328 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3329
3330 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3331 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3332
3333 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3334
3335 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3336
3337 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3338
3339 // Chroma
3340 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3341 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3342
3343 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3344 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3345
3346 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3347 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3348
3349 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3350
3351 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3352
3353 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3354
3355 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3356 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3357 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3358
3359 HAL_HVD_EX_FlushMemory();
3360
3361 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3362 break;
3363
3364 HAL_HVD_EX_ReadMemory();
3365 }
3366 }
3367
3368 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3369
3370 return TRUE;
3371 }
3372 #endif
3373
HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id,MS_BOOL * isVP8Used,MS_BOOL * isAECUsed,MS_BOOL * isAVCUsed)3374 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed , MS_BOOL *isAVCUsed)
3375 {
3376 MS_U8 i ;
3377 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3378
3379 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM ; i++)
3380 {
3381 if( _pHVDCtrls[i].bUsed && (i != u8DrvId))
3382 {
3383 MS_U32 u32TempModeFlag = (_pHVDCtrls[i].InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ;
3384 if((E_HVD_INIT_HW_VP8 == u32TempModeFlag))
3385 {
3386 *isVP8Used = TRUE ;
3387 }
3388 else if((E_HVD_INIT_HW_VP9 == u32TempModeFlag) || (E_HVD_INIT_HW_AVS == u32TempModeFlag))
3389 {
3390 *isAECUsed = TRUE ;
3391 }
3392 else if((E_HVD_INIT_HW_AVC == u32TempModeFlag))
3393 {
3394 *isAVCUsed = TRUE ;
3395 }
3396 }
3397 }
3398 }
3399
3400
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3401 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3402 {
3403 #ifndef VDEC3
3404 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3405 #endif
3406 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3407 MS_BOOL isVP8Used = FALSE;
3408 MS_BOOL isAECUsed = FALSE;
3409 MS_BOOL isAVCUsed = FALSE;
3410 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
3411 // MS_U8 u8MiuSel;
3412 // MS_U32 u32StartOffset;
3413
3414 #if SUPPORT_EVD
3415 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
3416 #else
3417 MS_BOOL isEVD = FALSE;
3418 #endif
3419 MS_BOOL isHVD = !isEVD;
3420
3421 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
3422 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3423
3424 if(pCtrl == NULL)
3425 {
3426 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
3427 //return FALSE;
3428 goto RESET;
3429 }
3430
3431 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3432 // re-setup clock.
3433 #if SUPPORT_G2VP9 && defined(VDEC3)
3434 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3435 #endif
3436
3437 if (isHVD)
3438 {
3439 if (!HAL_VPU_EX_HVDInUsed())
3440 {
3441 printf("HVD power on\n");
3442 HAL_HVD_EX_PowerCtrl(u32Id, TRUE);
3443 }
3444
3445 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3446 {
3447 HAL_VP8_PowerCtrl(TRUE);
3448 }
3449 else if(!isAECUsed &&( E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3450 {
3451 HAL_AEC_PowerCtrl(TRUE);
3452 }
3453
3454 #ifdef CONFIG_MSTAR_SRAMPD
3455 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3456 HVD_Delay_ms(1);
3457 #endif
3458 }
3459
3460 #if SUPPORT_EVD
3461 #ifdef VDEC3
3462 if (isEVD) /// Disable it for disable H264 IMI
3463 {
3464 if (!HAL_VPU_EX_EVDInUsed())
3465 {
3466 printf("EVD power on\n");
3467 HAL_EVD_EX_PowerCtrl(u32Id, TRUE);
3468 }
3469 if(!isAECUsed && (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3470 {
3471 HAL_AEC_PowerCtrl(TRUE);
3472 }
3473 }
3474 #endif
3475 #endif
3476
3477 #if SUPPORT_G2VP9 && defined(VDEC3)
3478 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3479 {
3480 if (!HAL_VPU_EX_G2VP9InUsed())
3481 {
3482 printf("G2 VP9 power on\n");
3483 HAL_VP9_EX_PowerCtrl(TRUE);
3484 }
3485 }
3486 #endif
3487
3488 if ((!HAL_VPU_EX_HVDInUsed()) )
3489 {
3490 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3491 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3492 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3493 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3494
3495 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3496
3497 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
3498 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
3499 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256);
3500 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256);
3501 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128);
3502 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128);
3503
3504 #if 0
3505 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
3506 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3507 {
3508 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
3509
3510 _HAL_HVD_Entry();
3511 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
3512 _HAL_HVD_Release();
3513
3514 }
3515 #endif
3516 }
3517
3518 #if SUPPORT_EVD
3519 if (isEVD)
3520 {
3521 #ifdef VDEC3
3522 if (!HAL_VPU_EX_EVDInUsed())
3523 #endif
3524 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3525 }
3526 #endif
3527
3528 #if SUPPORT_G2VP9 && defined(VDEC3)
3529 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3530 {
3531 if (!HAL_VPU_EX_G2VP9InUsed())
3532 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3533 }
3534 #endif
3535
3536 #if SUPPORT_EVD
3537 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
3538 {
3539 #ifdef VDEC3
3540 if (!HAL_VPU_EX_EVDInUsed())
3541 #endif
3542 {
3543 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3544 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3545 }
3546
3547 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3548 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3549 {
3550 #ifdef VDEC3
3551 if (0 == pCtrl->u32BBUId)
3552 #else
3553 if (0 == u8TaskId)
3554 #endif
3555 {
3556 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
3557 }
3558 else
3559 {
3560 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
3561 }
3562
3563 }
3564 goto RESET;
3565 }
3566 #endif
3567
3568 // HVD4, from JANUS and later chip
3569 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3570 {
3571 case E_HVD_INIT_HW_AVS:
3572 {
3573 #ifdef VDEC3
3574 if (0 == pCtrl->u32BBUId)
3575 #else
3576 if (0 == u8TaskId)
3577 #endif
3578 {
3579 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3580 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3581 }
3582 else
3583 {
3584 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3585 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3586 }
3587
3588 break;
3589 }
3590 case E_HVD_INIT_HW_RM:
3591 {
3592 #ifdef VDEC3
3593 if (0 == pCtrl->u32BBUId)
3594 #else
3595 if (0 == u8TaskId)
3596 #endif
3597 {
3598 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3599 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3600
3601 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3602 {
3603 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3604 }
3605 else // RV 8
3606 {
3607 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3608 }
3609 }
3610 else
3611 {
3612 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3613 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3614
3615 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3616 {
3617 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3618 }
3619 else // RV 8
3620 {
3621 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3622 }
3623
3624 }
3625
3626 break;
3627 }
3628 default:
3629 {
3630 #ifdef VDEC3
3631 if (0 == pCtrl->u32BBUId)
3632 #else
3633 if (0 == u8TaskId)
3634 #endif
3635 {
3636 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3637 }
3638 else
3639 {
3640 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3641 }
3642 break;
3643 }
3644 }
3645
3646 RESET:
3647
3648 #if 0 //use miu256bit
3649 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3650
3651 if (!HAL_VPU_EX_HVDInUsed())
3652 {
3653 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3654 }
3655
3656 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3657 #endif
3658
3659 #if SUPPORT_EVD
3660 if (isEVD)
3661 {
3662 #ifdef VDEC3
3663 if (!HAL_VPU_EX_EVDInUsed())
3664 #endif
3665 {
3666 printf("EVD miu 256 bits\n");
3667 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_128 & ~EVD_REG_RESET_MIU1_128));
3668 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_256 | EVD_REG_RESET_MIU1_256));
3669 }
3670 }
3671 #endif
3672 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3673 // Only ES buffer addrress needs to be set for VP8
3674 _HVD_EX_SetESBufferAddr(u32Id);
3675 #else
3676 if(DecoderType != E_VPU_EX_DECODER_MVD)
3677 {
3678 _HVD_EX_SetBufferAddr(u32Id);
3679 }
3680 #endif
3681 if (!HAL_VPU_EX_HVDInUsed())
3682 {
3683 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3684 }
3685
3686 #if SUPPORT_EVD
3687 if (isEVD)
3688 {
3689 #ifdef VDEC3
3690 if (!HAL_VPU_EX_EVDInUsed())
3691 #endif
3692 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
3693 }
3694 #endif
3695
3696 #if SUPPORT_G2VP9 && defined(VDEC3)
3697 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3698 {
3699 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3700
3701 if (!HAL_VPU_EX_G2VP9InUsed())
3702 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3703
3704 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3705 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
3706 }
3707 #endif
3708
3709 return TRUE;
3710 }
3711
HAL_HVD_EX_DeinitHW(MS_U32 u32Id)3712 MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id)
3713 {
3714 MS_U16 u16Timeout = 1000;
3715 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3716 MS_BOOL isVP8Used = FALSE;
3717 MS_BOOL isAECUsed = FALSE;
3718 MS_BOOL isAVCUsed = FALSE;
3719 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed , &isAVCUsed);
3720
3721 #if SUPPORT_EVD
3722 if(!isAVCUsed && E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) && !HAL_VPU_EX_EVDInUsed())
3723 {
3724 HAL_EVD_EX_DeinitHW(u32Id);//no AVC/EVD use , close EVD power
3725 }
3726 #endif
3727
3728 if(TRUE == HAL_VPU_EX_HVDInUsed())
3729 {
3730 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3731 {
3732 HAL_VP8_PowerCtrl(FALSE);
3733 }
3734 else if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3735 {
3736 HAL_AEC_PowerCtrl(FALSE);
3737 }
3738 return FALSE;
3739 }
3740 else
3741 {
3742 _HVD_EX_SetMIUProtectMask(TRUE);
3743
3744 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3745
3746 while (u16Timeout)
3747 {
3748 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
3749 {
3750 break;
3751 }
3752 u16Timeout--;
3753 }
3754
3755 HAL_HVD_EX_PowerCtrl(u32Id, FALSE);
3756
3757 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3758 {
3759 HAL_VP8_PowerCtrl(FALSE);
3760 }
3761 else if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3762 {
3763 HAL_AEC_PowerCtrl(FALSE);
3764 }
3765
3766 #ifdef CONFIG_MSTAR_SRAMPD
3767 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3768 HVD_Delay_ms(1);
3769 #endif
3770
3771 _HVD_EX_SetMIUProtectMask(FALSE);
3772
3773 return TRUE;
3774 }
3775
3776 return FALSE;
3777 }
3778
HAL_HVD_EX_FlushMemory(void)3779 void HAL_HVD_EX_FlushMemory(void)
3780 {
3781 MsOS_FlushMemory();
3782 }
3783
HAL_HVD_EX_ReadMemory(void)3784 void HAL_HVD_EX_ReadMemory(void)
3785 {
3786 MsOS_ReadMemory();
3787 }
3788
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)3789 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
3790 {
3791 _pHVDCtrls = pHVDCtrlsBase;
3792 }
3793
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)3794 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
3795 {
3796 return;
3797 }
3798
HAL_HVD_EX_GetHWVersionID(void)3799 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
3800 {
3801 return _HVD_Read2Byte(HVD_REG_REV_ID);
3802 }
3803
3804
HAL_HVD_EX_Init_Share_Mem(void)3805 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
3806 {
3807 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
3808 #if !defined(SUPPORT_X_MODEL_FEATURE)
3809 MS_U32 u32ShmId;
3810 MS_VIRT u32Addr;
3811 MS_U32 u32BufSize;
3812
3813
3814 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
3815 sizeof(HVD_Hal_CTX),
3816 &u32ShmId,
3817 &u32Addr,
3818 &u32BufSize,
3819 MSOS_SHM_QUERY))
3820 {
3821 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
3822 sizeof(HVD_Hal_CTX),
3823 &u32ShmId,
3824 &u32Addr,
3825 &u32BufSize,
3826 MSOS_SHM_CREATE))
3827 {
3828 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
3829 if(pHVDHalContext == NULL)
3830 {
3831 pHVDHalContext = &gHVDHalContext;
3832 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3833 _HVD_EX_Context_Init_HAL();
3834 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
3835 }
3836 else
3837 {
3838 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
3839 }
3840 //return FALSE;
3841 }
3842 else
3843 {
3844 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
3845 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
3846 _HVD_EX_Context_Init_HAL();
3847 }
3848 }
3849 else
3850 {
3851 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
3852 }
3853 #else
3854 if(pHVDHalContext == NULL)
3855 {
3856 pHVDHalContext = &gHVDHalContext;
3857 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3858 _HVD_EX_Context_Init_HAL();
3859 }
3860 #endif
3861 _HAL_HVD_MutexCreate();
3862 #else
3863 if(pHVDHalContext == NULL)
3864 {
3865 pHVDHalContext = &gHVDHalContext;
3866 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3867 _HVD_EX_Context_Init_HAL();
3868 }
3869 #endif
3870
3871 return TRUE;
3872 }
3873
3874
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)3875 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
3876 {
3877 MS_U32 i = 0;
3878
3879 if (eStreamType == E_HAL_HVD_MVC_STREAM)
3880 {
3881 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
3882 return pHVDHalContext->_stHVDStream[0].eStreamId;
3883 }
3884 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
3885 {
3886 for (i = 0;
3887 i <
3888 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3889 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3890 {
3891 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3892 {
3893 return pHVDHalContext->_stHVDStream[i].eStreamId;
3894 }
3895 }
3896 }
3897 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
3898 {
3899 for (i = 0;
3900 i <
3901 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3902 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3903 {
3904 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3905 {
3906 return pHVDHalContext->_stHVDStream[i].eStreamId;
3907 }
3908 }
3909 }
3910 #ifdef VDEC3
3911 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
3912 {
3913 i = eStreamType - E_HAL_HVD_N_STREAM;
3914 if (!pHVDHalContext->_stHVDStream[i].bUsed)
3915 return pHVDHalContext->_stHVDStream[i].eStreamId;
3916 }
3917 #endif
3918
3919 return E_HAL_HVD_STREAM_NONE;
3920 }
3921
HAL_VP8_PowerCtrl(MS_BOOL bEnable)3922 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable)
3923 {
3924 if (bEnable)
3925 {
3926 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3927
3928 switch (pHVDHalContext->u32HVDClockType)
3929 {
3930 case 384:
3931 {
3932 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3933 break;
3934 }
3935 case 345:
3936 {
3937 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3938 break;
3939 }
3940 case 320:
3941 {
3942 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3943 break;
3944 }
3945 case 288:
3946 {
3947 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3948 break;
3949 }
3950 case 240:
3951 {
3952 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
3953 break;
3954 }
3955 case 216:
3956 {
3957 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3958 break;
3959 }
3960 case 172:
3961 {
3962 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3963 break;
3964 }
3965 default:
3966 {
3967 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3968 break;
3969 }
3970 }
3971 }
3972 else
3973 {
3974 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3975 }
3976
3977 }
3978
HAL_AEC_PowerCtrl(MS_BOOL bEnable)3979 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable)
3980 {
3981 if (bEnable)
3982 {
3983 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3984
3985 switch (pHVDHalContext->u32HVDClockType)
3986 {
3987 case 384:
3988 {
3989 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3990 break;
3991 }
3992 case 345:
3993 {
3994 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3995 break;
3996 }
3997 case 320:
3998 {
3999 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4000 break;
4001 }
4002 case 288:
4003 {
4004 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4005 break;
4006 }
4007 case 240:
4008 {
4009 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4010 break;
4011 }
4012 case 216:
4013 {
4014 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4015 break;
4016 }
4017 case 172:
4018 {
4019 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4020 break;
4021 }
4022 default:
4023 {
4024 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4025 break;
4026 }
4027 }
4028 }
4029 else
4030 {
4031 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4032 }
4033
4034 }
4035
HAL_HVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)4036 void HAL_HVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
4037 {
4038 if (bEnable)
4039 {
4040 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4041 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4042 }
4043 else
4044 {
4045 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4046 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4047 }
4048
4049 // fix to not inverse
4050 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
4051
4052 switch (pHVDHalContext->u32HVDClockType)
4053 {
4054 #if 0 //for overclocking
4055 case 432:
4056 {
4057 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
4058 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4059 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_320MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4060 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK);
4061 break;
4062 }
4063 #endif
4064 case 384:
4065 {
4066 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4067 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4068 break;
4069 }
4070 case 345:
4071 {
4072 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_345MHZ, TOP_CKG_HVD_CLK_MASK);
4073 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4074 break;
4075 }
4076 case 320:
4077 {
4078 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_320MHZ, TOP_CKG_HVD_CLK_MASK);
4079 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_345MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4080 break;
4081 }
4082 case 288:
4083 {
4084 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
4085 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_320MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4086 break;
4087 }
4088 case 240:
4089 {
4090 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
4091 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4092 break;
4093 }
4094 case 216:
4095 {
4096 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
4097 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_240MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4098 break;
4099 }
4100 case 172:
4101 {
4102 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
4103 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_216MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4104 break;
4105 }
4106
4107 default:
4108 {
4109 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4110 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4111 break;
4112 }
4113 }
4114
4115 return;
4116 }
4117
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)4118 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
4119 {
4120 u32HVDRegOSBase = u32RegBase;
4121 HAL_VPU_EX_InitRegBase(u32RegBase);
4122 }
4123
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)4124 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
4125 {
4126 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
4127 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4128 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
4129 }
4130
HAL_HVD_EX_InitVariables(MS_U32 u32Id)4131 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
4132 {
4133 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4134 HVD_ShareMem *pShm = NULL;
4135 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4136 #if HVD_ENABLE_MVC
4137 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4138 #endif ///HVD_ENABLE_MVC
4139
4140 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4141 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4142 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4143 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
4144 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4145 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = TRUE;
4146 int i;
4147 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
4148 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
4149 #if HVD_ENABLE_MVC
4150 if(bMVC)
4151 {
4152 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
4153 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
4154 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
4155 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
4156 }
4157 #endif ///HVD_ENABLE_MVC
4158
4159 // set a local copy of FW code address; assuming there is only one copy of FW,
4160 // no matter how many task will be created.
4161
4162 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4163
4164 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
4165
4166 // global variables
4167 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
4168
4169
4170 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4171 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4172 // Create mutex
4173 //_HAL_HVD_MutexCreate();
4174
4175 // fill HVD init variables
4176 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4177 {
4178 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
4179 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
4180 }
4181 else
4182 #if HVD_ENABLE_RV_FEATURE
4183 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4184 {
4185 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
4186 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
4187 #ifdef VDEC3_FB
4188 pHVDHalContext->u32RV_VLCTableAddr = 0;
4189 #else
4190 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
4191 {
4192 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
4193 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
4194 }
4195 else
4196 {
4197 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
4198 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
4199 return E_HVD_RETURN_INVALID_PARAMETER;
4200 }
4201 #endif
4202 }
4203 else
4204 #endif
4205 {
4206 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
4207 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
4208 #if HVD_ENABLE_MVC
4209 if(bMVC)
4210 {
4211 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
4212 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
4213 }
4214 #endif /// HVD_ENABLE_MVC
4215 pHVDHalContext->u32RV_VLCTableAddr = 0;
4216 }
4217
4218 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
4219 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
4220 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
4221 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
4222 {
4223 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4224 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4225 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4226 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4227 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4228 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4229 #if HVD_ENABLE_MVC
4230 if(bMVC)
4231 {
4232 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
4233 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
4234 {
4235 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
4236 }
4237 }
4238 #endif /// HVD_ENABLE_MVC
4239
4240 return E_HVD_RETURN_SUCCESS;
4241 }
4242 else
4243 {
4244 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4245 (unsigned long)MS_VA2PA((MS_VIRT)pShm),
4246 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4247 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4248 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4249 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4250 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4251 return E_HVD_RETURN_INVALID_PARAMETER;
4252 }
4253 }
4254
4255 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)4256 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
4257 #else
4258 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
4259 #endif
4260 {
4261 MS_U32 u32Addr = 0;
4262 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4263 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4264 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4265
4266 MS_U32 u32TmpStartOffset;
4267 MS_U8 u8TmpMiuSel;
4268
4269
4270 memset(pShm, 0, sizeof(HVD_ShareMem));
4271
4272 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
4273
4274 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
4275 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
4276 #ifdef VDEC3
4277 if (bFWdecideFB || bCMAUsed)
4278 {
4279 pShm->u32FrameBufAddr = 0;
4280 pShm->u32FrameBufSize = 0;
4281 }
4282 else
4283 #endif
4284 {
4285 pShm->u32FrameBufAddr = u32Addr;
4286 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
4287 }
4288
4289 // FIXME: need to use the avaliable task resource instead of using next task resource
4290 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
4291 pShm->u8ExternalHeapIdx = u8Idx + 1;
4292 else
4293 pShm->u8ExternalHeapIdx = 0xFF;
4294 pShm->DispInfo.u16DispWidth = 1;
4295 pShm->DispInfo.u16DispHeight = 1;
4296 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
4297 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
4298 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
4299 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4300 //Chip info
4301 pShm->u16ChipID = E_MSTAR_CHIP_MASERATI;
4302 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4303 // PreSetControl
4304 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bOnePendingBuffer)
4305 {
4306 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4307 }
4308
4309 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bCalFrameRate)
4310 {
4311 pShm->u32PreSetControl |= PRESET_CAL_FRAMERATE;
4312 }
4313
4314 pShm->bUseTSPInBBUMode = FALSE;
4315
4316
4317 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable) &&
4318 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4319 {
4320 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4321
4322 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufAddr);
4323
4324 pShm->u32IapGnBufAddr = u32Addr;
4325 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufSize;
4326
4327 }
4328
4329 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
4330 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
4331 {
4332 case E_HVD_DEF_MFCODEC_DEFAULT:
4333 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4334 break;
4335 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
4336 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
4337 break;
4338 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
4339 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
4340 break;
4341 default:
4342 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4343 }
4344
4345 pShm->u8CodecFeature &= ~E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4346 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bDVSingleLayerMode)
4347 pShm->u8CodecFeature |= E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4348
4349 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
4350 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
4351 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
4352 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
4353 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
4354 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
4355
4356 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.bEnable))
4357 {
4358 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4359
4360 pShm->stDynmcDispPath.u8Connect = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.bConnect;
4361 pShm->stDynmcDispPath.u8DispPath = (MS_U8)(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.eMvopPath);
4362 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4363
4364 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, pShm->stDynmcDispPath.u8DispPath);
4365 }
4366 else
4367 {
4368 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4369
4370 MS_U8 u8Connect = FALSE;
4371 MS_U8 u8Path = E_CTL_DISPLAY_PATH_NONE;
4372 switch (pCtrl->eStream)
4373 {
4374 case E_HVD_ORIGINAL_MAIN_STREAM:
4375 u8Connect = TRUE;
4376 u8Path = E_CTL_DISPLAY_PATH_MVOP_0;
4377 break;
4378 case E_HVD_ORIGINAL_SUB_STREAM:
4379 u8Connect = TRUE;
4380 u8Path = E_CTL_DISPLAY_PATH_MVOP_1;
4381 break;
4382 case E_HVD_ORIGINAL_N_STREAM:
4383 default:
4384 u8Connect = FALSE;
4385 u8Path = E_CTL_DISPLAY_PATH_NONE;
4386 break;
4387 }
4388
4389 pShm->stDynmcDispPath.u8Connect = u8Connect;
4390 pShm->stDynmcDispPath.u8DispPath = u8Path;
4391 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4392
4393 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, u8Path);
4394 }
4395
4396 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
4397 {
4398 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.bEnable))
4399 {
4400 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
4401 pShm->u8InputTSP = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.u8InputTsp;
4402
4403 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
4404 }
4405 else
4406 {
4407 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
4408
4409 MS_U8 u8Input = E_CTL_INPUT_TSP_NONE;
4410 switch (pCtrl->eStream)
4411 {
4412 case E_HVD_ORIGINAL_MAIN_STREAM:
4413 u8Input = E_CTL_INPUT_TSP_0;
4414 break;
4415 case E_HVD_ORIGINAL_SUB_STREAM:
4416 u8Input = E_CTL_INPUT_TSP_1;
4417 break;
4418 case E_HVD_ORIGINAL_N_STREAM:
4419 default:
4420 u8Input = E_CTL_INPUT_TSP_NONE;
4421 break;
4422 }
4423
4424 pShm->u8InputTSP = u8Input;
4425
4426 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
4427 }
4428 }
4429 else
4430 {
4431 HVD_EX_MSG_DBG("[NDec][0x%x][%d] not TSP input, ignore PRESET_CONNECT_INPUT_TSP \n", u32Id, u8Idx);
4432 }
4433
4434 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4435 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4436 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4437 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4438 else
4439 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4440 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4441 {
4442 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4443 {
4444 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4445 }
4446 else
4447 {
4448 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4449 }
4450 }
4451 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4452 {
4453 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4454 {
4455 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4456 }
4457 else
4458 {
4459 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4460 }
4461 }
4462 else
4463 {
4464 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4465 }
4466
4467 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4468 {
4469 pShm->bHVDIMIEnable = TRUE;
4470 }
4471
4472 #if 0
4473 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bEnableDynamicCMA)
4474 {
4475 pShm->u8CodecFeature |= E_VDEC_DYNAMIC_CMA_MODE;
4476 }
4477 #endif
4478
4479 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4480 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4481 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4482 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4483 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4484 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4485 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4486 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4487 (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4488 {
4489 pShm->bUseWbMvop = 1;
4490 }
4491
4492 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
4493 E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4494 {
4495 #if 0 // Disable Fluidplay
4496 pShm->u8CodecFeature |= E_VDEC_TEMPORAL_SCALABILITY_MODE;
4497 #endif
4498 }
4499
4500 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4501
4502 #if (VPU_FORCE_MIU_MODE)
4503 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4504
4505 pShm->u32FWBaseAddr = u32TmpStartOffset;
4506
4507 #else
4508 ///TODO:
4509 /*
4510 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4511
4512 if(u8TmpMiuSel == E_CHIP_MIU_0)
4513 {
4514 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4515 }
4516 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4517 {
4518 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4519 }
4520 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4521 {
4522 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4523 }
4524 */
4525 #endif
4526 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4527 #else
4528 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4529 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4530 {
4531 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4532 }
4533 pShm->u32FWBaseAddr = u32Addr;
4534 #endif
4535
4536 // RM only
4537 #if HVD_ENABLE_RV_FEATURE
4538 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4539 && (pCtrl->InitParams.pRVFileInfo != NULL))
4540 {
4541 MS_U32 i = 0;
4542
4543 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4544 {
4545 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4546 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4547 }
4548
4549 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4550 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4551 #ifdef VDEC3_FB
4552 pShm->u32RM_VLCTableAddr = 0;
4553 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4554 #else
4555 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
4556
4557 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4558 u32Addr = u32TmpStartOffset;
4559
4560 pShm->u32RM_VLCTableAddr = u32Addr;
4561 #endif
4562 }
4563 #endif
4564
4565 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4566 && (pCtrl->InitParams.pRVFileInfo != NULL))
4567 {
4568 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4569 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4570 }
4571
4572 //if(pCtrl->InitParams.bColocateBBUMode)
4573 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4574 {
4575 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4576 }
4577
4578 #if SUPPORT_G2VP9
4579 // Enable SW detile support for G2 VP9
4580 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4581 {
4582 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4583 }
4584 #endif
4585
4586 HAL_HVD_EX_FlushMemory();
4587
4588 return E_HVD_RETURN_SUCCESS;
4589 }
4590 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4591 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4592 #else
4593 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4594 #endif
4595 {
4596 MS_BOOL bInitRet = FALSE;
4597
4598 #if 0
4599 // check MVD power on
4600 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4601 {
4602 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4603 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4604 HVD_Delay_ms(1);
4605 }
4606 // Check VPU power on
4607 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4608 {
4609 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4610 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4611 HVD_Delay_ms(1);
4612 }
4613 // check HVD power on
4614 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4615 {
4616 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4617 HAL_HVD_EX_PowerCtrl(TRUE);
4618 HVD_Delay_ms(1);
4619 }
4620 #endif
4621 #ifdef VDEC3
4622 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4623 #else
4624 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4625 #endif
4626 if (!bInitRet)
4627 {
4628 return E_HVD_RETURN_FAIL;
4629 }
4630
4631 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4632
4633 if (!bInitRet)
4634 {
4635 return E_HVD_RETURN_FAIL;
4636 }
4637
4638 return E_HVD_RETURN_SUCCESS;
4639 }
4640
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4641 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4642 {
4643 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4644
4645 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4646
4647 return E_HVD_RETURN_SUCCESS;
4648 }
4649
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)4650 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
4651 {
4652 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4653 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4654 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4655 MS_BOOL bMVC = FALSE;
4656 #if HVD_ENABLE_MVC
4657 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4658 #endif
4659
4660 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4661 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
4662
4663 switch (u32type)
4664 {
4665 // share memory
4666 // switch
4667 case E_HVD_SDATA_FRAMEBUF_ADDR:
4668 {
4669 pShm->u32FrameBufAddr = u32Data;
4670 break;
4671 }
4672 case E_HVD_SDATA_FRAMEBUF_SIZE:
4673 {
4674 pShm->u32FrameBufSize = u32Data;
4675 break;
4676 }
4677 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4678 {
4679 pShm->u32FrameBuf2Addr = u32Data;
4680 break;
4681 }
4682 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4683 {
4684 pShm->u32FrameBuf2Size = u32Data;
4685 break;
4686 }
4687 case E_HVD_SDATA_MAX_CMA_SIZE:
4688 {
4689 pShm->u32MaxCMAFrameBufSize = u32Data;
4690 break;
4691 }
4692 case E_HVD_SDATA_MAX_CMA_SIZE2:
4693 {
4694 pShm->u32MaxCMAFrameBuf2Size = u32Data;
4695 break;
4696 }
4697 case E_HVD_SDATA_CMA_USED:
4698 {
4699 pShm->bCMA_Use = u32Data;
4700 break;
4701 }
4702 case E_HVD_SDATA_CMA_ALLOC_DONE:
4703 {
4704 pShm->bCMA_AllocDone = u32Data;
4705 break;
4706 }
4707 case E_HVD_SDATA_CMA_TWO_MIU:
4708 {
4709 pShm->bCMA_TwoMIU = u32Data;
4710 break;
4711 }
4712 case E_HVD_SDATA_RM_PICTURE_SIZES:
4713 {
4714 if(u32Data != NULL)
4715 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4716 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4717 break;
4718 }
4719 case E_HVD_SDATA_ERROR_CODE:
4720 {
4721 pShm->u16ErrCode = (MS_U16) u32Data;
4722 break;
4723 }
4724 case E_HVD_SDATA_DISP_INFO_TH:
4725 {
4726 if(u32Data != NULL)
4727 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4728 sizeof(HVD_DISP_THRESHOLD));
4729 break;
4730 }
4731 case E_HVD_SDATA_FW_FLUSH_STATUS:
4732 {
4733 pShm->u8FlushStatus = (MS_U8)u32Data;
4734 break;
4735 }
4736 case E_HVD_SDATA_DMX_FRAMERATE:
4737 {
4738 pShm->u32DmxFrameRate = u32Data;
4739 break;
4740 }
4741 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4742 {
4743 pShm->u32DmxFrameRateBase = u32Data;
4744 break;
4745 }
4746 case E_HVD_SDATA_MIU_SEL:
4747 {
4748 pShm->u32VDEC_MIU_SEL = u32Data;
4749 break;
4750 }
4751 case E_HVD_SDATA_DV_XC_SHM_SIZE:
4752 {
4753 pShm->u32DolbyVisionXCShmSize = u32Data;
4754 break;
4755 }
4756 // SRAM
4757
4758 // Mailbox
4759 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4760 {
4761 if (u32Data != 0)
4762 {
4763 pShm->bEnableDispCtrl = TRUE;
4764 pShm->bIsTrigDisp = TRUE;
4765 }
4766 else
4767 {
4768 pShm->bEnableDispCtrl = FALSE;
4769 }
4770
4771 break;
4772 }
4773 case E_HVD_SDATA_GET_DISP_INFO_START:
4774 {
4775 pShm->bSpsChange = FALSE;
4776 break;
4777 }
4778 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4779 {
4780 pShm->u32VirtualBoxWidth = u32Data;
4781 break;
4782 }
4783 case E_HVD_SDATA_DV_INFO:
4784 {
4785 pShm->u8DVLevelFromDriverAPI = (MS_U8)(u32Data & 0xff);
4786 pShm->u8DVProfileFromDriverAPI = (MS_U8)((u32Data >> 8) & 0xff);
4787 pShm->u8DolbyMetaReorder = (MS_U8)((u32Data >> 16) & 0xff);
4788
4789 break;
4790 }
4791 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4792 {
4793 pShm->u32VirtualBoxHeight = u32Data;
4794 break;
4795 }
4796 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4797 {
4798 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4799 {
4800 //printf("DispFrame DqPtr: %d\n", u32Data);
4801 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4802 }
4803 break;
4804 }
4805 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4806 {
4807 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
4808 {
4809 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4810 {
4811 //printf("DispFrame DqPtr: %ld\n", u32Data);
4812 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4813 }
4814 }
4815 break;
4816 }
4817 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4818 {
4819 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4820 {
4821 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
4822 {
4823 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4824 {
4825 //ALOGE("R1: %x", u32Data);
4826 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
4827 }
4828 else
4829 {
4830 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4831 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4832 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
4833 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4834 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4835 }
4836 }
4837 else
4838 {
4839 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4840 }
4841 }
4842 else
4843 {
4844 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4845 {
4846 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4847 }
4848 }
4849 break;
4850 }
4851 #if (HVD_ENABLE_IQMEM)
4852 case E_HVD_SDATA_FW_IQMEM_CTRL:
4853 {
4854 pShm->u8IQmemCtrl= (MS_U8)u32Data;
4855 break;
4856
4857 }
4858 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
4859 {
4860 if (u32Data != 0)
4861 {
4862 pShm->bIQmemEnableIfSupport= TRUE;
4863 }
4864 else
4865 {
4866 pShm->bIQmemEnableIfSupport= FALSE;
4867 }
4868
4869
4870 break;
4871
4872 }
4873 #endif
4874 case E_HVD_SDATA_DYNMC_DISP_PATH_STATUS:
4875 {
4876 pShm->stDynmcDispPath.u8ConnectStatus = u32Data;
4877 break;
4878 }
4879
4880 default:
4881 break;
4882 }
4883
4884 HAL_HVD_EX_FlushMemory();
4885
4886 return eRet;
4887 }
4888
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4889 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4890 {
4891 MS_S64 s64Ret = 0;
4892 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4893
4894 HAL_HVD_EX_ReadMemory();
4895
4896 switch (eType)
4897 {
4898 case E_HVD_GDATA_PTS_STC_DIFF:
4899 s64Ret = pShm->s64PtsStcDiff;
4900 break;
4901 default:
4902 break;
4903 }
4904
4905 return s64Ret;
4906 }
4907
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4908 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4909 {
4910 MS_VIRT u32Ret = 0;
4911 //static MS_U64 u64pts_real = 0;
4912 MS_U64 u64pts_low = 0;
4913 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4914 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4915
4916 HAL_HVD_EX_ReadMemory();
4917
4918 if(pShm == NULL)
4919 {
4920 printf("########## VDEC patch for Debug ###########\n");
4921 return 0x0;
4922 }
4923
4924 switch (eType)
4925 {
4926 // share memory
4927 // switch
4928 case E_HVD_GDATA_DISP_INFO_ADDR:
4929 {
4930 u32Ret = (MS_VIRT) (&pShm->DispInfo);
4931 break;
4932 }
4933 case E_HVD_GDATA_MIU_SEL:
4934 u32Ret = pShm->u32VDEC_MIU_SEL;
4935 break;
4936 case E_HVD_GDATA_FRAMEBUF_ADDR:
4937 u32Ret = pShm->u32FrameBufAddr;
4938 break;
4939 case E_HVD_GDATA_FRAMEBUF_SIZE:
4940 u32Ret = pShm->u32FrameBufSize;
4941 break;
4942 case E_HVD_GDATA_FRAMEBUF2_ADDR:
4943 u32Ret = pShm->u32FrameBuf2Addr;
4944 break;
4945 case E_HVD_GDATA_FRAMEBUF2_SIZE:
4946 u32Ret = pShm->u32FrameBuf2Size;
4947 break;
4948 case E_HVD_GDATA_CMA_ALLOC_DONE:
4949 u32Ret = pShm->bCMA_AllocDone;
4950 break;
4951 case E_HVD_GDATA_CMA_USED:
4952 u32Ret = pShm->bCMA_Use;
4953 break;
4954 case E_HVD_GDATA_DYNMC_DISP_PATH_STATUS:
4955 u32Ret = pShm->stDynmcDispPath.u8ConnectStatus;//pShm->u8SetDynmcDispPathStatus;
4956 break;
4957 // report
4958 case E_HVD_GDATA_PTS:
4959 {
4960 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
4961 break;
4962 }
4963 case E_HVD_GDATA_U64PTS:
4964 {
4965 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
4966 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
4967 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4968 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4969 break;
4970 }
4971 case E_HVD_GDATA_U64PTS_PRE_PARSE:
4972 {
4973 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
4974 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
4975 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4976 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4977 break;
4978 }
4979 case E_HVD_GDATA_DECODE_CNT:
4980 {
4981 u32Ret = pShm->u32DecodeCnt;
4982 break;
4983 }
4984 case E_HVD_GDATA_DATA_ERROR_CNT:
4985 {
4986 u32Ret = pShm->u32DataErrCnt;
4987 break;
4988 }
4989 case E_HVD_GDATA_DEC_ERROR_CNT:
4990 {
4991 u32Ret = pShm->u32DecErrCnt;
4992 break;
4993 }
4994 case E_HVD_GDATA_ERROR_CODE:
4995 {
4996 u32Ret = (MS_U32) (pShm->u16ErrCode);
4997 break;
4998 }
4999 case E_HVD_GDATA_VPU_IDLE_CNT:
5000 {
5001 u32Ret = pShm->u32VPUIdleCnt;
5002 break;
5003 }
5004 case E_HVD_GDATA_DISP_FRM_INFO:
5005 {
5006 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
5007 break;
5008 }
5009 case E_HVD_GDATA_DEC_FRM_INFO:
5010 {
5011 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
5012 break;
5013 }
5014 case E_HVD_GDATA_ES_LEVEL:
5015 {
5016 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
5017 break;
5018 }
5019 #if HVD_ENABLE_MVC
5020 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
5021 {
5022 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
5023 break;
5024 }
5025 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
5026 {
5027 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
5028 break;
5029 }
5030 #endif
5031
5032 // user data
5033 case E_HVD_GDATA_USERDATA_WPTR:
5034 {
5035 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
5036 break;
5037 }
5038 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
5039 {
5040 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
5041 break;
5042 }
5043 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
5044 {
5045 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
5046 break;
5047 }
5048 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
5049 {
5050 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
5051 break;
5052 }
5053 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
5054 {
5055 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
5056 break;
5057 }
5058 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
5059 {
5060 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
5061 break;
5062 }
5063 // report - modes
5064 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
5065 {
5066 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
5067 break;
5068 }
5069 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
5070 {
5071 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
5072 break;
5073 }
5074 case E_HVD_GDATA_IS_ERR_CONCEAL:
5075 {
5076 u32Ret = pShm->ModeStatus.bIsErrConceal;
5077 break;
5078 }
5079 case E_HVD_GDATA_IS_SYNC_ON:
5080 {
5081 u32Ret = pShm->ModeStatus.bIsSyncOn;
5082 break;
5083 }
5084 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
5085 {
5086 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
5087 break;
5088 }
5089 case E_HVD_GDATA_SYNC_MODE:
5090 {
5091 u32Ret = pShm->ModeStatus.u8SyncType;
5092 break;
5093 }
5094 case E_HVD_GDATA_SKIP_MODE:
5095 {
5096 u32Ret = pShm->ModeStatus.u8SkipMode;
5097 break;
5098 }
5099 case E_HVD_GDATA_DROP_MODE:
5100 {
5101 u32Ret = pShm->ModeStatus.u8DropMode;
5102 break;
5103 }
5104 case E_HVD_GDATA_DISPLAY_DURATION:
5105 {
5106 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
5107 break;
5108 }
5109 case E_HVD_GDATA_FRC_MODE:
5110 {
5111 u32Ret = pShm->ModeStatus.u8FrcMode;
5112 break;
5113 }
5114 case E_HVD_GDATA_NEXT_PTS:
5115 {
5116 u32Ret = pShm->u32NextPTS;
5117 break;
5118 }
5119 case E_HVD_GDATA_DISP_Q_SIZE:
5120 {
5121 u32Ret = pShm->u16DispQSize;
5122 break;
5123 }
5124 case E_HVD_GDATA_DISP_Q_PTR:
5125 {
5126 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
5127 break;
5128 }
5129 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
5130 {
5131 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
5132 break;
5133 }
5134 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
5135 {
5136 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
5137 break;
5138 }
5139 case E_HVD_GDATA_REAL_FRAMERATE:
5140 {
5141 // return VPS/VUI timing info framerate, and 0 if timing info not exist
5142 u32Ret = pShm->u32RealFrameRate;
5143 break;
5144 }
5145 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
5146 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
5147 break;
5148 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
5149 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
5150 break;
5151 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
5152 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
5153 break;
5154 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
5155 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
5156 break;
5157 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
5158 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
5159 break;
5160 case E_HVD_GDATA_FW_STATUS_FLAG:
5161 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
5162 break;
5163
5164 // internal control
5165 case E_HVD_GDATA_IS_1ST_FRM_RDY:
5166 {
5167 u32Ret = pShm->bIs1stFrameRdy;
5168 break;
5169 }
5170 case E_HVD_GDATA_IS_I_FRM_FOUND:
5171 {
5172 u32Ret = pShm->bIsIFrmFound;
5173 break;
5174 }
5175 case E_HVD_GDATA_IS_SYNC_START:
5176 {
5177 u32Ret = pShm->bIsSyncStart;
5178 break;
5179 }
5180 case E_HVD_GDATA_IS_SYNC_REACH:
5181 {
5182 u32Ret = pShm->bIsSyncReach;
5183 break;
5184 }
5185 case E_HVD_GDATA_FW_VERSION_ID:
5186 {
5187 u32Ret = pShm->u32FWVersionID;
5188 break;
5189 }
5190 case E_HVD_GDATA_FW_IF_VERSION_ID:
5191 {
5192 u32Ret = pShm->u32FWIfVersionID;
5193 break;
5194 }
5195 case E_HVD_GDATA_BBU_Q_NUMB:
5196 {
5197 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
5198 break;
5199 }
5200 case E_HVD_GDATA_DEC_Q_NUMB:
5201 {
5202 u32Ret = pShm->u16DecQNumb;
5203 break;
5204 }
5205 case E_HVD_GDATA_DISP_Q_NUMB:
5206 {
5207 u32Ret = pShm->u16DispQNumb;
5208 break;
5209 }
5210 case E_HVD_GDATA_PTS_Q_NUMB:
5211 {
5212 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
5213 break;
5214 }
5215 case E_HVD_GDATA_FW_INIT_DONE:
5216 {
5217 u32Ret = pShm->bInitDone;
5218 break;
5219 }
5220 // debug
5221 case E_HVD_GDATA_SKIP_CNT:
5222 {
5223 u32Ret = pShm->u32SkipCnt;
5224 break;
5225 }
5226 case E_HVD_GDATA_GOP_CNT:
5227 {
5228 u32Ret = pShm->u32DropCnt;
5229 break;
5230 }
5231 case E_HVD_GDATA_DISP_CNT:
5232 {
5233 u32Ret = pShm->u32DispCnt;
5234 break;
5235 }
5236 case E_HVD_GDATA_DROP_CNT:
5237 {
5238 u32Ret = pShm->u32DropCnt;
5239 break;
5240 }
5241 case E_HVD_GDATA_DISP_STC:
5242 {
5243 u32Ret = pShm->u32DispSTC;
5244 break;
5245 }
5246 case E_HVD_GDATA_VSYNC_CNT:
5247 {
5248 u32Ret = pShm->u32VsyncCnt;
5249 break;
5250 }
5251 case E_HVD_GDATA_MAIN_LOOP_CNT:
5252 {
5253 u32Ret = pShm->u32MainLoopCnt;
5254 break;
5255 }
5256
5257 // AVC
5258 case E_HVD_GDATA_AVC_LEVEL_IDC:
5259 {
5260 u32Ret = pShm->u16AVC_SPS_LevelIDC;
5261 break;
5262 }
5263 case E_HVD_GDATA_AVC_LOW_DELAY:
5264 {
5265 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
5266 break;
5267 }
5268 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
5269 {
5270 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
5271 break;
5272 }
5273 case E_HVD_GDATA_FW_FLUSH_STATUS:
5274 {
5275 u32Ret = (MS_U32) (pShm->u8FlushStatus);
5276 break;
5277 }
5278 case E_HVD_GDATA_FW_CODEC_TYPE:
5279 {
5280 u32Ret = pShm->u32CodecType;
5281 break;
5282 }
5283 case E_HVD_GDATA_FW_ES_BUF_STATUS:
5284 {
5285 u32Ret = (MS_U32)pShm->u8ESBufStatus;
5286 break;
5287 }
5288 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
5289 {
5290 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
5291 {
5292 u32Ret = 1;
5293 }
5294 else
5295 {
5296 u32Ret = 0;
5297 }
5298 break;
5299 }
5300
5301 // SRAM
5302
5303 // Mailbox
5304 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
5305 {
5306 u32Ret = pShm->u32FwState;
5307 break;
5308 }
5309 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
5310 {
5311 u32Ret = pShm->bSpsChange;
5312 break;
5313 }
5314 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
5315 {
5316 u32Ret = pShm->bSpsChange;
5317
5318 if (pShm->bSpsChange &&
5319 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
5320 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
5321 {
5322 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
5323 }
5324
5325 break;
5326 }
5327 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
5328 {
5329 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5330
5331 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
5332 {
5333 u32Ret = pShm->u32FwInfo;
5334 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
5335 }
5336 break;
5337 }
5338 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
5339 {
5340 if (pShm->bIsTrigDisp) // not clear yet
5341 {
5342 u32Ret = FALSE;
5343 }
5344 else
5345 {
5346 u32Ret = TRUE;
5347 }
5348 break;
5349 }
5350 case E_HVD_GDATA_ES_READ_PTR:
5351 {
5352 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5353 break;
5354 }
5355 case E_HVD_GDATA_ES_WRITE_PTR:
5356 {
5357 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
5358 break;
5359 }
5360 case E_HVD_GDATA_BBU_READ_PTR:
5361 {
5362 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
5363 break;
5364 }
5365 case E_HVD_GDATA_BBU_WRITE_PTR:
5366 {
5367 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5368 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5369 {
5370 u32Ret = pHVDHalContext->u32VP8BBUWptr;
5371 }
5372 else
5373 {
5374 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5375 }
5376 break;
5377 }
5378 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
5379 {
5380 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5381
5382 u32Ret = pCtrl->u32BBUWptr_Fired;
5383
5384 break;
5385 }
5386 case E_HVD_GDATA_VPU_PC_CNT:
5387 {
5388 u32Ret = _HVD_EX_GetPC();
5389 break;
5390 }
5391 case E_HVD_GDATA_ES_QUANTITY:
5392 {
5393 u32Ret=_HVD_EX_GetESQuantity(u32Id);
5394 break;
5395 }
5396
5397
5398 // FW def
5399 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
5400 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
5401 break;
5402
5403 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
5404 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
5405 break;
5406 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
5407 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
5408 break;
5409 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
5410 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5411 break;
5412 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
5413 u32Ret = MAX_PTS_TABLE_SIZE;
5414 break;
5415 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
5416 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
5417 break;
5418 case E_HVD_GDATA_FW_DS_BUF_ADDR:
5419 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
5420 break;
5421 case E_HVD_GDATA_FW_DS_BUF_SIZE:
5422 u32Ret = pShm->u32DSBuffSize; //3k or 6k
5423 break;
5424 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
5425 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
5426 break;
5427 case E_HVD_GDATA_FW_DS_INFO_ADDR:
5428 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
5429 break;
5430 case E_HVD_GDATA_FW_DS_IS_ENABLED:
5431 {
5432 if (pShm->bDSIsRunning)
5433 {
5434 u32Ret = TRUE;
5435 }
5436 else
5437 {
5438 u32Ret = FALSE;
5439 }
5440 break;
5441 }
5442 #if (HVD_ENABLE_IQMEM)
5443 case E_HVD_GDATA_FW_IQMEM_CTRL:
5444 {
5445
5446 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
5447
5448 break;
5449 }
5450 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
5451 {
5452 if(pShm->bIsIQMEMSupport){
5453 u32Ret = TRUE;
5454 }
5455 else{
5456
5457 u32Ret = FALSE;
5458 }
5459
5460 break;
5461 }
5462 #endif
5463 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
5464 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
5465 break;
5466 case E_HVD_GDATA_FIELD_PIC_FLAG:
5467 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
5468 break;
5469 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
5470 u32Ret = pShm->u32SeamlessTSStatus;
5471 break;
5472 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
5473 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
5474 break;
5475 #ifdef VDEC3
5476 case E_HVD_GDATA_FW_VBBU_ADDR:
5477 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
5478 break;
5479 #endif
5480 case E_HVD_GDATA_SEQ_CHANGE_INFO:
5481 u32Ret = (MS_U32)pShm->u32SeqChangeInfo;
5482 break;
5483 default:
5484 break;
5485 }
5486 return u32Ret;
5487 }
5488
HAL_HVD_EX_GetDVSupportProfiles(void)5489 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
5490 {
5491 #if 0 // wait avc finish DV dual job
5492 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5493 #else
5494 return E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5495 #endif
5496 }
5497
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)5498 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
5499 {
5500 switch (u32DV_Stream_Profile)
5501 {
5502 #if 0 // wait avc finish DV dual job
5503 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
5504 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
5505 #endif
5506
5507 #if 0 // unsupported profile
5508 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
5509 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5510 #endif
5511
5512 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
5513 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5514
5515 #if 0 // unsupported profile
5516 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
5517 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5518 #endif
5519
5520 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
5521 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5522
5523 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
5524 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5525
5526 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
5527 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
5528
5529 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
5530 default:
5531 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5532 }
5533 }
5534
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)5535 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
5536 {
5537 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5538 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
5539 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5540 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5541 {
5542 // skip mutex
5543 }
5544 else
5545 {
5546 _HAL_HVD_Entry();
5547 }
5548 // check if old SVD cmds
5549 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5550 {
5551 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
5552
5553 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5554 {
5555 return E_HVD_RETURN_INVALID_PARAMETER;
5556 }
5557 else
5558 {
5559 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5560 }
5561 }
5562
5563 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5564 {
5565 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5566 }
5567
5568 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5569 {
5570 if (u32Cmd == E_HVD_CMD_FLUSH)
5571 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5572 }
5573
5574 if (u32Cmd == E_HVD_CMD_FLUSH &&
5575 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5576 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5577 {
5578 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5579 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5580 {
5581 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5582 {
5583 HVD_Delay_ms(1);
5584 }
5585 else
5586 {
5587 _HAL_HVD_Release();
5588 HVD_Delay_ms(1);
5589 _HAL_HVD_Entry();
5590 }
5591 }
5592 }
5593
5594 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
5595
5596 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5597 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5598 {
5599 return eRet;
5600 }
5601 else
5602 {
5603 _HAL_HVD_Return(eRet);
5604 }
5605 }
5606
HAL_HVD_EX_DeInit(MS_U32 u32Id)5607 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5608 {
5609 HVD_Return eRet = E_HVD_RETURN_FAIL;
5610 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5611 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5612 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5613 MS_U8 u8MiuSel;
5614 MS_U32 u32StartOffset;
5615 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5616
5617 #if HVD_ENABLE_TIME_MEASURE
5618 MS_U32 ExitTimeCnt = 0;
5619 ExitTimeCnt = HVD_GetSysTime_ms();
5620 #endif
5621
5622 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
5623
5624 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5625
5626 if (E_HVD_RETURN_SUCCESS != eRet)
5627 {
5628 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5629 }
5630
5631 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5632
5633 if (E_HVD_RETURN_SUCCESS != eRet)
5634 {
5635 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5636 }
5637
5638 // check FW state to make sure it's STOP DONE
5639 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5640 {
5641 if (HVD_GetSysTime_ms() > u32Timeout)
5642 {
5643 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
5644
5645 //return E_HVD_RETURN_TIMEOUT;
5646 eRet = E_HVD_RETURN_TIMEOUT;
5647 break;
5648 }
5649 }
5650
5651 if (pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt)
5652 {
5653 HVD_EX_MSG_INF("VDEC PLUS: DropRatio %d, Drop:0.%d (%d), Dec:0.%d (%d), Disp:0.%d\n",
5654 pShm->u8VdecPlusDropRatio,
5655 100*pShm->u32VdecPlusDropCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5656 pShm->u32VdecPlusDropCnt,
5657 100*pShm->u32VdecPlusDecCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5658 pShm->u32VdecPlusDecCnt,
5659 100*pShm->u32VdecPlusDispPicCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt));
5660 }
5661 else
5662 {
5663 HVD_EX_MSG_INF("VDEC PLUS DISABLE: DropRatio %d, Drop: %d, Dec: %d, Disp: %d\n",
5664 pShm->u8VdecPlusDropRatio,
5665 pShm->u32VdecPlusDropCnt,
5666 pShm->u32VdecPlusDecCnt,
5667 pShm->u32VdecPlusDispPicCnt);
5668 }
5669
5670 VPU_EX_FWCodeCfg fwCfg;
5671 VPU_EX_TaskInfo taskInfo;
5672 VPU_EX_NDecInitPara nDecInitPara;
5673
5674 nDecInitPara.pFWCodeCfg = &fwCfg;
5675 nDecInitPara.pTaskInfo = &taskInfo;
5676
5677 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5678 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5679
5680 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);//power control
5681 #if 0
5682 taskInfo.u32Id = u32Id;
5683 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5684 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5685 #endif
5686
5687 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5688 {
5689 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5690 }
5691 else
5692 {
5693 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5694 }
5695
5696 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5697 {
5698 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5699 }
5700
5701 /* clear es buffer */
5702 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5703 {
5704 //printf("Clear ES buffer\n");
5705
5706 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5707 }
5708
5709 //_HAL_HVD_MutexDelete();
5710
5711 #if HVD_ENABLE_TIME_MEASURE
5712 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5713 #endif
5714
5715 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
5716 #ifndef VDEC3
5717 // reset bbu wptr
5718 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5719 {
5720 if(TRUE == HAL_VPU_EX_HVDInUsed())
5721 {
5722 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5723 {
5724 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5725 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5726 }
5727 else
5728 {
5729 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5730 {
5731 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5732 }
5733 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5734 }
5735 }
5736 else
5737 {
5738 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
5739 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
5740 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
5741 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5742 {
5743 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5744 {
5745 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5746 }
5747 }
5748 else
5749 {
5750 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5751 }
5752 }
5753 }
5754 #endif
5755 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5756
5757 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5758 {
5759 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
5760 }
5761
5762 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
5763 {
5764
5765 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
5766
5767 _HAL_HVD_Entry();
5768 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
5769 _HAL_HVD_Release();
5770
5771 }
5772
5773 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
5774 HVD_EX_MSG_DBG("success\n");
5775
5776 return eRet;
5777 }
5778
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5779 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5780 {
5781 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5782 MS_U32 u32Addr = 0;
5783 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5784 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5785
5786 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5787
5788 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5789 {
5790 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5791
5792 if (E_HVD_RETURN_SUCCESS != eRet)
5793 {
5794 return eRet;
5795 }
5796 }
5797
5798 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5799
5800 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5801 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5802 {
5803 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5804
5805 if (E_HVD_RETURN_SUCCESS != eRet)
5806 {
5807 return eRet;
5808 }
5809 }
5810
5811 u32Addr = pInfo->u32Staddr;
5812
5813 if (pInfo->bRVBrokenPacket)
5814 {
5815 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5816 }
5817
5818 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5819 {
5820 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5821 }
5822 else
5823 {
5824 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5825 }
5826
5827 if (E_HVD_RETURN_SUCCESS != eRet)
5828 {
5829 return eRet;
5830 }
5831
5832 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5833 {
5834 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5835 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5836
5837 if (E_HVD_RETURN_SUCCESS != eRet)
5838 {
5839 return eRet;
5840 }
5841 }
5842
5843 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5844
5845 // do not add local pointer
5846 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5847 {
5848 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5849
5850 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5851 (u32PacketStAddr <
5852 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5853 {
5854 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5855 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5856 }
5857 else
5858 {
5859 //null packet
5860 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5861 pCtrl->LastNal.u32NalSize = 0;
5862 }
5863 }
5864 else
5865 {
5866 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5867 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5868 }
5869
5870 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5871 pCtrl->u32BBUPacketCnt++;
5872
5873 return eRet;
5874 }
5875
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5876 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5877 {
5878 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5879 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5880 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
5881 if(bCurrentStatus == bEnable)
5882 return;
5883
5884 if (bEnable)
5885 {
5886 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5887 }
5888 else
5889 {
5890 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5891 }
5892 }
5893
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5894 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5895 {
5896 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5897 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5898
5899 if (bEnable)
5900 {
5901 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5902 }
5903 else
5904 {
5905 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5906 }
5907 }
5908
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)5909 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
5910 {
5911 MS_U32 u32RB = 0;
5912 switch(eISRType)
5913 {
5914 case E_HWDEC_ISR_HVD:
5915 u32RB = REG_HVD_BASE;
5916 break;
5917 #if SUPPORT_EVD
5918 case E_HWDEC_ISR_EVD:
5919 u32RB = REG_EVD_BASE;
5920 break;
5921 #endif
5922 #if SUPPORT_G2VP9
5923 case E_HWDEC_ISR_G2VP9:
5924 break;
5925 #endif
5926 default:
5927 break;
5928 }
5929 if(u32RB)
5930 {
5931 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5932 }
5933 }
5934
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5935 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5936 {
5937 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5938 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5939
5940 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5941 }
5942
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)5943 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
5944 {
5945 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5946 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5947
5948 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
5949 {
5950 return FALSE;
5951 }
5952 else
5953 {
5954 return TRUE;
5955 }
5956 }
5957
HAL_HVD_EX_IsAlive(MS_U32 u32Id)5958 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
5959 {
5960 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5961
5962 if (pCtrl)
5963 {
5964 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
5965 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
5966 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
5967 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
5968 {
5969 return FALSE;
5970 }
5971 else
5972 {
5973 return TRUE;
5974 }
5975 }
5976 else
5977 {
5978 return FALSE;
5979 }
5980 }
5981
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)5982 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
5983 {
5984 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5985 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5986 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5987
5988 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5989 {
5990 HAL_HVD_EX_ReadMemory();
5991
5992 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
5993 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
5994
5995 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
5996 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
5997 }
5998
5999 return TRUE;
6000 }
6001
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)6002 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
6003 {
6004 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6005 HVD_EX_Drv_Ctrl *pCtrl = NULL;
6006 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6007 MS_U32 u32Data;
6008 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6009
6010 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
6011
6012 HAL_HVD_EX_FlushMemory();
6013 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
6014 {
6015 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
6016 pCtrl->LastNal.u32NalAddr = u32Data;
6017 pCtrl->LastNal.u32NalSize = 0;
6018 }
6019
6020 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
6021 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
6022
6023 return TRUE;
6024 }
6025
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)6026 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
6027 {
6028 if (bEnable)
6029 {
6030 if (HAL_VPU_EX_IsEVDR2())
6031 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6032 else
6033 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
6034 }
6035 else
6036 {
6037 #if defined (__aeon__)
6038 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6039 #else // defined (__mips__)
6040 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
6041 #endif
6042 }
6043 }
6044
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)6045 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
6046 {
6047 return 0;
6048 }
6049
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)6050 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
6051 {
6052 return;
6053 }
6054
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)6055 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
6056 {
6057 //if( u16Clock == 0 )
6058 return 216; //140;
6059 //if( )
6060 }
6061
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)6062 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
6063 {
6064 //MS_BOOL bBitMIU1 = FALSE;
6065 //MS_BOOL bCodeMIU1 = FALSE;
6066 MS_U8 u8BitMiuSel = 0;
6067 MS_U8 u8CodeMiuSel = 0;
6068 MS_U32 u32BitStartOffset;
6069 MS_U32 u32CodeStartOffset;
6070 //MS_U8 u8MiuSel;
6071 //MS_U32 u32StartOffset;
6072 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6073 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6074 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6075 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
6076
6077 #if HVD_ENABLE_MVC
6078 if(HAL_HVD_EX_CheckMVCID(u32Id))
6079 {
6080 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
6081 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
6082 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
6083 {
6084 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
6085 }
6086 }
6087 #endif /// HVD_ENABLE_MVC
6088
6089 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6090 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6091
6092
6093
6094
6095 if (u8BitMiuSel != u8CodeMiuSel)
6096 {
6097 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
6098 BDMA_Result bdmaRlt;
6099 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6100
6101 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6102 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
6103 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6104
6105 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
6106
6107 if (E_BDMA_OK != bdmaRlt)
6108 {
6109 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
6110 }
6111 #else
6112 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6113
6114 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6115 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
6116 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6117
6118 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
6119 #endif
6120 }
6121
6122 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
6123
6124 HAL_HVD_EX_FlushMemory();
6125
6126 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6127 {
6128 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
6129 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
6130 }
6131 else
6132 {
6133 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
6134
6135 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
6136 }
6137 }
6138
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)6139 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
6140 {
6141 if (bEnable)
6142 {
6143 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
6144 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
6145 }
6146 else
6147 {
6148 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
6149 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
6150 }
6151 }
6152
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)6153 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
6154 {
6155 MS_U32 tmp1 = 0;
6156 MS_U32 tmp2 = 0;
6157 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6158
6159 HAL_HVD_EX_ReadMemory();
6160
6161 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
6162 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
6163
6164 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6165 {
6166 MS_U32 u32Tmp = u32UartCtrl;
6167
6168 HVD_EX_MSG_DBG("\n");
6169 u32UartCtrl = 0; // turn off debug message to prevent other function prints
6170 printf("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
6171 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
6172
6173 printf("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
6174 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
6175 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
6176 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
6177
6178 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
6179 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
6180 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
6181
6182 printf("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
6183 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
6184 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
6185 _HVD_EX_GetESLevel(u32Id));
6186
6187 printf("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
6188 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
6189 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
6190 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
6191 printf
6192 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
6193 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
6194 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
6195 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
6196 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
6197 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
6198 pShm->ModeStatus.bShowOneField);
6199
6200 u32UartCtrl = u32Tmp; // recover debug level
6201 }
6202 }
6203
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)6204 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
6205 {
6206 MS_U8 *u32Addr = NULL;
6207 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6208 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6209
6210 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6211 {
6212 return;
6213 }
6214
6215 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
6216
6217 *u32NalSize = *(u32Addr + 2) & 0x1f;
6218 *u32NalSize <<= 8;
6219 *u32NalSize |= *(u32Addr + 1) & 0xff;
6220 *u32NalSize <<= 8;
6221 *u32NalSize |= *(u32Addr) & 0xff;
6222
6223 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
6224 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
6225 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
6226 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
6227 }
6228
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)6229 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
6230 {
6231 MS_U32 u32CurIdx = 0;
6232 MS_BOOL bFinished = FALSE;
6233 MS_U32 u32NalOffset = 0;
6234 MS_U32 u32NalSize = 0;
6235 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6236
6237 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
6238 {
6239 return;
6240 }
6241
6242 u32CurIdx = u32StartIdx;
6243
6244 do
6245 {
6246 if (u32CurIdx == u32EndIdx)
6247 {
6248 bFinished = TRUE;
6249 }
6250
6251 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
6252
6253 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
6254 {
6255 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
6256 }
6257
6258 u32CurIdx++;
6259
6260 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6261 {
6262 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
6263 }
6264 } while (bFinished == TRUE);
6265 }
6266
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)6267 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
6268 {
6269 MS_U32 i = 0;
6270 MS_U32 value = 0;
6271
6272 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6273 {
6274 HVD_EX_MSG_DBG("\n");
6275
6276 for (i = 0; i <= u32Num; i++)
6277 {
6278 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
6279 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
6280 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
6281
6282 if (value == 0)
6283 {
6284 break;
6285 }
6286
6287 printf(" %08x", value);
6288
6289 if (((i % 8) + 1) == 8)
6290 {
6291 printf(" |%u\n", i + 1);
6292 }
6293 }
6294
6295 printf("\nHVD Dump HW status End: total number:%u\n", i);
6296 }
6297 }
6298
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)6299 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
6300 {
6301 if (pDrvCtrl)
6302 {
6303 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
6304 }
6305 }
6306
6307 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)6308 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
6309 {
6310 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
6311 }
6312
HAL_HVD_EX_GetView(MS_U32 u32Id)6313 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
6314 {
6315 if( (0xFF & (u32Id >> 8)) == 0x10)
6316 return E_VDEC_EX_MAIN_VIEW;
6317 else
6318 return E_VDEC_EX_SUB_VIEW;
6319 }
6320 #endif ///HVD_ENABLE_MVC
6321
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)6322 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
6323 {
6324 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
6325 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
6326 return;
6327 }
6328
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)6329 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
6330 {
6331 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
6332 return;
6333 }
6334
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)6335 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
6336 {
6337 MS_U64 _hw_max_pixel = 0;
6338 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
6339
6340 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
6341 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
6342 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
6343 }
6344
6345
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)6346 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
6347 {
6348 #if 1
6349 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6350 MS_U16 u16QNum = pShm->u16DispQNumb;
6351 MS_U16 u16QPtr = pShm->u16DispQPtr;
6352 // MS_U16 u16QSize = pShm->u16DispQSize;
6353 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
6354 MS_U32 u32DispQNum = 0;
6355 #if HVD_ENABLE_MVC
6356 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
6357
6358 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6359 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
6360
6361 if(bMVC || bDolbyVision)
6362 {
6363 #if 0
6364 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
6365 {
6366 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
6367 }
6368 #endif
6369
6370 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
6371 //search the next frame to display
6372 while (u16QNum > 0)
6373 {
6374 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
6375 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
6376 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6377
6378 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
6379 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6380 {
6381 /// For MVC. Output views after the pair of (base and depend) views were decoded.
6382 /// Check the depned view was initial when Output the base view.
6383 if((u16QPtr%2) == 0)
6384 {
6385 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
6386 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
6387 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
6388 {
6389 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
6390 ///printf("Return NULL.\n");
6391 break;
6392 }
6393 }
6394 u32DispQNum++;
6395 }
6396
6397 u16QNum--;
6398 //go to next frame in the dispQ
6399 u16QPtr++;
6400
6401 if (u16QPtr >= pShm->u16DispQSize)
6402 {
6403 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
6404 }
6405 }
6406 }
6407 else
6408 #endif ///HVD_ENABLE_MVC
6409 {
6410 #if 0
6411 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
6412 {
6413 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
6414 }
6415 #endif
6416 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
6417 //search the next frame to display
6418 while (u16QNum != 0)
6419 {
6420 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6421
6422 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
6423 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6424 {
6425 u32DispQNum++;
6426 }
6427
6428 u16QNum--;
6429 //go to next frame in the dispQ
6430 u16QPtr++;
6431
6432 if (u16QPtr == pShm->u16DispQSize)
6433 {
6434 u16QPtr = 0; //wrap to the begin
6435 }
6436 }
6437 }
6438
6439 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
6440 return u32DispQNum;
6441 #else
6442 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
6443 return pShm->u16DispQNumb;
6444 #endif
6445 }
6446
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)6447 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
6448 {
6449 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6450 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
6451 (u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
6452 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6453 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
6454 #if SUPPORT_G2VP9 && defined(VDEC3)
6455 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
6456 #else // Not using G2 VP9 implies using Mstar EVD VP9
6457 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6458 #endif
6459 else
6460 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
6461 }
6462
6463 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)6464 void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
6465 {
6466 #ifdef CONFIG_MSTAR_CLKM
6467 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD, bEnable);
6468 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_PPU, bEnable);
6469 #else
6470 if (bEnable)
6471 {
6472 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6473 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6474 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6475 }
6476 else
6477 {
6478 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6479 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6480 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6481 }
6482
6483 switch (pHVDHalContext->u32EVDClockType)
6484 {
6485 case 576:
6486 {
6487 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6488 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6489 break;
6490 }
6491 case 532:
6492 {
6493 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
6494 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
6495 break;
6496 }
6497 case 456:
6498 {
6499 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6500 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6501 _HVD_WriteWordMask(REG_EVDPLL_LOOP_DIV_SECOND, REG_EVDPLL_LOOP_DIV_SECOND_456MHZ, REG_EVDPLL_LOOP_DIV_SECOND_MASK);
6502 break;
6503 }
6504 case 466:
6505 {
6506 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6507 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
6508 break;
6509 }
6510 case 480:
6511 {
6512 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
6513 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6514 break;
6515 }
6516 case 384:
6517 {
6518 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
6519 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
6520 break;
6521 }
6522 case 320:
6523 {
6524 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
6525 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
6526 break;
6527 }
6528 case 240:
6529 {
6530 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
6531 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6532 break;
6533 }
6534 case 192:
6535 {
6536 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
6537 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
6538 break;
6539 }
6540 default:
6541 {
6542 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6543 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6544 break;
6545 }
6546 }
6547 #endif
6548 #ifdef CONFIG_MSTAR_SRAMPD
6549 if (bEnable)
6550 {
6551 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6552 HVD_Delay_ms(1);
6553 }
6554 else
6555 {
6556 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6557 HVD_Delay_ms(1);
6558 }
6559 #endif
6560 return;
6561 }
6562
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)6563 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
6564 {
6565 #ifndef VDEC3
6566 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6567 #endif
6568 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6569 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6570 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6571
6572 #ifdef VDEC3
6573 if (0 == pCtrl->u32BBUId)
6574 #else
6575 if (0 == u8TaskId)
6576 #endif
6577 {
6578 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
6579 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6580 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)) & (~HVD_REG_BBU_TSP_INPUT));
6581 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)));
6582 }
6583 else
6584 {
6585 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
6586 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6587 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)) & (~HVD_REG_BBU_TSP_INPUT_BS2));
6588 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)));
6589 }
6590
6591 return;
6592 }
6593
HAL_EVD_EX_DeinitHW(MS_U32 u32Id)6594 MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id)
6595 {
6596 MS_U16 u16Timeout = 1000;
6597 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6598 MS_BOOL isVP8Used = FALSE;
6599 MS_BOOL isAECUsed = FALSE;
6600 MS_BOOL isAVCUsed = FALSE;
6601 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
6602
6603 if(TRUE == HAL_VPU_EX_EVDInUsed())
6604 {
6605 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6606 {
6607 HAL_AEC_PowerCtrl(FALSE);
6608 }
6609 return FALSE;
6610 }
6611 else if(!isAVCUsed)//no AVC/EVD use , close EVD power
6612 {
6613 _HVD_EX_SetMIUProtectMask(TRUE);
6614
6615 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
6616
6617 while (u16Timeout)
6618 {
6619 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
6620 {
6621 break;
6622 }
6623 u16Timeout--;
6624 }
6625
6626 HAL_EVD_EX_PowerCtrl(u32Id, FALSE);
6627
6628 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6629 {
6630 HAL_AEC_PowerCtrl(FALSE);
6631 }
6632
6633 _HVD_EX_SetMIUProtectMask(FALSE);
6634
6635 return TRUE;
6636 }
6637
6638 return FALSE;
6639
6640 }
6641 #endif
6642
6643 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)6644 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
6645 {
6646 if (bEnable)
6647 {
6648 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6649 }
6650 else
6651 {
6652 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6653 }
6654
6655 switch (pHVDHalContext->u32VP9ClockType)
6656 {
6657 case 432:
6658 {
6659 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6660 break;
6661 }
6662 case 384:
6663 {
6664 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6665 break;
6666 }
6667 case 345:
6668 {
6669 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6670 break;
6671 }
6672 case 320:
6673 {
6674 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6675 break;
6676 }
6677 case 288:
6678 {
6679 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6680 break;
6681 }
6682 case 240:
6683 {
6684 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6685 break;
6686 }
6687 case 216:
6688 {
6689 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6690 break;
6691 }
6692 case 172:
6693 {
6694 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
6695 break;
6696 }
6697 default:
6698 {
6699 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6700 break;
6701 }
6702 }
6703
6704 return;
6705 }
6706
HAL_VP9_EX_DeinitHW(void)6707 MS_BOOL HAL_VP9_EX_DeinitHW(void)
6708 {
6709 MS_U16 u16Timeout = 1000;
6710
6711 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6712
6713 while (u16Timeout)
6714 {
6715 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6716 {
6717 break;
6718 }
6719 u16Timeout--;
6720 }
6721
6722 HAL_VP9_EX_PowerCtrl(FALSE);
6723
6724 return TRUE;
6725 }
6726 #endif
6727
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6728 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6729 {
6730 return TRUE;
6731 }
6732
HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)6733 void HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)
6734 {
6735 MS_VIRT u32StAddr = 0;
6736 MS_U8 u8BitMiuSel = 0;
6737 MS_U8 u8CodeMiuSel = 0;
6738 MS_U8 u8TmpMiuSel = 0;
6739 MS_U32 u32BitStartOffset;
6740 MS_U32 u32CodeStartOffset;
6741
6742 #ifndef VDEC3
6743 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6744 #endif
6745 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6746 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6747 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6748 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6749
6750 _HAL_HVD_Entry();
6751
6752 if (pCtrl == NULL)
6753 {
6754 _HAL_HVD_Return();
6755 }
6756
6757 MS_BOOL bNalTblAlreadySet = FALSE;
6758 VPU_EX_TaskInfo taskInfo;
6759 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
6760 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
6761
6762 bNalTblAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
6763
6764
6765
6766 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6767 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6768
6769 if (u8BitMiuSel != u8CodeMiuSel)
6770 {
6771 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
6772 }
6773 else
6774 {
6775 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
6776 }
6777
6778 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6779 {
6780 #ifdef VDEC3
6781 if (!_HAL_EX_BBU_VP8_InUsed())
6782 #endif
6783 {
6784 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
6785
6786 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
6787 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
6788 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6789
6790 u32StAddr += VP8_BBU_TBL_SIZE;
6791
6792 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
6793 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
6794 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6795 }
6796
6797 _HAL_HVD_Return();
6798 }
6799
6800 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
6801
6802 #ifdef VDEC3
6803 if (!bNalTblAlreadySet)
6804 {
6805 if (pCtrl->u32BBUId == 0)
6806 {
6807 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
6808 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
6809 // -1 is for NAL_TAB_LEN counts from zero.
6810 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6811 }
6812 else
6813 {
6814 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
6815 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
6816 // -1 is for NAL_TAB_LEN counts from zero.
6817 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6818 }
6819 }
6820 #else
6821 if (0 == u8TaskId)
6822 {
6823 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
6824 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
6825 // -1 is for NAL_TAB_LEN counts from zero.
6826 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6827 }
6828 else
6829 {
6830 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
6831 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
6832 // -1 is for NAL_TAB_LEN counts from zero.
6833 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6834 }
6835 #endif
6836
6837
6838 #if (HVD_ENABLE_MVC)
6839 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
6840 {
6841 /// Used sub stream to record sub view data.
6842 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
6843 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
6844
6845 if (u8BitMiuSel != u8CodeMiuSel)
6846 {
6847 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
6848 }
6849 else
6850 {
6851 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
6852 }
6853
6854 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
6855 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
6856 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
6857 // -1 is for NAL_TAB_LEN counts from zero.
6858 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
6859 }
6860 #endif
6861
6862 if (!bNalTblAlreadySet)
6863 {
6864 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
6865 }
6866
6867 _HAL_HVD_Return();
6868 }
6869
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)6870 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6871 {
6872 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6873
6874 if(pCtrl->InitParams.u16ChipECONum == 0)
6875 return FALSE;
6876 else
6877 return TRUE;
6878 }
6879
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6880 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6881 {
6882
6883 }
6884
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6885 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6886 {
6887
6888 }
6889 #endif
6890