1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #include <string.h>
101 #include "drvHVD_Common.h"
102
103 // Internal Definition
104 #include "drvHVD_def.h"
105 #include "fwHVD_if.h"
106 #include "halVPU_EX.h"
107 #include "halHVD_EX.h"
108 #include "regHVD_EX.h"
109
110 //-------------------------------------------------------------------------------------------------
111 // Driver Compiler Options
112 //-------------------------------------------------------------------------------------------------
113 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
114 #include "ULog.h"
115 #define VPRINTF(format,args...) ULOGI("VDEC", format, ##args)
116
117 //-------------------------------------------------------------------------------------------------
118 // Local Defines
119 //-------------------------------------------------------------------------------------------------
120 #define RV_VLC_TABLE_SIZE 0x20000
121 /* Add for Mobile Platform by Ted Sun */
122 //#define HVD_DISPQ_PREFETCH_COUNT 2
123 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
124 #define VPU_QMEM_BASE 0x20000000UL
125
126 //max support pixel(by chip capacity)
127 #define HVD_HW_MAX_PIXEL (1920*1088*61000ULL) // FHD@60p
128 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
129 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
130
131 #if 0
132 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
133 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
134 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
135 static MS_U16 _u16DispQPtr = 0;
136 #endif
137
138 #define IS_TASK_ALIVE(id) ((id) != -1)
139 #ifndef UNUSED
140 #define UNUSED(x) (void)(x)
141 #endif
142
143
144 //---------------------------------- Mutex settings -----------------------------------------
145 #if HAL_HVD_ENABLE_MUTEX_PROTECT
146 #define _HAL_HVD_MutexCreate() \
147 do \
148 { \
149 if (s32HVDMutexID < 0) \
150 { \
151 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
152 } \
153 } while (0)
154
155 #define _HAL_HVD_MutexDelete() \
156 do \
157 { \
158 if (s32HVDMutexID >= 0) \
159 { \
160 OSAL_HVD_MutexDelete(s32HVDMutexID); \
161 s32HVDMutexID = -1; \
162 } \
163 } while (0)
164
165 #define _HAL_HVD_Entry() \
166 do \
167 { \
168 if (s32HVDMutexID >= 0) \
169 { \
170 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
171 { \
172 VPRINTF("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
173 } \
174 } \
175 } while (0)
176
177 #define _HAL_HVD_Return(_ret_) \
178 do \
179 { \
180 if (s32HVDMutexID >= 0) \
181 { \
182 OSAL_HVD_MutexRelease(s32HVDMutexID); \
183 } \
184 return _ret_; \
185 } while(0)
186
187 #define _HAL_HVD_Release() \
188 do \
189 { \
190 if (s32HVDMutexID >= 0) \
191 { \
192 OSAL_HVD_MutexRelease(s32HVDMutexID); \
193 } \
194 } while (0)
195 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
196
197 #define _HAL_HVD_MutexCreate()
198 #define _HAL_HVD_MutexDelete()
199 #define _HAL_HVD_Entry()
200 #define _HAL_HVD_Return(_ret) {return _ret;}
201 #define _HAL_HVD_Release()
202
203 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
204
205 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
206 #define IS_TASK_ALIVE(id) ((id) != -1)
207 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
208
209 //------------------------------ MIU SETTINGS ----------------------------------
210 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
211 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
212 #define _MaskMiuReq_HVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(2))
213 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(1))
214
215 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
216 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
217 #define _MaskMiu1Req_HVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(2))
218 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(1))
219
220 #define HVD_MVD_RW_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0)
221 #define HVD_MVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0)
222 #define HVD_HVD_RW_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0)
223 #define HVD_HVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(1)) == 0)
224
225 #define HVD_MVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == BIT(4))
226 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
227 #define HVD_HVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(2)) == BIT(2))
228 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(1)) == BIT(1))
229
230 #if SUPPORT_EVD
231 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK+1, m, BIT(2))
232 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK+1, m, BIT(2))
233 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK+1, m, BIT(2))
234 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK+1, m, BIT(2))
235
236 #define HVD_EVD_RW_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(10)) == 0)
237 #define HVD_EVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(10)) == 0)
238 #define HVD_EVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(10)) == BIT(10))
239 #define HVD_EVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(10)) == BIT(10))
240 #endif
241
242 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
243 do \
244 { \
245 if (HVD_##miu_clients##_ON_MIU0 == 1) \
246 { \
247 _MaskMiuReq_##miu_clients(mask); \
248 } \
249 else \
250 { \
251 _MaskMiu1Req_##miu_clients(mask); \
252 } \
253 } while (0)
254
255 // check RM is supported or not
256 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
257 #ifdef VDEC3
258 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 4
259 #else
260 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
261 #endif
262 //-------------------------------------------------------------------------------------------------
263 // Local Structures
264 //-------------------------------------------------------------------------------------------------
265
266 //-------------------------------------------------------------------------------------------------
267 // Local Functions Prototype
268 //-------------------------------------------------------------------------------------------------
269 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
270 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
271 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
272 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
273 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
274 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
275 static MS_U32 _HVD_EX_GetPC(void);
276 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
277 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
278 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
279 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
280 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
281 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
282 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
283 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
284 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
285 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
286 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
287 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
288 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
289 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
290 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
291 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
292 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
293 #if SUPPORT_EVD
294 static void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable);
295 static MS_BOOL HAL_EVD_EX_DeinitHW(void);
296 #endif
297 #if SUPPORT_G2VP9 && defined(VDEC3)
298 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
299 #endif
300 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
301 #if SUPPORT_G2VP9 && defined(VDEC3)
302 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
303 #endif
304 //-------------------------------------------------------------------------------------------------
305 // Global Variables
306 //-------------------------------------------------------------------------------------------------
307 #if defined (__aeon__)
308 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
309 #else
310 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
311 #endif
312 #if HAL_HVD_ENABLE_MUTEX_PROTECT
313 MS_S32 s32HVDMutexID = -1;
314 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
315 #endif
316
317
318 #define HVD_EX_STACK_SIZE 4096
319 //-------------------------------------------------------------------------------------------------
320 // Local Variables
321 //-------------------------------------------------------------------------------------------------
322 typedef struct
323 {
324
325 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
326 MS_U8 g_hvd_nal_fill_pair[2][8];
327 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
328 MS_U16 _u16DispQPtr;
329 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
330
331 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
332 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
333 MS_U32 u32VPUClockType;
334 MS_U32 u32HVDClockType;//160
335 #if SUPPORT_EVD
336 MS_U32 u32EVDClockType;
337 #endif
338 #if SUPPORT_G2VP9 && defined(VDEC3)
339 MS_U32 u32VP9ClockType;
340 #endif
341 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
342
343 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
344 MS_BOOL g_RstFlag;
345 MS_U64 u64pts_real;
346 MS_PHY u32VP8BBUWptr;
347 MS_PHY u32EVDBBUWptr;
348 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
349 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
350 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
351 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
352 //pre_set
353 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
354 } HVD_Hal_CTX;
355
356 HVD_Hal_CTX* pHVDHalContext = NULL;
357 HVD_Hal_CTX gHVDHalContext;
358 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
359
360 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
361 {
362 {FALSE},
363 {FALSE},
364 {FALSE},
365 #ifdef VDEC3
366 {FALSE},
367 #endif
368 };
369
370 //-------------------------------------------------------------------------------------------------
371 // Debug Functions
372 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)373 void HVD_EX_SetRstFlag(MS_BOOL bRst)
374 {
375 pHVDHalContext->g_RstFlag = bRst;
376 }
HVD_EX_GetRstFlag(void)377 MS_BOOL HVD_EX_GetRstFlag(void)
378 {
379 return pHVDHalContext->g_RstFlag;
380 }
381
382 //-------------------------------------------------------------------------------------------------
383 // Local Functions
384 //-------------------------------------------------------------------------------------------------
385
386 #ifdef VDEC3
387 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
388 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)389 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
390 {
391
392 MS_U32 ret = TRUE;
393 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
394
395 if(pCtrl == NULL || pstTaskInfo == NULL)
396 return FALSE;
397
398 pstTaskInfo->u32Id = u32Id;
399
400 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
401 {
402 case E_HVD_INIT_HW_RM:
403 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
404 break;
405 case E_HVD_INIT_HW_VP8:
406 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
407 break;
408 case E_HVD_INIT_HW_MVC:
409 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
410 break;
411 case E_HVD_INIT_HW_HEVC:
412 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
413 break;
414 #if SUPPORT_MSVP9
415 case E_HVD_INIT_HW_VP9:
416 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
417 break;
418 #endif
419 #if SUPPORT_G2VP9
420 case E_HVD_INIT_HW_VP9:
421 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
422 break;
423 #endif
424 default:
425 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
426 break;
427 }
428
429 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
430
431 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
432 {
433 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
434 }
435 else
436 {
437 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
438 }
439
440 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
441
442 #ifdef SUPPORT_EVD
443 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
444 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
445 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
446 #endif
447 return ret;
448
449 }
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)450 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
451 {
452 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
453 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
454 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
455 _HAL_HVD_Entry();
456
457 if(pCtrl == NULL)
458 _HAL_HVD_Return(ret);
459
460 VPU_EX_TaskInfo taskInfo;
461 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
462
463 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
464
465 taskInfo.u8HalId = u8Idx;
466 ret = HAL_VPU_EX_GetBBUId(u32Id,&taskInfo, pCtrl->bNStreamMode);
467
468 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
469 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
470
471 _HAL_HVD_Return(ret);
472 }
473
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)474 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
475 {
476 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
477 MS_BOOL ret = FALSE;
478 _HAL_HVD_Entry();
479
480 if(pCtrl == NULL)
481 _HAL_HVD_Return(ret);
482 VPU_EX_TaskInfo taskInfo;
483 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
484
485 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
486
487 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
488
489 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
490 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
491
492 _HAL_HVD_Return(ret);
493 }
494 #endif
495
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)496 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
497 {
498 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
499 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
500 pstHVDStream->s32HvdPpTaskId = -1;
501 }
502
_HVD_EX_Context_Init_HAL(void)503 static void _HVD_EX_Context_Init_HAL(void)
504 {
505 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
506 pHVDHalContext->u32VPUClockType = 432;
507 pHVDHalContext->u32HVDClockType = 384;
508 #if SUPPORT_EVD
509 pHVDHalContext->u32EVDClockType = 480;
510 #endif
511 #if SUPPORT_G2VP9 && defined(VDEC3)
512 pHVDHalContext->u32VP9ClockType = 384;
513 #endif
514 #ifdef VDEC3
515 MS_U8 i;
516
517 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
518 {
519 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
520 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
521 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
522 }
523 #else
524 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
525 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
526 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
527 #endif
528 }
529
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)530 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
531 {
532 MS_U16 u16Ret = 0;
533 #if (HVD_ENABLE_MVC || (!VDEC3))
534 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
535 #endif
536 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
537 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
538 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
539 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
540
541 #if HVD_ENABLE_MVC
542 if(HAL_HVD_EX_CheckMVCID(u32Id))
543 {
544 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
545 }
546 #endif /// HVD_ENABLE_MVC
547
548 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
549 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
550
551 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
552 {
553 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
554 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
555 }
556 else
557 #ifdef VDEC3
558 if (0 == pCtrl->u32BBUId)
559 #else
560 if (0 == u8TaskId)
561 #endif
562 {
563 //if(pCtrl->InitParams.bColocateBBUMode)
564 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
565 u16Ret = pShm->u32ColocateBBUReadPtr;
566 else
567 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
568 }
569 else
570 {
571 //if(pCtrl->InitParams.bColocateBBUMode)
572 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
573 u16Ret = pShm->u32ColocateBBUReadPtr;
574 else
575 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
576 }
577
578 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
579 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
580
581 return u16Ret;
582 }
583
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)584 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
585 {
586 MS_U16 u16Ret = 0;
587 #if (HVD_ENABLE_MVC || (!VDEC3))
588 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
589 #endif
590 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
591 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
592 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
593 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
594
595 #if HVD_ENABLE_MVC
596 if (HAL_HVD_EX_CheckMVCID(u32Id))
597 {
598 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
599 }
600 #endif /// HVD_ENABLE_MVC
601 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
602 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
603
604 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
605 {
606 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
607 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
608 }
609 else
610 #ifdef VDEC3
611 if (0 == pDrvCtrl->u32BBUId)
612 #else
613 if (0 == u8TaskId)
614 #endif
615 {
616 //if(pDrvCtrl->InitParams.bColocateBBUMode)
617 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
618 u16Ret = pShm->u32ColocateBBUWritePtr;
619 else
620 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
621 }
622 else
623 {
624 //if(pDrvCtrl->InitParams.bColocateBBUMode)
625 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
626 u16Ret = pShm->u32ColocateBBUWritePtr;
627 else
628 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
629 }
630
631 return u16Ret;
632 }
633
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)634 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
635 {
636 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
637 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
638
639 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
640 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
641 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
642 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
643 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
644 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
645 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
646 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
647 }
648
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)649 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
650 {
651 #if (HVD_ENABLE_MVC || (!VDEC3))
652 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
653 #endif
654 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
655 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
656 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
657 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
658
659 #if HVD_ENABLE_MVC
660 if (HAL_HVD_EX_CheckMVCID(u32Id))
661 {
662 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
663 }
664 #endif /// HVD_ENABLE_MVC
665
666 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
667 {
668 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
669 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
670 }
671 else
672 #ifdef VDEC3
673 if (0 == pCtrl->u32BBUId)
674 #else
675 if (0 == u8TaskId)
676 #endif
677 {
678 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
679 //if(pCtrl->InitParams.bColocateBBUMode)
680 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
681 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
682 }
683 else
684 {
685 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
686 //if(pCtrl->InitParams.bColocateBBUMode)
687 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
688 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
689 }
690
691 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
692 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
693
694 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
695 }
696
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)697 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
698 {
699 MS_BOOL bResult = TRUE;
700 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
701 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
702
703 switch (u8MBox)
704 {
705 case E_HVD_HI_0:
706 {
707 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
708 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
709 break;
710 }
711 case E_HVD_HI_1:
712 {
713 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
714 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
715 break;
716 }
717 case E_HVD_VPU_HI_0:
718 {
719 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
720 break;
721 }
722 case E_HVD_VPU_HI_1:
723 {
724 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
725 break;
726 }
727 default:
728 {
729 bResult = FALSE;
730 break;
731 }
732 }
733
734 return bResult;
735 }
736
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)737 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
738 {
739 MS_BOOL bResult = TRUE;
740 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
741 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
742
743 switch (u8MBox)
744 {
745 case E_HVD_HI_0:
746 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
747 break;
748 case E_HVD_HI_1:
749 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
750 break;
751 case E_HVD_RISC_0:
752 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
753 break;
754 case E_HVD_RISC_1:
755 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
756 break;
757 case E_HVD_VPU_HI_0:
758 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
759 break;
760 case E_HVD_VPU_HI_1:
761 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
762 break;
763 case E_HVD_VPU_RISC_0:
764 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
765 break;
766 case E_HVD_VPU_RISC_1:
767 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
768 break;
769 default:
770 break;
771 }
772
773 return bResult;
774 }
775
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)776 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
777 {
778 MS_BOOL bResult = TRUE;
779 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
780 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
781
782 switch (u8MBox)
783 {
784 case E_HVD_HI_0:
785 {
786 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
787 break;
788 }
789 case E_HVD_HI_1:
790 {
791 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
792 break;
793 }
794 case E_HVD_RISC_0:
795 {
796 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
797 break;
798 }
799 case E_HVD_RISC_1:
800 {
801 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
802 break;
803 }
804 case E_HVD_VPU_RISC_0:
805 {
806 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
807 break;
808 }
809 case E_HVD_VPU_RISC_1:
810 {
811 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
812 break;
813 }
814 default:
815 {
816 bResult = FALSE;
817 break;
818 }
819 }
820
821 return bResult;
822 }
823
824 #if 0
825 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
826 {
827 switch (u8MBox)
828 {
829 case E_HVD_RISC_0:
830 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
831 break;
832 case E_HVD_RISC_1:
833 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
834 break;
835 case E_HVD_VPU_RISC_0:
836 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
837 break;
838 case E_HVD_VPU_RISC_1:
839 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
840 break;
841 default:
842 break;
843 }
844 }
845 #endif
846
_HVD_EX_GetPC(void)847 static MS_U32 _HVD_EX_GetPC(void)
848 {
849 MS_U32 u32PC = 0;
850 u32PC = HAL_VPU_EX_GetProgCnt();
851 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
852 return u32PC;
853 }
854
_HVD_EX_GetESWritePtr(MS_U32 u32Id)855 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
856 {
857 MS_U32 u32Data = 0;
858 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
859 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
860
861 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
862 {
863 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
864
865 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
866 {
867 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
868
869 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
870 }
871 }
872 else
873 {
874 #if HVD_ENABLE_MVC
875 MS_U8 u8ViewIdx = 0;
876 if(HAL_HVD_EX_CheckMVCID(u32Id))
877 {
878 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
879 }
880 if(u8ViewIdx != 0) /// 2nd ES ptr.
881 {
882 u32Data = pShm->u32ES2WritePtr;
883 }
884 else
885 {
886 u32Data = pShm->u32ESWritePtr;
887 }
888 #else
889 u32Data = pShm->u32ESWritePtr;
890 #endif
891 }
892
893 return u32Data;
894 }
895
896 #define NAL_UNIT_LEN_BITS 21
897 #define NAL_UNIT_OFT_BITS 30
898 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
899 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
900 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
901
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)902 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
903 {
904 MS_U32 u32Data = 0;
905 MS_U8 u8TaskId = 0;
906 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
907 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
908 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
909 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
910 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
911
912 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
913 #if HVD_ENABLE_MVC
914 if(HAL_HVD_EX_CheckMVCID(u32Id))
915 {
916 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
917 }
918 #endif /// HVD_ENABLE_MVC
919
920 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
921 {
922 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
923 {
924 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
925 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
926 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
927 MS_U32 *u32Adr;
928 MS_U32 u32Tmp;
929
930 if (u16ReadPtr == u16WritePtr)
931 {
932 u32Data = _HVD_EX_GetESWritePtr(u32Id);
933 }
934 else
935 {
936 if (u16ReadPtr)
937 u16ReadPtr--;
938 else
939 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
940
941 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
942
943 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
944 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
945 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
946 u32Data = u32Data | u32Tmp;
947
948 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
949 //while(1);
950 }
951 goto EXIT;
952 }
953 // set reg_poll_nal_rptr 0
954 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
955 // set reg_poll_nal_rptr 1
956 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
957
958 // read reg_nal_rptr_hi
959 #ifdef VDEC3
960 if (0 == pCtrl->u32BBUId)
961 #else
962 if (0 == u8TaskId)
963 #endif
964 {
965 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
966 u32Data >>= 6;
967 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
968 }
969 else
970 {
971 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
972 u32Data >>= 6;
973 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
974 }
975
976 u32Data <<= 3; // unit
977
978 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
979 {
980 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
981
982 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
983 {
984 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
985 u32Data = u32ESWptr;
986 }
987 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
988 {
989 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
990 u32Data = u32ESWptr;
991 }
992 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
993 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
994 {
995 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
996 u32Data = u32ESWptr;
997 }
998 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
999 && ((u32Data - u32ESWptr) < 32)
1000 && (pCtrl->u32FlushRstPtr == 1))
1001 {
1002 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1003 u32Data = u32ESWptr;
1004 }
1005 }
1006
1007 // remove illegal pointer
1008 #if 1
1009 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1010 {
1011 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1012
1013 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1014 (u32PacketStaddr <
1015 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1016 {
1017 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1018 u32Data = pCtrl->u32LastESRptr;
1019 }
1020 }
1021 #endif
1022 }
1023 else
1024 {
1025 #if HVD_ENABLE_MVC
1026 MS_U8 u8ViewIdx = 0;
1027 if(HAL_HVD_EX_CheckMVCID(u32Id))
1028 {
1029 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1030 }
1031 if(u8ViewIdx != 0) /// 2nd ES ptr.
1032 {
1033 u32Data = pShm->u32ES2ReadPtr;
1034 }
1035 else
1036 {
1037 u32Data = pShm->u32ESReadPtr;
1038 }
1039 #else
1040 u32Data = pShm->u32ESReadPtr;
1041 #endif
1042 }
1043
1044 EXIT:
1045
1046 pCtrl->u32LastESRptr = u32Data;
1047
1048 return u32Data;
1049 }
1050
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1051 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1052 {
1053 MS_U16 u16TimeOut = 0xFFFF;
1054 MS_BOOL bResult = FALSE;
1055
1056 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
1057
1058 while (--u16TimeOut)
1059 {
1060 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1061 {
1062 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1063 break;
1064 }
1065 }
1066
1067 return bResult;
1068 }
1069
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1070 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1071 {
1072 MS_U16 u16TimeOut = 0xFFFF;
1073 MS_BOOL bResult = FALSE;
1074 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1075
1076 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
1077
1078 #if HVD_ENABLE_MVC
1079 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1080 {
1081 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1082 }
1083 #endif /// HVD_ENABLE_MVC
1084
1085 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1086
1087 while (--u16TimeOut)
1088 {
1089 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1090 {
1091 u32Cmd |= (u8TaskId << 24);
1092 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1093 break;
1094 }
1095 }
1096 return bResult;
1097 }
1098
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)1099 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
1100 {
1101 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1102 #ifdef VDEC3
1103 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1104 MS_BOOL IsSent = FALSE;
1105 MS_BOOL IsMailBox = FALSE;
1106 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1107
1108 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
1109 {
1110 do {
1111 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1112 if (!SentRet)
1113 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1114 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1115 break;
1116 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1117 IsSent = TRUE;
1118 break;
1119 }
1120 else if (HVD_GetSysTime_ms() > u32timeout)
1121 {
1122 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1123 break;
1124 }
1125 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1126 }
1127 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
1128 {
1129 do {
1130 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1131 if (!SentRet)
1132 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1133 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1134 break;
1135 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1136 IsSent = TRUE;
1137 break;
1138 }
1139 else if (HVD_GetSysTime_ms() > u32timeout)
1140 {
1141 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1142 break;
1143 }
1144 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1145 }
1146 if (!IsSent) {
1147 IsMailBox = TRUE;
1148 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1149 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1150 #else
1151 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1152 #endif
1153 {
1154 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1155 if (HVD_GetSysTime_ms() > u32timeout)
1156 {
1157 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1158 return E_HVD_RETURN_TIMEOUT;
1159 }
1160 #endif
1161
1162 #if 0
1163 if (u32Cmd == E_HVD_CMD_STOP)
1164 {
1165 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1166 #if HVD_ENABLE_MVC
1167 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1168 {
1169 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1170 }
1171 #endif /// HVD_ENABLE_MVC
1172 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1173
1174 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1175 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1176
1177 return E_HVD_RETURN_SUCCESS;
1178 }
1179 #endif
1180
1181 if(u32Cmd < E_DUAL_CMD_BASE)
1182 {
1183 //_HVD_EX_GetPC();
1184 HAL_HVD_EX_Dump_FW_Status(u32Id);
1185 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1186 }
1187 }
1188
1189 #ifdef VDEC3
1190 }
1191 IsSent = FALSE;
1192 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1193 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
1194 {
1195 do {
1196 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1197 if (!SentRet)
1198 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1199 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1200 break;
1201 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1202 IsSent = TRUE;
1203 break;
1204 }
1205 else if (HVD_GetSysTime_ms() > u32timeout)
1206 {
1207 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1208 break;
1209 }
1210 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1211 }
1212 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
1213 {
1214 do {
1215 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1216 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1217 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1218 }
1219 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1220 break;
1221 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1222 IsSent = TRUE;
1223 break;
1224 }
1225 else if (HVD_GetSysTime_ms() > u32timeout)
1226 {
1227 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1228 break;
1229 }
1230 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1231 }
1232 if (!IsSent)
1233 {
1234 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1235 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1236 #else
1237 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1238
1239 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1240 #endif
1241 {
1242 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1243 if (HVD_GetSysTime_ms() > u32timeout)
1244 {
1245 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
1246 return E_HVD_RETURN_TIMEOUT;
1247 }
1248 #endif
1249 if(u32Cmd < E_DUAL_CMD_BASE)
1250 {
1251 //_HVD_EX_GetPC();
1252 HAL_HVD_EX_Dump_FW_Status(u32Id);
1253 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1254 }
1255 }
1256 #ifdef VDEC3
1257 }
1258 else
1259 {
1260 HAL_HVD_EX_FlushMemory();
1261 }
1262 #endif
1263 return E_HVD_RETURN_SUCCESS;
1264 }
1265
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)1266 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
1267 {
1268 #if HAL_HVD_ENABLE_MIU_PROTECT
1269 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
1270 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1271 #if SUPPORT_EVD
1272 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
1273 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1274 #endif
1275 _HVD_MIU_SetReqMask(HVD_RW, bEnable);
1276 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1277 HAL_VPU_EX_MIU_RW_Protect(bEnable);
1278 //HVD_Delay_ms(1);
1279 #endif
1280 return;
1281 }
1282
1283 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)1284 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
1285 {
1286 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1287
1288 if (u32CodecType == E_HVD_INIT_HW_HEVC
1289 #if SUPPORT_MSVP9
1290 || u32CodecType == E_HVD_INIT_HW_VP9
1291 #endif
1292 )
1293 return TRUE;
1294
1295 return FALSE;
1296 }
1297
_HAL_EX_IS_HVD(MS_U32 u32ModeFlag)1298 static MS_BOOL _HAL_EX_IS_HVD(MS_U32 u32ModeFlag) // VP8 isn't included
1299 {
1300 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1301
1302 if ((u32CodecType == E_HVD_INIT_HW_MVC) ||
1303 (u32CodecType == E_HVD_INIT_HW_AVC) ||
1304 (u32CodecType == E_HVD_INIT_HW_AVS) ||
1305 (u32CodecType == E_HVD_INIT_HW_RM))
1306 return TRUE;
1307
1308 return FALSE;
1309 }
1310
_HAL_EX_BBU_EVD_InUsed(void)1311 static MS_BOOL _HAL_EX_BBU_EVD_InUsed(void)
1312 {
1313 if (!pHVDHalContext)
1314 return FALSE;
1315
1316 MS_U32 i;
1317 MS_BOOL bRet = FALSE;
1318
1319 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1320 {
1321 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1322 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_HEVC)
1323 #if SUPPORT_MSVP9
1324 ||(pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP9)
1325 #endif
1326 ))
1327 {
1328 bRet = TRUE;
1329 break;
1330 }
1331 }
1332
1333 return bRet;
1334 }
1335
_HAL_EX_BBU_HVD_InUsed(void)1336 static MS_BOOL _HAL_EX_BBU_HVD_InUsed(void) // VP8 isn't included
1337 {
1338 if (!pHVDHalContext)
1339 return FALSE;
1340
1341 MS_U32 i;
1342 MS_BOOL bRet = FALSE;
1343
1344 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1345 {
1346 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1347 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVC) ||
1348 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVS) ||
1349 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_RM)))
1350 {
1351 bRet = TRUE;
1352 break;
1353 }
1354 }
1355
1356 return bRet;
1357 }
1358
_HAL_EX_BBU_VP8_InUsed(void)1359 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
1360 {
1361 if (!pHVDHalContext)
1362 return FALSE;
1363
1364 MS_U32 i;
1365 MS_BOOL bRet = FALSE;
1366
1367 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1368 {
1369 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
1370 {
1371 bRet = TRUE;
1372 break;
1373 }
1374 }
1375
1376 return bRet;
1377 }
1378
1379 #endif
1380
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1381 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1382 {
1383 MS_U16 u16Reg = 0;
1384 MS_VIRT u32StAddr = 0;
1385 #ifdef VDEC3
1386 MS_U32 u32Length = 0;
1387 #endif
1388 //MS_BOOL bBitMIU1 = FALSE;
1389 //MS_BOOL bCodeMIU1 = FALSE;
1390 MS_U8 u8BitMiuSel = 0;
1391 MS_U8 u8CodeMiuSel = 0;
1392 MS_U8 u8FBMiuSel = 0;
1393 MS_U32 u32BitStartOffset;
1394 MS_U32 u32CodeStartOffset;
1395 MS_U32 u32FBStartOffset;
1396
1397 MS_U8 u8TaskId = 0;
1398 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1399 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1400 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1401 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1402
1403 // MS_U32 u32TmpStartOffset;
1404 MS_U8 u8TmpMiuSel;
1405
1406
1407
1408 if(pCtrl == NULL) return;
1409
1410 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1411 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1412 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1413
1414 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1415 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1416 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1417 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1418 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1419 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1420 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1421 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1422 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1423 (u8FBMiuSel << VDEC_PPIN_MIUSEL));
1424
1425 if (u8BitMiuSel != u8CodeMiuSel)
1426 {
1427 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
1428 }
1429 else
1430 {
1431 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
1432 }
1433
1434 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1435 {
1436 #ifdef VDEC3
1437 if (!_HAL_EX_BBU_VP8_InUsed())
1438 #endif
1439 {
1440 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1441
1442 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
1443 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
1444 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1445
1446 u32StAddr += 0x2000;
1447
1448 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
1449 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
1450 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1451 }
1452
1453 // ES buffer
1454 #ifdef VDEC3
1455 if(pCtrl->bNStreamMode)
1456 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1457 else
1458 #endif
1459 u32StAddr = u32BitStartOffset;
1460
1461 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1462
1463 #ifdef VDEC3
1464 if (!_HAL_EX_BBU_VP8_InUsed())
1465 #endif
1466 {
1467 HVD_EX_MSG_ERR("ESB start addr=%lx\n", (unsigned long)u32StAddr);
1468
1469 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1470 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1471
1472 #ifdef VDEC3
1473 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1474 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1475 #else
1476 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1477 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1478 #endif
1479
1480 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1481 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1482 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1483 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1484 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1485 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1486 }
1487
1488 return;
1489 }
1490
1491 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1492
1493 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
1494
1495 #ifdef VDEC3
1496 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1497 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1498 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1499 {
1500 if (pCtrl->u32BBUId == 0)
1501 {
1502 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1503 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1504 // -1 is for NAL_TAB_LEN counts from zero.
1505 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1506 }
1507 else
1508 {
1509 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1510 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1511 // -1 is for NAL_TAB_LEN counts from zero.
1512 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1513 }
1514 }
1515 #else
1516 if (0 == u8TaskId)
1517 {
1518 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1519 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1520 // -1 is for NAL_TAB_LEN counts from zero.
1521 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1522 }
1523 else
1524 {
1525 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1526 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1527 // -1 is for NAL_TAB_LEN counts from zero.
1528 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1529 }
1530 #endif
1531
1532 // ES buffer
1533 #ifdef VDEC3
1534 if(!pCtrl->bNStreamMode || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1535 {
1536 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1537 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1538 }
1539 else
1540 {
1541 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1542 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1543 }
1544 #else
1545 u32StAddr = u32BitStartOffset;
1546 #endif
1547
1548 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1549
1550 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1551
1552 #ifdef VDEC3
1553 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1554 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1555 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1556 {
1557 if (pCtrl->u32BBUId == 0)
1558 {
1559 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1560 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1561
1562 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1563 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1564 }
1565 else
1566 {
1567 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1568 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1569
1570 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1571 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1572 }
1573 }
1574 #else
1575 if (0 == u8TaskId)
1576 {
1577 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1578 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1579
1580 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1581 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1582 }
1583 else
1584 {
1585 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1586 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1587
1588 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1589 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1590 }
1591 #endif
1592
1593 // others
1594 #ifdef VDEC3
1595 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1596 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1597 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1598 {
1599 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1600
1601 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1602 {
1603 if (pCtrl->u32BBUId == 0)
1604 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1605 else
1606 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1607 }
1608 else
1609 {
1610 if (pCtrl->u32BBUId == 0)
1611 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1612 else
1613 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1614 }
1615
1616 if (pCtrl->u32BBUId == 0)
1617 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1618 else
1619 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1620
1621 if (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // RM
1622 {
1623 if (pCtrl->u32BBUId == 0) // force BBU to remove nothing, RM only
1624 u16Reg |= HVD_REG_BBU_PASER_DISABLE;
1625 else
1626 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2;
1627 }
1628 #if SUPPORT_MSVP9
1629 else if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1630 {
1631 if (pCtrl->u32BBUId == 0)
1632 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03;
1633 else
1634 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03_BS2;
1635 }
1636 #endif
1637 else // AVS or AVC or HEVC
1638 {
1639 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1640 {
1641 if (pCtrl->u32BBUId == 0)
1642 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1643 else
1644 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1645 }
1646 else // start code remained
1647 {
1648 if (pCtrl->u32BBUId == 0)
1649 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1650 else
1651 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1652 }
1653 }
1654
1655 if (pCtrl->u32BBUId == 0)
1656 {
1657 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1658 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1659 }
1660 else
1661 {
1662 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1663 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1664 }
1665 }
1666 #else
1667 if (0 == u8TaskId)
1668 {
1669 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1670
1671 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1672 {
1673 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1674 }
1675 else
1676 {
1677 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1678 }
1679
1680 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1681
1682 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1683 {
1684 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1685 }
1686 else // AVS or AVC
1687 {
1688 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1689 {
1690 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1691 }
1692 else // start code remained
1693 {
1694 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1695 }
1696 }
1697
1698 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1699
1700 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1701 }
1702 else
1703 {
1704 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1705
1706 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1707 {
1708 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1709 }
1710 else
1711 {
1712 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1713 }
1714
1715 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1716
1717 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1718 {
1719 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1720 }
1721 else // AVS or AVC
1722 {
1723 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1724 {
1725 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1726 }
1727 else // start code remained
1728 {
1729 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1730 }
1731 }
1732
1733 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1734
1735 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1736 }
1737 #endif
1738
1739 #if (HVD_ENABLE_MVC)
1740 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1741 {
1742 /// Used sub stream to record sub view data.
1743 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1744 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1745
1746 if (u8BitMiuSel != u8CodeMiuSel)
1747 {
1748 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
1749 }
1750 else
1751 {
1752 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
1753 }
1754
1755
1756 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
1757 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
1758 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
1759 // -1 is for NAL_TAB_LEN counts from zero.
1760 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
1761
1762 // ES buffer
1763 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1764
1765 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1766 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1767 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1768
1769 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1770 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1771
1772 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1773 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1774 {
1775 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1776 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1777 }
1778 else
1779 {
1780 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1781 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1782 }
1783 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1784 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1785 {
1786 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1787 }
1788 else // AVS or AVC
1789 {
1790 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1791 {
1792 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1793 }
1794 else // start code remained
1795 {
1796 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1797 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1798 }
1799 }
1800 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1801 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1802 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1803 }
1804 #endif
1805
1806 // MIF offset
1807 #if 0
1808 {
1809 MS_U16 offaddr = 0;
1810 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1811 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1812 {
1813 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1814 }
1815 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1816 offaddr = (MS_U16) ((u32StAddr) >> 20);
1817 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1818 //0x1FF; // 9 bits(L + H)
1819 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1820 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1821 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1822 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1823 {
1824 u16Reg |= HVD_REG_MIF_OFFSET_H;
1825 }
1826 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1827 }
1828 #endif
1829 }
1830
1831 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1832 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1833 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1834 {
1835 MS_U16 u16Reg = 0;
1836 MS_U32 u32StAddr = 0;
1837 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1838 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1839 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1840
1841 if(pCtrl == NULL) return;
1842
1843 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1844 {
1845 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1846
1847 // ES buffer
1848 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1849
1850 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1851 {
1852 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1853 }
1854
1855 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1856 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1857
1858 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1859 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1860
1861 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1862 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1863 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1864 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1865 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1866 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1867
1868 return;
1869 }
1870
1871 // ES buffer
1872 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1873
1874 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1875 {
1876 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1877 }
1878
1879 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1880
1881 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1882 {
1883 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1884 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1885
1886 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1887 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1888 }
1889 else
1890 {
1891 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1892 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1893
1894 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1895 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1896 }
1897 }
1898 #endif
1899
_HVD_EX_GetESLevel(MS_U32 u32Id)1900 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1901 {
1902 MS_U32 u32Wptr = 0;
1903 MS_U32 u32Rptr = 0;
1904 MS_U32 u32CurMBX = 0;
1905 MS_U32 u32ESsize = 0;
1906 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1907 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1908
1909 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1910 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1911 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1912
1913 if (u32Rptr >= u32Wptr)
1914 {
1915 u32CurMBX = u32Rptr - u32Wptr;
1916 }
1917 else
1918 {
1919 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1920 }
1921
1922 if (u32CurMBX == 0)
1923 {
1924 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1925 }
1926 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1927 {
1928 u32Ret = E_HVD_ESB_LEVEL_OVER;
1929 }
1930 else
1931 {
1932 u32CurMBX = u32ESsize - u32CurMBX;
1933 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1934 {
1935 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1936 }
1937 }
1938
1939 return u32Ret;
1940 }
1941
_HVD_EX_GetESQuantity(MS_U32 u32Id)1942 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1943 {
1944 MS_U32 u32Wptr = 0;
1945 MS_U32 u32Rptr = 0;
1946 MS_U32 u32ESsize = 0;
1947 MS_U32 u32Ret = 0;
1948 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1949
1950 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1951 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1952 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1953
1954
1955 if(u32Wptr >= u32Rptr)
1956 {
1957 u32Ret = u32Wptr - u32Rptr;
1958 }
1959 else
1960 {
1961 u32Ret = u32ESsize - u32Rptr + u32Wptr;
1962 }
1963 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
1964 return u32Ret;
1965 }
1966
1967 #if (HVD_ENABLE_IQMEM)
HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)1968 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
1969 {
1970
1971 MS_U32 u32Timeout = 20000;
1972
1973 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
1974 {
1975
1976 HAL_VPU_EX_IQMemSetDAMode(TRUE);
1977
1978 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
1979
1980
1981 while (u32Timeout)
1982 {
1983
1984 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
1985 {
1986 break;
1987 }
1988 u32Timeout--;
1989 HVD_Delay_ms(1);
1990 }
1991
1992 HAL_VPU_EX_IQMemSetDAMode(FALSE);
1993
1994 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
1995
1996 if (u32Timeout==0)
1997 {
1998 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
1999 return FALSE;
2000 }
2001
2002
2003 }
2004 return TRUE;
2005 }
2006
2007 #endif
2008
2009 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)2010 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
2011 #else
2012 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
2013 #endif
2014 {
2015 MS_U32 u32FirmVer = 0;
2016 MS_U32 u32Timeout = 20000;
2017 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2018
2019 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
2020
2021 #if HVD_ENABLE_TIME_MEASURE
2022 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2023 #endif
2024
2025 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
2026
2027 VPU_EX_FWCodeCfg fwCfg;
2028 VPU_EX_TaskInfo taskInfo;
2029 VPU_EX_VLCTblCfg vlcCfg;
2030 #ifdef VDEC3
2031 VPU_EX_FBCfg fbCfg;
2032 #endif
2033 VPU_EX_NDecInitPara nDecInitPara;
2034
2035 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
2036 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2037 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
2038 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
2039 #ifdef VDEC3_FB
2040 nDecInitPara.pVLCCfg = NULL;
2041 #else
2042 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2043 {
2044 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
2045 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2046 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2047 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
2048 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
2049 nDecInitPara.pVLCCfg = &vlcCfg;
2050 }
2051 #endif
2052 nDecInitPara.pFWCodeCfg = &fwCfg;
2053 nDecInitPara.pTaskInfo = &taskInfo;
2054 #ifdef VDEC3
2055 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
2056 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2057
2058 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2059 {
2060 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2061 }
2062
2063 nDecInitPara.pFBCfg = &fbCfg;
2064 #endif
2065
2066 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
2067 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
2068 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
2069 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
2070 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
2071
2072 taskInfo.u32Id = u32Id;
2073
2074 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2075 {
2076 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
2077 }
2078 #ifdef VDEC3
2079 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
2080 {
2081 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2082 }
2083 #if SUPPORT_MSVP9
2084 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2085 {
2086 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2087 }
2088 #endif
2089 #if SUPPORT_G2VP9
2090 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2091 {
2092 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2093 }
2094 #endif
2095 #endif
2096 else
2097 {
2098 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2099 }
2100
2101 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2102
2103 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2104 {
2105 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2106 }
2107 else
2108 {
2109 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2110 }
2111 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2112
2113 #ifdef SUPPORT_EVD
2114 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2115 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2116 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2117 #endif
2118
2119 if(TRUE == HVD_EX_GetRstFlag())
2120 {
2121 //Delete task for Rst
2122 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2123 {
2124 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2125 }
2126 HVD_EX_SetRstFlag(FALSE);
2127 }
2128
2129 #if (HVD_ENABLE_IQMEM)
2130 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2131 #endif
2132
2133 #ifdef VDEC3
2134 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2135 #else
2136 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2137 #endif
2138 {
2139 HVD_EX_MSG_ERR("Task create fail!\n");
2140
2141 return FALSE;
2142 }
2143
2144 while (u32Timeout)
2145 {
2146 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2147
2148 if (u32FirmVer != 0)
2149 {
2150 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2151 break;
2152 }
2153 u32Timeout--;
2154 HVD_Delay_ms(1);
2155 }
2156
2157 #ifdef VDEC3_FB
2158 #if HVD_ENABLE_RV_FEATURE
2159 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2160
2161 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2162 {
2163 if(pShm->u32RM_VLCTableAddr == 0) {
2164 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2165 }
2166 else
2167 {
2168 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2169 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2170 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2171 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2172 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2173 nDecInitPara.pVLCCfg = &vlcCfg;
2174 }
2175 }
2176
2177 if (nDecInitPara.pVLCCfg)
2178 {
2179 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2180 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2181 {
2182 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2183 return FALSE;
2184 }
2185 }
2186 #endif
2187 #endif
2188 if (u32Timeout > 0)
2189 {
2190 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2191
2192 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2193
2194 #ifdef VDEC3
2195 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2196 {
2197 case E_HVD_INIT_HW_AVC:
2198 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2199 break;
2200 case E_HVD_INIT_HW_AVS:
2201 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2202 break;
2203 case E_HVD_INIT_HW_RM:
2204 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2205 break;
2206 case E_HVD_INIT_HW_MVC:
2207 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2208 break;
2209 case E_HVD_INIT_HW_VP8:
2210 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2211 break;
2212 case E_HVD_INIT_HW_MJPEG:
2213 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2214 break;
2215 case E_HVD_INIT_HW_VP6:
2216 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2217 break;
2218 case E_HVD_INIT_HW_HEVC:
2219 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2220 break;
2221 case E_HVD_INIT_HW_VP9:
2222 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2223 break;
2224 default:
2225 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2226 break;
2227 }
2228 #endif
2229
2230 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2231 }
2232 else
2233 {
2234 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2235 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2236
2237 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2238 {
2239 HVD_EX_MSG_ERR("Task delete fail!\n");
2240 }
2241
2242 return FALSE;
2243 }
2244
2245
2246
2247 #if (HVD_ENABLE_IQMEM)
2248
2249 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
2250 {
2251
2252 HAL_HVD_EX_IQMem_Init(u32Id);
2253 }
2254 else{
2255 HVD_EX_MSG_DBG("not support IQMEM\n");
2256 }
2257 #endif
2258
2259
2260
2261
2262
2263
2264 #if HVD_ENABLE_TIME_MEASURE
2265 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2266 #endif
2267
2268 return TRUE;
2269 }
2270
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2271 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2272 {
2273 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2274 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2275 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2276 {
2277 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2278 }
2279 else
2280 {
2281 return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2282 }
2283 }
2284
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2285 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2286 {
2287 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2288 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2289
2290 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2291 {
2292 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2293 }
2294 else
2295 {
2296 return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2297 }
2298 }
2299
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2300 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2301 {
2302 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2303 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2304
2305 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2306 {
2307 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2308 {
2309 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2310 }
2311 }
2312 else
2313 {
2314 *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2315 }
2316 }
2317
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2318 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2319 {
2320 MS_VIRT u32PTSWptr = HVD_U32_MAX;
2321 MS_VIRT u32PTSRptr = HVD_U32_MAX;
2322 MS_VIRT u32DestAddr = 0;
2323 HVD_PTS_Entry PTSEntry;
2324 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2325 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2326 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2327
2328 // update R & W ptr
2329 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2330
2331 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
2332
2333 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2334 {
2335 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
2336 (MS_U32) MAX_PTS_TABLE_SIZE);
2337 return E_HVD_RETURN_FAIL;
2338 }
2339
2340 // check queue is full or not
2341 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2342 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2343
2344 if (u32PTSWptr == u32PTSRptr)
2345 {
2346 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
2347 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2348 return E_HVD_RETURN_FAIL;
2349 }
2350
2351 // add one PTS entry
2352 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2353 PTSEntry.u32ID_L = pInfo->u32ID_L;
2354 PTSEntry.u32ID_H = pInfo->u32ID_H;
2355 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2356
2357 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2358
2359 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
2360
2361 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2362
2363 HAL_HVD_EX_FlushMemory();
2364
2365 // update Write ptr
2366 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2367
2368 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2369
2370 return E_HVD_RETURN_SUCCESS;
2371 }
2372
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2373 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2374 {
2375 //---------------------------------------------------
2376 // item format in nal table:
2377 // reserved |borken| u32NalOffset | u32NalLen
2378 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2379 //---------------------------------------------------
2380 MS_VIRT u32Adr = 0;
2381 MS_U32 u32BBUNewWptr = 0;
2382 MS_U8 item[8];
2383 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2384 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2385 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2386 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2387
2388 #if HVD_ENABLE_MVC
2389 if(HAL_HVD_EX_CheckMVCID(u32Id))
2390 {
2391 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2392 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2393 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2394 {
2395 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2396 }
2397 }
2398 #endif /// HVD_ENABLE_MVC
2399
2400 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2401 {
2402 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
2403 }
2404 else
2405 {
2406 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2407 }
2408 u32BBUNewWptr++;
2409 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
2410
2411 // prepare nal entry
2412
2413 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2414 {
2415 // NAL len 22 bits , HEVC level5 constrain
2416 item[0] = u32NalLen & 0xff;
2417 item[1] = (u32NalLen >> 8) & 0xff;
2418 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2419 item[3] = (u32NalOffset >> 2) & 0xff;
2420 item[4] = (u32NalOffset >> 10) & 0xff;
2421 item[5] = (u32NalOffset >> 18) & 0xff;
2422 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2423 item[7] = 0;
2424 }
2425 else
2426 {
2427 item[0] = u32NalLen & 0xff;
2428 item[1] = (u32NalLen >> 8) & 0xff;
2429 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2430 item[3] = (u32NalOffset >> 3) & 0xff;
2431 item[4] = (u32NalOffset >> 11) & 0xff;
2432 item[5] = (u32NalOffset >> 19) & 0xff;
2433 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2434 item[7] = 0;
2435 }
2436
2437 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2438 {
2439 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
2440 }
2441 else
2442 {
2443 // add nal entry
2444 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2445 }
2446
2447 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2448
2449 HAL_HVD_EX_FlushMemory();
2450
2451 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2452
2453 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2454 {
2455 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
2456 }
2457 else
2458 {
2459 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2460 }
2461
2462 return E_HVD_RETURN_SUCCESS;
2463 }
2464
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2465 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2466 {
2467 MS_U8 item[8];
2468 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2469 MS_VIRT u32Adr = 0;
2470 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2471 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2472 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2473
2474 /*
2475 printf("nal2 offset=0x%x, len=0x%x\n",
2476 u32NalOffset2, u32NalLen2);
2477 */
2478
2479 item[0] = u32NalLen2 & 0xff;
2480 item[1] = (u32NalLen2 >> 8) & 0xff;
2481 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2482 item[3] = (u32NalOffset2 >> 3) & 0xff;
2483 item[4] = (u32NalOffset2 >> 11) & 0xff;
2484 item[5] = (u32NalOffset2 >> 19) & 0xff;
2485 item[6] = (u32NalOffset2 >> 27) & 0x07;
2486 item[7] = 0;
2487
2488 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2489 {
2490 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
2491 }
2492 else
2493 {
2494 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2495 }
2496
2497 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2498
2499 HAL_HVD_EX_FlushMemory();
2500
2501 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2502 }
2503
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2504 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2505 {
2506 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2507 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2508
2509 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2510 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
2511 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
2512 {
2513 MS_U16 i;
2514 MS_PHY u32VUIAddr;
2515 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
2516
2517 HAL_HVD_EX_ReadMemory();
2518 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2519
2520 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2521 {
2522 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2523 {
2524 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2525 }
2526 else
2527 {
2528 *pData = *((MS_VIRT *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2529 }
2530 pData++;
2531 }
2532 }
2533 else
2534 {
2535 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2536 }
2537
2538 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
2539 }
2540
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2541 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2542 {
2543 MS_U32 u32ReadPtr = 0;
2544 MS_U32 eRet = 0;
2545 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2546 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2547
2548 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2549 MS_U32 u32WritePtr = 0;
2550
2551 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2552 {
2553 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
2554 }
2555 else
2556 {
2557 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2558 }
2559
2560 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
2561
2562 if (u32WritePtr >= u32ReadPtr)
2563 {
2564 eRet = u32WritePtr - u32ReadPtr;
2565 }
2566 else
2567 {
2568 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2569 }
2570
2571 #if 0
2572 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2573 {
2574 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2575 }
2576 else
2577 {
2578 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2579 }
2580
2581 #endif
2582 return eRet;
2583 }
2584
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2585 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2586 {
2587 MS_U32 u32ReadPtr = 0;
2588 MS_U32 eRet = 0;
2589 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2590
2591 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2592
2593 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2594 {
2595 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
2596 (MS_U32) MAX_PTS_TABLE_SIZE);
2597 return 0;
2598 }
2599
2600 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2601
2602 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2603 {
2604 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2605 }
2606 else
2607 {
2608 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2609 }
2610
2611 return eRet;
2612 }
2613
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)2614 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
2615 {
2616 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2617
2618 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
2619 }
2620
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2621 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2622 {
2623 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2624 MS_U16 u16QNum = pShm->u16DispQNumb;
2625 MS_U16 u16QPtr = pShm->u16DispQPtr;
2626 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2627
2628 #if (HVD_ENABLE_MVC)
2629 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2630
2631 if(bMVC)
2632 {
2633 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2634 {
2635 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
2636 MS_U16 u16UsedFrm = 0;
2637
2638 if (u16RealQPtr != u16QPtr)
2639 {
2640 if (u16RealQPtr > u16QPtr)
2641 {
2642 u16UsedFrm = u16RealQPtr - u16QPtr;
2643 }
2644 else
2645 {
2646 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2647 }
2648 }
2649
2650 if (u16QNum > u16UsedFrm)
2651 {
2652 volatile HVD_Frm_Information *pHvdFrm;
2653
2654 u16QNum -= u16UsedFrm;
2655 u16QPtr = u16RealQPtr;
2656 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2657
2658 if ((u16QPtr%2) == 0) //For MVC mode, we must check the pair of display entry is ready or not
2659 {
2660 volatile HVD_Frm_Information *pHvdFrmNext = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr+1];
2661
2662 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2663 {
2664 return NULL;
2665 }
2666 }
2667
2668 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2669 {
2670 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2671 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2672
2673 if ((u16QPtr%2) == 0)
2674 {
2675 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2676 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2677 }
2678 else
2679 {
2680 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2681 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
2682 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2683 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2684 }
2685
2686 u16QPtr++;
2687 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2688 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2689
2690 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2691 }
2692 }
2693
2694 return NULL;
2695 }
2696
2697 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2698 //search the next frame to display
2699 while (u16QNum > 0)
2700 {
2701 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2702 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2703 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2704
2705 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2706 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2707 {
2708 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2709 /// Check the depned view was initial when Output the base view.
2710 if((u16QPtr%2) == 0)
2711 {
2712 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2713 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2714 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2715 {
2716 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2717 ///printf("Return NULL.\n");
2718 return NULL;
2719 }
2720 }
2721
2722 //printf("V:%d.\n",u16QPtr);
2723 pHVDHalContext->_u16DispQPtr = u16QPtr;
2724 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2725 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2726 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2727 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2728 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2729 }
2730
2731 u16QNum--;
2732 //go to next frame in the dispQ
2733 u16QPtr++;
2734
2735 if (u16QPtr >= pShm->u16DispQSize)
2736 {
2737 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2738 }
2739 }
2740 }
2741 else
2742 #endif ///HVD_ENABLE_MVC
2743 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
2744 if (_HVD_EX_IsHevcInterlaceField(u32Id))
2745 {
2746 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
2747 volatile HVD_Frm_Information *pHvdFrm_first = NULL;
2748
2749 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
2750 return NULL;
2751 }
2752
2753 while (u16QNum != 0)
2754 {
2755 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2756 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2757 {
2758 if (!first_field) // second get frame, we will check at least one paired in disp queue.
2759 {
2760 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2761 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2762 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
2763
2764 if(pHvdFrm->u8FieldType == 1 || pHvdFrm->u8FieldType == 9 || pHvdFrm->u8FieldType == 11)
2765 pHvdFrm->u8FieldType = 0;
2766 else
2767 pHvdFrm->u8FieldType = 1;
2768 return pHvdFrm;
2769 }
2770 else // first get frame, we will check at least one paired in disp queue.
2771 {
2772 if (pHvdFrm_first == NULL)
2773 {
2774 pHvdFrm_first = pHvdFrm;
2775 }
2776 else
2777 {
2778 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2779 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
2780
2781 //After flush, we cannot get the correct field type of first field from sei, so we use second field type to decide first field type.
2782 if (pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 0xff)
2783 {
2784 if (pHvdFrm->u8FieldType == 9)
2785 pHvdFrm_first->u8FieldType = 12;
2786 else if (pHvdFrm->u8FieldType == 10)
2787 pHvdFrm_first->u8FieldType = 11;
2788 else if (pHvdFrm->u8FieldType == 10)
2789 pHvdFrm_first->u8FieldType = 11;
2790 else if (pHvdFrm->u8FieldType == 1)
2791 pHvdFrm_first->u8FieldType = 2;
2792 else if (pHvdFrm->u8FieldType == 2)
2793 pHvdFrm_first->u8FieldType = 1;
2794 else
2795 {
2796 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2797 return NULL;
2798 }
2799 if ((pHvdFrm_first->u32ID_L >> 16) & 0x1)
2800 pHvdFrm_first->u32ID_L |= (1 << 16);
2801 else
2802 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2803 }
2804 else if (pHvdFrm_first->u8FieldType == 9 || pHvdFrm_first->u8FieldType == 10)
2805 {
2806 if (pHvdFrm_first->u8FieldType == 9 && pHvdFrm->u8FieldType == 12)
2807 {
2808 pHvdFrm_first->u32ID_L |= (1 << 16);
2809 pHvdFrm->u32ID_L |= (1 << 16);
2810 }
2811 else if (pHvdFrm_first->u8FieldType == 10 && pHvdFrm->u8FieldType == 11)
2812 {
2813 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2814 pHvdFrm->u32ID_L &= (~(1 << 16));
2815 }
2816 else
2817 {
2818 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2819 return NULL;
2820 }
2821 }
2822 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
2823 if (pHvdFrm_first->u8FieldType == 1 || pHvdFrm_first->u8FieldType == 9 || pHvdFrm_first->u8FieldType == 11)
2824 pHvdFrm_first->u8FieldType = 0;
2825 else
2826 pHvdFrm_first->u8FieldType = 1;
2827 return pHvdFrm_first;
2828 }
2829 }
2830 }
2831 u16QNum--;
2832 //go to next frame in the dispQ
2833 u16QPtr++;
2834
2835 if (u16QPtr == pShm->u16DispQSize)
2836 {
2837 u16QPtr = 0; //wrap to the begin
2838 }
2839
2840 }
2841 return NULL;
2842 }
2843 else
2844 {
2845 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2846
2847 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2848 {
2849
2850 while (u16QNum != 0)
2851 {
2852 pHvdFrm = (volatile HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
2853
2854 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2855 {
2856 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2857 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2858 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2859 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2860 }
2861 u16QNum--;
2862 //go to next frame in the dispQ
2863 u16QPtr++;
2864
2865 if (u16QPtr == pShm->u16DispQSize)
2866 {
2867 u16QPtr = 0; //wrap to the begin
2868 }
2869 }
2870
2871 return NULL;
2872 }
2873
2874 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2875 //search the next frame to display
2876 while (u16QNum != 0)
2877 {
2878 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2879
2880 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2881 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2882 {
2883 pHVDHalContext->_u16DispQPtr = u16QPtr;
2884 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2885 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2886 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2887 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2888 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2889 }
2890
2891 u16QNum--;
2892 //go to next frame in the dispQ
2893 u16QPtr++;
2894
2895 if (u16QPtr == pShm->u16DispQSize)
2896 {
2897 u16QPtr = 0; //wrap to the begin
2898 }
2899 }
2900 }
2901
2902 return NULL;
2903 }
2904
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2905 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2906 {
2907 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2908 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2909 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2910 {
2911 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2912 if(pVsyncBridgeExt != NULL)
2913 {
2914 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
2915 }
2916 }
2917 return pFrmInfoExt;
2918 }
2919
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)2920 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
2921 {
2922 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2923 MS_U64 u64Ret = 0;
2924 #if SUPPORT_EVD
2925 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2926 #if SUPPORT_MSVP9
2927 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2928 #endif
2929 #endif
2930
2931 #if SUPPORT_EVD
2932 if (isEVD)
2933 {
2934 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
2935 }
2936 else
2937 #endif
2938 #if SUPPORT_G2VP9
2939 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2940 {
2941 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
2942 }
2943 else
2944 #endif
2945 {
2946 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
2947 }
2948
2949 return u64Ret;
2950 }
2951
2952 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)2953 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
2954 {
2955 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2956 MS_U16 u16QNum = pShm->u16DispQNumb;
2957 MS_U16 u16QPtr = pShm->u16DispQPtr;
2958 static volatile HVD_Frm_Information *pHvdFrm = NULL;
2959 MS_BOOL bMVC = FALSE;
2960 #if HVD_ENABLE_MVC
2961 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2962 #endif
2963
2964 if (bMVC || _HVD_EX_IsHevcInterlaceField(u32Id))
2965 {
2966 if (u16QNum == 1) return TRUE;
2967 }
2968
2969 while (u16QNum != 0)
2970 {
2971 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2972 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2973 {
2974 return FALSE;
2975 }
2976 u16QNum--;
2977 u16QPtr++;
2978 if (u16QPtr == pShm->u16DispQSize)
2979 {
2980 u16QPtr = 0; //wrap to the begin
2981 }
2982 }
2983
2984 return TRUE;
2985 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)2986 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
2987 {
2988 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
2989
2990 return &(_pHVDCtrls[u8DrvId]);
2991 }
2992
_HVD_EX_GetStreamIdx(MS_U32 u32Id)2993 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
2994 {
2995 MS_U8 u8OffsetIdx = 0;
2996 MS_U8 u8SidBaseMask = 0xF0;
2997 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
2998
2999 switch (eSidBase)
3000 {
3001 case E_HAL_HVD_MAIN_STREAM_BASE:
3002 {
3003 u8OffsetIdx = 0;
3004 break;
3005 }
3006 case E_HAL_VPU_SUB_STREAM_BASE:
3007 {
3008 u8OffsetIdx = 1;
3009 break;
3010 }
3011 case E_HAL_VPU_MVC_STREAM_BASE:
3012 {
3013 u8OffsetIdx = 0;
3014 break;
3015 }
3016 #ifdef VDEC3
3017 case E_HAL_VPU_N_STREAM_BASE:
3018 {
3019 u8OffsetIdx = (u32Id>>8) & 0xF;
3020 break;
3021 }
3022 #endif
3023 default:
3024 {
3025 u8OffsetIdx = 0;
3026 break;
3027 }
3028 }
3029
3030 return u8OffsetIdx;
3031 }
3032 /*
3033 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
3034 {
3035 MS_U32 i = 0;
3036 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3037 {
3038 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
3039 {
3040 return TRUE;
3041 }
3042 }
3043 return FALSE;
3044 }
3045 */
3046
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)3047 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
3048 {
3049 MS_PHY u32PhyAddr = 0x0;
3050 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3051
3052 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3053 {
3054 return 0;
3055 }
3056
3057 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3058
3059 if (u32PhyAddr == 0xFFFFFFFF) //boris
3060 {
3061 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3062 }
3063 else
3064 {
3065 #if defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3066 //u32PhyAddr += 0; // if define HVD_OLD_LAYOUT_SHARE_MEM_BIAS under SUPPORT_NEW_MEM_LAYOUT, then we could refine the codes here
3067 #else
3068 u32PhyAddr += HVD_OLD_LAYOUT_SHARE_MEM_BIAS;
3069 #endif
3070 }
3071
3072 return MsOS_PA2KSEG1(u32PhyAddr);
3073 }
3074
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3075 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3076 {
3077 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3078 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3079
3080 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3081 {
3082 return 0;
3083 }
3084
3085 MS_PHY u32PhyAddr = 0x0;
3086 #if 0
3087 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3088
3089 if (u32PhyAddr == 0xFFFFFFFF)
3090 {
3091 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3092 }
3093 #endif
3094 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3095 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3096
3097 return MsOS_PA2KSEG1(u32PhyAddr);
3098 }
3099
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3100 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3101 {
3102
3103 if (u8MiuSel == E_CHIP_MIU_0)
3104 {
3105 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3106 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3107 }
3108 else if (u8MiuSel == E_CHIP_MIU_1)
3109 {
3110 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3111 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3112 }
3113 else // 2
3114 {
3115 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3116 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, MIU2_CLIENT_SELECT_GP4_HVD_MIF1, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3117 }
3118
3119 }
3120
3121 #if SUPPORT_G2VP9 && defined(VDEC3)
3122 #ifdef __ARM_NEON__
3123 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3124 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3125 {
3126 uint32x4x4_t data, data2;
3127 MS_U8* raster2 = raster + tile_w * 4;
3128
3129 data = vld4q_u32((const uint32_t *)tile);
3130 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3131
3132 vst1q_u32((uint32_t *)raster, data.val[0]);
3133 raster += stride;
3134 vst1q_u32((uint32_t *)raster, data.val[1]);
3135 raster += stride;
3136 vst1q_u32((uint32_t *)raster, data.val[2]);
3137 raster += stride;
3138 vst1q_u32((uint32_t *)raster, data.val[3]);
3139
3140
3141 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3142 raster2 += stride;
3143 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3144 raster2 += stride;
3145 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3146 raster2 += stride;
3147 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3148 }
3149 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3150 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3151 {
3152 MS_U8* tile0 = tile;
3153 MS_U8* tile1 = tile+16;
3154 MS_U8* tile2 = tile+32;
3155 MS_U8* tile3 = tile+48;
3156 int i;
3157
3158 for (i=0; i<4; i++) {
3159 raster[i] = tile0[i];
3160 raster[4+i] = tile1[i];
3161 raster[8+i] = tile2[i];
3162 raster[12+i] = tile3[i];
3163 }
3164
3165 for (i=0; i<4; i++) {
3166 raster[stride+i] = tile0[4+i];
3167 raster[stride+4+i] = tile1[4+i];
3168 raster[stride+8+i] = tile2[4+i];
3169 raster[stride+12+i] = tile3[4+i];
3170 }
3171
3172 for (i=0; i<4; i++) {
3173 raster[2*stride+i] = tile0[8+i];
3174 raster[2*stride+4+i] = tile1[8+i];
3175 raster[2*stride+8+i] = tile2[8+i];
3176 raster[2*stride+12+i] = tile3[8+i];
3177 }
3178
3179 for (i=0; i<4; i++) {
3180 raster[3*stride+i] = tile0[12+i];
3181 raster[3*stride+4+i] = tile1[12+i];
3182 raster[3*stride+8+i] = tile2[12+i];
3183 raster[3*stride+12+i] = tile3[12+i];
3184 }
3185 }
3186 #endif // #ifdef __ARM_NEON__
3187
3188 #if SUPPORT_G2VP9 && defined(VDEC3)
3189
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)3190 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
3191 {
3192 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
3193 u32Id,
3194 E_TASK_PRI_MEDIUM,
3195 TRUE,
3196 NULL,
3197 32, // stack size..
3198 "HVD_PostProcess_task");
3199
3200 if (s32HvdPpTaskId < 0)
3201 {
3202 HVD_EX_MSG_ERR("Pp Task create failed\n");
3203
3204 return FALSE;
3205 }
3206
3207 HVD_EX_MSG_DBG("Pp Task create success\n");
3208 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
3209
3210 return TRUE;
3211 }
3212 #endif
3213
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3214 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3215 {
3216 return y * stride * h + x * w * h;
3217 }
3218
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3219 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3220 {
3221 return y * stride * h + x * w;
3222 }
3223
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3224 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3225 {
3226 raster[0] = tile[0];
3227 raster[1] = tile[1];
3228 raster[2] = tile[2];
3229 raster[3] = tile[3];
3230 raster[stride] = tile[4];
3231 raster[stride + 1] = tile[5];
3232 raster[stride + 2] = tile[6];
3233 raster[stride + 3] = tile[7];
3234 raster[2 * stride] = tile[8];
3235 raster[2 * stride + 1] = tile[9];
3236 raster[2 * stride + 2] = tile[10];
3237 raster[2 * stride + 3] = tile[11];
3238 raster[3 * stride] = tile[12];
3239 raster[3 * stride + 1] = tile[13];
3240 raster[3 * stride + 2] = tile[14];
3241 raster[3 * stride + 3] = tile[15];
3242 }
3243
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3244 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3245 {
3246 const MS_U32 tile_w = 4;
3247 const MS_U32 tile_h = 4;
3248 MS_U32 tile_stride = w;
3249 MS_U32 x, y;
3250 MS_U8 *dst1, *dst2;
3251 MS_U8 *src1, *src2;
3252
3253 #ifdef __ARM_NEON__
3254 // To overlap load and store, handle two blocks at the same time.
3255 dst1 = dst;
3256 src1 = src;
3257 for (y = 0; y < h / tile_h; y++)
3258 {
3259 dst2 = dst1;
3260 src2 = src1;
3261 for (x = 0; x <= (w/tile_w - 8); x+=8)
3262 {
3263 tile4x4_to_raster_8(
3264 dst2,
3265 src2,
3266 raster_stride, tile_w, tile_h);
3267 dst2 += tile_w * 8;
3268 src2 += tile_w * tile_h * 8;
3269 }
3270 dst1 += raster_stride * tile_h;
3271 src1 += tile_stride * tile_h;
3272 for (; x < w / tile_w; x++)
3273 {
3274 tile4x4_to_raster(
3275 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3276 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3277 raster_stride);
3278 }
3279 }
3280 #else
3281 dst1 = NULL;
3282 src1 = NULL;
3283 dst2 = NULL;
3284 src2 = NULL;
3285
3286 for (y = 0; y < h / tile_h; y++)
3287 {
3288 for (x = 0; x <= (w/tile_w - 4); x+=4)
3289 {
3290 tile4x4_to_raster_4(
3291 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3292 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3293 raster_stride);
3294 }
3295 for (; x < w / tile_w; x++)
3296 {
3297 tile4x4_to_raster(
3298 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3299 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3300 raster_stride);
3301 }
3302 }
3303 #endif
3304 }
3305
3306 #define FLUSH_CACHE_SIZE (256 * 1024)
3307
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3308 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3309 {
3310 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
3311 if (u32Size > FLUSH_CACHE_SIZE)
3312 u32Size = FLUSH_CACHE_SIZE;
3313
3314 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
3315 }
3316
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3317 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3318 {
3319 MS_U32 u32SkipSize = 0;
3320
3321 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3322 if (u32Size > FLUSH_CACHE_SIZE)
3323 {
3324 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3325 u32Size = FLUSH_CACHE_SIZE;
3326 }
3327
3328 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
3329 }
3330
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3331 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3332 {
3333 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
3334 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3335 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3336 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3337
3338 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3339
3340 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3341
3342 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3343 {
3344 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3345 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3346
3347 HVD_Delay_ms(1); // FIXME
3348
3349 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3350 continue;
3351
3352 HAL_HVD_EX_ReadMemory();
3353
3354 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3355 {
3356 MS_U8 *pSrcVA, *pDstVA;
3357 MS_U32 u32SrcPA, u32DstPA;
3358 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3359 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3360
3361 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3362 {
3363 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3364
3365 u16Width = pFrmInfo->u16Width;
3366 u16Height = pFrmInfo->u16Height;
3367 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3368 }
3369
3370 // Luma
3371 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3372 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3373
3374 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3375 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3376
3377 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3378 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3379
3380 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3381
3382 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3383
3384 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3385
3386 // Chroma
3387 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3388 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3389
3390 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3391 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3392
3393 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3394 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3395
3396 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3397
3398 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3399
3400 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3401
3402 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3403 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3404 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3405
3406 HAL_HVD_EX_FlushMemory();
3407
3408 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3409 break;
3410
3411 HAL_HVD_EX_ReadMemory();
3412 }
3413 }
3414
3415 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3416
3417 return TRUE;
3418 }
3419 #endif
3420
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3421 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3422 {
3423 #ifndef VDEC3
3424 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3425 #endif
3426 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3427 // MS_U8 u8MiuSel;
3428 // MS_U32 u32StartOffset;
3429
3430 #if SUPPORT_EVD
3431 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3432 #if SUPPORT_MSVP9
3433 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3434 #endif
3435 #endif
3436 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
3437 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3438
3439 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3440 // re-setup clock.
3441 #if SUPPORT_G2VP9 && defined(VDEC3)
3442 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3443 #endif
3444
3445
3446 if (!HAL_VPU_EX_HVDInUsed())
3447 {
3448 HVD_EX_MSG_INF("HVD power on\n");
3449 HAL_HVD_EX_PowerCtrl(TRUE);
3450 }
3451
3452 #if SUPPORT_EVD
3453 if (isEVD || (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3454 {
3455 #ifdef VDEC3
3456 if (!HAL_VPU_EX_EVDInUsed())
3457 #endif
3458 {
3459 HVD_EX_MSG_INF("EVD power on\n");
3460 HAL_EVD_EX_PowerCtrl(TRUE);
3461 }
3462 }
3463 #endif
3464
3465 #if SUPPORT_G2VP9 && defined(VDEC3)
3466 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3467 {
3468 if (!HAL_VPU_EX_G2VP9InUsed())
3469 {
3470 HVD_EX_MSG_INF("G2 VP9 power on\n");
3471 HAL_VP9_EX_PowerCtrl(TRUE);
3472 }
3473 }
3474 #endif
3475
3476 if ((!HAL_VPU_EX_HVDInUsed()) )
3477 {
3478 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3479 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3480 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3481 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3482
3483 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3484
3485 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_128 , HVD_REG_RESET_MIU_128);
3486
3487 #if 0
3488 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
3489 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3490 {
3491 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
3492
3493 _HAL_HVD_Entry();
3494 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
3495 _HAL_HVD_Release();
3496
3497 }
3498 #endif
3499 }
3500
3501 #if SUPPORT_EVD
3502 if (isEVD)
3503 {
3504 #ifdef VDEC3
3505 if (!HAL_VPU_EX_EVDInUsed())
3506 #endif
3507 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3508 }
3509 #endif
3510
3511 #if SUPPORT_G2VP9 && defined(VDEC3)
3512 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3513 {
3514 if (!HAL_VPU_EX_G2VP9InUsed())
3515 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3516 }
3517 #endif
3518
3519
3520 if(pCtrl == NULL)
3521 {
3522 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
3523 //return FALSE;
3524 goto RESET;
3525 }
3526
3527 #if SUPPORT_EVD
3528 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
3529 {
3530 #ifdef VDEC3
3531 if (!HAL_VPU_EX_EVDInUsed())
3532 #endif
3533 {
3534 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3535 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3536 }
3537
3538 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3539 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3540 {
3541 #ifdef VDEC3
3542 if (0 == pCtrl->u32BBUId)
3543 #else
3544 if (0 == u8TaskId)
3545 #endif
3546 {
3547 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
3548 }
3549 else
3550 {
3551 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
3552 }
3553 }
3554 goto RESET;
3555 }
3556 #endif
3557
3558 // HVD4, from JANUS and later chip
3559 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3560 {
3561 case E_HVD_INIT_HW_AVS:
3562 {
3563 #ifdef VDEC3
3564 if (0 == pCtrl->u32BBUId)
3565 #else
3566 if (0 == u8TaskId)
3567 #endif
3568 {
3569 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3570 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3571 }
3572 else
3573 {
3574 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3575 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3576 }
3577
3578 break;
3579 }
3580 case E_HVD_INIT_HW_RM:
3581 {
3582 #ifdef VDEC3
3583 if (0 == pCtrl->u32BBUId)
3584 #else
3585 if (0 == u8TaskId)
3586 #endif
3587 {
3588 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3589 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3590
3591 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3592 {
3593 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3594 }
3595 else // RV 8
3596 {
3597 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3598 }
3599 }
3600 else
3601 {
3602 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3603 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3604
3605 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3606 {
3607 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3608 }
3609 else // RV 8
3610 {
3611 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3612 }
3613
3614 }
3615
3616 break;
3617 }
3618 default:
3619 {
3620 #ifdef VDEC3
3621 if (0 == pCtrl->u32BBUId)
3622 #else
3623 if (0 == u8TaskId)
3624 #endif
3625 {
3626 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3627 }
3628 else
3629 {
3630 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3631 }
3632 break;
3633 }
3634 }
3635
3636 RESET:
3637
3638 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3639
3640 if (!HAL_VPU_EX_HVDInUsed())
3641 {
3642 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3643 }
3644
3645 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3646
3647 #if SUPPORT_EVD
3648 if (isEVD)
3649 {
3650 #ifdef VDEC3
3651 if (!HAL_VPU_EX_EVDInUsed())
3652 #endif
3653 {
3654 HVD_EX_MSG_INF("EVD miu 128 bits\n");
3655 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_256& ~EVD_REG_RESET_MIU1_256));
3656 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_128| EVD_REG_RESET_MIU1_128));
3657 }
3658 // This is for Messi using 256 bits bbu.
3659 // If BBU has its own port, need to set bbu 128/256; otherwise, keep default value reg_bbu_miu_256 = 1
3660 HVD_EX_MSG_INF("EVD BBU 256 bits\n");
3661 _HVD_Write2Byte(EVD_REG_BBU_MIU_WIDTH, EVD_REG_BBU_MIU_256);
3662 }
3663
3664 #endif
3665 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3666 // Only ES buffer addrress needs to be set for VP8
3667 _HVD_EX_SetESBufferAddr(u32Id);
3668 #else
3669 if(DecoderType != E_VPU_EX_DECODER_MVD)
3670 {
3671 _HVD_EX_SetBufferAddr(u32Id);
3672 }
3673 #endif
3674 if (!HAL_VPU_EX_HVDInUsed())
3675 {
3676 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3677 }
3678
3679 #if SUPPORT_EVD
3680 if (isEVD)
3681 {
3682 #ifdef VDEC3
3683 if (!HAL_VPU_EX_EVDInUsed())
3684 #endif
3685 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
3686 }
3687 #endif
3688
3689 #if SUPPORT_G2VP9 && defined(VDEC3)
3690 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3691 {
3692 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3693
3694 if (!HAL_VPU_EX_G2VP9InUsed())
3695 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3696
3697 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3698 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
3699 }
3700 #endif
3701
3702 return TRUE;
3703 }
3704
HAL_HVD_EX_DeinitHW(void)3705 MS_BOOL HAL_HVD_EX_DeinitHW(void)
3706 {
3707 MS_U16 u16Timeout = 1000;
3708
3709 _HVD_EX_SetMIUProtectMask(TRUE);
3710
3711 #if SUPPORT_EVD //EVD using HVD DIU, it should be turn off EVD first
3712 HAL_EVD_EX_DeinitHW();
3713 #endif
3714
3715 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3716
3717 while (u16Timeout)
3718 {
3719 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
3720 {
3721 break;
3722 }
3723 u16Timeout--;
3724 }
3725
3726 HAL_HVD_EX_PowerCtrl(FALSE);
3727
3728 _HVD_EX_SetMIUProtectMask(FALSE);
3729
3730 return TRUE;
3731 }
3732
HAL_HVD_EX_FlushMemory(void)3733 void HAL_HVD_EX_FlushMemory(void)
3734 {
3735 MsOS_FlushMemory();
3736 }
3737
HAL_HVD_EX_ReadMemory(void)3738 void HAL_HVD_EX_ReadMemory(void)
3739 {
3740 MsOS_ReadMemory();
3741 }
3742
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)3743 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
3744 {
3745 _pHVDCtrls = pHVDCtrlsBase;
3746 }
3747
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)3748 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
3749 {
3750 return;
3751 }
3752
HAL_HVD_EX_GetHWVersionID(void)3753 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
3754 {
3755 return _HVD_Read2Byte(HVD_REG_REV_ID);
3756 }
3757
3758
HAL_HVD_EX_Init_Share_Mem(void)3759 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
3760 {
3761 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
3762 #if !defined(SUPPORT_X_MODEL_FEATURE)
3763 MS_U32 u32ShmId;
3764 MS_VIRT u32Addr;
3765 MS_U32 u32BufSize;
3766
3767
3768 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
3769 sizeof(HVD_Hal_CTX),
3770 &u32ShmId,
3771 &u32Addr,
3772 &u32BufSize,
3773 MSOS_SHM_QUERY))
3774 {
3775 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
3776 sizeof(HVD_Hal_CTX),
3777 &u32ShmId,
3778 &u32Addr,
3779 &u32BufSize,
3780 MSOS_SHM_CREATE))
3781 {
3782 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
3783 if(pHVDHalContext == NULL)
3784 {
3785 pHVDHalContext = &gHVDHalContext;
3786 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3787 _HVD_EX_Context_Init_HAL();
3788 HVD_EX_MSG_INF("[%s]Global structure init Success!!!\n",__FUNCTION__);
3789 }
3790 else
3791 {
3792 HVD_EX_MSG_INF("[%s]Global structure exists!!!\n",__FUNCTION__);
3793 }
3794 //return FALSE;
3795 }
3796 else
3797 {
3798 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
3799 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
3800 _HVD_EX_Context_Init_HAL();
3801 }
3802 }
3803 else
3804 {
3805 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
3806 }
3807 #else
3808 if(pHVDHalContext == NULL)
3809 {
3810 pHVDHalContext = &gHVDHalContext;
3811 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3812 _HVD_EX_Context_Init_HAL();
3813 }
3814 #endif
3815 _HAL_HVD_MutexCreate();
3816 #else
3817 if(pHVDHalContext == NULL)
3818 {
3819 pHVDHalContext = &gHVDHalContext;
3820 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3821 _HVD_EX_Context_Init_HAL();
3822 }
3823 #endif
3824
3825 return TRUE;
3826 }
3827
3828
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)3829 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
3830 {
3831 MS_U32 i = 0;
3832
3833 if (eStreamType == E_HAL_HVD_MVC_STREAM)
3834 {
3835 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
3836 return pHVDHalContext->_stHVDStream[0].eStreamId;
3837 }
3838 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
3839 {
3840 for (i = 0;
3841 i <
3842 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3843 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3844 {
3845 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3846 {
3847 return pHVDHalContext->_stHVDStream[i].eStreamId;
3848 }
3849 }
3850 }
3851 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
3852 {
3853 for (i = 0;
3854 i <
3855 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3856 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3857 {
3858 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3859 {
3860 return pHVDHalContext->_stHVDStream[i].eStreamId;
3861 }
3862 }
3863 }
3864 #ifdef VDEC3
3865 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
3866 {
3867 i = eStreamType - E_HAL_HVD_N_STREAM;
3868 if (!pHVDHalContext->_stHVDStream[i].bUsed)
3869 return pHVDHalContext->_stHVDStream[i].eStreamId;
3870 }
3871 #endif
3872
3873 return E_HAL_HVD_STREAM_NONE;
3874 }
3875
HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)3876 void HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)
3877 {
3878 if (bEnable)
3879 {
3880 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3881 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3882 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3883 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
3884 }
3885 else
3886 {
3887 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3888 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3889 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3890 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
3891 }
3892
3893 // fix to not inverse
3894 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
3895
3896 switch (pHVDHalContext->u32HVDClockType)
3897 {
3898 #if 0 //for overclocking
3899 case 432:
3900 {
3901 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
3902 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3903 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_320MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3904 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK);
3905 break;
3906 }
3907 #endif
3908 case 384:
3909 {
3910 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
3911 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3912 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3913 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3914 break;
3915 }
3916 case 345:
3917 {
3918 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_345MHZ, TOP_CKG_HVD_CLK_MASK);
3919 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3920 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3921 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3922 break;
3923 }
3924 case 320:
3925 {
3926 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_320MHZ, TOP_CKG_HVD_CLK_MASK);
3927 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_345MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3928 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3929 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3930 break;
3931 }
3932 case 288:
3933 {
3934 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
3935 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_320MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3936 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3937 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3938 break;
3939 }
3940 case 240:
3941 {
3942 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
3943 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3944 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3945 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
3946 break;
3947 }
3948 case 216:
3949 {
3950 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
3951 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_240MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3952 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3953 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3954 break;
3955 }
3956 case 172:
3957 {
3958 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
3959 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_216MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3960 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3961 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3962 break;
3963 }
3964
3965 default:
3966 {
3967 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
3968 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3969 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3970 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3971 break;
3972 }
3973 }
3974
3975 return;
3976 }
3977
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)3978 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
3979 {
3980 u32HVDRegOSBase = u32RegBase;
3981 HAL_VPU_EX_InitRegBase(u32RegBase);
3982 }
3983
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)3984 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
3985 {
3986 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
3987 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3988 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
3989 }
3990
HAL_HVD_EX_InitVariables(MS_U32 u32Id)3991 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
3992 {
3993 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3994 HVD_ShareMem *pShm = NULL;
3995 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3996 #if HVD_ENABLE_MVC
3997 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3998 #endif ///HVD_ENABLE_MVC
3999
4000 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4001 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4002 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4003 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
4004 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4005 int i;
4006 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
4007 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
4008 #if HVD_ENABLE_MVC
4009 if(bMVC)
4010 {
4011 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
4012 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
4013 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
4014 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
4015 }
4016 #endif ///HVD_ENABLE_MVC
4017
4018 // set a local copy of FW code address; assuming there is only one copy of FW,
4019 // no matter how many task will be created.
4020
4021 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4022
4023 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
4024
4025 // global variables
4026 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
4027
4028
4029 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4030 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4031 // Create mutex
4032 //_HAL_HVD_MutexCreate();
4033
4034 // fill HVD init variables
4035 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4036 {
4037 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
4038 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
4039 }
4040 else
4041 #if HVD_ENABLE_RV_FEATURE
4042 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4043 {
4044 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
4045 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
4046 #ifdef VDEC3_FB
4047 pHVDHalContext->u32RV_VLCTableAddr = 0;
4048 #else
4049 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
4050 {
4051 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
4052 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
4053 }
4054 else
4055 {
4056 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
4057 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
4058 return E_HVD_RETURN_INVALID_PARAMETER;
4059 }
4060 #endif
4061 }
4062 else
4063 #endif
4064 {
4065 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
4066 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
4067 #if HVD_ENABLE_MVC
4068 if(bMVC)
4069 {
4070 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
4071 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
4072 }
4073 #endif /// HVD_ENABLE_MVC
4074 pHVDHalContext->u32RV_VLCTableAddr = 0;
4075 }
4076
4077 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
4078 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
4079 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
4080 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
4081 {
4082 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4083 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4084 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4085 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4086 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4087 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4088 #if HVD_ENABLE_MVC
4089 if(bMVC)
4090 {
4091 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
4092 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
4093 {
4094 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
4095 }
4096 }
4097 #endif /// HVD_ENABLE_MVC
4098
4099 return E_HVD_RETURN_SUCCESS;
4100 }
4101 else
4102 {
4103 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4104 (unsigned long)MS_PA2KSEG1((MS_VIRT) pShm),
4105 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4106 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4107 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4108 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4109 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4110 return E_HVD_RETURN_INVALID_PARAMETER;
4111 }
4112 }
4113
4114 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)4115 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
4116 #else
4117 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
4118 #endif
4119 {
4120 MS_U32 u32Addr = 0;
4121 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4122 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4123 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4124
4125 MS_U32 u32TmpStartOffset;
4126 MS_U8 u8TmpMiuSel;
4127
4128
4129 memset(pShm, 0, sizeof(HVD_ShareMem));
4130
4131 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
4132
4133 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
4134 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
4135 #ifdef VDEC3
4136 if (bFWdecideFB || bCMAUsed)
4137 {
4138 pShm->u32FrameBufAddr = 0;
4139 pShm->u32FrameBufSize = 0;
4140 }
4141 else
4142 #endif
4143 {
4144 pShm->u32FrameBufAddr = u32Addr;
4145 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
4146 }
4147
4148 pShm->DispInfo.u16DispWidth = 1;
4149 pShm->DispInfo.u16DispHeight = 1;
4150 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
4151 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
4152 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
4153 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4154 //Chip info
4155 pShm->u16ChipID = E_MSTAR_CHIP_MESSI;
4156 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4157 // PreSetControl
4158 if (pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->bOnePendingBuffer)
4159 {
4160 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4161 }
4162 pShm->bUseTSPInBBUMode = FALSE;
4163
4164
4165 if ((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
4166 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4167 {
4168 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4169
4170 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
4171
4172 pShm->u32IapGnBufAddr = u32Addr;
4173 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufSize;
4174
4175 }
4176
4177 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
4178 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
4179 {
4180 case E_HVD_DEF_MFCODEC_DEFAULT:
4181 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4182 break;
4183 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
4184 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
4185 break;
4186 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
4187 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
4188 break;
4189 default:
4190 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4191 }
4192 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
4193 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
4194 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
4195 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
4196 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
4197 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
4198
4199 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4200 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4201 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4202 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4203 else
4204 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4205 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4206 {
4207 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4208 {
4209 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4210 }
4211 else
4212 {
4213 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4214 }
4215 }
4216 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4217 {
4218 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4219 {
4220 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4221 }
4222 else
4223 {
4224 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4225 }
4226 }
4227 else
4228 {
4229 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4230 }
4231 /* Messi does not support 4k2k
4232 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4233 {
4234 pShm->bHVDIMIEnable = TRUE;
4235 }*/
4236
4237 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bEnableDynamicCMA)
4238 {
4239 pShm->u8CodecFeature |= E_VDEC_DYNAMIC_CMA_MODE;
4240 }
4241
4242
4243 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4244 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4245 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4246 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4247 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4248 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4249 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4250 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4251 {
4252 pShm->bUseWbMvop = 1;
4253 }
4254
4255 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
4256 E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4257 {
4258 pShm->u8CodecFeature |= E_VDEC_TEMPORAL_SCALABILITY_MODE;
4259 }
4260
4261 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4262
4263 #if (VPU_FORCE_MIU_MODE)
4264 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4265
4266 pShm->u32FWBaseAddr = u32TmpStartOffset;
4267
4268 #else
4269 ///TODO:
4270 /*
4271 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4272
4273 if(u8TmpMiuSel == E_CHIP_MIU_0)
4274 {
4275 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4276 }
4277 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4278 {
4279 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4280 }
4281 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4282 {
4283 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4284 }
4285 */
4286 #endif
4287 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4288 #else
4289 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4290 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4291 {
4292 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4293 }
4294 pShm->u32FWBaseAddr = u32Addr;
4295 #endif
4296
4297 // RM only
4298 #if HVD_ENABLE_RV_FEATURE
4299 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4300 && (pCtrl->InitParams.pRVFileInfo != NULL))
4301 {
4302 MS_U32 i = 0;
4303
4304 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4305 {
4306 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4307 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4308 }
4309
4310 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4311 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4312 #ifdef VDEC3_FB
4313 pShm->u32RM_VLCTableAddr = 0;
4314 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4315 #else
4316 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
4317
4318 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4319 u32Addr = u32TmpStartOffset;
4320
4321 pShm->u32RM_VLCTableAddr = u32Addr;
4322 #endif
4323 }
4324 #endif
4325
4326 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4327 && (pCtrl->InitParams.pRVFileInfo != NULL))
4328 {
4329 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4330 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4331 }
4332
4333 //if(pCtrl->InitParams.bColocateBBUMode)
4334 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4335 {
4336 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4337 }
4338
4339 #if SUPPORT_G2VP9
4340 // Enable SW detile support for G2 VP9
4341 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4342 {
4343 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4344 }
4345 #endif
4346
4347 HAL_HVD_EX_FlushMemory();
4348
4349 return E_HVD_RETURN_SUCCESS;
4350 }
4351 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4352 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4353 #else
4354 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4355 #endif
4356 {
4357 MS_BOOL bInitRet = FALSE;
4358
4359 #if 0
4360 // check MVD power on
4361 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4362 {
4363 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4364 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4365 HVD_Delay_ms(1);
4366 }
4367 // Check VPU power on
4368 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4369 {
4370 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4371 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4372 HVD_Delay_ms(1);
4373 }
4374 // check HVD power on
4375 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4376 {
4377 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4378 HAL_HVD_EX_PowerCtrl(TRUE);
4379 HVD_Delay_ms(1);
4380 }
4381 #endif
4382 #ifdef VDEC3
4383 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4384 #else
4385 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4386 #endif
4387 if (!bInitRet)
4388 {
4389 return E_HVD_RETURN_FAIL;
4390 }
4391
4392 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4393
4394 if (!bInitRet)
4395 {
4396 return E_HVD_RETURN_FAIL;
4397 }
4398
4399 return E_HVD_RETURN_SUCCESS;
4400 }
4401
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4402 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4403 {
4404 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4405
4406 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4407
4408 return E_HVD_RETURN_SUCCESS;
4409 }
4410
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)4411 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
4412 {
4413 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4414 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4415 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4416 MS_BOOL bMVC = FALSE;
4417 #if HVD_ENABLE_MVC
4418 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4419 #endif
4420
4421 switch (u32type)
4422 {
4423 // share memory
4424 // switch
4425 case E_HVD_SDATA_FRAMEBUF_ADDR:
4426 {
4427 pShm->u32FrameBufAddr = u32Data;
4428 break;
4429 }
4430 case E_HVD_SDATA_FRAMEBUF_SIZE:
4431 {
4432 pShm->u32FrameBufSize = u32Data;
4433 break;
4434 }
4435 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4436 {
4437 pShm->u32FrameBuf2Addr = u32Data;
4438 break;
4439 }
4440 case E_HVD_SDATA_MAX_CMA_SIZE:
4441 {
4442 pShm->u32MaxCMAFrameBufSize = u32Data;
4443 break;
4444 }
4445 case E_HVD_SDATA_MAX_CMA_SIZE2:
4446 {
4447 pShm->u32MaxCMAFrameBuf2Size = u32Data;
4448 break;
4449 }
4450 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4451 {
4452 pShm->u32FrameBuf2Size = u32Data;
4453 break;
4454 }
4455 case E_HVD_SDATA_CMA_USED:
4456 {
4457 pShm->bCMA_Use = u32Data;
4458 break;
4459 }
4460 case E_HVD_SDATA_CMA_ALLOC_DONE:
4461 {
4462 pShm->bCMA_AllocDone = u32Data;
4463 break;
4464 }
4465 case E_HVD_SDATA_CMA_TWO_MIU:
4466 {
4467 pShm->bCMA_TwoMIU = u32Data;
4468 break;
4469 }
4470 case E_HVD_SDATA_RM_PICTURE_SIZES:
4471 {
4472 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4473 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4474 break;
4475 }
4476 case E_HVD_SDATA_ERROR_CODE:
4477 {
4478 pShm->u16ErrCode = (MS_U16) u32Data;
4479 break;
4480 }
4481 case E_HVD_SDATA_DISP_INFO_TH:
4482 {
4483 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4484 sizeof(HVD_DISP_THRESHOLD));
4485 break;
4486 }
4487 case E_HVD_SDATA_FW_FLUSH_STATUS:
4488 {
4489 pShm->u8FlushStatus = (MS_U8)u32Data;
4490 break;
4491 }
4492 case E_HVD_SDATA_DMX_FRAMERATE:
4493 {
4494 pShm->u32DmxFrameRate = u32Data;
4495 break;
4496 }
4497 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4498 {
4499 pShm->u32DmxFrameRateBase = u32Data;
4500 break;
4501 }
4502 case E_HVD_SDATA_MIU_SEL:
4503 {
4504 pShm->u32VDEC_MIU_SEL = u32Data;
4505 break;
4506 }
4507 // SRAM
4508
4509 // Mailbox
4510 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4511 {
4512 if (u32Data != 0)
4513 {
4514 pShm->bEnableDispCtrl = TRUE;
4515 pShm->bIsTrigDisp = TRUE;
4516 }
4517 else
4518 {
4519 pShm->bEnableDispCtrl = FALSE;
4520 }
4521
4522 break;
4523 }
4524 case E_HVD_SDATA_GET_DISP_INFO_START:
4525 {
4526 pShm->bSpsChange = FALSE;
4527 break;
4528 }
4529 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4530 {
4531 pShm->u32VirtualBoxWidth = u32Data;
4532 break;
4533 }
4534 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4535 {
4536 pShm->u32VirtualBoxHeight = u32Data;
4537 break;
4538 }
4539 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4540 {
4541 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4542 {
4543 //printf("DispFrame DqPtr: %d\n", u32Data);
4544 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4545 }
4546 break;
4547 }
4548 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4549 {
4550 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
4551 {
4552 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4553 {
4554 //printf("DispFrame DqPtr: %ld\n", u32Data);
4555 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4556 }
4557 }
4558 break;
4559 }
4560 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4561 {
4562 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4563 {
4564 if (bMVC)
4565 {
4566 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4567 {
4568 //ALOGE("R1: %x", u32Data);
4569 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
4570 }
4571 else
4572 {
4573 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4574 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4575 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
4576 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4577 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4578 }
4579 }
4580 else
4581 {
4582 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4583 }
4584 }
4585 else
4586 {
4587 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4588 {
4589 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4590 }
4591 }
4592 break;
4593 }
4594 #if (HVD_ENABLE_IQMEM)
4595 case E_HVD_SDATA_FW_IQMEM_CTRL:
4596 {
4597 pShm->u8IQmemCtrl= (MS_U8)u32Data;
4598 break;
4599
4600 }
4601 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
4602 {
4603 if (u32Data != 0)
4604 {
4605 pShm->bIQmemEnableIfSupport= TRUE;
4606 }
4607 else
4608 {
4609 pShm->bIQmemEnableIfSupport= FALSE;
4610 }
4611
4612
4613 break;
4614
4615 }
4616 #endif
4617
4618 default:
4619 break;
4620 }
4621
4622 HAL_HVD_EX_FlushMemory();
4623
4624 return eRet;
4625 }
4626
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4627 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4628 {
4629 MS_S64 s64Ret = 0;
4630 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4631
4632 HAL_HVD_EX_ReadMemory();
4633
4634 switch (eType)
4635 {
4636 case E_HVD_GDATA_PTS_STC_DIFF:
4637 s64Ret = pShm->s64PtsStcDiff;
4638 break;
4639 default:
4640 break;
4641 }
4642
4643 return s64Ret;
4644 }
4645
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4646 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4647 {
4648 MS_VIRT u32Ret = 0;
4649 //static MS_U64 u64pts_real = 0;
4650 MS_U64 u64pts_low = 0;
4651 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4652 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4653
4654 HAL_HVD_EX_ReadMemory();
4655
4656 if(pShm == NULL)
4657 {
4658 HVD_EX_MSG_ERR("########## VDEC patch for Debug ###########\n");
4659 return 0x0;
4660 }
4661
4662 switch (eType)
4663 {
4664 // share memory
4665 // switch
4666 case E_HVD_GDATA_DISP_INFO_ADDR:
4667 {
4668 u32Ret = (MS_VIRT) (&pShm->DispInfo);
4669 break;
4670 }
4671 case E_HVD_GDATA_MIU_SEL:
4672 u32Ret = pShm->u32VDEC_MIU_SEL;
4673 break;
4674 case E_HVD_GDATA_FRAMEBUF_ADDR:
4675 u32Ret = pShm->u32FrameBufAddr;
4676 break;
4677 case E_HVD_GDATA_FRAMEBUF_SIZE:
4678 u32Ret = pShm->u32FrameBufSize;
4679 break;
4680 case E_HVD_GDATA_FRAMEBUF2_ADDR:
4681 u32Ret = pShm->u32FrameBuf2Addr;
4682 break;
4683 case E_HVD_GDATA_FRAMEBUF2_SIZE:
4684 u32Ret = pShm->u32FrameBuf2Size;
4685 break;
4686 case E_HVD_GDATA_CMA_ALLOC_DONE:
4687 u32Ret = pShm->bCMA_AllocDone;
4688 break;
4689 case E_HVD_GDATA_CMA_USED:
4690 u32Ret = pShm->bCMA_Use;
4691 break;
4692 // report
4693 case E_HVD_GDATA_PTS:
4694 {
4695 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
4696 break;
4697 }
4698 case E_HVD_GDATA_U64PTS:
4699 {
4700 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
4701 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
4702 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4703 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4704 break;
4705 }
4706 case E_HVD_GDATA_U64PTS_PRE_PARSE:
4707 {
4708 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
4709 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
4710 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4711 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4712 break;
4713 }
4714 case E_HVD_GDATA_DECODE_CNT:
4715 {
4716 u32Ret = pShm->u32DecodeCnt;
4717 break;
4718 }
4719 case E_HVD_GDATA_DATA_ERROR_CNT:
4720 {
4721 u32Ret = pShm->u32DataErrCnt;
4722 break;
4723 }
4724 case E_HVD_GDATA_DEC_ERROR_CNT:
4725 {
4726 u32Ret = pShm->u32DecErrCnt;
4727 break;
4728 }
4729 case E_HVD_GDATA_ERROR_CODE:
4730 {
4731 u32Ret = (MS_U32) (pShm->u16ErrCode);
4732 break;
4733 }
4734 case E_HVD_GDATA_VPU_IDLE_CNT:
4735 {
4736 u32Ret = pShm->u32VPUIdleCnt;
4737 break;
4738 }
4739 case E_HVD_GDATA_DISP_FRM_INFO:
4740 {
4741 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
4742 break;
4743 }
4744 case E_HVD_GDATA_DEC_FRM_INFO:
4745 {
4746 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
4747 break;
4748 }
4749 case E_HVD_GDATA_ES_LEVEL:
4750 {
4751 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
4752 break;
4753 }
4754 #if HVD_ENABLE_MVC
4755 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
4756 {
4757 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
4758 break;
4759 }
4760 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
4761 {
4762 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
4763 break;
4764 }
4765 #endif
4766
4767 // user data
4768 case E_HVD_GDATA_USERDATA_WPTR:
4769 {
4770 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
4771 break;
4772 }
4773 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
4774 {
4775 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
4776 break;
4777 }
4778 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
4779 {
4780 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
4781 break;
4782 }
4783 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
4784 {
4785 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
4786 break;
4787 }
4788 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
4789 {
4790 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
4791 break;
4792 }
4793 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
4794 {
4795 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
4796 break;
4797 }
4798 // report - modes
4799 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
4800 {
4801 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
4802 break;
4803 }
4804 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
4805 {
4806 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
4807 break;
4808 }
4809 case E_HVD_GDATA_IS_ERR_CONCEAL:
4810 {
4811 u32Ret = pShm->ModeStatus.bIsErrConceal;
4812 break;
4813 }
4814 case E_HVD_GDATA_IS_SYNC_ON:
4815 {
4816 u32Ret = pShm->ModeStatus.bIsSyncOn;
4817 break;
4818 }
4819 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
4820 {
4821 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
4822 break;
4823 }
4824 case E_HVD_GDATA_SYNC_MODE:
4825 {
4826 u32Ret = pShm->ModeStatus.u8SyncType;
4827 break;
4828 }
4829 case E_HVD_GDATA_SKIP_MODE:
4830 {
4831 u32Ret = pShm->ModeStatus.u8SkipMode;
4832 break;
4833 }
4834 case E_HVD_GDATA_DROP_MODE:
4835 {
4836 u32Ret = pShm->ModeStatus.u8DropMode;
4837 break;
4838 }
4839 case E_HVD_GDATA_DISPLAY_DURATION:
4840 {
4841 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
4842 break;
4843 }
4844 case E_HVD_GDATA_FRC_MODE:
4845 {
4846 u32Ret = pShm->ModeStatus.u8FrcMode;
4847 break;
4848 }
4849 case E_HVD_GDATA_NEXT_PTS:
4850 {
4851 u32Ret = pShm->u32NextPTS;
4852 break;
4853 }
4854 case E_HVD_GDATA_DISP_Q_SIZE:
4855 {
4856 u32Ret = pShm->u16DispQSize;
4857 break;
4858 }
4859 case E_HVD_GDATA_DISP_Q_PTR:
4860 {
4861 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
4862 break;
4863 }
4864 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
4865 {
4866 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
4867 break;
4868 }
4869 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
4870 {
4871 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
4872 break;
4873 }
4874 case E_HVD_GDATA_REAL_FRAMERATE:
4875 {
4876 // return VPS/VUI timing info framerate, and 0 if timing info not exist
4877 u32Ret = pShm->u32RealFrameRate;
4878 break;
4879 }
4880 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
4881 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
4882 break;
4883 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
4884 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
4885 break;
4886 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
4887 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
4888 break;
4889 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
4890 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
4891 break;
4892 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
4893 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
4894 break;
4895 case E_HVD_GDATA_FW_STATUS_FLAG:
4896 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
4897 break;
4898
4899 // internal control
4900 case E_HVD_GDATA_IS_1ST_FRM_RDY:
4901 {
4902 u32Ret = pShm->bIs1stFrameRdy;
4903 break;
4904 }
4905 case E_HVD_GDATA_IS_I_FRM_FOUND:
4906 {
4907 u32Ret = pShm->bIsIFrmFound;
4908 break;
4909 }
4910 case E_HVD_GDATA_IS_SYNC_START:
4911 {
4912 u32Ret = pShm->bIsSyncStart;
4913 break;
4914 }
4915 case E_HVD_GDATA_IS_SYNC_REACH:
4916 {
4917 u32Ret = pShm->bIsSyncReach;
4918 break;
4919 }
4920 case E_HVD_GDATA_FW_VERSION_ID:
4921 {
4922 u32Ret = pShm->u32FWVersionID;
4923 break;
4924 }
4925 case E_HVD_GDATA_FW_IF_VERSION_ID:
4926 {
4927 u32Ret = pShm->u32FWIfVersionID;
4928 break;
4929 }
4930 case E_HVD_GDATA_BBU_Q_NUMB:
4931 {
4932 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
4933 break;
4934 }
4935 case E_HVD_GDATA_DEC_Q_NUMB:
4936 {
4937 u32Ret = pShm->u16DecQNumb;
4938 break;
4939 }
4940 case E_HVD_GDATA_DISP_Q_NUMB:
4941 {
4942 u32Ret = pShm->u16DispQNumb;
4943 break;
4944 }
4945 case E_HVD_GDATA_PTS_Q_NUMB:
4946 {
4947 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
4948 break;
4949 }
4950 case E_HVD_GDATA_FW_INIT_DONE:
4951 {
4952 u32Ret = pShm->bInitDone;
4953 break;
4954 }
4955 // debug
4956 case E_HVD_GDATA_SKIP_CNT:
4957 {
4958 u32Ret = pShm->u32SkipCnt;
4959 break;
4960 }
4961 case E_HVD_GDATA_GOP_CNT:
4962 {
4963 u32Ret = pShm->u32DropCnt;
4964 break;
4965 }
4966 case E_HVD_GDATA_DISP_CNT:
4967 {
4968 u32Ret = pShm->u32DispCnt;
4969 break;
4970 }
4971 case E_HVD_GDATA_DROP_CNT:
4972 {
4973 u32Ret = pShm->u32DropCnt;
4974 break;
4975 }
4976 case E_HVD_GDATA_DISP_STC:
4977 {
4978 u32Ret = pShm->u32DispSTC;
4979 break;
4980 }
4981 case E_HVD_GDATA_VSYNC_CNT:
4982 {
4983 u32Ret = pShm->u32VsyncCnt;
4984 break;
4985 }
4986 case E_HVD_GDATA_MAIN_LOOP_CNT:
4987 {
4988 u32Ret = pShm->u32MainLoopCnt;
4989 break;
4990 }
4991
4992 // AVC
4993 case E_HVD_GDATA_AVC_LEVEL_IDC:
4994 {
4995 u32Ret = pShm->u16AVC_SPS_LevelIDC;
4996 break;
4997 }
4998 case E_HVD_GDATA_AVC_LOW_DELAY:
4999 {
5000 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
5001 break;
5002 }
5003 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
5004 {
5005 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
5006 break;
5007 }
5008 case E_HVD_GDATA_FW_FLUSH_STATUS:
5009 {
5010 u32Ret = (MS_U32) (pShm->u8FlushStatus);
5011 break;
5012 }
5013 case E_HVD_GDATA_FW_CODEC_TYPE:
5014 {
5015 u32Ret = pShm->u32CodecType;
5016 break;
5017 }
5018 case E_HVD_GDATA_FW_ES_BUF_STATUS:
5019 {
5020 u32Ret = (MS_U32)pShm->u8ESBufStatus;
5021 break;
5022 }
5023 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
5024 {
5025 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
5026 {
5027 u32Ret = 1;
5028 }
5029 else
5030 {
5031 u32Ret = 0;
5032 }
5033 break;
5034 }
5035
5036 // SRAM
5037
5038 // Mailbox
5039 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
5040 {
5041 u32Ret = pShm->u32FwState;
5042 break;
5043 }
5044 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
5045 {
5046 u32Ret = pShm->bSpsChange;
5047 break;
5048 }
5049 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
5050 {
5051 u32Ret = pShm->bSpsChange;
5052
5053 if (pShm->bSpsChange &&
5054 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
5055 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
5056 {
5057 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
5058 }
5059
5060 break;
5061 }
5062 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
5063 {
5064 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5065
5066 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
5067 {
5068 u32Ret = pShm->u32FwInfo;
5069 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
5070 }
5071 break;
5072 }
5073 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
5074 {
5075 if (pShm->bIsTrigDisp) // not clear yet
5076 {
5077 u32Ret = FALSE;
5078 }
5079 else
5080 {
5081 u32Ret = TRUE;
5082 }
5083 break;
5084 }
5085 case E_HVD_GDATA_ES_READ_PTR:
5086 {
5087 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5088 break;
5089 }
5090 case E_HVD_GDATA_ES_WRITE_PTR:
5091 {
5092 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
5093 break;
5094 }
5095 case E_HVD_GDATA_BBU_READ_PTR:
5096 {
5097 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
5098 break;
5099 }
5100 case E_HVD_GDATA_BBU_WRITE_PTR:
5101 {
5102 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5103 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5104 {
5105 u32Ret = pHVDHalContext->u32VP8BBUWptr;
5106 }
5107 else
5108 {
5109 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5110 }
5111 break;
5112 }
5113 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
5114 {
5115 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5116
5117 u32Ret = pCtrl->u32BBUWptr_Fired;
5118
5119 break;
5120 }
5121 case E_HVD_GDATA_VPU_PC_CNT:
5122 {
5123 u32Ret = _HVD_EX_GetPC();
5124 break;
5125 }
5126 case E_HVD_GDATA_ES_QUANTITY:
5127 {
5128 u32Ret=_HVD_EX_GetESQuantity(u32Id);
5129 break;
5130 }
5131
5132
5133 // FW def
5134 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
5135 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
5136 break;
5137
5138 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
5139 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
5140 break;
5141 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
5142 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
5143 break;
5144 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
5145 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5146 break;
5147 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
5148 u32Ret = MAX_PTS_TABLE_SIZE;
5149 break;
5150 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
5151 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
5152 break;
5153 case E_HVD_GDATA_FW_DS_BUF_ADDR:
5154 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
5155 break;
5156 case E_HVD_GDATA_FW_DS_BUF_SIZE:
5157 u32Ret = pShm->u32DSBuffSize; //3k or 6k
5158 break;
5159 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
5160 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
5161 break;
5162 case E_HVD_GDATA_FW_DS_INFO_ADDR:
5163 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
5164 break;
5165 case E_HVD_GDATA_FW_DS_IS_ENABLED:
5166 {
5167 if (pShm->bDSIsRunning)
5168 {
5169 u32Ret = TRUE;
5170 }
5171 else
5172 {
5173 u32Ret = FALSE;
5174 }
5175 break;
5176 }
5177 #if (HVD_ENABLE_IQMEM)
5178 case E_HVD_GDATA_FW_IQMEM_CTRL:
5179 {
5180
5181 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
5182
5183 break;
5184 }
5185 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
5186 {
5187 if(pShm->bIsIQMEMSupport){
5188 u32Ret = TRUE;
5189 }
5190 else{
5191
5192 u32Ret = FALSE;
5193 }
5194
5195 break;
5196 }
5197 #endif
5198 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
5199 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
5200 break;
5201 case E_HVD_GDATA_FIELD_PIC_FLAG:
5202 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
5203 break;
5204 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
5205 u32Ret = pShm->u32SeamlessTSStatus;
5206 break;
5207 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
5208 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
5209 break;
5210 #ifdef VDEC3
5211 case E_HVD_GDATA_FW_VBBU_ADDR:
5212 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
5213 break;
5214 #endif
5215 default:
5216 break;
5217 }
5218 return u32Ret;
5219 }
5220
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)5221 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
5222 {
5223 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5224 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
5225 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5226
5227 _HAL_HVD_Entry();
5228
5229 // check if old SVD cmds
5230 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5231 {
5232 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
5233
5234 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5235 }
5236
5237 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5238 {
5239 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5240 }
5241
5242 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5243 {
5244 if (u32Cmd == E_HVD_CMD_FLUSH)
5245 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5246 }
5247
5248 if (u32Cmd == E_HVD_CMD_FLUSH &&
5249 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5250 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5251 {
5252 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5253 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5254 {
5255 _HAL_HVD_Release();
5256 HVD_Delay_ms(1);
5257 _HAL_HVD_Entry();
5258 }
5259 }
5260
5261 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
5262
5263 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5264
5265 _HAL_HVD_Return(eRet);
5266 }
5267
HAL_HVD_EX_DeInit(MS_U32 u32Id)5268 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5269 {
5270 HVD_Return eRet = E_HVD_RETURN_FAIL;
5271 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5272 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5273 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5274 MS_U8 u8MiuSel;
5275 MS_U32 u32StartOffset;
5276 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5277
5278 #if HVD_ENABLE_TIME_MEASURE
5279 MS_U32 ExitTimeCnt = 0;
5280 ExitTimeCnt = HVD_GetSysTime_ms();
5281 #endif
5282
5283 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
5284
5285 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5286
5287 if (E_HVD_RETURN_SUCCESS != eRet)
5288 {
5289 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5290 }
5291
5292 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5293
5294 if (E_HVD_RETURN_SUCCESS != eRet)
5295 {
5296 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5297 }
5298
5299 // check FW state to make sure it's STOP DONE
5300 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5301 {
5302 if (HVD_GetSysTime_ms() > u32Timeout)
5303 {
5304 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
5305
5306 //return E_HVD_RETURN_TIMEOUT;
5307 eRet = E_HVD_RETURN_TIMEOUT;
5308 break;
5309 }
5310 }
5311
5312 if (pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt)
5313 {
5314 HVD_EX_MSG_INF("VDEC PLUS: DropRatio %d, Drop:0.%d (%d), Dec:0.%d (%d), Disp:0.%d\n",
5315 pShm->u8VdecPlusDropRatio,
5316 100*pShm->u32VdecPlusDropCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5317 pShm->u32VdecPlusDropCnt,
5318 100*pShm->u32VdecPlusDecCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5319 pShm->u32VdecPlusDecCnt,
5320 100*pShm->u32VdecPlusDispPicCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt));
5321 }
5322 else
5323 {
5324 HVD_EX_MSG_INF("VDEC PLUS DISABLE: DropRatio %d, Drop: %d, Dec: %d, Disp: %d\n",
5325 pShm->u8VdecPlusDropRatio,
5326 pShm->u32VdecPlusDropCnt,
5327 pShm->u32VdecPlusDecCnt,
5328 pShm->u32VdecPlusDispPicCnt);
5329 }
5330
5331 VPU_EX_FWCodeCfg fwCfg;
5332 VPU_EX_TaskInfo taskInfo;
5333 VPU_EX_NDecInitPara nDecInitPara;
5334
5335 nDecInitPara.pFWCodeCfg = &fwCfg;
5336 nDecInitPara.pTaskInfo = &taskInfo;
5337
5338 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5339 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5340
5341 taskInfo.u32Id = u32Id;
5342 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5343 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5344
5345 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5346 {
5347 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5348 }
5349 else
5350 {
5351 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5352 }
5353
5354 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5355 {
5356 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5357 }
5358
5359 /* clear es buffer */
5360 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5361 {
5362 //printf("Clear ES buffer\n");
5363
5364 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5365 }
5366
5367 //_HAL_HVD_MutexDelete();
5368
5369 #if HVD_ENABLE_TIME_MEASURE
5370 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5371 #endif
5372
5373 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
5374 #ifndef VDEC3
5375 // reset bbu wptr
5376 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5377 {
5378 if(TRUE == HAL_VPU_EX_HVDInUsed())
5379 {
5380 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5381 {
5382 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5383 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5384 }
5385 else
5386 {
5387 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5388 {
5389 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5390 }
5391 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5392 }
5393 }
5394 else
5395 {
5396 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
5397 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
5398 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
5399 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5400 {
5401 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5402 {
5403 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5404 }
5405 }
5406 else
5407 {
5408 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5409 }
5410 }
5411 }
5412 #endif
5413 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5414
5415 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5416 {
5417 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
5418 }
5419
5420 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
5421 {
5422
5423 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
5424
5425 _HAL_HVD_Entry();
5426 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
5427 _HAL_HVD_Release();
5428
5429 }
5430
5431 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
5432 HVD_EX_MSG_DBG("success\n");
5433
5434 return eRet;
5435 }
5436
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5437 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5438 {
5439 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5440 MS_U32 u32Addr = 0;
5441 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5442 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5443
5444 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5445
5446 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5447 {
5448 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5449
5450 if (E_HVD_RETURN_SUCCESS != eRet)
5451 {
5452 return eRet;
5453 }
5454 }
5455
5456 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5457
5458 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5459 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5460 {
5461 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5462
5463 if (E_HVD_RETURN_SUCCESS != eRet)
5464 {
5465 return eRet;
5466 }
5467 }
5468
5469 u32Addr = pInfo->u32Staddr;
5470
5471 if (pInfo->bRVBrokenPacket)
5472 {
5473 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5474 }
5475
5476 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5477 {
5478 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5479 }
5480 else
5481 {
5482 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5483 }
5484
5485 if (E_HVD_RETURN_SUCCESS != eRet)
5486 {
5487 return eRet;
5488 }
5489
5490 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5491 {
5492 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5493 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5494
5495 if (E_HVD_RETURN_SUCCESS != eRet)
5496 {
5497 return eRet;
5498 }
5499 }
5500
5501 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5502
5503 // do not add local pointer
5504 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5505 {
5506 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5507
5508 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5509 (u32PacketStAddr <
5510 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5511 {
5512 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5513 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5514 }
5515 else
5516 {
5517 //null packet
5518 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5519 pCtrl->LastNal.u32NalSize = 0;
5520 }
5521 }
5522 else
5523 {
5524 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5525 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5526 }
5527
5528 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5529 pCtrl->u32BBUPacketCnt++;
5530
5531 return eRet;
5532 }
5533
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5534 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5535 {
5536 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5537 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5538 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
5539 if(bCurrentStatus == bEnable)
5540 return;
5541
5542 if (bEnable)
5543 {
5544 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5545 }
5546 else
5547 {
5548 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5549 }
5550 }
5551
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5552 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5553 {
5554 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5555 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5556
5557 if (bEnable)
5558 {
5559 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5560 }
5561 else
5562 {
5563 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5564 }
5565 }
5566
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)5567 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
5568 {
5569 MS_U32 u32RB = 0;
5570 switch(eISRType)
5571 {
5572 case E_HWDEC_ISR_HVD:
5573 u32RB = REG_HVD_BASE;
5574 break;
5575 #if SUPPORT_EVD
5576 case E_HWDEC_ISR_EVD:
5577 u32RB = REG_EVD_BASE;
5578 break;
5579 #endif
5580 #if SUPPORT_G2VP9
5581 case E_HWDEC_ISR_G2VP9:
5582 break;
5583 #endif
5584 default:
5585 break;
5586 }
5587 if(u32RB)
5588 {
5589 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5590 }
5591 }
5592
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5593 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5594 {
5595 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5596 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5597
5598 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5599 }
5600
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)5601 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
5602 {
5603 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5604 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5605
5606 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
5607 {
5608 return FALSE;
5609 }
5610 else
5611 {
5612 return TRUE;
5613 }
5614 }
5615
HAL_HVD_EX_IsAlive(MS_U32 u32Id)5616 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
5617 {
5618 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5619
5620 if (pCtrl)
5621 {
5622 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
5623 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
5624 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
5625 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
5626 {
5627 return FALSE;
5628 }
5629 else
5630 {
5631 return TRUE;
5632 }
5633 }
5634 else
5635 {
5636 return FALSE;
5637 }
5638 }
5639
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)5640 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
5641 {
5642 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5643 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5644 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5645
5646 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5647 {
5648 HAL_HVD_EX_ReadMemory();
5649
5650 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
5651 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
5652
5653 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
5654 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
5655 }
5656
5657 return TRUE;
5658 }
5659
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)5660 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
5661 {
5662 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5663 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5664 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5665 MS_U32 u32Data;
5666 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5667
5668 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
5669
5670 HAL_HVD_EX_FlushMemory();
5671 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5672 {
5673 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5674 pCtrl->LastNal.u32NalAddr = u32Data;
5675 pCtrl->LastNal.u32NalSize = 0;
5676 }
5677
5678 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5679 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
5680
5681 return TRUE;
5682 }
5683
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)5684 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
5685 {
5686 if (bEnable)
5687 {
5688 if (HAL_VPU_EX_IsEVDR2())
5689 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5690 else
5691 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
5692 }
5693 else
5694 {
5695 #if defined (__aeon__)
5696 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5697 #else // defined (__mips__)
5698 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
5699 #endif
5700 }
5701 }
5702
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)5703 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
5704 {
5705 return 0;
5706 }
5707
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)5708 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
5709 {
5710 return;
5711 }
5712
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)5713 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
5714 {
5715 //if( u16Clock == 0 )
5716 return 216; //140;
5717 //if( )
5718 }
5719
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)5720 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
5721 {
5722 //MS_BOOL bBitMIU1 = FALSE;
5723 //MS_BOOL bCodeMIU1 = FALSE;
5724 MS_U8 u8BitMiuSel = 0;
5725 MS_U8 u8CodeMiuSel = 0;
5726 MS_U32 u32BitStartOffset;
5727 MS_U32 u32CodeStartOffset;
5728 //MS_U8 u8MiuSel;
5729 //MS_U32 u32StartOffset;
5730 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5731 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5732 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5733 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
5734
5735 #if HVD_ENABLE_MVC
5736 if(HAL_HVD_EX_CheckMVCID(u32Id))
5737 {
5738 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
5739 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
5740 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
5741 {
5742 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
5743 }
5744 }
5745 #endif /// HVD_ENABLE_MVC
5746
5747 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
5748 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5749
5750
5751
5752
5753 if (u8BitMiuSel != u8CodeMiuSel)
5754 {
5755 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
5756 BDMA_Result bdmaRlt;
5757 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5758
5759 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5760 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
5761 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5762
5763 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
5764
5765 if (E_BDMA_OK != bdmaRlt)
5766 {
5767 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
5768 }
5769 #else
5770 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5771
5772 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5773 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
5774 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5775
5776 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
5777 #endif
5778 }
5779
5780 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
5781
5782 HAL_HVD_EX_FlushMemory();
5783
5784 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5785 {
5786 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
5787 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
5788 }
5789 else
5790 {
5791 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
5792
5793 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5794 }
5795 }
5796
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)5797 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
5798 {
5799 if (bEnable)
5800 {
5801 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
5802 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
5803 }
5804 else
5805 {
5806 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
5807 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
5808 }
5809 }
5810
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)5811 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
5812 {
5813 MS_U32 tmp1 = 0;
5814 MS_U32 tmp2 = 0;
5815 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5816
5817 HAL_HVD_EX_ReadMemory();
5818
5819 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
5820 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
5821
5822 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
5823 {
5824 MS_U32 u32Tmp = u32UartCtrl;
5825
5826 HVD_EX_MSG_DBG("\n");
5827 u32UartCtrl = 0; // turn off debug message to prevent other function prints
5828 HVD_EX_MSG_INF("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
5829 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
5830
5831 HVD_EX_MSG_INF("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
5832 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
5833 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
5834 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
5835
5836 HVD_EX_MSG_INF("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
5837 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
5838 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
5839
5840 HVD_EX_MSG_INF("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
5841 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
5842 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
5843 _HVD_EX_GetESLevel(u32Id));
5844
5845 HVD_EX_MSG_INF("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
5846 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
5847 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
5848 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
5849 HVD_EX_MSG_INF
5850 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
5851 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
5852 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
5853 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
5854 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
5855 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
5856 pShm->ModeStatus.bShowOneField);
5857
5858 u32UartCtrl = u32Tmp; // recover debug level
5859 }
5860 }
5861
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)5862 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
5863 {
5864 MS_U8 *u32Addr = NULL;
5865 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5866 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5867
5868 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
5869 {
5870 return;
5871 }
5872
5873 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
5874
5875 *u32NalSize = *(u32Addr + 2) & 0x1f;
5876 *u32NalSize <<= 8;
5877 *u32NalSize |= *(u32Addr + 1) & 0xff;
5878 *u32NalSize <<= 8;
5879 *u32NalSize |= *(u32Addr) & 0xff;
5880
5881 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
5882 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
5883 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
5884 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
5885 }
5886
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)5887 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
5888 {
5889 MS_U32 u32CurIdx = 0;
5890 MS_BOOL bFinished = FALSE;
5891 MS_U32 u32NalOffset = 0;
5892 MS_U32 u32NalSize = 0;
5893 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5894
5895 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
5896 {
5897 return;
5898 }
5899
5900 u32CurIdx = u32StartIdx;
5901
5902 do
5903 {
5904 if (u32CurIdx == u32EndIdx)
5905 {
5906 bFinished = TRUE;
5907 }
5908
5909 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
5910
5911 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
5912 {
5913 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
5914 }
5915
5916 u32CurIdx++;
5917
5918 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
5919 {
5920 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5921 }
5922 } while (bFinished == TRUE);
5923 }
5924
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)5925 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
5926 {
5927 MS_U32 i = 0;
5928 MS_U32 value = 0;
5929
5930 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
5931 {
5932 HVD_EX_MSG_DBG("\n");
5933
5934 for (i = 0; i <= u32Num; i++)
5935 {
5936 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
5937 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
5938 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
5939
5940 if (value == 0)
5941 {
5942 break;
5943 }
5944
5945 HVD_EX_MSG_DBG(" %08x", value);
5946
5947 if (((i % 8) + 1) == 8)
5948 {
5949 HVD_EX_MSG_DBG(" |%u\n", i + 1);
5950 }
5951 }
5952
5953 HVD_EX_MSG_DBG("\nHVD Dump HW status End: total number:%u\n", i);
5954 }
5955 }
5956
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)5957 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
5958 {
5959 if (pDrvCtrl)
5960 {
5961 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
5962 }
5963 }
5964
5965 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)5966 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
5967 {
5968 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
5969 }
5970
HAL_HVD_EX_GetView(MS_U32 u32Id)5971 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
5972 {
5973 if( (0xFF & (u32Id >> 8)) == 0x10)
5974 return E_VDEC_EX_MAIN_VIEW;
5975 else
5976 return E_VDEC_EX_SUB_VIEW;
5977 }
5978 #endif ///HVD_ENABLE_MVC
5979
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)5980 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
5981 {
5982 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
5983 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
5984 return;
5985 }
5986
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)5987 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
5988 {
5989 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
5990 return;
5991 }
5992
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)5993 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
5994 {
5995 MS_U64 _hw_max_pixel = 0;
5996 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
5997
5998 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
5999 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
6000 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
6001 }
6002
6003
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)6004 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
6005 {
6006 #if 1
6007 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6008 MS_U16 u16QNum = pShm->u16DispQNumb;
6009 MS_U16 u16QPtr = pShm->u16DispQPtr;
6010 // MS_U16 u16QSize = pShm->u16DispQSize;
6011 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
6012 MS_U32 u32DispQNum = 0;
6013 #if HVD_ENABLE_MVC
6014 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
6015
6016 if(bMVC)
6017 {
6018 #if 0
6019 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
6020 {
6021 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
6022 }
6023 #endif
6024
6025 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
6026 //search the next frame to display
6027 while (u16QNum > 0)
6028 {
6029 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
6030 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
6031 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6032
6033 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
6034 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6035 {
6036 /// For MVC. Output views after the pair of (base and depend) views were decoded.
6037 /// Check the depned view was initial when Output the base view.
6038 if((u16QPtr%2) == 0)
6039 {
6040 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
6041 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
6042 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
6043 {
6044 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
6045 ///printf("Return NULL.\n");
6046 continue;
6047 }
6048 }
6049 u32DispQNum++;
6050 }
6051
6052 u16QNum--;
6053 //go to next frame in the dispQ
6054 u16QPtr++;
6055
6056 if (u16QPtr >= pShm->u16DispQSize)
6057 {
6058 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
6059 }
6060 }
6061 }
6062 else
6063 #endif ///HVD_ENABLE_MVC
6064 {
6065 #if 0
6066 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
6067 {
6068 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
6069 }
6070 #endif
6071 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
6072 //search the next frame to display
6073 while (u16QNum != 0)
6074 {
6075 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6076
6077 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
6078 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6079 {
6080 u32DispQNum++;
6081 }
6082
6083 u16QNum--;
6084 //go to next frame in the dispQ
6085 u16QPtr++;
6086
6087 if (u16QPtr == pShm->u16DispQSize)
6088 {
6089 u16QPtr = 0; //wrap to the begin
6090 }
6091 }
6092 }
6093
6094 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
6095 return u32DispQNum;
6096 #else
6097 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
6098 return pShm->u16DispQNumb;
6099 #endif
6100 }
6101
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)6102 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
6103 {
6104 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6105 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
6106 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6107 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
6108 #if SUPPORT_G2VP9 && defined(VDEC3)
6109 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
6110 #else // Not using G2 VP9 implies using Mstar EVD VP9
6111 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6112 #endif
6113 else
6114 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
6115 }
6116
6117 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)6118 void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)
6119 {
6120 if (bEnable)
6121 {
6122 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6123 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6124 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6125 }
6126 else
6127 {
6128 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6129 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6130 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6131 }
6132
6133 switch (pHVDHalContext->u32EVDClockType)
6134 {
6135 case 576:
6136 {
6137 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6138 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6139 break;
6140 }
6141 case 532:
6142 {
6143 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
6144 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
6145 break;
6146 }
6147 case 466:
6148 {
6149 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6150 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
6151 break;
6152 }
6153 case 480:
6154 {
6155 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6156 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6157 break;
6158 }
6159 case 384:
6160 {
6161 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
6162 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
6163 break;
6164 }
6165 case 320:
6166 {
6167 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
6168 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
6169 break;
6170 }
6171 case 240:
6172 {
6173 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
6174 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6175 break;
6176 }
6177 case 192:
6178 {
6179 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
6180 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
6181 break;
6182 }
6183 default:
6184 {
6185 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6186 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6187 break;
6188 }
6189 }
6190
6191 return;
6192 }
6193
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)6194 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
6195 {
6196 #ifndef VDEC3
6197 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6198 #endif
6199 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6200 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6201 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6202
6203 #ifdef VDEC3
6204 if (0 == pCtrl->u32BBUId)
6205 #else
6206 if (0 == u8TaskId)
6207 #endif
6208 {
6209 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
6210 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6211 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)) & (~HVD_REG_BBU_TSP_INPUT));
6212 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)));
6213 }
6214 else
6215 {
6216 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
6217 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6218 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)) & (~HVD_REG_BBU_TSP_INPUT_BS2));
6219 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)));
6220 }
6221
6222 return;
6223 }
6224
HAL_EVD_EX_DeinitHW(void)6225 static MS_BOOL HAL_EVD_EX_DeinitHW(void)
6226 {
6227 MS_U16 u16Timeout = 1000;
6228
6229 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
6230
6231 while (u16Timeout)
6232 {
6233 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
6234 {
6235 break;
6236 }
6237 u16Timeout--;
6238 }
6239
6240 HAL_EVD_EX_PowerCtrl(FALSE);
6241
6242 return TRUE;
6243 }
6244 #endif
6245
6246 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)6247 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
6248 {
6249 if (bEnable)
6250 {
6251 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6252 }
6253 else
6254 {
6255 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6256 }
6257
6258 switch (pHVDHalContext->u32VP9ClockType)
6259 {
6260 case 432:
6261 {
6262 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6263 break;
6264 }
6265 case 384:
6266 {
6267 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6268 break;
6269 }
6270 case 345:
6271 {
6272 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6273 break;
6274 }
6275 case 320:
6276 {
6277 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6278 break;
6279 }
6280 case 288:
6281 {
6282 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6283 break;
6284 }
6285 case 240:
6286 {
6287 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6288 break;
6289 }
6290 case 216:
6291 {
6292 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6293 break;
6294 }
6295 case 172:
6296 {
6297 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
6298 break;
6299 }
6300 default:
6301 {
6302 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6303 break;
6304 }
6305 }
6306
6307 return;
6308 }
6309
HAL_VP9_EX_DeinitHW(void)6310 MS_BOOL HAL_VP9_EX_DeinitHW(void)
6311 {
6312 MS_U16 u16Timeout = 1000;
6313
6314 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6315
6316 while (u16Timeout)
6317 {
6318 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6319 {
6320 break;
6321 }
6322 u16Timeout--;
6323 }
6324
6325 HAL_VP9_EX_PowerCtrl(FALSE);
6326
6327 return TRUE;
6328 }
6329 #endif
6330
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6331 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6332 {
6333 return TRUE;
6334 }
HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)6335 void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)
6336 {
6337 _HVD_EX_SetBufferAddr(u32Id);
6338 }
6339
6340
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)6341 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6342 {
6343 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6344
6345 if(pCtrl->InitParams.u16ChipECONum == 0)
6346 return FALSE;
6347 else
6348 return TRUE;
6349
6350 }
6351
6352
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6353 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6354 {
6355
6356 }
6357
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6358 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6359 {
6360
6361 }
6362 #endif
6363