1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126 #define RV_VLC_TABLE_SIZE 0x20000
127 /* Add for Mobile Platform by Ted Sun */
128 //#define HVD_DISPQ_PREFETCH_COUNT 2
129 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
130 #define VPU_QMEM_BASE 0x20000000UL
131
132 //max support pixel(by chip capacity)
133 #define HVD_HW_MAX_PIXEL (1920*1080*61000ULL) // FHD@60p
134 #define HEVC_HW_MAX_PIXEL (2048*1088*61000ULL) // UHD@60p
135 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
136
137 #if 0
138 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
139 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
140 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
141 static MS_U16 _u16DispQPtr = 0;
142 #endif
143
144 #define IS_TASK_ALIVE(id) ((id) != -1)
145 #ifndef UNUSED
146 #define UNUSED(x) (void)(x)
147 #endif
148
149
150 //---------------------------------- Mutex settings -----------------------------------------
151 #if HAL_HVD_ENABLE_MUTEX_PROTECT
152 #define _HAL_HVD_MutexCreate() \
153 do \
154 { \
155 if (s32HVDMutexID < 0) \
156 { \
157 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
158 } \
159 } while (0)
160
161 #define _HAL_HVD_MutexDelete() \
162 do \
163 { \
164 if (s32HVDMutexID >= 0) \
165 { \
166 OSAL_HVD_MutexDelete(s32HVDMutexID); \
167 s32HVDMutexID = -1; \
168 } \
169 } while (0)
170
171 #define _HAL_HVD_Entry() \
172 do \
173 { \
174 if (s32HVDMutexID >= 0) \
175 { \
176 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
177 { \
178 HVD_PRINT("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
179 } \
180 } \
181 } while (0)
182
183 #define _HAL_HVD_Return(_ret_) \
184 do \
185 { \
186 if (s32HVDMutexID >= 0) \
187 { \
188 OSAL_HVD_MutexRelease(s32HVDMutexID); \
189 } \
190 return _ret_; \
191 } while(0)
192
193 #define _HAL_HVD_Release() \
194 do \
195 { \
196 if (s32HVDMutexID >= 0) \
197 { \
198 OSAL_HVD_MutexRelease(s32HVDMutexID); \
199 } \
200 } while (0)
201 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
202
203 #define _HAL_HVD_MutexCreate()
204 #define _HAL_HVD_MutexDelete()
205 #define _HAL_HVD_Entry()
206 #define _HAL_HVD_Return(_ret) {return _ret;}
207 #define _HAL_HVD_Release()
208
209 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
210
211 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
212 #define IS_TASK_ALIVE(id) ((id) != -1)
213 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
214
215 //------------------------------ MIU SETTINGS ----------------------------------
216 #define _MaskMiuReq_MVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(6))
217 //#define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
218 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(2))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(5))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(3))
222
223 #define _MaskMiu1Req_MVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(6))
224 //#define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
225 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(2))
226 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(4))
227 #define _MaskMiu1Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(5))
228 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK+1, m, BIT(3))
229
230
231 #define HVD_MVD_RW_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == 0))
232 #define HVD_MVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == 0))
233 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0))
234 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == 0))
235 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == 0))
236
237 #define HVD_MVD_RW_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(6)) == BIT(6)))
238 #define HVD_MVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(10)) == BIT(10)))
239 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4)))
240 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(5)) == BIT(5)))
241 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(11)) == BIT(11)))
242
243
244
245 #if SUPPORT_EVD
246 #define _MaskMiuReq_EVD_RW1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
247 #define _MaskMiuReq_EVD_RW2( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(1))
248 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK+1, m, BIT(2))
249
250 #define _MaskMiu1Req_EVD_RW1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
251 #define _MaskMiu1Req_EVD_RW2( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(1))
252 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK+1, m, BIT(2))
253
254
255
256
257 #define HVD_EVD_RW1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0))
258 #define HVD_EVD_RW2_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == 0))
259 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == 0))
260
261 #define HVD_EVD_RW1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)))
262 #define HVD_EVD_RW2_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(1)) == BIT(1)))
263 #define HVD_EVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(10)) == BIT(10)))
264
265 #endif
266
267 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
268 do \
269 { \
270 if (HVD_##miu_clients##_ON_MIU0 == 1) \
271 { \
272 _MaskMiuReq_##miu_clients(mask); \
273 } \
274 else \
275 { \
276 if (HVD_##miu_clients##_ON_MIU1 == 1) \
277 { \
278 _MaskMiu1Req_##miu_clients(mask); \
279 } \
280 } \
281 } while (0)
282
283 // check RM is supported or not
284 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
285 #ifdef VDEC3
286 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
287 #else
288 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
289 #endif
290
291 #define DIFF(a, b) (a > b ? (a-b) : (b-a)) // abs diff
292
293 //-------------------------------------------------------------------------------------------------
294 // Local Structures
295 //-------------------------------------------------------------------------------------------------
296
297 //-------------------------------------------------------------------------------------------------
298 // Local Functions Prototype
299 //-------------------------------------------------------------------------------------------------
300 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
301 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
302 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
303 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
304 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
305 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
306 static MS_U32 _HVD_EX_GetPC(void);
307 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
308 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
309 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
310 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
311 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
312 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
313 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
314 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
315 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
316 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
317 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
318 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
319 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
320 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
321 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
322 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
323 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
324 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed, MS_BOOL *isAVCUsed);
325 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable);
326 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable);
327 #if SUPPORT_EVD
328 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable);
329 #endif
330 #ifdef CONFIG_MSTAR_CLKM
331 static void HAL_EVD_EX_PowerCtrl_CLKM(MS_U32 u32Id, MS_BOOL bEnable);
332 #endif
333 #if SUPPORT_G2VP9 && defined(VDEC3)
334 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
335 #endif
336 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
337 #if SUPPORT_G2VP9 && defined(VDEC3)
338 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
339 #endif
340
341 //-------------------------------------------------------------------------------------------------
342 // Global Variables
343 //-------------------------------------------------------------------------------------------------
344 #if defined (__aeon__)
345 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
346 #else
347 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
348 #endif
349 #if HAL_HVD_ENABLE_MUTEX_PROTECT
350 MS_S32 s32HVDMutexID = -1;
351 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
352 #endif
353
354
355 #define HVD_EX_STACK_SIZE 4096
356 //-------------------------------------------------------------------------------------------------
357 // Local Variables
358 //-------------------------------------------------------------------------------------------------
359 typedef struct
360 {
361
362 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
363 MS_U8 g_hvd_nal_fill_pair[2][8];
364 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
365 MS_U16 _u16DispQPtr;
366 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
367
368 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
369 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
370 MS_U32 u32VPUClockType;
371 MS_U32 u32HVDClockType;//160
372 #if SUPPORT_EVD
373 MS_U32 u32EVDClockType;
374 #endif
375 #if SUPPORT_G2VP9 && defined(VDEC3)
376 MS_U32 u32VP9ClockType;
377 #endif
378 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
379
380 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
381 MS_BOOL g_RstFlag;
382 MS_U64 u64pts_real;
383 MS_PHY u32VP8BBUWptr;
384 MS_PHY u32EVDBBUWptr;
385 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
386 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
387 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
388 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
389 //pre_set
390 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
391 } HVD_Hal_CTX;
392
393 HVD_Hal_CTX* pHVDHalContext = NULL;
394 HVD_Hal_CTX gHVDHalContext;
395 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
396
397 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
398 {
399 {FALSE},
400 {FALSE},
401 {FALSE},
402 #ifdef VDEC3
403 {FALSE},
404 #endif
405 };
406
407 //-------------------------------------------------------------------------------------------------
408 // Debug Functions
409 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)410 void HVD_EX_SetRstFlag(MS_BOOL bRst)
411 {
412 pHVDHalContext->g_RstFlag = bRst;
413 }
HVD_EX_GetRstFlag(void)414 MS_BOOL HVD_EX_GetRstFlag(void)
415 {
416 return pHVDHalContext->g_RstFlag;
417 }
418
419 //-------------------------------------------------------------------------------------------------
420 // Local Functions
421 //-------------------------------------------------------------------------------------------------
422 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)423 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
424 {
425 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
426
427 if (u32CodecType == E_HVD_INIT_HW_HEVC || u32CodecType == E_HVD_INIT_HW_HEVC_DV
428 #if SUPPORT_MSVP9
429 || u32CodecType == E_HVD_INIT_HW_VP9
430 #endif
431 )
432 return TRUE;
433
434 return FALSE;
435 }
436
_HAL_EX_BBU_VP8_InUsed(void)437 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
438 {
439 if (!pHVDHalContext)
440 return FALSE;
441
442 MS_U32 i;
443 MS_BOOL bRet = FALSE;
444
445 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
446 {
447 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
448 {
449 bRet = TRUE;
450 break;
451 }
452 }
453
454 return bRet;
455 }
456
457 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
458 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)459 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
460 {
461
462 MS_U32 ret = TRUE;
463 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
464
465 if(pCtrl == NULL || pstTaskInfo == NULL)
466 return FALSE;
467
468 pstTaskInfo->u32Id = u32Id;
469
470 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
471 {
472 case E_HVD_INIT_HW_RM:
473 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
474 break;
475 case E_HVD_INIT_HW_VP8:
476 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
477 break;
478 case E_HVD_INIT_HW_MVC:
479 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
480 break;
481 case E_HVD_INIT_HW_HEVC:
482 case E_HVD_INIT_HW_HEVC_DV:
483 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
484 break;
485 #if SUPPORT_MSVP9
486 case E_HVD_INIT_HW_VP9:
487 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
488 break;
489 #endif
490 #if SUPPORT_G2VP9
491 case E_HVD_INIT_HW_VP9:
492 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
493 break;
494 #endif
495 default:
496 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
497 break;
498 }
499
500 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
501
502 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
503 {
504 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
505 }
506 else
507 {
508 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
509 }
510
511 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
512
513 #ifdef SUPPORT_EVD
514 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
515 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
516 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
517 #endif
518 return ret;
519
520 }
521
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)522 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
523 {
524 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
525 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
526 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
527 _HAL_HVD_Entry();
528
529 if(pCtrl == NULL)
530 _HAL_HVD_Return(ret);
531
532 VPU_EX_TaskInfo taskInfo;
533 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
534
535 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
536
537 taskInfo.u8HalId = u8Idx;
538 ret = HAL_VPU_EX_GetBBUId(u32Id, &taskInfo, pCtrl->bShareBBU);
539
540 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
541 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
542
543 _HAL_HVD_Return(ret);
544 }
545
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)546 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
547 {
548 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
549 MS_BOOL ret = FALSE;
550 _HAL_HVD_Entry();
551
552 if(pCtrl == NULL)
553 _HAL_HVD_Return(ret);
554 VPU_EX_TaskInfo taskInfo;
555 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
556
557 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
558
559 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
560
561 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
562 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
563
564 _HAL_HVD_Return(ret);
565 }
566
HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId)567 MS_BOOL HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId)
568 {
569 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
570 MS_BOOL ret = FALSE;
571 _HAL_HVD_Entry();
572
573 if(pCtrl == NULL)
574 _HAL_HVD_Return(ret);
575 VPU_EX_TaskInfo taskInfo;
576 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
577
578 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
579
580 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, taskInfo.eDecType);
581
582 _HAL_HVD_Return(TRUE);
583 }
584 #endif
585
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)586 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
587 {
588 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
589 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
590 pstHVDStream->s32HvdPpTaskId = -1;
591 }
592
_HVD_EX_Context_Init_HAL(void)593 static void _HVD_EX_Context_Init_HAL(void)
594 {
595 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
596 pHVDHalContext->u32VPUClockType = 240;
597 pHVDHalContext->u32HVDClockType = 240;
598 #if SUPPORT_EVD
599 pHVDHalContext->u32EVDClockType = 240;
600 #endif
601 #if SUPPORT_G2VP9 && defined(VDEC3)
602 pHVDHalContext->u32VP9ClockType = 384;
603 #endif
604 #ifdef VDEC3
605 MS_U8 i;
606
607 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
608 {
609 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
610 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
611 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
612 }
613 #else
614 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
615 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
616 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
617 #endif
618 }
619
620
_HVD_EX_Get_REG_NAL_RPTR_HI(MS_U32 u32Id)621 static MS_U32 _HVD_EX_Get_REG_NAL_RPTR_HI(MS_U32 u32Id)
622 {
623 #if (HVD_ENABLE_MVC || (!VDEC3))
624 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
625 #endif
626 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
627 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
628 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
629 //HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
630
631 #if HVD_ENABLE_MVC
632 if(HAL_HVD_EX_CheckMVCID(u32Id))
633 {
634 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
635 }
636 #endif /// HVD_ENABLE_MVC
637
638
639 MS_U32 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI(u32RB);
640
641 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
642
643
644 #ifdef VDEC3
645 if ((0 == pCtrl->u32BBUId))
646 #else
647 if ((0 == u8TaskId))
648 #endif
649 {
650 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI(u32RB);
651
652 }
653 #ifdef VDEC3
654 else if (1 == pCtrl->u32BBUId)
655 #else
656 else if (1 == u8TaskId)
657 #endif
658 {
659 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI_BS2(u32RB);
660 }
661 #ifdef VDEC3
662 else if (2 == pCtrl->u32BBUId)
663 #else
664 else if (2 == u8TaskId)
665 #endif
666 {
667 if(isEVD)
668 u32RegNalRptrHi = EVD_REG_NAL_RPTR_HI_BS3;
669 else
670 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI_BS5;
671 }
672 #ifdef VDEC3
673 else if (3 == pCtrl->u32BBUId)
674 #else
675 else if (3 == u8TaskId)
676 #endif
677 {
678 if(isEVD)
679 u32RegNalRptrHi = EVD_REG_NAL_RPTR_HI_BS4;
680 else
681 u32RegNalRptrHi = HVD_REG_NAL_RPTR_HI_BS6;
682 }
683 else
684 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
685
686
687 return u32RegNalRptrHi;
688
689 }
690
691
_HVD_EX_Get_REG_NAL_WPTR_HI(MS_U32 u32Id)692 static MS_U32 _HVD_EX_Get_REG_NAL_WPTR_HI(MS_U32 u32Id)
693 {
694 #if (HVD_ENABLE_MVC || (!VDEC3))
695 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
696 #endif
697 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
698 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
699 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
700 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
701
702 #if HVD_ENABLE_MVC
703 if(HAL_HVD_EX_CheckMVCID(u32Id))
704 {
705 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
706 }
707 #endif /// HVD_ENABLE_MVC
708
709
710 MS_U32 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI(u32RB);
711
712 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
713
714
715
716 #ifdef VDEC3
717 if ((0 == pCtrl->u32BBUId))
718 #else
719 if ((0 == u8TaskId))
720 #endif
721 {
722 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI(u32RB);
723
724 }
725 #ifdef VDEC3
726 else if (1 == pCtrl->u32BBUId)
727 #else
728 else if (1 == u8TaskId)
729 #endif
730 {
731 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI_BS2(u32RB);
732 }
733 #ifdef VDEC3
734 else if (2 == pCtrl->u32BBUId)
735 #else
736 else if (2 == u8TaskId)
737 #endif
738 {
739 if(isEVD)
740 u32RegNalWptrHi = EVD_REG_NAL_WPTR_HI_BS3;
741 else
742 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI_BS5;
743 }
744 #ifdef VDEC3
745 else if (3 == pCtrl->u32BBUId)
746 #else
747 else if (3 == u8TaskId)
748 #endif
749 {
750 if(isEVD)
751 u32RegNalWptrHi = EVD_REG_NAL_WPTR_HI_BS4;
752 else
753 u32RegNalWptrHi = HVD_REG_NAL_WPTR_HI_BS6;
754 }
755 else
756 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
757
758
759 return u32RegNalWptrHi;
760
761 }
762
763
764
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)765 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
766 {
767 MS_U16 u16Ret = 0;
768 #if (HVD_ENABLE_MVC || (!VDEC3))
769 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
770 #endif
771 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
772 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
773 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
774 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
775
776 #if HVD_ENABLE_MVC
777 if(HAL_HVD_EX_CheckMVCID(u32Id))
778 {
779 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
780 }
781 #endif /// HVD_ENABLE_MVC
782
783 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
784 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
785
786 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
787 {
788 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
789 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
790 }
791 else
792 {
793 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
794 {
795 if(!pShm) {
796 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
797 return 0;
798 }
799 u16Ret = pShm->u32ColocateBBUReadPtr;
800 }
801 else
802 u16Ret = _HVD_Read2Byte(_HVD_EX_Get_REG_NAL_RPTR_HI(u32Id));
803 }
804
805 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
806 if(isEVD)
807 {
808 HVD_EX_MSG_DBG("isEVD: %d, Task0=%d, Task1=%d, Task2=%d, Task4=%d\n",
809 isEVD, _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)), _HVD_Read2Byte(EVD_REG_NAL_RPTR_HI_BS3), _HVD_Read2Byte(EVD_REG_NAL_RPTR_HI_BS4));
810 }
811 else
812 {
813 HVD_EX_MSG_DBG("isEVD:%d, Task0=%d, Task1=%d, Task2=%d, Task4=%d\n",
814 isEVD, _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS5), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS6));
815
816 }
817
818 return u16Ret;
819 }
820
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)821 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
822 {
823 MS_U16 u16Ret = 0;
824 #if (HVD_ENABLE_MVC || (!VDEC3))
825 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
826 #endif
827 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
828 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
829 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
830 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
831
832 #if HVD_ENABLE_MVC
833 if (HAL_HVD_EX_CheckMVCID(u32Id))
834 {
835 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
836 }
837 #endif /// HVD_ENABLE_MVC
838 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
839 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
840
841 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
842 {
843 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
844 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
845 }
846 else
847 {
848 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
849 {
850 if(!pShm) {
851 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
852 return 0;
853 }
854 u16Ret = pShm->u32ColocateBBUWritePtr;
855 }
856 else
857 u16Ret = _HVD_Read2Byte(_HVD_EX_Get_REG_NAL_WPTR_HI(u32Id));
858
859 }
860
861 return u16Ret;
862 }
863
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)864 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
865 {
866 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
867 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
868
869 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
870 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
871 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
872 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
873 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
874 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
875 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
876 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
877
878
879
880 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS5, 0);
881 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
882 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS6, 0);
883 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
884 _HVD_Write2Byte(EVD_REG_NAL_RPTR_HI_BS3, 0);
885 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
886 _HVD_Write2Byte(EVD_REG_NAL_RPTR_HI_BS4, 0);
887 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
888
889 }
890
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)891 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
892 {
893 #if (HVD_ENABLE_MVC || (!VDEC3))
894 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
895 #endif
896 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
897 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
898 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
899 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
900
901 #if HVD_ENABLE_MVC
902 if (HAL_HVD_EX_CheckMVCID(u32Id))
903 {
904 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
905 }
906 #endif /// HVD_ENABLE_MVC
907
908 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
909 {
910 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
911 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
912 }
913 else
914 {
915 _HVD_Write2Byte(_HVD_EX_Get_REG_NAL_WPTR_HI(u32Id), u16BBUNewWptr);
916 if(!pShm) {
917 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
918 return 0;
919 }
920
921 //if(pCtrl->InitParams.bColocateBBUMode)
922 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
923 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
924
925 }
926
927
928
929 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
930
931 if(isEVD)
932 {
933 HVD_EX_MSG_DBG("isEVD:%d, Task0=%d, Task1=%d, Task2=%d, Task3=%d\n",
934 isEVD, _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)), _HVD_Read2Byte(EVD_REG_NAL_WPTR_HI_BS3), _HVD_Read2Byte(EVD_REG_NAL_WPTR_HI_BS4));
935 }
936 else
937 {
938 HVD_EX_MSG_DBG("isEVD:%d, Task0=%d, Task1=%d, Task2=%d, Task3=%d\n",
939 isEVD, _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS5), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS6));
940 }
941
942 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
943 }
944
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)945 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
946 {
947 MS_BOOL bResult = TRUE;
948 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
949 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
950
951 switch (u8MBox)
952 {
953 case E_HVD_HI_0:
954 {
955 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
956 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
957 break;
958 }
959 case E_HVD_HI_1:
960 {
961 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
962 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
963 break;
964 }
965 case E_HVD_VPU_HI_0:
966 {
967 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
968 break;
969 }
970 case E_HVD_VPU_HI_1:
971 {
972 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
973 break;
974 }
975 default:
976 {
977 bResult = FALSE;
978 break;
979 }
980 }
981
982 return bResult;
983 }
984
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)985 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
986 {
987 MS_BOOL bResult = TRUE;
988 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
989 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
990
991 switch (u8MBox)
992 {
993 case E_HVD_HI_0:
994 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
995 break;
996 case E_HVD_HI_1:
997 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
998 break;
999 case E_HVD_RISC_0:
1000 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
1001 break;
1002 case E_HVD_RISC_1:
1003 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
1004 break;
1005 case E_HVD_VPU_HI_0:
1006 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
1007 break;
1008 case E_HVD_VPU_HI_1:
1009 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
1010 break;
1011 case E_HVD_VPU_RISC_0:
1012 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
1013 break;
1014 case E_HVD_VPU_RISC_1:
1015 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
1016 break;
1017 default:
1018 break;
1019 }
1020
1021 return bResult;
1022 }
1023
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)1024 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
1025 {
1026 MS_BOOL bResult = TRUE;
1027 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1028 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1029
1030 switch (u8MBox)
1031 {
1032 case E_HVD_HI_0:
1033 {
1034 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
1035 break;
1036 }
1037 case E_HVD_HI_1:
1038 {
1039 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
1040 break;
1041 }
1042 case E_HVD_RISC_0:
1043 {
1044 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
1045 break;
1046 }
1047 case E_HVD_RISC_1:
1048 {
1049 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
1050 break;
1051 }
1052 case E_HVD_VPU_RISC_0:
1053 {
1054 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
1055 break;
1056 }
1057 case E_HVD_VPU_RISC_1:
1058 {
1059 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
1060 break;
1061 }
1062 default:
1063 {
1064 bResult = FALSE;
1065 break;
1066 }
1067 }
1068
1069 return bResult;
1070 }
1071
1072 #if 0
1073 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
1074 {
1075 switch (u8MBox)
1076 {
1077 case E_HVD_RISC_0:
1078 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
1079 break;
1080 case E_HVD_RISC_1:
1081 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
1082 break;
1083 case E_HVD_VPU_RISC_0:
1084 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
1085 break;
1086 case E_HVD_VPU_RISC_1:
1087 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
1088 break;
1089 default:
1090 break;
1091 }
1092 }
1093 #endif
1094
_HVD_EX_GetPC(void)1095 static MS_U32 _HVD_EX_GetPC(void)
1096 {
1097 MS_U32 u32PC = 0;
1098 u32PC = HAL_VPU_EX_GetProgCnt();
1099 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
1100 return u32PC;
1101 }
1102
_HVD_EX_Get_REG_ES_RPTR_L(MS_U32 u32Id)1103 static MS_U32 _HVD_EX_Get_REG_ES_RPTR_L(MS_U32 u32Id)
1104 {
1105 #if (HVD_ENABLE_MVC || (!VDEC3))
1106 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1107 #endif
1108 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1109 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1110 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1111 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1112
1113 #if HVD_ENABLE_MVC
1114 if(HAL_HVD_EX_CheckMVCID(u32Id))
1115 {
1116 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1117 }
1118 #endif /// HVD_ENABLE_MVC
1119
1120
1121 MS_U32 u32RegESRptrLow = HVD_REG_ESB_RPTR(u32RB);
1122
1123 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1124
1125
1126
1127 #ifdef VDEC3
1128 if ((0 == pCtrl->u32BBUId))
1129 #else
1130 if ((0 == u8TaskId))
1131 #endif
1132 {
1133 u32RegESRptrLow = HVD_REG_ESB_RPTR(u32RB);
1134
1135 }
1136 #ifdef VDEC3
1137 else if (1 == pCtrl->u32BBUId)
1138 #else
1139 else if (1 == u8TaskId)
1140 #endif
1141 {
1142 u32RegESRptrLow = HVD_REG_ESB_RPTR_L_BS2(u32RB);
1143 }
1144 #ifdef VDEC3
1145 else if (2 == pCtrl->u32BBUId)
1146 #else
1147 else if (2 == u8TaskId)
1148 #endif
1149 {
1150 if(isEVD)
1151 u32RegESRptrLow = EVD_REG_ESB_RPTR_L_BS3;
1152 else
1153 u32RegESRptrLow = HVD_REG_ESB_RPTR_L_BS5;
1154 }
1155 #ifdef VDEC3
1156 else if (3 == pCtrl->u32BBUId)
1157 #else
1158 else if (3 == u8TaskId)
1159 #endif
1160 {
1161 if(isEVD)
1162 u32RegESRptrLow = EVD_REG_ESB_RPTR_L_BS4;
1163 else
1164 u32RegESRptrLow = HVD_REG_ESB_RPTR_L_BS6;
1165 }
1166 else
1167 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1168
1169
1170 return u32RegESRptrLow;
1171
1172 }
1173
_HVD_EX_Get_REG_ES_RPTR_H(MS_U32 u32Id)1174 static MS_U32 _HVD_EX_Get_REG_ES_RPTR_H(MS_U32 u32Id)
1175 {
1176 #if (HVD_ENABLE_MVC || (!VDEC3))
1177 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1178 #endif
1179 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1180 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1181 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1182 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1183
1184 #if HVD_ENABLE_MVC
1185 if(HAL_HVD_EX_CheckMVCID(u32Id))
1186 {
1187 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1188 }
1189 #endif /// HVD_ENABLE_MVC
1190
1191
1192 MS_U32 u32RegESRptrHi = HVD_REG_ESB_RPTR_H(u32RB);
1193
1194 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1195
1196
1197
1198 #ifdef VDEC3
1199 if ((0 == pCtrl->u32BBUId))
1200 #else
1201 if ((0 == u8TaskId))
1202 #endif
1203 {
1204 u32RegESRptrHi = HVD_REG_ESB_RPTR_H(u32RB);
1205
1206 }
1207 #ifdef VDEC3
1208 else if (1 == pCtrl->u32BBUId)
1209 #else
1210 else if (1 == u8TaskId)
1211 #endif
1212 {
1213 u32RegESRptrHi = HVD_REG_ESB_RPTR_H_BS2(u32RB);
1214 }
1215 #ifdef VDEC3
1216 else if (2 == pCtrl->u32BBUId)
1217 #else
1218 else if (2 == u8TaskId)
1219 #endif
1220 {
1221 if(isEVD)
1222 u32RegESRptrHi = EVD_REG_ESB_RPTR_H_BS3;
1223 else
1224 u32RegESRptrHi = HVD_REG_ESB_RPTR_H_BS5;
1225 }
1226 #ifdef VDEC3
1227 else if (3 == pCtrl->u32BBUId)
1228 #else
1229 else if (3 == u8TaskId)
1230 #endif
1231 {
1232 if(isEVD)
1233 u32RegESRptrHi = EVD_REG_ESB_RPTR_H_BS4;
1234 else
1235 u32RegESRptrHi = HVD_REG_ESB_RPTR_H_BS6;
1236 }
1237 else
1238 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1239
1240
1241 return u32RegESRptrHi;
1242
1243 }
1244
1245
1246
1247
_HVD_EX_Get_NAL_TBL_ST_ADDR_L(MS_U32 u32Id)1248 static MS_U32 _HVD_EX_Get_NAL_TBL_ST_ADDR_L(MS_U32 u32Id)
1249 {
1250 #if (HVD_ENABLE_MVC || (!VDEC3))
1251 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1252 #endif
1253 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1254 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1255 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1256 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1257
1258 #if HVD_ENABLE_MVC
1259 if(HAL_HVD_EX_CheckMVCID(u32Id))
1260 {
1261 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1262 }
1263 #endif /// HVD_ENABLE_MVC
1264
1265
1266 MS_U32 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L(u32RB);
1267
1268 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1269
1270
1271
1272 #ifdef VDEC3
1273 if ((0 == pCtrl->u32BBUId))
1274 #else
1275 if ((0 == u8TaskId))
1276 #endif
1277 {
1278 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L(u32RB);
1279
1280 }
1281 #ifdef VDEC3
1282 else if (1 == pCtrl->u32BBUId)
1283 #else
1284 else if (1 == u8TaskId)
1285 #endif
1286 {
1287 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB);
1288 }
1289 #ifdef VDEC3
1290 else if (2 == pCtrl->u32BBUId)
1291 #else
1292 else if (2 == u8TaskId)
1293 #endif
1294 {
1295 if(isEVD)
1296 u32RegNalTblAddrLo = EVD_REG_NAL_TBL_ST_ADDR_L_BS3;
1297 else
1298 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L_BS5;
1299 }
1300 #ifdef VDEC3
1301 else if (3 == pCtrl->u32BBUId)
1302 #else
1303 else if (3 == u8TaskId)
1304 #endif
1305 {
1306 if(isEVD)
1307 u32RegNalTblAddrLo = EVD_REG_NAL_TBL_ST_ADDR_L_BS4;
1308 else
1309 u32RegNalTblAddrLo = HVD_REG_NAL_TBL_ST_ADDR_L_BS6;
1310 }
1311 else
1312 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1313
1314
1315 return u32RegNalTblAddrLo;
1316
1317 }
1318
1319
_HVD_EX_Get_NAL_TBL_ST_ADDR_H(MS_U32 u32Id)1320 static MS_U32 _HVD_EX_Get_NAL_TBL_ST_ADDR_H(MS_U32 u32Id)
1321 {
1322 #if (HVD_ENABLE_MVC || (!VDEC3))
1323 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1324 #endif
1325 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1326 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1327 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1328 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1329
1330 #if HVD_ENABLE_MVC
1331 if(HAL_HVD_EX_CheckMVCID(u32Id))
1332 {
1333 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1334 }
1335 #endif /// HVD_ENABLE_MVC
1336
1337
1338 MS_U32 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H(u32RB);
1339
1340 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1341
1342
1343
1344 #ifdef VDEC3
1345 if ((0 == pCtrl->u32BBUId))
1346 #else
1347 if ((0 == u8TaskId))
1348 #endif
1349 {
1350 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H(u32RB);
1351
1352 }
1353 #ifdef VDEC3
1354 else if (1 == pCtrl->u32BBUId)
1355 #else
1356 else if (1 == u8TaskId)
1357 #endif
1358 {
1359 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB);
1360 }
1361 #ifdef VDEC3
1362 else if (2 == pCtrl->u32BBUId)
1363 #else
1364 else if (2 == u8TaskId)
1365 #endif
1366 {
1367 if(isEVD)
1368 u32RegNalTblAddrHi = EVD_REG_NAL_TBL_ST_ADDR_H_BS3;
1369 else
1370 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H_BS5;
1371 }
1372 #ifdef VDEC3
1373 else if (3 == pCtrl->u32BBUId)
1374 #else
1375 else if (3 == u8TaskId)
1376 #endif
1377 {
1378 if(isEVD)
1379 u32RegNalTblAddrHi = EVD_REG_NAL_TBL_ST_ADDR_H_BS4;
1380 else
1381 u32RegNalTblAddrHi = HVD_REG_NAL_TBL_ST_ADDR_H_BS6;
1382 }
1383 else
1384 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1385
1386
1387 return u32RegNalTblAddrHi;
1388
1389 }
1390
_HVD_EX_Get_NAL_TAB_LEN(MS_U32 u32Id)1391 static MS_U32 _HVD_EX_Get_NAL_TAB_LEN(MS_U32 u32Id)
1392 {
1393 #if (HVD_ENABLE_MVC || (!VDEC3))
1394 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1395 #endif
1396 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1397 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1398 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1399 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1400
1401 #if HVD_ENABLE_MVC
1402 if(HAL_HVD_EX_CheckMVCID(u32Id))
1403 {
1404 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1405 }
1406 #endif /// HVD_ENABLE_MVC
1407
1408
1409 MS_U32 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN(u32RB);
1410
1411 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1412
1413
1414
1415 #ifdef VDEC3
1416 if ((0 == pCtrl->u32BBUId))
1417 #else
1418 if ((0 == u8TaskId))
1419 #endif
1420 {
1421 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN(u32RB);
1422
1423 }
1424 #ifdef VDEC3
1425 else if (1 == pCtrl->u32BBUId)
1426 #else
1427 else if (1 == u8TaskId)
1428 #endif
1429 {
1430 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN_BS2(u32RB);
1431 }
1432 #ifdef VDEC3
1433 else if (2 == pCtrl->u32BBUId)
1434 #else
1435 else if (2 == u8TaskId)
1436 #endif
1437 {
1438 if(isEVD)
1439 u32RegNalTblLen = EVD_REG_NAL_TAB_LEN_BS3;
1440 else
1441 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN_BS5;
1442 }
1443 #ifdef VDEC3
1444 else if (3 == pCtrl->u32BBUId)
1445 #else
1446 else if (3 == u8TaskId)
1447 #endif
1448 {
1449 if(isEVD)
1450 u32RegNalTblLen = EVD_REG_NAL_TAB_LEN_BS4;
1451 else
1452 u32RegNalTblLen = HVD_REG_NAL_TAB_LEN_BS6;
1453 }
1454 else
1455 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1456
1457
1458 return u32RegNalTblLen;
1459
1460 }
1461
1462
1463
_HVD_EX_Get_ESB_ST_ADDR_L(MS_U32 u32Id)1464 static MS_U32 _HVD_EX_Get_ESB_ST_ADDR_L(MS_U32 u32Id)
1465 {
1466 #if (HVD_ENABLE_MVC || (!VDEC3))
1467 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1468 #endif
1469 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1470 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1471 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1472 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1473
1474 #if HVD_ENABLE_MVC
1475 if(HAL_HVD_EX_CheckMVCID(u32Id))
1476 {
1477 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1478 }
1479 #endif /// HVD_ENABLE_MVC
1480
1481
1482 MS_U32 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L(u32RB);
1483
1484 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1485
1486
1487
1488 #ifdef VDEC3
1489 if ((0 == pCtrl->u32BBUId))
1490 #else
1491 if ((0 == u8TaskId))
1492 #endif
1493 {
1494 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L(u32RB);
1495
1496 }
1497 #ifdef VDEC3
1498 else if (1 == pCtrl->u32BBUId)
1499 #else
1500 else if (1 == u8TaskId)
1501 #endif
1502 {
1503 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L_BS2(u32RB);
1504 }
1505 #ifdef VDEC3
1506 else if (2 == pCtrl->u32BBUId)
1507 #else
1508 else if (2 == u8TaskId)
1509 #endif
1510 {
1511 if(isEVD)
1512 u32RegEsbAddrLo = EVD_REG_ESB_ST_ADDR_L_BS3;
1513 else
1514 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L_BS5;
1515 }
1516 #ifdef VDEC3
1517 else if (3 == pCtrl->u32BBUId)
1518 #else
1519 else if (3 == u8TaskId)
1520 #endif
1521 {
1522 if(isEVD)
1523 u32RegEsbAddrLo = EVD_REG_ESB_ST_ADDR_L_BS4;
1524 else
1525 u32RegEsbAddrLo = HVD_REG_ESB_ST_ADDR_L_BS6;
1526 }
1527 else
1528 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1529
1530
1531 return u32RegEsbAddrLo;
1532
1533 }
1534
1535
_HVD_EX_Get_ESB_ST_ADDR_H(MS_U32 u32Id)1536 static MS_U32 _HVD_EX_Get_ESB_ST_ADDR_H(MS_U32 u32Id)
1537 {
1538 #if (HVD_ENABLE_MVC || (!VDEC3))
1539 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1540 #endif
1541 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1542 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1543 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1544 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1545
1546 #if HVD_ENABLE_MVC
1547 if(HAL_HVD_EX_CheckMVCID(u32Id))
1548 {
1549 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1550 }
1551 #endif /// HVD_ENABLE_MVC
1552
1553
1554 MS_U32 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H(u32RB);
1555
1556 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1557
1558
1559
1560 #ifdef VDEC3
1561 if ((0 == pCtrl->u32BBUId))
1562 #else
1563 if ((0 == u8TaskId))
1564 #endif
1565 {
1566 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H(u32RB);
1567
1568 }
1569 #ifdef VDEC3
1570 else if (1 == pCtrl->u32BBUId)
1571 #else
1572 else if (1 == u8TaskId)
1573 #endif
1574 {
1575 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H_BS2(u32RB);
1576 }
1577 #ifdef VDEC3
1578 else if (2 == pCtrl->u32BBUId)
1579 #else
1580 else if (2 == u8TaskId)
1581 #endif
1582 {
1583 if(isEVD)
1584 u32RegEsbAddrHi = EVD_REG_ESB_ST_ADDR_H_BS3;
1585 else
1586 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H_BS5;
1587 }
1588 #ifdef VDEC3
1589 else if (3 == pCtrl->u32BBUId)
1590 #else
1591 else if (3 == u8TaskId)
1592 #endif
1593 {
1594 if(isEVD)
1595 u32RegEsbAddrHi = EVD_REG_ESB_ST_ADDR_H_BS4;
1596 else
1597 u32RegEsbAddrHi = HVD_REG_ESB_ST_ADDR_H_BS6;
1598 }
1599 else
1600 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1601
1602
1603 return u32RegEsbAddrHi;
1604
1605 }
1606
1607
1608
_HVD_EX_Get_ESB_LENGTH_L(MS_U32 u32Id)1609 static MS_U32 _HVD_EX_Get_ESB_LENGTH_L(MS_U32 u32Id)
1610 {
1611 #if (HVD_ENABLE_MVC || (!VDEC3))
1612 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1613 #endif
1614 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1615 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1616 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1617 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1618
1619 #if HVD_ENABLE_MVC
1620 if(HAL_HVD_EX_CheckMVCID(u32Id))
1621 {
1622 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1623 }
1624 #endif /// HVD_ENABLE_MVC
1625
1626
1627 MS_U32 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L(u32RB);
1628
1629 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1630
1631
1632
1633 #ifdef VDEC3
1634 if ((0 == pCtrl->u32BBUId))
1635 #else
1636 if ((0 == u8TaskId))
1637 #endif
1638 {
1639 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L(u32RB);
1640
1641 }
1642 #ifdef VDEC3
1643 else if (1 == pCtrl->u32BBUId)
1644 #else
1645 else if (1 == u8TaskId)
1646 #endif
1647 {
1648 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L_BS2(u32RB);
1649 }
1650 #ifdef VDEC3
1651 else if (2 == pCtrl->u32BBUId)
1652 #else
1653 else if (2 == u8TaskId)
1654 #endif
1655 {
1656 if(isEVD)
1657 u32RegEsbLenLo = EVD_REG_ESB_LENGTH_L_BS3;
1658 else
1659 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L_BS5;
1660 }
1661 #ifdef VDEC3
1662 else if (3 == pCtrl->u32BBUId)
1663 #else
1664 else if (3 == u8TaskId)
1665 #endif
1666 {
1667 if(isEVD)
1668 u32RegEsbLenLo = EVD_REG_ESB_LENGTH_L_BS4;
1669 else
1670 u32RegEsbLenLo = HVD_REG_ESB_LENGTH_L_BS6;
1671 }
1672 else
1673 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1674
1675
1676 return u32RegEsbLenLo;
1677
1678 }
1679
1680
_HVD_EX_Get_ESB_LENGTH_H(MS_U32 u32Id)1681 static MS_U32 _HVD_EX_Get_ESB_LENGTH_H(MS_U32 u32Id)
1682 {
1683 #if (HVD_ENABLE_MVC || (!VDEC3))
1684 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1685 #endif
1686 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1687 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1688 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1689 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1690
1691 #if HVD_ENABLE_MVC
1692 if(HAL_HVD_EX_CheckMVCID(u32Id))
1693 {
1694 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1695 }
1696 #endif /// HVD_ENABLE_MVC
1697
1698
1699 MS_U32 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H(u32RB);
1700
1701 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1702
1703
1704
1705 #ifdef VDEC3
1706 if ((0 == pCtrl->u32BBUId))
1707 #else
1708 if ((0 == u8TaskId))
1709 #endif
1710 {
1711 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H(u32RB);
1712
1713 }
1714 #ifdef VDEC3
1715 else if (1 == pCtrl->u32BBUId)
1716 #else
1717 else if (1 == u8TaskId)
1718 #endif
1719 {
1720 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H_BS2(u32RB);
1721 }
1722 #ifdef VDEC3
1723 else if (2 == pCtrl->u32BBUId)
1724 #else
1725 else if (2 == u8TaskId)
1726 #endif
1727 {
1728 if(isEVD)
1729 u32RegEsbLenHi = EVD_REG_ESB_LENGTH_H_BS3;
1730 else
1731 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H_BS5;
1732 }
1733 #ifdef VDEC3
1734 else if (3 == pCtrl->u32BBUId)
1735 #else
1736 else if (3 == u8TaskId)
1737 #endif
1738 {
1739 if(isEVD)
1740 u32RegEsbLenHi = EVD_REG_ESB_LENGTH_H_BS4;
1741 else
1742 u32RegEsbLenHi = HVD_REG_ESB_LENGTH_H_BS6;
1743 }
1744 else
1745 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1746
1747
1748 return u32RegEsbLenHi;
1749
1750 }
1751
1752
_HVD_EX_Get_MIF_BBU(MS_U32 u32Id)1753 static MS_U32 _HVD_EX_Get_MIF_BBU(MS_U32 u32Id)
1754 {
1755 #if (HVD_ENABLE_MVC || (!VDEC3))
1756 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1757 #endif
1758 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1759 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1760 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1761 // HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1762
1763 #if HVD_ENABLE_MVC
1764 if(HAL_HVD_EX_CheckMVCID(u32Id))
1765 {
1766 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1767 }
1768 #endif /// HVD_ENABLE_MVC
1769
1770
1771 MS_U32 u32RegMIFBBU = HVD_REG_MIF_BBU(u32RB);
1772
1773 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
1774
1775
1776
1777 #ifdef VDEC3
1778 if ((0 == pCtrl->u32BBUId))
1779 #else
1780 if ((0 == u8TaskId))
1781 #endif
1782 {
1783 u32RegMIFBBU = HVD_REG_MIF_BBU(u32RB);
1784
1785 }
1786 #ifdef VDEC3
1787 else if (1 == pCtrl->u32BBUId)
1788 #else
1789 else if (1 == u8TaskId)
1790 #endif
1791 {
1792 u32RegMIFBBU = HVD_REG_MIF_BBU_BS2(u32RB);
1793 }
1794 #ifdef VDEC3
1795 else if (2 == pCtrl->u32BBUId)
1796 #else
1797 else if (2 == u8TaskId)
1798 #endif
1799 {
1800 if(isEVD)
1801 u32RegMIFBBU = EVD_REG_MIF_BBU_BS3;
1802 else
1803 u32RegMIFBBU = HVD_REG_MIF_BBU_BS5;
1804 }
1805 #ifdef VDEC3
1806 else if (3 == pCtrl->u32BBUId)
1807 #else
1808 else if (3 == u8TaskId)
1809 #endif
1810 {
1811 if(isEVD)
1812 u32RegMIFBBU = EVD_REG_MIF_BBU_BS4;
1813 else
1814 u32RegMIFBBU = HVD_REG_MIF_BBU_BS6;
1815 }
1816 else
1817 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
1818
1819
1820 return u32RegMIFBBU;
1821
1822 }
1823
1824
1825
_HVD_EX_GetESWritePtr(MS_U32 u32Id)1826 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
1827 {
1828 MS_U32 u32Data = 0;
1829 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1830 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1831
1832 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1833 {
1834 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
1835
1836 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
1837 {
1838 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
1839
1840 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
1841 }
1842 }
1843 else
1844 {
1845 #if HVD_ENABLE_MVC
1846 MS_U8 u8ViewIdx = 0;
1847 if(!pShm) {
1848 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
1849 return 0;
1850 }
1851
1852 if(HAL_HVD_EX_CheckMVCID(u32Id))
1853 {
1854 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1855 }
1856 if(u8ViewIdx != 0) /// 2nd ES ptr.
1857 {
1858 u32Data = pShm->u32ES2WritePtr;
1859 }
1860 else
1861 {
1862 u32Data = pShm->u32ESWritePtr;
1863 }
1864 #else
1865 u32Data = pShm->u32ESWritePtr;
1866 #endif
1867 }
1868
1869 return u32Data;
1870 }
1871
1872 #define NAL_UNIT_LEN_BITS 21
1873 #define NAL_UNIT_OFT_BITS 30
1874 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
1875 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
1876 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
1877
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)1878 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
1879 {
1880 MS_U32 u32Data = 0;
1881 MS_U8 u8TaskId = 0;
1882 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1883 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1884 if(!pShm) {
1885 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
1886 return 0;
1887 }
1888
1889 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1890 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1891 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
1892
1893 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1894 #if HVD_ENABLE_MVC
1895 if(HAL_HVD_EX_CheckMVCID(u32Id))
1896 {
1897 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1898 }
1899 #endif /// HVD_ENABLE_MVC
1900
1901 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
1902 {
1903 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
1904 {
1905 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1906 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
1907 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
1908 MS_U32 *u32Adr;
1909 MS_U32 u32Tmp;
1910
1911 if (u16ReadPtr == u16WritePtr)
1912 {
1913 u32Data = _HVD_EX_GetESWritePtr(u32Id);
1914 }
1915 else
1916 {
1917 if (u16ReadPtr)
1918 u16ReadPtr--;
1919 else
1920 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
1921
1922 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
1923
1924 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
1925 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
1926 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
1927 u32Data = u32Data | u32Tmp;
1928
1929 //HVD_PRINT("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
1930 //while(1);
1931 }
1932 goto EXIT;
1933 }
1934 // set reg_poll_nal_rptr 0
1935 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
1936 // set reg_poll_nal_rptr 1
1937 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
1938
1939
1940
1941
1942
1943 // read reg_nal_rptr_hi
1944
1945 u32Data = _HVD_Read2Byte(_HVD_EX_Get_REG_ES_RPTR_L(u32Id)) & 0xFFC0;
1946 u32Data >>= 6;
1947 u32Data |= _HVD_Read2Byte(_HVD_EX_Get_REG_ES_RPTR_H(u32Id)) << 10;
1948
1949 u32Data <<= 3; // unit
1950
1951 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1952 {
1953 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1954
1955 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1956 {
1957 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1958 u32Data = u32ESWptr;
1959 }
1960 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1961 {
1962 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1963 u32Data = u32ESWptr;
1964 }
1965 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1966 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1967 {
1968 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1969 u32Data = u32ESWptr;
1970 }
1971 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1972 && ((u32Data - u32ESWptr) < 32)
1973 && (pCtrl->u32FlushRstPtr == 1))
1974 {
1975 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1976 u32Data = u32ESWptr;
1977 }
1978 }
1979
1980 // remove illegal pointer
1981 #if 1
1982 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1983 {
1984 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1985
1986 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1987 (u32PacketStaddr <
1988 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1989 {
1990 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1991 u32Data = pCtrl->u32LastESRptr;
1992 }
1993 }
1994 #endif
1995 }
1996 else
1997 {
1998 #if HVD_ENABLE_MVC
1999 MS_U8 u8ViewIdx = 0;
2000 if(HAL_HVD_EX_CheckMVCID(u32Id))
2001 {
2002 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
2003 }
2004 if(u8ViewIdx != 0) /// 2nd ES ptr.
2005 {
2006 u32Data = pShm->u32ES2ReadPtr;
2007 }
2008 else
2009 {
2010 u32Data = pShm->u32ESReadPtr;
2011 }
2012 #else
2013 u32Data = pShm->u32ESReadPtr;
2014 #endif
2015 }
2016
2017 EXIT:
2018
2019 pCtrl->u32LastESRptr = u32Data;
2020
2021 return u32Data;
2022 }
2023
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)2024 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
2025 {
2026 MS_U16 u16TimeOut = 0xFFFF;
2027 MS_BOOL bResult = FALSE;
2028
2029 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
2030
2031 while (--u16TimeOut)
2032 {
2033 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
2034 {
2035 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
2036 break;
2037 }
2038 }
2039
2040 return bResult;
2041 }
2042
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)2043 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
2044 {
2045 MS_U16 u16TimeOut = 0xFFFF;
2046 MS_BOOL bResult = FALSE;
2047 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2048
2049 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
2050
2051 #if HVD_ENABLE_MVC
2052 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
2053 {
2054 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
2055 }
2056 #endif /// HVD_ENABLE_MVC
2057
2058 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
2059
2060 while (--u16TimeOut)
2061 {
2062 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
2063 {
2064 u32Cmd |= (u8TaskId << 24);
2065 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
2066 break;
2067 }
2068 }
2069 return bResult;
2070 }
2071
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)2072 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
2073 {
2074 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2075 #ifdef VDEC3
2076 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
2077 MS_BOOL IsSent = FALSE;
2078 MS_BOOL IsMailBox = FALSE;
2079 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2080 if(!pShm) {
2081 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
2082 return E_HVD_RETURN_FAIL;
2083 }
2084
2085 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
2086 {
2087 do {
2088 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
2089 if (!SentRet)
2090 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2091 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2092 break;
2093 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
2094 IsSent = TRUE;
2095 break;
2096 }
2097 else if (HVD_GetSysTime_ms() > u32timeout)
2098 {
2099 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2100 break;
2101 }
2102 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2103 }
2104 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
2105 {
2106 do {
2107 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
2108 if (!SentRet)
2109 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2110 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2111 break;
2112 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
2113 IsSent = TRUE;
2114 break;
2115 }
2116 else if (HVD_GetSysTime_ms() > u32timeout)
2117 {
2118 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2119 break;
2120 }
2121 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2122 }
2123 if (!IsSent) {
2124 IsMailBox = TRUE;
2125 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2126 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
2127 #else
2128 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
2129 #endif
2130 {
2131 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2132 if (HVD_GetSysTime_ms() > u32timeout)
2133 {
2134 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2135 return E_HVD_RETURN_TIMEOUT;
2136 }
2137 #endif
2138
2139 #if 0
2140 if (u32Cmd == E_HVD_CMD_STOP)
2141 {
2142 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2143 #if HVD_ENABLE_MVC
2144 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
2145 {
2146 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
2147 }
2148 #endif /// HVD_ENABLE_MVC
2149 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
2150
2151 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
2152 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
2153
2154 return E_HVD_RETURN_SUCCESS;
2155 }
2156 #endif
2157
2158 if(u32Cmd < E_DUAL_CMD_BASE)
2159 {
2160 //_HVD_EX_GetPC();
2161 HAL_HVD_EX_Dump_FW_Status(u32Id);
2162 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
2163 }
2164 }
2165
2166 #ifdef VDEC3
2167 }
2168 IsSent = FALSE;
2169 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2170 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
2171 {
2172 do {
2173 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
2174 if (!SentRet)
2175 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2176 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2177 break;
2178 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
2179 IsSent = TRUE;
2180 break;
2181 }
2182 else if (HVD_GetSysTime_ms() > u32timeout)
2183 {
2184 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2185 break;
2186 }
2187 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2188 }
2189 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
2190 {
2191 do {
2192 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
2193 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
2194 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
2195 }
2196 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
2197 break;
2198 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
2199 IsSent = TRUE;
2200 break;
2201 }
2202 else if (HVD_GetSysTime_ms() > u32timeout)
2203 {
2204 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
2205 break;
2206 }
2207 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
2208 }
2209 if (!IsSent)
2210 {
2211 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2212 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
2213 #else
2214 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
2215
2216 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
2217 #endif
2218 {
2219 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
2220 if (HVD_GetSysTime_ms() > u32timeout)
2221 {
2222 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
2223 return E_HVD_RETURN_TIMEOUT;
2224 }
2225 #endif
2226 if(u32Cmd < E_DUAL_CMD_BASE)
2227 {
2228 //_HVD_EX_GetPC();
2229 HAL_HVD_EX_Dump_FW_Status(u32Id);
2230 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
2231 }
2232 }
2233 #ifdef VDEC3
2234 }
2235 else
2236 {
2237 HAL_HVD_EX_FlushMemory();
2238 }
2239 #endif
2240 return E_HVD_RETURN_SUCCESS;
2241 }
2242
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)2243 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
2244 {
2245 #if HAL_HVD_ENABLE_MIU_PROTECT
2246 _HVD_MIU_SetReqMask(MVD_RW, bEnable);
2247 //_HVD_MIU_SetReqMask(MVD_RW_1, bEnable);
2248 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
2249 #if SUPPORT_EVD
2250 _HVD_MIU_SetReqMask(EVD_RW1, bEnable);
2251 _HVD_MIU_SetReqMask(EVD_RW2, bEnable);
2252 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
2253 #endif
2254 _HVD_MIU_SetReqMask(HVD_RW_MIF0, bEnable);
2255 _HVD_MIU_SetReqMask(HVD_RW_MIF1, bEnable);
2256 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
2257 HAL_VPU_EX_MIU_RW_Protect(bEnable);
2258 //HVD_Delay_ms(1);
2259 #endif
2260 return;
2261 }
2262
_HVD_EX_SetBufferAddr(MS_U32 u32Id)2263 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
2264 {
2265 MS_U16 u16Reg = 0;
2266 MS_VIRT u32StAddr = 0;
2267 #ifdef VDEC3
2268 MS_U32 u32Length = 0;
2269 #endif
2270 MS_U8 u8BitMiuSel = 0;
2271 MS_U8 u8CodeMiuSel = 0;
2272 MS_U8 u8FBMiuSel = 0;
2273 MS_U8 u8TmpMiuSel = 0;
2274
2275 MS_U32 u32BitStartOffset;
2276 MS_U32 u32CodeStartOffset;
2277 MS_U32 u32FBStartOffset;
2278
2279 #ifndef VDEC3
2280 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
2281 #endif
2282 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2283 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2284 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
2285
2286 _HAL_HVD_Entry();
2287
2288 if (pCtrl == NULL)
2289 {
2290 _HAL_HVD_Return();
2291 }
2292
2293 MS_BOOL bIsEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
2294 MS_BOOL bESBufferAlreadySet = FALSE;
2295 VPU_EX_TaskInfo taskInfo;
2296 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2297
2298 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
2299
2300 bESBufferAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
2301
2302
2303
2304 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
2305 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
2306 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
2307
2308 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
2309 (u8BitMiuSel << VDEC_BS_MIUSEL) |
2310 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
2311 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
2312 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
2313 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
2314 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
2315 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
2316 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
2317 (u8FBMiuSel << VDEC_PPIN_MIUSEL) |
2318 (u8FBMiuSel << VDEC_XCSHM_MIUSEL));
2319
2320 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2321 {
2322 // ES buffer
2323 #ifdef VDEC3
2324 if(pCtrl->bShareBBU)
2325 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
2326 else
2327 #endif
2328 u32StAddr = u32BitStartOffset;
2329
2330 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
2331
2332 #ifdef VDEC3
2333 if (!_HAL_EX_BBU_VP8_InUsed())
2334 #endif
2335 {
2336 HVD_EX_MSG_ERR("ESB start addr=%lx\n", (unsigned long)u32StAddr);
2337
2338 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
2339 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
2340
2341 #ifdef VDEC3
2342 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
2343 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
2344 #else
2345 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2346 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2347 #endif
2348
2349 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
2350 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
2351 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
2352 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
2353 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
2354 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
2355 }
2356
2357 _HAL_HVD_Return();
2358 }
2359
2360 // ES buffer
2361 #ifdef VDEC3
2362 if(!pCtrl->bShareBBU || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
2363 {
2364 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2365 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
2366 }
2367 else
2368 {
2369 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
2370 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
2371 }
2372 #else
2373 u32StAddr = u32BitStartOffset;
2374 #endif
2375
2376 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
2377
2378 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
2379
2380 #ifdef VDEC3
2381 if (!bESBufferAlreadySet)
2382 {
2383 _HVD_Write2Byte(_HVD_EX_Get_ESB_ST_ADDR_L(u32Id), HVD_LWORD(u32StAddr >> 3));
2384 _HVD_Write2Byte(_HVD_EX_Get_ESB_ST_ADDR_H(u32Id), HVD_HWORD(u32StAddr >> 3));
2385
2386 _HVD_Write2Byte(_HVD_EX_Get_ESB_LENGTH_L(u32Id), HVD_LWORD(u32Length));
2387 _HVD_Write2Byte(_HVD_EX_Get_ESB_LENGTH_H(u32Id), HVD_HWORD(u32Length));
2388 }
2389 #else
2390 if (0 == u8TaskId)
2391 {
2392 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
2393 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
2394
2395 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2396 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2397 }
2398 else
2399 {
2400 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
2401 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
2402
2403 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2404 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2405 }
2406 #endif
2407
2408 // others
2409 #ifdef VDEC3
2410 if (!bESBufferAlreadySet)
2411 {
2412 u16Reg = _HVD_Read2Byte(_HVD_EX_Get_MIF_BBU(u32Id));
2413
2414 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2415 {
2416 if (pCtrl->u32BBUId == 0)
2417 u16Reg |= HVD_REG_BBU_TSP_INPUT;
2418 else if (pCtrl->u32BBUId == 1)
2419 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
2420 else if (pCtrl->u32BBUId == 2)
2421 {
2422 if(bIsEVD)
2423 u16Reg |= EVD_REG_BBU_TSP_INPUT_BS3;
2424 else
2425 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS5;
2426 }
2427 else
2428 {
2429 if(bIsEVD)
2430 u16Reg |= EVD_REG_BBU_TSP_INPUT_BS4;
2431 else
2432 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS6;
2433 }
2434 }
2435 else
2436 {
2437 if (pCtrl->u32BBUId == 0)
2438 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
2439 else if (pCtrl->u32BBUId == 1)
2440 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
2441 else if (pCtrl->u32BBUId == 2)
2442 {
2443 if(bIsEVD)
2444 u16Reg &= ~EVD_REG_BBU_TSP_INPUT_BS3;
2445 else
2446 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS5;
2447 }
2448 else
2449 {
2450 if(bIsEVD)
2451 u16Reg &= ~EVD_REG_BBU_TSP_INPUT_BS4;
2452 else
2453 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS6;
2454 }
2455 }
2456
2457 // do not set parsing setting in DRV, and we set it in FW (hvd_switch_bbu)
2458 if (pCtrl->u32BBUId == 0)
2459 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
2460 else if(pCtrl->u32BBUId == 1)
2461 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
2462 else if(pCtrl->u32BBUId == 2)
2463 {
2464 if(bIsEVD)
2465 u16Reg &= ~EVD_REG_BBU_PASER_MASK_BS3;
2466 else
2467 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS5;
2468 }
2469 else
2470 {
2471 if(bIsEVD)
2472 u16Reg &= ~EVD_REG_BBU_PASER_MASK_BS4;
2473 else
2474 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS6;
2475 }
2476
2477 if (pCtrl->u32BBUId == 0)
2478 {
2479 #ifdef VDEC_FW31_HVD_NONAUTO_BBU
2480 if (!bIsEVD)
2481 {
2482 u16Reg &= ~HVD_REG_BBU_AUTO_NAL_TAB;
2483 }
2484 else
2485 #endif
2486 {
2487 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
2488 }
2489 }
2490 else if (pCtrl->u32BBUId == 1)
2491 {
2492 #ifdef VDEC_FW31_HVD_NONAUTO_BBU
2493 if (!bIsEVD)
2494 {
2495 u16Reg &= ~HVD_REG_BBU_AUTO_NAL_TAB_BS2;
2496 }
2497 else
2498 #endif
2499 {
2500 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
2501 }
2502 }
2503 else if (pCtrl->u32BBUId == 2)
2504 {
2505 #ifdef VDEC_FW31_HVD_NONAUTO_BBU
2506 if (!bIsEVD)
2507 {
2508 u16Reg &= ~HVD_REG_BBU_AUTO_NAL_TAB_BS5;
2509 }
2510 else
2511 #endif
2512 {
2513 if (bIsEVD)
2514 u16Reg |= EVD_REG_BBU_AUTO_NAL_TAB_BS3;
2515 else
2516 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS5;
2517 }
2518 }
2519 else
2520 {
2521 #ifdef VDEC_FW31_HVD_NONAUTO_BBU
2522 if (!bIsEVD)
2523 {
2524 u16Reg &= ~HVD_REG_BBU_AUTO_NAL_TAB_BS6;
2525 }
2526 else
2527 #endif
2528 {
2529 if (bIsEVD)
2530 u16Reg |= EVD_REG_BBU_AUTO_NAL_TAB_BS4;
2531 else
2532 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS6;
2533 }
2534 }
2535
2536 _HVD_Write2Byte(_HVD_EX_Get_MIF_BBU(u32Id), u16Reg);
2537 }
2538 #else
2539 if (0 == u8TaskId)
2540 {
2541 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
2542
2543 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2544 {
2545 u16Reg |= HVD_REG_BBU_TSP_INPUT;
2546 }
2547 else
2548 {
2549 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
2550 }
2551
2552 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
2553
2554 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
2555 {
2556 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
2557 }
2558 else // AVS or AVC
2559 {
2560 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
2561 {
2562 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
2563 }
2564 else // start code remained
2565 {
2566 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
2567 }
2568 }
2569
2570 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
2571
2572 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
2573 }
2574 else
2575 {
2576 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
2577
2578 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2579 {
2580 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
2581 }
2582 else
2583 {
2584 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
2585 }
2586
2587 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
2588
2589 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
2590 {
2591 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
2592 }
2593 else // AVS or AVC
2594 {
2595 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
2596 {
2597 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
2598 }
2599 else // start code remained
2600 {
2601 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
2602 }
2603 }
2604
2605 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
2606
2607 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
2608 }
2609 #endif
2610
2611 #if (HVD_ENABLE_MVC)
2612 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2613 {
2614 /// Used sub stream to record sub view data.
2615 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
2616 //HVD_PRINT("**************** Buffer setting for MVC dual-BBU *************\n");
2617
2618 // ES buffer
2619 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
2620
2621 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
2622 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
2623 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
2624
2625 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
2626 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
2627
2628 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
2629 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
2630 {
2631 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
2632 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
2633 }
2634 else
2635 {
2636 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
2637 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
2638 }
2639 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
2640 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
2641 {
2642 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
2643 }
2644 else // AVS or AVC
2645 {
2646 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
2647 {
2648 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
2649 }
2650 else // start code remained
2651 {
2652 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
2653 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
2654 }
2655 }
2656 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
2657 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
2658 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
2659 }
2660 #endif
2661
2662 // MIF offset
2663 #if 0
2664 {
2665 MS_U16 offaddr = 0;
2666 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
2667 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2668 {
2669 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2670 }
2671 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
2672 offaddr = (MS_U16) ((u32StAddr) >> 20);
2673 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
2674 //0x1FF; // 9 bits(L + H)
2675 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
2676 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
2677 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
2678 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
2679 {
2680 u16Reg |= HVD_REG_MIF_OFFSET_H;
2681 }
2682 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
2683 }
2684 #endif
2685
2686 if (!bESBufferAlreadySet)
2687 {
2688 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
2689 }
2690
2691 _HAL_HVD_Return();
2692 }
2693
2694 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
2695 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
2696 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
2697 {
2698 MS_U16 u16Reg = 0;
2699 MS_U32 u32StAddr = 0;
2700 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2701 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2702 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
2703
2704 if(pCtrl == NULL) return;
2705
2706 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2707 {
2708 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
2709
2710 // ES buffer
2711 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2712
2713 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2714 {
2715 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2716 }
2717
2718 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
2719 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
2720
2721 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2722 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2723
2724 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
2725 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
2726 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
2727 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
2728 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
2729 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
2730
2731 return;
2732 }
2733
2734 // ES buffer
2735 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
2736
2737 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2738 {
2739 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2740 }
2741
2742 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
2743
2744 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
2745 {
2746 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
2747 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
2748
2749 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2750 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2751 }
2752 else
2753 {
2754 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
2755 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
2756
2757 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2758 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
2759 }
2760 }
2761 #endif
2762
_HVD_EX_GetESLevel(MS_U32 u32Id)2763 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
2764 {
2765 MS_U32 u32Wptr = 0;
2766 MS_U32 u32Rptr = 0;
2767 MS_U32 u32CurMBX = 0;
2768 MS_U32 u32ESsize = 0;
2769 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
2770 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2771
2772 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
2773 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
2774 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
2775
2776 if (u32Rptr >= u32Wptr)
2777 {
2778 u32CurMBX = u32Rptr - u32Wptr;
2779 }
2780 else
2781 {
2782 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
2783 }
2784
2785 if (u32CurMBX == 0)
2786 {
2787 u32Ret = E_HVD_ESB_LEVEL_UNDER;
2788 }
2789 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
2790 {
2791 u32Ret = E_HVD_ESB_LEVEL_OVER;
2792 }
2793 else
2794 {
2795 u32CurMBX = u32ESsize - u32CurMBX;
2796 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
2797 {
2798 u32Ret = E_HVD_ESB_LEVEL_UNDER;
2799 }
2800 }
2801
2802 return u32Ret;
2803 }
2804
_HVD_EX_GetESQuantity(MS_U32 u32Id)2805 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
2806 {
2807 MS_U32 u32Wptr = 0;
2808 MS_U32 u32Rptr = 0;
2809 MS_U32 u32ESsize = 0;
2810 MS_U32 u32Ret = 0;
2811 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2812
2813 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
2814 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
2815 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
2816
2817
2818 if(u32Wptr >= u32Rptr)
2819 {
2820 u32Ret = u32Wptr - u32Rptr;
2821 }
2822 else
2823 {
2824 u32Ret = u32ESsize - u32Rptr + u32Wptr;
2825 }
2826 //HVD_PRINT("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
2827 return u32Ret;
2828 }
2829
2830 #if 0//(HVD_ENABLE_IQMEM)
2831 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
2832 {
2833
2834 MS_U32 u32Timeout = 20000;
2835
2836 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
2837 {
2838
2839 HAL_VPU_EX_IQMemSetDAMode(TRUE);
2840
2841 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
2842
2843
2844 while (u32Timeout)
2845 {
2846
2847 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
2848 {
2849 break;
2850 }
2851 u32Timeout--;
2852 HVD_Delay_ms(1);
2853 }
2854
2855 HAL_VPU_EX_IQMemSetDAMode(FALSE);
2856
2857 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
2858
2859 if (u32Timeout==0)
2860 {
2861 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
2862 return FALSE;
2863 }
2864
2865
2866 }
2867 return TRUE;
2868 }
2869
2870 #endif
2871
2872 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)2873 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
2874 #else
2875 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
2876 #endif
2877 {
2878 MS_U32 u32FirmVer = 0;
2879 MS_U32 u32Timeout = 20000;
2880 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2881
2882 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
2883
2884 #if HVD_ENABLE_TIME_MEASURE
2885 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2886 #endif
2887
2888 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
2889
2890 VPU_EX_FWCodeCfg fwCfg;
2891 VPU_EX_TaskInfo taskInfo;
2892 VPU_EX_VLCTblCfg vlcCfg;
2893 #ifdef VDEC3
2894 VPU_EX_FBCfg fbCfg;
2895 #endif
2896 VPU_EX_NDecInitPara nDecInitPara;
2897
2898 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
2899 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2900 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
2901 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
2902 #ifdef VDEC3_FB
2903 nDecInitPara.pVLCCfg = NULL;
2904 #else
2905 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2906 {
2907 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
2908 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2909 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2910 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
2911 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
2912 nDecInitPara.pVLCCfg = &vlcCfg;
2913 }
2914 #endif
2915 nDecInitPara.pFWCodeCfg = &fwCfg;
2916 nDecInitPara.pTaskInfo = &taskInfo;
2917 #ifdef VDEC3
2918 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
2919 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2920
2921 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2922 {
2923 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2924 }
2925
2926 nDecInitPara.pFBCfg = &fbCfg;
2927 #endif
2928
2929 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
2930 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
2931 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
2932 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
2933 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
2934
2935 taskInfo.u32Id = u32Id;
2936
2937 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2938 {
2939 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
2940 }
2941 #ifdef VDEC3
2942 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2943 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
2944 {
2945 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2946 }
2947 #if SUPPORT_MSVP9
2948 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2949 {
2950 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2951 }
2952 #endif
2953 #if SUPPORT_G2VP9
2954 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2955 {
2956 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2957 }
2958 #endif
2959 #endif
2960 else
2961 {
2962 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2963 }
2964
2965 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2966
2967 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2968 {
2969 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2970 }
2971 else
2972 {
2973 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2974 }
2975 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2976
2977 #ifdef SUPPORT_EVD
2978 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2979 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2980 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2981 #endif
2982
2983 if(TRUE == HVD_EX_GetRstFlag())
2984 {
2985 //Delete task for Rst
2986 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2987 {
2988 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2989 }
2990 HVD_EX_SetRstFlag(FALSE);
2991 }
2992
2993 #if 0//(HVD_ENABLE_IQMEM)
2994 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2995 #endif
2996
2997 #ifdef VDEC3
2998 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2999 #else
3000 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
3001 #endif
3002 {
3003 HVD_EX_MSG_ERR("Task create fail!\n");
3004
3005 return FALSE;
3006 }
3007
3008 while (u32Timeout)
3009 {
3010 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
3011
3012 if (u32FirmVer != 0)
3013 {
3014 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
3015 break;
3016 }
3017 u32Timeout--;
3018 HVD_Delay_ms(1);
3019 }
3020
3021 #ifdef VDEC3_FB
3022 #if HVD_ENABLE_RV_FEATURE
3023 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3024
3025 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
3026 {
3027 if(!pShm) {
3028 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3029 return 0;
3030 }
3031
3032 if(pShm->u32RM_VLCTableAddr == 0) {
3033 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
3034 }
3035 else
3036 {
3037 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
3038 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
3039 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
3040 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
3041 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
3042 nDecInitPara.pVLCCfg = &vlcCfg;
3043 }
3044 }
3045
3046 if (nDecInitPara.pVLCCfg)
3047 {
3048 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
3049 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
3050 {
3051 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
3052 return FALSE;
3053 }
3054 }
3055 #endif
3056 #endif
3057 if (u32Timeout > 0)
3058 {
3059 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3060
3061 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
3062
3063 #ifdef VDEC3
3064 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
3065 {
3066 case E_HVD_INIT_HW_AVC:
3067 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
3068 break;
3069 case E_HVD_INIT_HW_AVS:
3070 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
3071 break;
3072 case E_HVD_INIT_HW_RM:
3073 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
3074 break;
3075 case E_HVD_INIT_HW_MVC:
3076 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
3077 break;
3078 case E_HVD_INIT_HW_VP8:
3079 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
3080 break;
3081 case E_HVD_INIT_HW_MJPEG:
3082 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
3083 break;
3084 case E_HVD_INIT_HW_VP6:
3085 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
3086 break;
3087 case E_HVD_INIT_HW_HEVC:
3088 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
3089 break;
3090 case E_HVD_INIT_HW_VP9:
3091 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
3092 break;
3093 case E_HVD_INIT_HW_HEVC_DV:
3094 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC_DV;
3095 break;
3096 default:
3097 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
3098 break;
3099 }
3100 #endif
3101
3102 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
3103 }
3104 else
3105 {
3106 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
3107 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
3108
3109 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
3110 {
3111 HVD_EX_MSG_ERR("Task delete fail!\n");
3112 }
3113
3114 return FALSE;
3115 }
3116
3117
3118
3119 #if 0//(HVD_ENABLE_IQMEM)
3120
3121 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
3122 {
3123
3124 HAL_HVD_EX_IQMem_Init(u32Id);
3125 }
3126 else{
3127 HVD_EX_MSG_DBG("not support IQMEM\n");
3128 }
3129 #endif
3130
3131
3132
3133
3134
3135
3136 #if HVD_ENABLE_TIME_MEASURE
3137 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
3138 #endif
3139
3140 return TRUE;
3141 }
3142
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)3143 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
3144 {
3145 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3146 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3147 if(!pShm) {
3148 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3149 return 0;
3150 }
3151
3152 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
3153 {
3154 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
3155 }
3156 else
3157 {
3158 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3159 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3160 }
3161 }
3162
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)3163 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
3164 {
3165 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3166 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3167 if(!pShm) {
3168 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3169 return 0;
3170 }
3171
3172 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
3173 {
3174 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
3175 }
3176 else
3177 {
3178 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3179 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
3180 }
3181 }
3182
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)3183 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
3184 {
3185 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3186 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3187 if(!pShm) {
3188 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3189 return;
3190 }
3191
3192 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
3193 {
3194 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
3195 {
3196 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
3197 }
3198 }
3199 else
3200 {
3201 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
3202 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
3203 }
3204 }
3205
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)3206 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
3207 {
3208 MS_VIRT u32PTSWptr = HVD_U32_MAX;
3209 MS_VIRT u32PTSRptr = HVD_U32_MAX;
3210 MS_VIRT u32DestAddr = 0;
3211 HVD_PTS_Entry PTSEntry;
3212 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3213 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3214 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3215 if(!pShm) {
3216 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3217 return E_HVD_RETURN_FAIL;
3218 }
3219
3220 // update R & W ptr
3221 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
3222
3223 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
3224
3225 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
3226 {
3227 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
3228 (MS_U32) MAX_PTS_TABLE_SIZE);
3229 return E_HVD_RETURN_FAIL;
3230 }
3231
3232 // check queue is full or not
3233 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
3234 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
3235
3236 if (u32PTSWptr == u32PTSRptr)
3237 {
3238 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
3239 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
3240 return E_HVD_RETURN_FAIL;
3241 }
3242
3243 // add one PTS entry
3244 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
3245 PTSEntry.u32ID_L = pInfo->u32ID_L;
3246 PTSEntry.u32ID_H = pInfo->u32ID_H;
3247 PTSEntry.u32PTS = pInfo->u32TimeStamp;
3248
3249 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
3250
3251 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
3252
3253 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
3254
3255 HAL_HVD_EX_FlushMemory();
3256
3257 // update Write ptr
3258 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
3259
3260 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
3261
3262 return E_HVD_RETURN_SUCCESS;
3263 }
3264
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)3265 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
3266 {
3267 //---------------------------------------------------
3268 // item format in nal table:
3269 // reserved |borken| u32NalOffset | u32NalLen
3270 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
3271 //---------------------------------------------------
3272 MS_VIRT u32Adr = 0;
3273 MS_U32 u32BBUNewWptr = 0;
3274 MS_U8 item[8];
3275 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3276 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3277 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3278 if(!pShm) {
3279 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3280 return E_HVD_RETURN_FAIL;
3281 }
3282 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
3283
3284
3285 #if HVD_ENABLE_MVC
3286 if(HAL_HVD_EX_CheckMVCID(u32Id))
3287 {
3288 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
3289 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
3290 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
3291 {
3292 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
3293 }
3294 }
3295 #endif /// HVD_ENABLE_MVC
3296
3297 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3298 {
3299 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
3300 }
3301 else
3302 {
3303 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
3304 }
3305 u32BBUNewWptr++;
3306 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
3307
3308 // prepare nal entry
3309
3310 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
3311 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3312 {
3313 // NAL len 22 bits , HEVC level5 constrain
3314 item[0] = u32NalLen & 0xff;
3315 item[1] = (u32NalLen >> 8) & 0xff;
3316 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
3317 item[3] = (u32NalOffset >> 2) & 0xff;
3318 item[4] = (u32NalOffset >> 10) & 0xff;
3319 item[5] = (u32NalOffset >> 18) & 0xff;
3320 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
3321 item[7] = 0;
3322 }
3323 else
3324 {
3325 item[0] = u32NalLen & 0xff;
3326 item[1] = (u32NalLen >> 8) & 0xff;
3327 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
3328 item[3] = (u32NalOffset >> 3) & 0xff;
3329 item[4] = (u32NalOffset >> 11) & 0xff;
3330 item[5] = (u32NalOffset >> 19) & 0xff;
3331 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
3332 item[7] = 0;
3333 }
3334
3335 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3336 {
3337 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
3338 }
3339 else
3340 {
3341 // add nal entry
3342 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
3343 }
3344
3345 HVD_memcpy((void *) u32Adr, (void *) item, 8);
3346
3347 HAL_HVD_EX_FlushMemory();
3348
3349 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
3350
3351 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3352 {
3353 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
3354 }
3355 else
3356 {
3357 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
3358 }
3359
3360 return E_HVD_RETURN_SUCCESS;
3361 }
3362
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)3363 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
3364 {
3365 MS_U8 item[8];
3366 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3367 MS_VIRT u32Adr = 0;
3368 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3369 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3370 if(!pShm) {
3371 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3372 return E_HVD_RETURN_FAIL;
3373 }
3374
3375 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
3376
3377 /*
3378 HVD_PRINT("nal2 offset=0x%x, len=0x%x\n",
3379 u32NalOffset2, u32NalLen2);
3380 */
3381
3382 item[0] = u32NalLen2 & 0xff;
3383 item[1] = (u32NalLen2 >> 8) & 0xff;
3384 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
3385 item[3] = (u32NalOffset2 >> 3) & 0xff;
3386 item[4] = (u32NalOffset2 >> 11) & 0xff;
3387 item[5] = (u32NalOffset2 >> 19) & 0xff;
3388 item[6] = (u32NalOffset2 >> 27) & 0x07;
3389 item[7] = 0;
3390
3391 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3392 {
3393 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
3394 }
3395 else
3396 {
3397 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
3398 }
3399
3400 HVD_memcpy((void *) u32Adr, (void *) item, 8);
3401
3402 HAL_HVD_EX_FlushMemory();
3403
3404 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
3405 }
3406
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)3407 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
3408 {
3409 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3410 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3411
3412 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
3413 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
3414 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
3415 {
3416 MS_U16 i;
3417 MS_PHY u32VUIAddr;
3418 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
3419
3420 HAL_HVD_EX_ReadMemory();
3421 if(!pShm) {
3422 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3423 return 0;
3424 }
3425 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
3426
3427 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
3428 {
3429 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
3430 {
3431 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
3432 }
3433 else
3434 {
3435 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
3436 }
3437 pData++;
3438 }
3439 }
3440 else
3441 {
3442 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
3443 }
3444
3445 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
3446 }
3447
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)3448 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
3449 {
3450 MS_U32 u32ReadPtr = 0;
3451 MS_U32 eRet = 0;
3452 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3453 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3454
3455 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
3456 MS_U32 u32WritePtr = 0;
3457
3458 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3459 {
3460 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
3461 }
3462 else
3463 {
3464 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
3465 }
3466
3467 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
3468
3469 if (u32WritePtr >= u32ReadPtr)
3470 {
3471 eRet = u32WritePtr - u32ReadPtr;
3472 }
3473 else
3474 {
3475 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
3476 }
3477
3478 #if 0
3479 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
3480 {
3481 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
3482 }
3483 else
3484 {
3485 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
3486 }
3487
3488 #endif
3489 return eRet;
3490 }
3491
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)3492 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
3493 {
3494 MS_U32 u32ReadPtr = 0;
3495 MS_U32 eRet = 0;
3496 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3497
3498 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
3499
3500 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
3501 {
3502 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
3503 (MS_U32) MAX_PTS_TABLE_SIZE);
3504 return 0;
3505 }
3506
3507 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3508
3509 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
3510 {
3511 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
3512 }
3513 else
3514 {
3515 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
3516 }
3517
3518 return eRet;
3519 }
3520
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)3521 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
3522 {
3523 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3524 if(!pShm) {
3525 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3526 return 0;
3527 }
3528
3529 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
3530 }
3531
hevc_get_paired(HEVC_PIC_STRUCT pic_struct,int first_field)3532 static HEVC_PIC_STRUCT hevc_get_paired(HEVC_PIC_STRUCT pic_struct, int first_field)
3533 {
3534 if (pic_struct == EVD_TOP_FIELD)
3535 return EVD_BOTTOM_FIELD;
3536 else if (pic_struct == EVD_BOTTOM_FIELD)
3537 return EVD_TOP_FIELD;
3538
3539 if (first_field)
3540 {
3541 // pic_struct is the first field and must pair with the next one
3542 if (pic_struct == EVD_TOP_WITH_NEXT)
3543 return EVD_BOTTOM_WITH_PREV;
3544 else if (pic_struct == EVD_BOTTOM_WITH_NEXT)
3545 return EVD_TOP_WITH_PREV;
3546 }
3547 else
3548 {
3549 // pic_struct is the second field and must pair with the previous one
3550 if (pic_struct == EVD_TOP_WITH_PREV)
3551 return EVD_BOTTOM_WITH_NEXT;
3552 else if (pic_struct == EVD_BOTTOM_WITH_PREV)
3553 return EVD_TOP_WITH_NEXT;
3554 }
3555
3556 return EVD_UNKNOWN_TYPE;
3557 }
3558
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)3559 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
3560 {
3561 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3562
3563 /* deal return 0 */
3564 if (!pShm) {
3565 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3566 return NULL;
3567 }
3568
3569 MS_U16 u16QNum = pShm->u16DispQNumb;
3570 MS_U16 u16QPtr = pShm->u16DispQPtr;
3571 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3572
3573 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3574 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3575
3576 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
3577 static MS_BOOL bfirstTime = TRUE;
3578 if (bDolbyVision)
3579 {
3580 if (bfirstTime && u16QNum < 4) // first time we need to wait 4 pic to ensure we got the correct layer type
3581 {
3582 return NULL;
3583 }
3584 else
3585 {
3586 bfirstTime = FALSE;
3587 }
3588 }
3589
3590 #if (HVD_ENABLE_MVC)
3591 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3592 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
3593 {
3594 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3595 {
3596 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
3597 MS_U16 u16UsedFrm = 0;
3598
3599 if (u16RealQPtr != u16QPtr)
3600 {
3601 if (u16RealQPtr > u16QPtr)
3602 {
3603 u16UsedFrm = u16RealQPtr - u16QPtr;
3604 }
3605 else
3606 {
3607 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
3608 }
3609 }
3610
3611 if (u16QNum > u16UsedFrm)
3612 {
3613 u16QNum -= u16UsedFrm;
3614 u16QPtr = u16RealQPtr;
3615 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
3616
3617 if ((u16QPtr%2) == 0) //For MVC mode, we must check the pair of display entry is ready or not
3618 {
3619 volatile HVD_Frm_Information *pHvdFrmNext = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr+1];
3620
3621 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
3622 {
3623 return NULL;
3624 }
3625 }
3626
3627 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
3628 {
3629 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
3630 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3631
3632 if ((u16QPtr%2) == 0)
3633 {
3634 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
3635 if(bDolbyVision)
3636 HVD_PRINT("BL pts: %d, u16QPtr: %d, u16QNum:%d, u32PrivateData:%d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData);
3637 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
3638 }
3639 else
3640 {
3641 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
3642 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
3643 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
3644 if(bDolbyVision)
3645 {
3646 HVD_PRINT("EL pts: %d, u16QPtr: %d, u16QNum:%d, u32PrivateData:%d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData);
3647
3648 volatile HVD_Frm_Information *pPrevHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr-1];//BL
3649 if(DIFF(pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp) > 1000)
3650 HVD_EX_MSG_ERR("BL pts: %d, EL pts: %d matched failed!!\n",pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp);
3651 }
3652 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
3653 }
3654
3655 u16QPtr++;
3656 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
3657 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
3658
3659 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
3660 }
3661 }
3662
3663 return NULL;
3664 }
3665
3666 //HVD_PRINT("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
3667 //search the next frame to display
3668 while (u16QNum > 0)
3669 {
3670 //HVD_PRINT("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
3671 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
3672 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3673
3674 //HVD_PRINT("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
3675 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3676 {
3677 /// For MVC. Output views after the pair of (base and depend) views were decoded.
3678 /// Check the depned view was initial when Output the base view.
3679 if((u16QPtr%2) == 0)
3680 {
3681 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
3682 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
3683 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
3684 {
3685 ///HVD_PRINT("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
3686 ///HVD_PRINT("Return NULL.\n");
3687 return NULL;
3688 }
3689 }
3690
3691 //HVD_PRINT("V:%d.\n",u16QPtr);
3692 pHVDHalContext->_u16DispQPtr = u16QPtr;
3693 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
3694 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
3695 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
3696 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
3697 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
3698 }
3699
3700 u16QNum--;
3701 //go to next frame in the dispQ
3702 u16QPtr++;
3703
3704 if (u16QPtr >= pShm->u16DispQSize)
3705 {
3706 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
3707 }
3708 }
3709 }
3710 else
3711 #endif ///HVD_ENABLE_MVC
3712 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
3713 if (_HVD_EX_IsHevcInterlaceField(u32Id))
3714 {
3715 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
3716 volatile HVD_Frm_Information *pHvdFrm_first = NULL;
3717
3718 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
3719 return NULL;
3720 }
3721
3722 while (u16QNum != 0)
3723 {
3724 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3725 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
3726 {
3727 if (!first_field) // second get frame, we will check at least one paired in disp queue.
3728 {
3729 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3730 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
3731 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
3732
3733 if(pHvdFrm->u8FieldType == EVD_TOP_FIELD || pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
3734 pHvdFrm->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
3735 else
3736 pHvdFrm->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
3737 return (HVD_Frm_Information *)pHvdFrm;
3738 }
3739 else // first get frame, we will check at least one paired in disp queue.
3740 {
3741 if (pHvdFrm_first == NULL)
3742 {
3743 pHvdFrm_first = pHvdFrm;
3744 }
3745 else
3746 {
3747 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3748 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
3749
3750 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV)
3751 {
3752 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV && pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_NEXT)
3753 {
3754 pHvdFrm_first->u32ID_L |= (1 << 16);
3755 pHvdFrm->u32ID_L |= (1 << 16);
3756 }
3757 else if (pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV && pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
3758 {
3759 pHvdFrm_first->u32ID_L &= (~(1 << 16));
3760 pHvdFrm->u32ID_L &= (~(1 << 16));
3761 }
3762 else
3763 {
3764 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
3765 return NULL;
3766 }
3767 }
3768 else
3769 {
3770 if (hevc_get_paired(pHvdFrm->u8FieldType, 0) != pHvdFrm_first->u8FieldType)
3771 {
3772 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
3773 return NULL;
3774 }
3775 }
3776
3777 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
3778 if (pHvdFrm_first->u8FieldType == EVD_TOP_FIELD || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_NEXT)
3779 pHvdFrm_first->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
3780 else
3781 pHvdFrm_first->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
3782 return (HVD_Frm_Information *)pHvdFrm_first;
3783 }
3784 }
3785 }
3786 u16QNum--;
3787 //go to next frame in the dispQ
3788 u16QPtr++;
3789
3790 if (u16QPtr == pShm->u16DispQSize)
3791 {
3792 u16QPtr = 0; //wrap to the begin
3793 }
3794
3795 }
3796 return NULL;
3797 }
3798 else
3799 {
3800 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3801 {
3802
3803 while (u16QNum != 0)
3804 {
3805 pHvdFrm = (volatile HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
3806
3807 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
3808 {
3809 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
3810 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
3811 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
3812 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
3813 }
3814 u16QNum--;
3815 //go to next frame in the dispQ
3816 if (bDolbyVision)
3817 u16QPtr += 2; // single layer must in even ptr
3818 else
3819 u16QPtr++;
3820
3821 if (u16QPtr >= pShm->u16DispQSize)
3822 {
3823 u16QPtr = 0; //wrap to the begin
3824 }
3825 }
3826
3827 return NULL;
3828 }
3829
3830 //HVD_PRINT("Q: %d %d\n", u16QNum, u16QPtr);
3831 //search the next frame to display
3832 while (u16QNum != 0)
3833 {
3834 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3835
3836 //HVD_PRINT("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
3837 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3838 {
3839 pHVDHalContext->_u16DispQPtr = u16QPtr;
3840 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
3841 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
3842 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
3843 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
3844 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
3845 }
3846
3847 u16QNum--;
3848 //go to next frame in the dispQ
3849 u16QPtr++;
3850
3851 if (u16QPtr == pShm->u16DispQSize)
3852 {
3853 u16QPtr = 0; //wrap to the begin
3854 }
3855 }
3856 }
3857
3858 return NULL;
3859 }
3860
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)3861 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
3862 {
3863 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
3864 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
3865 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
3866 {
3867 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
3868 if(pVsyncBridgeExt != NULL)
3869 {
3870 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
3871 }
3872 }
3873 return pFrmInfoExt;
3874 }
3875
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)3876 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
3877 {
3878 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3879 MS_U64 u64Ret = 0;
3880
3881 #if SUPPORT_EVD
3882 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
3883 if (isEVD)
3884 {
3885 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
3886 }
3887 else
3888 #endif
3889 #if SUPPORT_G2VP9
3890 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3891 {
3892 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
3893 }
3894 else
3895 #endif
3896 {
3897 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
3898 }
3899
3900 return u64Ret;
3901 }
3902
3903 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)3904 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
3905 {
3906 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3907 if(!pShm) {
3908 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
3909 return 0;
3910 }
3911
3912 MS_U16 u16QNum = pShm->u16DispQNumb;
3913 MS_U16 u16QPtr = pShm->u16DispQPtr;
3914 static volatile HVD_Frm_Information *pHvdFrm = NULL;
3915 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3916 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3917 MS_BOOL bMVC = FALSE;
3918 #if HVD_ENABLE_MVC
3919 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3920 #endif
3921
3922
3923 if (bMVC || (bDolbyVision && !pShm->bSingleLayer) || _HVD_EX_IsHevcInterlaceField(u32Id))
3924 {
3925 if (u16QNum == 1) return TRUE;
3926 }
3927
3928 while (u16QNum != 0)
3929 {
3930 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3931 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3932 {
3933 return FALSE;
3934 }
3935 u16QNum--;
3936
3937 if (bDolbyVision)
3938 u16QPtr += 2; // single layer must in even ptr
3939 else
3940 u16QPtr++;
3941
3942 if (u16QPtr >= pShm->u16DispQSize)
3943 {
3944 u16QPtr = 0; //wrap to the begin
3945 }
3946 }
3947
3948 return TRUE;
3949 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)3950 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
3951 {
3952 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3953
3954 return &(_pHVDCtrls[u8DrvId]);
3955 }
3956
_HVD_EX_GetStreamIdx(MS_U32 u32Id)3957 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
3958 {
3959 MS_U8 u8OffsetIdx = 0;
3960 MS_U8 u8SidBaseMask = 0xF0;
3961 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
3962
3963 switch (eSidBase)
3964 {
3965 case E_HAL_HVD_MAIN_STREAM_BASE:
3966 {
3967 u8OffsetIdx = 0;
3968 break;
3969 }
3970 case E_HAL_VPU_SUB_STREAM_BASE:
3971 {
3972 u8OffsetIdx = 1;
3973 break;
3974 }
3975 case E_HAL_VPU_MVC_STREAM_BASE:
3976 {
3977 u8OffsetIdx = 0;
3978 break;
3979 }
3980 #ifdef VDEC3
3981 case E_HAL_VPU_N_STREAM_BASE:
3982 {
3983 u8OffsetIdx = (u32Id>>8) & 0xF;
3984 break;
3985 }
3986 #endif
3987 default:
3988 {
3989 u8OffsetIdx = 0;
3990 break;
3991 }
3992 }
3993
3994 return u8OffsetIdx;
3995 }
3996 /*
3997 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
3998 {
3999 MS_U32 i = 0;
4000 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
4001 {
4002 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
4003 {
4004 return TRUE;
4005 }
4006 }
4007 return FALSE;
4008 }
4009 */
4010
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)4011 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
4012 {
4013 MS_PHY u32PhyAddr = 0x0;
4014 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4015
4016 if (pCtrl->MemMap.u32CodeBufAddr == 0)
4017 {
4018 printk("pCtrl->MemMap.u32CodeBufAddr == 0, chid:%d, return null pointer\n", u32Id);
4019 return 0;
4020 }
4021
4022 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
4023
4024 if (u32PhyAddr == 0xFFFFFFFF) //boris
4025 {
4026 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
4027 }
4028 else
4029 {
4030 // TEE, common + share_info
4031 u32PhyAddr += COMMON_AREA_SIZE;
4032 }
4033
4034 return MsOS_PA2KSEG1(u32PhyAddr);
4035 }
4036
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)4037 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
4038 {
4039 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4040 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4041
4042 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
4043 {
4044 return 0;
4045 }
4046
4047 MS_PHY u32PhyAddr = 0x0;
4048 #if 0
4049 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
4050
4051 if (u32PhyAddr == 0xFFFFFFFF)
4052 {
4053 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
4054 }
4055 #endif
4056 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
4057 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
4058
4059 return MsOS_PA2KSEG1(u32PhyAddr);
4060 }
4061
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)4062 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
4063 {
4064
4065 if (u8MiuSel == E_CHIP_MIU_0)
4066 {
4067 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
4068 //_HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
4069 }
4070 else if (u8MiuSel == E_CHIP_MIU_1)
4071 {
4072 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
4073 //_HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
4074 }
4075 /*
4076 else // 2
4077 {
4078 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
4079 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, MIU2_CLIENT_SELECT_GP4_HVD_MIF1, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
4080 }*/
4081
4082 }
4083
4084 #if SUPPORT_G2VP9 && defined(VDEC3)
4085 #ifdef __ARM_NEON__
4086 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)4087 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
4088 {
4089 uint32x4x4_t data, data2;
4090 MS_U8* raster2 = raster + tile_w * 4;
4091
4092 data = vld4q_u32((const uint32_t *)tile);
4093 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
4094
4095 vst1q_u32((uint32_t *)raster, data.val[0]);
4096 raster += stride;
4097 vst1q_u32((uint32_t *)raster, data.val[1]);
4098 raster += stride;
4099 vst1q_u32((uint32_t *)raster, data.val[2]);
4100 raster += stride;
4101 vst1q_u32((uint32_t *)raster, data.val[3]);
4102
4103
4104 vst1q_u32((uint32_t *)raster2, data2.val[0]);
4105 raster2 += stride;
4106 vst1q_u32((uint32_t *)raster2, data2.val[1]);
4107 raster2 += stride;
4108 vst1q_u32((uint32_t *)raster2, data2.val[2]);
4109 raster2 += stride;
4110 vst1q_u32((uint32_t *)raster2, data2.val[3]);
4111 }
4112 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)4113 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
4114 {
4115 MS_U8* tile0 = tile;
4116 MS_U8* tile1 = tile+16;
4117 MS_U8* tile2 = tile+32;
4118 MS_U8* tile3 = tile+48;
4119 int i;
4120
4121 for (i=0; i<4; i++) {
4122 raster[i] = tile0[i];
4123 raster[4+i] = tile1[i];
4124 raster[8+i] = tile2[i];
4125 raster[12+i] = tile3[i];
4126 }
4127
4128 for (i=0; i<4; i++) {
4129 raster[stride+i] = tile0[4+i];
4130 raster[stride+4+i] = tile1[4+i];
4131 raster[stride+8+i] = tile2[4+i];
4132 raster[stride+12+i] = tile3[4+i];
4133 }
4134
4135 for (i=0; i<4; i++) {
4136 raster[2*stride+i] = tile0[8+i];
4137 raster[2*stride+4+i] = tile1[8+i];
4138 raster[2*stride+8+i] = tile2[8+i];
4139 raster[2*stride+12+i] = tile3[8+i];
4140 }
4141
4142 for (i=0; i<4; i++) {
4143 raster[3*stride+i] = tile0[12+i];
4144 raster[3*stride+4+i] = tile1[12+i];
4145 raster[3*stride+8+i] = tile2[12+i];
4146 raster[3*stride+12+i] = tile3[12+i];
4147 }
4148 }
4149 #endif // #ifdef __ARM_NEON__
4150
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)4151 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
4152 {
4153 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
4154 u32Id,
4155 E_TASK_PRI_MEDIUM,
4156 TRUE,
4157 NULL,
4158 32, // stack size..
4159 "HVD_PostProcess_task");
4160
4161 if (s32HvdPpTaskId < 0)
4162 {
4163 HVD_EX_MSG_ERR("Pp Task create failed\n");
4164
4165 return FALSE;
4166 }
4167
4168 HVD_EX_MSG_DBG("Pp Task create success\n");
4169 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
4170
4171 return TRUE;
4172 }
4173
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)4174 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
4175 {
4176 return y * stride * h + x * w * h;
4177 }
4178
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)4179 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
4180 {
4181 return y * stride * h + x * w;
4182 }
4183
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)4184 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
4185 {
4186 raster[0] = tile[0];
4187 raster[1] = tile[1];
4188 raster[2] = tile[2];
4189 raster[3] = tile[3];
4190 raster[stride] = tile[4];
4191 raster[stride + 1] = tile[5];
4192 raster[stride + 2] = tile[6];
4193 raster[stride + 3] = tile[7];
4194 raster[2 * stride] = tile[8];
4195 raster[2 * stride + 1] = tile[9];
4196 raster[2 * stride + 2] = tile[10];
4197 raster[2 * stride + 3] = tile[11];
4198 raster[3 * stride] = tile[12];
4199 raster[3 * stride + 1] = tile[13];
4200 raster[3 * stride + 2] = tile[14];
4201 raster[3 * stride + 3] = tile[15];
4202 }
4203
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)4204 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
4205 {
4206 const MS_U32 tile_w = 4;
4207 const MS_U32 tile_h = 4;
4208 MS_U32 tile_stride = w;
4209 MS_U32 x, y;
4210 MS_U8 *dst1, *dst2;
4211 MS_U8 *src1, *src2;
4212
4213 #ifdef __ARM_NEON__
4214 // To overlap load and store, handle two blocks at the same time.
4215 dst1 = dst;
4216 src1 = src;
4217 for (y = 0; y < h / tile_h; y++)
4218 {
4219 dst2 = dst1;
4220 src2 = src1;
4221 for (x = 0; x <= (w/tile_w - 8); x+=8)
4222 {
4223 tile4x4_to_raster_8(
4224 dst2,
4225 src2,
4226 raster_stride, tile_w, tile_h);
4227 dst2 += tile_w * 8;
4228 src2 += tile_w * tile_h * 8;
4229 }
4230 dst1 += raster_stride * tile_h;
4231 src1 += tile_stride * tile_h;
4232 for (; x < w / tile_w; x++)
4233 {
4234 tile4x4_to_raster(
4235 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
4236 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
4237 raster_stride);
4238 }
4239 }
4240 #else
4241 dst1 = NULL;
4242 src1 = NULL;
4243 dst2 = NULL;
4244 src2 = NULL;
4245
4246 for (y = 0; y < h / tile_h; y++)
4247 {
4248 for (x = 0; x <= (w/tile_w - 4); x+=4)
4249 {
4250 tile4x4_to_raster_4(
4251 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
4252 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
4253 raster_stride);
4254 }
4255 for (; x < w / tile_w; x++)
4256 {
4257 tile4x4_to_raster(
4258 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
4259 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
4260 raster_stride);
4261 }
4262 }
4263 #endif
4264 }
4265
4266 #define FLUSH_CACHE_SIZE (256 * 1024)
4267
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)4268 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
4269 {
4270 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
4271 if (u32Size > FLUSH_CACHE_SIZE)
4272 u32Size = FLUSH_CACHE_SIZE;
4273
4274 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
4275 }
4276
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)4277 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
4278 {
4279 MS_U32 u32SkipSize = 0;
4280
4281 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
4282 if (u32Size > FLUSH_CACHE_SIZE)
4283 {
4284 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
4285 u32Size = FLUSH_CACHE_SIZE;
4286 }
4287
4288 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
4289 }
4290
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)4291 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
4292 {
4293 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
4294 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4295 MS_U32 u32SrcMiuSel, u32DstMiuSel;
4296 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
4297 if(!pShm) {
4298 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
4299 return 0;
4300 }
4301
4302 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
4303
4304 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
4305
4306 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
4307 {
4308 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
4309 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
4310
4311 HVD_Delay_ms(1); // FIXME
4312
4313 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
4314 continue;
4315
4316 HAL_HVD_EX_ReadMemory();
4317
4318 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
4319 {
4320 MS_U8 *pSrcVA, *pDstVA;
4321 MS_U32 u32SrcPA, u32DstPA;
4322 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
4323 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
4324
4325 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
4326 {
4327 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
4328
4329 u16Width = pFrmInfo->u16Width;
4330 u16Height = pFrmInfo->u16Height;
4331 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
4332 }
4333
4334 // Luma
4335 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
4336 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
4337
4338 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
4339 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
4340
4341 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
4342 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
4343
4344 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
4345
4346 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
4347
4348 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
4349
4350 // Chroma
4351 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
4352 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
4353
4354 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
4355 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
4356
4357 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
4358 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
4359
4360 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
4361
4362 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
4363
4364 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
4365
4366 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
4367 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
4368 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
4369
4370 HAL_HVD_EX_FlushMemory();
4371
4372 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
4373 break;
4374
4375 HAL_HVD_EX_ReadMemory();
4376 }
4377 }
4378
4379 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
4380
4381 return TRUE;
4382 }
4383 #endif
4384
HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id,MS_BOOL * isVP8Used,MS_BOOL * isAECUsed,MS_BOOL * isAVCUsed)4385 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed , MS_BOOL *isAVCUsed)
4386 {
4387 MS_U8 i ;
4388 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
4389
4390 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM ; i++)
4391 {
4392 if( _pHVDCtrls[i].bUsed && (i != u8DrvId))
4393 {
4394 MS_U32 u32TempModeFlag = (_pHVDCtrls[i].InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ;
4395 if((E_HVD_INIT_HW_VP8 == u32TempModeFlag))
4396 {
4397 *isVP8Used = TRUE ;
4398 }
4399 else if((E_HVD_INIT_HW_VP9 == u32TempModeFlag) || (E_HVD_INIT_HW_AVS == u32TempModeFlag))
4400 {
4401 *isAECUsed = TRUE ;
4402 }
4403 else if((E_HVD_INIT_HW_AVC == u32TempModeFlag))
4404 {
4405 *isAVCUsed = TRUE ;
4406 }
4407 }
4408 }
4409 }
4410
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)4411 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
4412 {
4413 #ifndef VDEC3
4414 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
4415 #endif
4416 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4417 MS_BOOL isVP8Used = FALSE;
4418 MS_BOOL isAECUsed = FALSE;
4419 MS_BOOL isAVCUsed = FALSE;
4420 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
4421 // MS_U8 u8MiuSel;
4422 // MS_U32 u32StartOffset;
4423
4424 #if SUPPORT_EVD
4425 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
4426 #else
4427 MS_BOOL isEVD = FALSE;
4428 #endif
4429 MS_BOOL isHVD = !isEVD;
4430
4431 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
4432 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
4433
4434 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
4435 // re-setup clock.
4436 #if SUPPORT_G2VP9 && defined(VDEC3)
4437 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4438 #endif
4439
4440 if(isHVD)
4441 {
4442 if(!HAL_VPU_EX_HVDInUsed())
4443 {
4444 HVD_PRINT("HVD power on\n");
4445 #ifdef CONFIG_MSTAR_CLKM
4446 HAL_HVD_EX_PowerCtrl_CLKM(u32Id, TRUE);
4447 #else
4448 HAL_HVD_EX_PowerCtrl(u32Id, TRUE);
4449 #endif
4450 }
4451
4452 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4453 {
4454 HAL_VP8_PowerCtrl(TRUE);
4455 }
4456 else if(!isAECUsed &&( E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4457 {
4458 HAL_AEC_PowerCtrl(TRUE);
4459 }
4460
4461 #ifdef CONFIG_MSTAR_SRAMPD
4462 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
4463 HVD_Delay_ms(1);
4464 #endif
4465 }
4466
4467 #if SUPPORT_EVD
4468 #ifdef VDEC3
4469 if (isEVD)
4470 {
4471 if(!HAL_VPU_EX_EVDInUsed())
4472 {
4473 HVD_PRINT("EVD power on\n");
4474 #ifdef CONFIG_MSTAR_CLKM
4475 HAL_EVD_EX_PowerCtrl_CLKM(u32Id, TRUE);
4476 #else
4477 HAL_EVD_EX_PowerCtrl(u32Id, TRUE);
4478 #endif
4479 }
4480 if(!isAECUsed && (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4481 {
4482 HAL_AEC_PowerCtrl(TRUE);
4483 }
4484 }
4485 #endif
4486 #endif
4487
4488
4489
4490
4491 #if SUPPORT_G2VP9 && defined(VDEC3)
4492 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4493 {
4494 if (!HAL_VPU_EX_G2VP9InUsed())
4495 {
4496 HVD_PRINT("G2 VP9 power on\n");
4497 HAL_VP9_EX_PowerCtrl(TRUE);
4498 }
4499 }
4500 #endif
4501
4502 if ((!HAL_VPU_EX_HVDInUsed()) )
4503 {
4504 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
4505 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
4506 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
4507 _HVD_EX_ResetMainSubBBUWptr(u32Id);
4508
4509 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
4510
4511 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
4512 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
4513 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_128 , HVD_REG_RESET_MIU_128);
4514 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_128 , HVD_REG_RESET_MIU1_128 );
4515 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_256 );
4516 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_256);
4517 //BWA
4518 _HVD_Write2Byte(HVD_REG_BWA_CLK, ((_HVD_Read2Byte(HVD_REG_BWA_CLK))&((~HVD_REG_CLK_HVD_SW_OV_EN & ~HVD_REG_CLK_HVD_IDB_SW_OV_EN))));
4519
4520 #if 0
4521 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
4522 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4523 {
4524 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
4525
4526 _HAL_HVD_Entry();
4527 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
4528 _HAL_HVD_Release();
4529
4530 }
4531 #endif
4532 }
4533
4534 #if SUPPORT_EVD
4535 if (isEVD)
4536 {
4537 #ifdef VDEC3
4538 if (!HAL_VPU_EX_EVDInUsed())
4539 #endif
4540 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
4541 }
4542 #endif
4543
4544 #if SUPPORT_G2VP9 && defined(VDEC3)
4545 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4546 {
4547 if (!HAL_VPU_EX_G2VP9InUsed())
4548 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
4549 }
4550 #endif
4551
4552
4553 if(pCtrl == NULL)
4554 {
4555 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
4556 //return FALSE;
4557 goto RESET;
4558 }
4559
4560 #if SUPPORT_EVD
4561 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
4562 {
4563 #ifdef VDEC3
4564 if (!HAL_VPU_EX_EVDInUsed())
4565 #endif
4566 {
4567 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4568 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
4569 }
4570
4571 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
4572 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
4573 {
4574 #ifdef VDEC3
4575 if (0 == pCtrl->u32BBUId)
4576 #else
4577 if (0 == u8TaskId)
4578 #endif
4579 {
4580 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
4581 }
4582 #ifdef VDEC3
4583 else if (1 == pCtrl->u32BBUId)
4584 #else
4585 else if (1 == u8TaskId)
4586 #endif
4587 {
4588 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
4589 }
4590 #ifdef VDEC3
4591 else if (2 == pCtrl->u32BBUId)
4592 #else
4593 else if (2 == u8TaskId)
4594 #endif
4595 {
4596 _HVD_WriteWordMask(EVD_BBU23_SETTING, REG_TSP2EVD_EN_BS3, REG_TSP2EVD_EN_BS3);
4597 }
4598 else
4599 {
4600 #ifdef VDEC3
4601 if (pCtrl->u32BBUId > 3)
4602 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
4603 #else
4604 if (u8TaskId > 3)
4605 HVD_PRINT("Error u8TaskId = %d , %s:%d\n",u8TaskId,__FUNCTION__,__LINE__);
4606 #endif
4607
4608 _HVD_WriteWordMask(EVD_BBU23_SETTING, REG_TSP2EVD_EN_BS4, REG_TSP2EVD_EN_BS4);
4609 }
4610 }
4611 goto RESET;
4612 }
4613 #endif
4614
4615 // HVD4, from JANUS and later chip
4616 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
4617 {
4618 case E_HVD_INIT_HW_AVS:
4619 {
4620 #ifdef VDEC3
4621 if (0 == pCtrl->u32BBUId)
4622 #else
4623 if (0 == u8TaskId)
4624 #endif
4625 {
4626 _HVD_WriteWordMask(HVD_REG_RESET, 0,
4627 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
4628 }
4629 else
4630 {
4631 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
4632 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
4633 }
4634
4635 break;
4636 }
4637 case E_HVD_INIT_HW_RM:
4638 {
4639 #ifdef VDEC3
4640 if (0 == pCtrl->u32BBUId)
4641 #else
4642 if (0 == u8TaskId)
4643 #endif
4644 {
4645 _HVD_WriteWordMask(HVD_REG_RESET, 0,
4646 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
4647
4648 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
4649 {
4650 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
4651 }
4652 else // RV 8
4653 {
4654 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
4655 }
4656 }
4657 else
4658 {
4659 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
4660 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
4661
4662 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
4663 {
4664 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
4665 }
4666 else // RV 8
4667 {
4668 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
4669 }
4670
4671 }
4672
4673 break;
4674 }
4675 default:
4676 {
4677 #ifdef VDEC3
4678 if (0 == pCtrl->u32BBUId)
4679 #else
4680 if (0 == u8TaskId)
4681 #endif
4682 {
4683 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
4684 }
4685 else
4686 {
4687 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
4688 }
4689 break;
4690 }
4691 }
4692
4693 RESET:
4694
4695 #if 0 //use miu256bit
4696 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
4697
4698 if (!HAL_VPU_EX_HVDInUsed())
4699 {
4700 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
4701 }
4702
4703 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
4704 #endif
4705
4706 #if SUPPORT_EVD
4707 if (isEVD)
4708 {
4709 #ifdef VDEC3
4710 if (!HAL_VPU_EX_EVDInUsed())
4711 #endif
4712 {
4713 HVD_PRINT("EVD miu 128 bits\n");
4714 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_256 & ~EVD_REG_RESET_MIU1_256));
4715 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_128 | EVD_REG_RESET_MIU1_128));
4716 HVD_PRINT("EVD BBU 128 bits\n");
4717 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) & ~REG_BBU_MIU_256));
4718 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) | REG_BBU_MIU_128));
4719 _HVD_Write2Byte(REG_CLK_EVD, (_HVD_Read2Byte(REG_CLK_EVD) & ~REG_CLK_EVD_SW_OV_EN & ~REG_CLK_EVD_PPU_SW_OV_EN));//set 0 firmware
4720 }
4721 }
4722 #endif
4723 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
4724 // Only ES buffer addrress needs to be set for VP8
4725 _HVD_EX_SetESBufferAddr(u32Id);
4726 #else
4727 if(DecoderType != E_VPU_EX_DECODER_MVD)
4728 {
4729 _HVD_EX_SetBufferAddr(u32Id);
4730 }
4731 #endif
4732 if (!HAL_VPU_EX_HVDInUsed())
4733 {
4734 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
4735 }
4736
4737 #if SUPPORT_EVD
4738 if (isEVD)
4739 {
4740 #ifdef VDEC3
4741 if (!HAL_VPU_EX_EVDInUsed())
4742 #endif
4743 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
4744 }
4745 #endif
4746
4747 #if SUPPORT_G2VP9 && defined(VDEC3)
4748 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4749 {
4750 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4751 if(!pShm) {
4752 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
4753 return 0;
4754 }
4755
4756 if (!HAL_VPU_EX_G2VP9InUsed())
4757 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
4758
4759 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
4760 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
4761 }
4762 #endif
4763
4764 return TRUE;
4765 }
4766
HAL_HVD_EX_DeinitHW(MS_U32 u32Id)4767 MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id)
4768 {
4769 MS_U16 u16Timeout = 1000;
4770 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4771 MS_BOOL isVP8Used = FALSE;
4772 MS_BOOL isAECUsed = FALSE;
4773 MS_BOOL isAVCUsed = FALSE;
4774 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed , &isAVCUsed);
4775
4776 #if SUPPORT_EVD
4777 if(!isAVCUsed && E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) && !HAL_VPU_EX_EVDInUsed())
4778 {
4779 HAL_EVD_EX_DeinitHW(u32Id);//no AVC/EVD use , close EVD power
4780 }
4781 #endif
4782
4783 if(TRUE == HAL_VPU_EX_HVDInUsed())
4784 {
4785 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4786 {
4787 HAL_VP8_PowerCtrl(FALSE);
4788 }
4789 else if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4790 {
4791 HAL_AEC_PowerCtrl(FALSE);
4792 }
4793 return FALSE;
4794 }
4795 else
4796 {
4797 _HVD_EX_SetMIUProtectMask(TRUE);
4798
4799 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
4800
4801 while (u16Timeout)
4802 {
4803 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
4804 {
4805 break;
4806 }
4807 u16Timeout--;
4808 }
4809
4810 #ifdef CONFIG_MSTAR_CLKM
4811 HAL_HVD_EX_PowerCtrl_CLKM(u32Id, FALSE);
4812 #else
4813 HAL_HVD_EX_PowerCtrl(u32Id, FALSE);
4814 #endif
4815
4816 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4817 {
4818 HAL_VP8_PowerCtrl(FALSE);
4819 }
4820 else if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4821 {
4822 HAL_AEC_PowerCtrl(FALSE);
4823 }
4824
4825 #ifdef CONFIG_MSTAR_SRAMPD
4826 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
4827 HVD_Delay_ms(1);
4828 #endif
4829
4830 _HVD_EX_SetMIUProtectMask(FALSE);
4831
4832 return TRUE;
4833 }
4834
4835 return FALSE;
4836 }
4837
HAL_HVD_EX_FlushMemory(void)4838 void HAL_HVD_EX_FlushMemory(void)
4839 {
4840 MsOS_FlushMemory();
4841 }
4842
HAL_HVD_EX_ReadMemory(void)4843 void HAL_HVD_EX_ReadMemory(void)
4844 {
4845 MsOS_ReadMemory();
4846 }
4847
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)4848 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
4849 {
4850 _pHVDCtrls = pHVDCtrlsBase;
4851 }
4852
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)4853 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
4854 {
4855 return;
4856 }
4857
HAL_HVD_EX_GetHWVersionID(void)4858 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
4859 {
4860 return _HVD_Read2Byte(HVD_REG_REV_ID);
4861 }
4862
4863
HAL_HVD_EX_Init_Share_Mem(void)4864 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
4865 {
4866 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
4867 #if !defined(SUPPORT_X_MODEL_FEATURE)
4868 MS_U32 u32ShmId;
4869 MS_VIRT u32Addr;
4870 MS_U32 u32BufSize;
4871
4872
4873 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
4874 sizeof(HVD_Hal_CTX),
4875 &u32ShmId,
4876 &u32Addr,
4877 &u32BufSize,
4878 MSOS_SHM_QUERY))
4879 {
4880 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
4881 sizeof(HVD_Hal_CTX),
4882 &u32ShmId,
4883 &u32Addr,
4884 &u32BufSize,
4885 MSOS_SHM_CREATE))
4886 {
4887 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
4888 if(pHVDHalContext == NULL)
4889 {
4890 pHVDHalContext = &gHVDHalContext;
4891 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4892 _HVD_EX_Context_Init_HAL();
4893 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
4894 }
4895 else
4896 {
4897 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
4898 }
4899 //return FALSE;
4900 }
4901 else
4902 {
4903 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
4904 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
4905 _HVD_EX_Context_Init_HAL();
4906 }
4907 }
4908 else
4909 {
4910 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
4911 }
4912 #else
4913 if(pHVDHalContext == NULL)
4914 {
4915 pHVDHalContext = &gHVDHalContext;
4916 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4917 _HVD_EX_Context_Init_HAL();
4918 }
4919 #endif
4920 _HAL_HVD_MutexCreate();
4921 #else
4922 if(pHVDHalContext == NULL)
4923 {
4924 pHVDHalContext = &gHVDHalContext;
4925 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
4926 _HVD_EX_Context_Init_HAL();
4927 }
4928 #endif
4929
4930 return TRUE;
4931 }
4932
4933
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)4934 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
4935 {
4936 MS_U32 i = 0;
4937
4938 if (eStreamType == E_HAL_HVD_MVC_STREAM)
4939 {
4940 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
4941 return pHVDHalContext->_stHVDStream[0].eStreamId;
4942 }
4943 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
4944 {
4945 for (i = 0;
4946 i <
4947 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
4948 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
4949 {
4950 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
4951 {
4952 return pHVDHalContext->_stHVDStream[i].eStreamId;
4953 }
4954 }
4955 }
4956 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
4957 {
4958 for (i = 0;
4959 i <
4960 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
4961 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
4962 {
4963 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
4964 {
4965 return pHVDHalContext->_stHVDStream[i].eStreamId;
4966 }
4967 }
4968 }
4969 #ifdef VDEC3
4970 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
4971 {
4972 i = eStreamType - E_HAL_HVD_N_STREAM;
4973 if (!pHVDHalContext->_stHVDStream[i].bUsed)
4974 return pHVDHalContext->_stHVDStream[i].eStreamId;
4975 }
4976 #endif
4977
4978 return E_HAL_HVD_STREAM_NONE;
4979 }
4980
HAL_VP8_PowerCtrl(MS_BOOL bEnable)4981 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable)
4982 {
4983 if (bEnable)
4984 {
4985 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
4986
4987 switch (pHVDHalContext->u32HVDClockType)
4988 {
4989 case 216:
4990 {
4991 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
4992 break;
4993 }
4994 default:
4995 {
4996 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
4997 break;
4998 }
4999 }
5000 }
5001 else
5002 {
5003 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
5004 }
5005
5006 }
5007
HAL_AEC_PowerCtrl(MS_BOOL bEnable)5008 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable)
5009 {
5010 if (bEnable)
5011 {
5012 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
5013
5014 switch (pHVDHalContext->u32HVDClockType)
5015 {
5016 case 240:
5017 {
5018 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
5019 break;
5020 }
5021 default:
5022 {
5023 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
5024 break;
5025 }
5026 }
5027 }
5028 else
5029 {
5030 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
5031 }
5032
5033 }
5034
5035
HAL_HVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)5036 void HAL_HVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
5037 {
5038
5039 if (bEnable)
5040 {
5041 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
5042 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
5043 }
5044 else
5045 {
5046 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
5047 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
5048 }
5049
5050 // fix to not inverse
5051 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
5052
5053 switch (pHVDHalContext->u32HVDClockType)
5054 {
5055 #if 0 //for overclocking
5056 case 432:
5057 {
5058 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
5059 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
5060 break;
5061 }
5062 #endif
5063 case 240:
5064 {
5065 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
5066 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
5067 break;
5068 }
5069 case 216:
5070 {
5071 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
5072 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
5073 break;
5074 }
5075 default:
5076 {
5077 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
5078 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
5079 break;
5080 }
5081 }
5082 }
5083
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)5084 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
5085 {
5086 u32HVDRegOSBase = u32RegBase;
5087 HAL_VPU_EX_InitRegBase(u32RegBase);
5088 }
5089
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)5090 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
5091 {
5092 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
5093 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5094 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
5095 }
5096
HAL_HVD_EX_InitVariables(MS_U32 u32Id)5097 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
5098 {
5099 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5100 HVD_ShareMem *pShm = NULL;
5101 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5102 #if HVD_ENABLE_MVC
5103 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
5104 #endif ///HVD_ENABLE_MVC
5105
5106 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
5107 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
5108 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
5109 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5110 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
5111 int i;
5112 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
5113 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
5114 #if HVD_ENABLE_MVC
5115 if(bMVC)
5116 {
5117 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
5118 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
5119 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
5120 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
5121 }
5122 #endif ///HVD_ENABLE_MVC
5123
5124 // set a local copy of FW code address; assuming there is only one copy of FW,
5125 // no matter how many task will be created.
5126
5127 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5128 if(!pShm) {
5129 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
5130 return E_HVD_RETURN_FAIL;
5131 }
5132
5133 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
5134
5135 // global variables
5136 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
5137
5138
5139 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
5140 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
5141 // Create mutex
5142 //_HAL_HVD_MutexCreate();
5143
5144 // fill HVD init variables
5145 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5146 {
5147 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
5148 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
5149 }
5150 else
5151 #if HVD_ENABLE_RV_FEATURE
5152 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
5153 {
5154 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
5155 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
5156 #ifdef VDEC3_FB
5157 pHVDHalContext->u32RV_VLCTableAddr = 0;
5158 #else
5159 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
5160 {
5161 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
5162 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
5163 }
5164 else
5165 {
5166 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
5167 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
5168 return E_HVD_RETURN_INVALID_PARAMETER;
5169 }
5170 #endif
5171 }
5172 else
5173 #endif
5174 {
5175 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
5176 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
5177 #if HVD_ENABLE_MVC
5178 if(bMVC)
5179 {
5180 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
5181 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
5182 }
5183 #endif /// HVD_ENABLE_MVC
5184 pHVDHalContext->u32RV_VLCTableAddr = 0;
5185 }
5186
5187 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
5188 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
5189 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
5190 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
5191 {
5192 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
5193 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
5194 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
5195 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
5196 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
5197 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
5198 #if HVD_ENABLE_MVC
5199 if(bMVC)
5200 {
5201 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
5202 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
5203 {
5204 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
5205 }
5206 }
5207 #endif /// HVD_ENABLE_MVC
5208
5209 return E_HVD_RETURN_SUCCESS;
5210 }
5211 else
5212 {
5213 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
5214 (unsigned long)MS_VA2PA((MS_VIRT)pShm),
5215 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
5216 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
5217 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
5218 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
5219 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
5220 return E_HVD_RETURN_INVALID_PARAMETER;
5221 }
5222 }
5223
5224 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)5225 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
5226 #else
5227 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
5228 #endif
5229 {
5230 MS_U32 u32Addr = 0;
5231 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5232 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5233 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5234 if(!pShm) {
5235 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
5236 return E_HVD_RETURN_FAIL;
5237 }
5238
5239 MS_U32 u32TmpStartOffset;
5240 MS_U8 u8TmpMiuSel;
5241
5242
5243 memset(pShm, 0, sizeof(HVD_ShareMem));
5244
5245 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
5246
5247 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
5248 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
5249 #ifdef VDEC3
5250 if (bFWdecideFB || bCMAUsed)
5251 {
5252 pShm->u32FrameBufAddr = 0;
5253 pShm->u32FrameBufSize = 0;
5254 }
5255 else
5256 #endif
5257 {
5258 pShm->u32FrameBufAddr = u32Addr;
5259 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
5260 }
5261
5262 // FIXME: need to use the avaliable task resource instead of using next task resource
5263 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
5264 pShm->u8ExternalHeapIdx = u8Idx + 1;
5265 else
5266 pShm->u8ExternalHeapIdx = 0xFF;
5267 pShm->DispInfo.u16DispWidth = 1;
5268 pShm->DispInfo.u16DispHeight = 1;
5269 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
5270 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
5271 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
5272 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
5273 //Chip info
5274 pShm->u16ChipID = E_MSTAR_CHIP_K6LITE;
5275 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
5276 // PreSetControl
5277 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bOnePendingBuffer)
5278 {
5279 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
5280 }
5281
5282 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bCalFrameRate)
5283 {
5284 pShm->u32PreSetControl |= PRESET_CAL_FRAMERATE;
5285 }
5286
5287
5288 pShm->bUseTSPInBBUMode = FALSE;
5289
5290
5291 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable) &&
5292 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
5293 {
5294 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
5295
5296 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufAddr);
5297
5298 pShm->u32IapGnBufAddr = u32Addr;
5299 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufSize;
5300
5301 }
5302
5303 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
5304 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
5305 {
5306 case E_HVD_DEF_MFCODEC_DEFAULT:
5307 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
5308 break;
5309 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
5310 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
5311 break;
5312 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
5313 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
5314 break;
5315 default:
5316 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
5317 }
5318
5319 pShm->u8CodecFeature &= ~E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
5320 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bDVSingleLayerMode)
5321 pShm->u8CodecFeature |= E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
5322
5323 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
5324 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
5325 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
5326 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
5327 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
5328 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
5329
5330 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.bEnable))
5331 {
5332 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
5333
5334 pShm->stDynmcDispPath.u8Connect = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.bConnect;
5335 pShm->stDynmcDispPath.u8DispPath = (MS_U8)(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.eMvopPath);
5336 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
5337
5338 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, pShm->stDynmcDispPath.u8DispPath);
5339 }
5340 else
5341 {
5342 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
5343
5344 MS_U8 u8Connect = FALSE;
5345 MS_U8 u8Path = E_CTL_DISPLAY_PATH_NONE;
5346 switch (pCtrl->eStream)
5347 {
5348 case E_HVD_ORIGINAL_MAIN_STREAM:
5349 u8Connect = TRUE;
5350 u8Path = E_CTL_DISPLAY_PATH_MVOP_0;
5351 break;
5352 case E_HVD_ORIGINAL_SUB_STREAM:
5353 u8Connect = TRUE;
5354 u8Path = E_CTL_DISPLAY_PATH_MVOP_1;
5355 break;
5356 case E_HVD_ORIGINAL_N_STREAM:
5357 default:
5358 u8Connect = FALSE;
5359 u8Path = E_CTL_DISPLAY_PATH_NONE;
5360 break;
5361 }
5362
5363 pShm->stDynmcDispPath.u8Connect = u8Connect;
5364 pShm->stDynmcDispPath.u8DispPath = u8Path;
5365 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
5366
5367 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, u8Path);
5368 }
5369
5370 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5371 {
5372 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.bEnable))
5373 {
5374 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
5375 pShm->u8InputTSP = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.u8InputTsp;
5376
5377 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
5378 }
5379 else
5380 {
5381 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
5382
5383 MS_U8 u8Input = E_CTL_INPUT_TSP_NONE;
5384 switch (pCtrl->eStream)
5385 {
5386 case E_HVD_ORIGINAL_MAIN_STREAM:
5387 u8Input = E_CTL_INPUT_TSP_0;
5388 break;
5389 case E_HVD_ORIGINAL_SUB_STREAM:
5390 u8Input = E_CTL_INPUT_TSP_1;
5391 break;
5392 case E_HVD_ORIGINAL_N_STREAM:
5393 default:
5394 u8Input = E_CTL_INPUT_TSP_NONE;
5395 break;
5396 }
5397
5398 pShm->u8InputTSP = u8Input;
5399
5400 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
5401 }
5402 }
5403 else
5404 {
5405 HVD_EX_MSG_DBG("[NDec][0x%x][%d] not TSP input, ignore PRESET_CONNECT_INPUT_TSP \n", u32Id, u8Idx);
5406 }
5407
5408 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
5409 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
5410 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
5411 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
5412 else
5413 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
5414 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
5415 {
5416 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
5417 {
5418 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
5419 }
5420 else
5421 {
5422 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
5423 }
5424 }
5425 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
5426 {
5427 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
5428 {
5429 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
5430 }
5431 else
5432 {
5433 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
5434 }
5435 }
5436 else
5437 {
5438 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
5439 }
5440
5441 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5442 {
5443 pShm->bHVDIMIEnable = TRUE;
5444 }
5445
5446 #if 0
5447 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bEnableDynamicCMA)
5448 {
5449 pShm->u8CodecFeature |= E_VDEC_DYNAMIC_CMA_MODE;
5450 }
5451 #endif
5452
5453 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5454 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5455 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5456 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5457 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5458 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5459 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5460 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
5461 (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
5462 {
5463 pShm->bUseWbMvop = 1;
5464 }
5465
5466
5467 // disable AVC fluidplay temporarily
5468 //if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
5469 // E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5470 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5471 {
5472 pShm->u8CodecFeature |= E_VDEC_TEMPORAL_SCALABILITY_MODE;
5473 }
5474
5475 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
5476
5477 #if (VPU_FORCE_MIU_MODE)
5478 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5479
5480 pShm->u32FWBaseAddr = u32TmpStartOffset;
5481
5482 #else
5483 ///TODO:
5484 /*
5485 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5486
5487 if(u8TmpMiuSel == E_CHIP_MIU_0)
5488 {
5489 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
5490 }
5491 else if(u8TmpMiuSel == E_CHIP_MIU_1)
5492 {
5493 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
5494 }
5495 else if(u8TmpMiuSel == E_CHIP_MIU_2)
5496 {
5497 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
5498 }
5499 */
5500 #endif
5501 //HVD_PRINT("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
5502 #else
5503 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
5504 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
5505 {
5506 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
5507 }
5508 pShm->u32FWBaseAddr = u32Addr;
5509 #endif
5510
5511 // RM only
5512 #if HVD_ENABLE_RV_FEATURE
5513 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
5514 && (pCtrl->InitParams.pRVFileInfo != NULL))
5515 {
5516 MS_U32 i = 0;
5517
5518 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
5519 {
5520 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
5521 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
5522 }
5523
5524 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
5525 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
5526 #ifdef VDEC3_FB
5527 pShm->u32RM_VLCTableAddr = 0;
5528 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
5529 #else
5530 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
5531
5532 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
5533 u32Addr = u32TmpStartOffset;
5534
5535 pShm->u32RM_VLCTableAddr = u32Addr;
5536 #endif
5537 }
5538 #endif
5539
5540 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5541 && (pCtrl->InitParams.pRVFileInfo != NULL))
5542 {
5543 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
5544 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
5545 }
5546
5547 //if(pCtrl->InitParams.bColocateBBUMode)
5548 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
5549 {
5550 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5551 }
5552
5553 #if SUPPORT_G2VP9
5554 // Enable SW detile support for G2 VP9
5555 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5556 {
5557 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
5558 }
5559 #endif
5560
5561 HAL_HVD_EX_FlushMemory();
5562
5563 return E_HVD_RETURN_SUCCESS;
5564 }
5565 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)5566 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
5567 #else
5568 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
5569 #endif
5570 {
5571 MS_BOOL bInitRet = FALSE;
5572
5573 #if 0
5574 // check MVD power on
5575 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
5576 {
5577 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
5578 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
5579 HVD_Delay_ms(1);
5580 }
5581 // Check VPU power on
5582 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
5583 {
5584 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
5585 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
5586 HVD_Delay_ms(1);
5587 }
5588 // check HVD power on
5589 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
5590 {
5591 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
5592 HAL_HVD_EX_PowerCtrl(TRUE);
5593 HVD_Delay_ms(1);
5594 }
5595 #endif
5596 #ifdef VDEC3
5597 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
5598 #else
5599 bInitRet = _HVD_EX_SetRegCPU(u32Id);
5600 #endif
5601 if (!bInitRet)
5602 {
5603 return E_HVD_RETURN_FAIL;
5604 }
5605
5606 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
5607
5608 if (!bInitRet)
5609 {
5610 return E_HVD_RETURN_FAIL;
5611 }
5612
5613 return E_HVD_RETURN_SUCCESS;
5614 }
5615
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)5616 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
5617 {
5618 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5619
5620 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
5621
5622 return E_HVD_RETURN_SUCCESS;
5623 }
5624
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)5625 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
5626 {
5627 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5628 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5629 if(!pShm) {
5630 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
5631 return E_HVD_RETURN_FAIL;
5632 }
5633
5634 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5635 MS_BOOL bMVC = FALSE;
5636 #if HVD_ENABLE_MVC
5637 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
5638 #endif
5639
5640 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5641 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
5642
5643 switch (u32type)
5644 {
5645 // share memory
5646 // switch
5647 case E_HVD_SDATA_FRAMEBUF_ADDR:
5648 {
5649 pShm->u32FrameBufAddr = u32Data;
5650 break;
5651 }
5652 case E_HVD_SDATA_FRAMEBUF_SIZE:
5653 {
5654 pShm->u32FrameBufSize = u32Data;
5655 break;
5656 }
5657 case E_HVD_SDATA_FRAMEBUF2_ADDR:
5658 {
5659 pShm->u32FrameBuf2Addr = u32Data;
5660 break;
5661 }
5662 case E_HVD_SDATA_FRAMEBUF2_SIZE:
5663 {
5664 pShm->u32FrameBuf2Size = u32Data;
5665 break;
5666 }
5667 case E_HVD_SDATA_MAX_CMA_SIZE:
5668 {
5669 pShm->u32MaxCMAFrameBufSize = u32Data;
5670 break;
5671 }
5672 case E_HVD_SDATA_MAX_CMA_SIZE2:
5673 {
5674 pShm->u32MaxCMAFrameBuf2Size = u32Data;
5675 break;
5676 }
5677 case E_HVD_SDATA_CMA_USED:
5678 {
5679 pShm->bCMA_Use = u32Data;
5680 break;
5681 }
5682 case E_HVD_SDATA_CMA_ALLOC_DONE:
5683 {
5684 pShm->bCMA_AllocDone = u32Data;
5685 break;
5686 }
5687 case E_HVD_SDATA_CMA_TWO_MIU:
5688 {
5689 pShm->bCMA_TwoMIU = u32Data;
5690 break;
5691 }
5692 case E_HVD_SDATA_RM_PICTURE_SIZES:
5693 {
5694 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
5695 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
5696 break;
5697 }
5698 case E_HVD_SDATA_ERROR_CODE:
5699 {
5700 pShm->u16ErrCode = (MS_U16) u32Data;
5701 break;
5702 }
5703 case E_HVD_SDATA_DISP_INFO_TH:
5704 {
5705 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
5706 sizeof(HVD_DISP_THRESHOLD));
5707 break;
5708 }
5709 case E_HVD_SDATA_FW_FLUSH_STATUS:
5710 {
5711 pShm->u8FlushStatus = (MS_U8)u32Data;
5712 break;
5713 }
5714 case E_HVD_SDATA_DMX_FRAMERATE:
5715 {
5716 pShm->u32DmxFrameRate = u32Data;
5717 break;
5718 }
5719 case E_HVD_SDATA_DMX_FRAMERATEBASE:
5720 {
5721 pShm->u32DmxFrameRateBase = u32Data;
5722 break;
5723 }
5724 case E_HVD_SDATA_MIU_SEL:
5725 {
5726 pShm->u32VDEC_MIU_SEL = u32Data;
5727 break;
5728 }
5729 case E_HVD_SDATA_DV_XC_SHM_SIZE:
5730 {
5731 pShm->u32DolbyVisionXCShmSize = u32Data;
5732 break;
5733 }
5734 // SRAM
5735
5736 // Mailbox
5737 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
5738 {
5739 if (u32Data != 0)
5740 {
5741 pShm->bEnableDispCtrl = TRUE;
5742 pShm->bIsTrigDisp = TRUE;
5743 }
5744 else
5745 {
5746 pShm->bEnableDispCtrl = FALSE;
5747 }
5748
5749 break;
5750 }
5751 case E_HVD_SDATA_GET_DISP_INFO_START:
5752 {
5753 pShm->bSpsChange = FALSE;
5754 break;
5755 }
5756 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
5757 {
5758 pShm->u32VirtualBoxWidth = u32Data;
5759 break;
5760 }
5761 case E_HVD_SDATA_DV_INFO:
5762 {
5763 MS_U8 u8DVLevel = u32Data & 0x00ff;
5764 MS_U8 u8DVProfile = (u32Data >> 8) & 0x00ff;
5765
5766 pShm->u8DVLevelFromDriverAPI = u8DVLevel;
5767 pShm->u8DVProfileFromDriverAPI = u8DVProfile;
5768 }
5769 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
5770 {
5771 pShm->u32VirtualBoxHeight = u32Data;
5772 break;
5773 }
5774 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
5775 {
5776 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
5777 {
5778 //HVD_PRINT("DispFrame DqPtr: %d\n", u32Data);
5779 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
5780 }
5781 break;
5782 }
5783 case E_HVD_SDATA_DISPQ_STATUS_DISP:
5784 {
5785 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
5786 {
5787 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
5788 {
5789 //HVD_PRINT("DispFrame DqPtr: %ld\n", u32Data);
5790 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
5791 }
5792 }
5793 break;
5794 }
5795 case E_HVD_SDATA_DISPQ_STATUS_FREE:
5796 {
5797 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5798 {
5799 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
5800 {
5801 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
5802 {
5803 //ALOGE("R1: %x", u32Data);
5804 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
5805 }
5806 else
5807 {
5808 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
5809 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
5810 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
5811 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
5812 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
5813 }
5814 }
5815 else
5816 {
5817 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
5818 }
5819 }
5820 else
5821 {
5822 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
5823 {
5824 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
5825 }
5826 }
5827 break;
5828 }
5829 #if 0//(HVD_ENABLE_IQMEM)
5830 case E_HVD_SDATA_FW_IQMEM_CTRL:
5831 {
5832 pShm->u8IQmemCtrl= (MS_U8)u32Data;
5833 break;
5834
5835 }
5836 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
5837 {
5838 if (u32Data != 0)
5839 {
5840 pShm->bIQmemEnableIfSupport= TRUE;
5841 }
5842 else
5843 {
5844 pShm->bIQmemEnableIfSupport= FALSE;
5845 }
5846
5847
5848 break;
5849
5850 }
5851 #endif
5852 case E_HVD_SDATA_DYNMC_DISP_PATH_STATUS:
5853 {
5854 pShm->stDynmcDispPath.u8ConnectStatus = u32Data;
5855 break;
5856 }
5857 case E_HVD_SDATA_VP9HDR10INFO:
5858 {
5859 int i,j;
5860 HVD_Config_VP9HDR10* stVP9HDR10Info = (HVD_Config_VP9HDR10*) u32Data;
5861
5862 pShm->VP9HDR10Info.u32Version = stVP9HDR10Info->u32Version;
5863 pShm->VP9HDR10Info.u8MatrixCoefficients = stVP9HDR10Info->u8MatrixCoefficients;
5864 pShm->VP9HDR10Info.u8BitsPerChannel = stVP9HDR10Info->u8BitsPerChannel;
5865 pShm->VP9HDR10Info.u8ChromaSubsamplingHorz = stVP9HDR10Info->u8ChromaSubsamplingHorz;
5866 pShm->VP9HDR10Info.u8ChromaSubsamplingVert = stVP9HDR10Info->u8ChromaSubsamplingVert;
5867 pShm->VP9HDR10Info.u8CbSubsamplingHorz = stVP9HDR10Info->u8CbSubsamplingHorz;
5868 pShm->VP9HDR10Info.u8CbSubsamplingVert = stVP9HDR10Info->u8CbSubsamplingVert;
5869 pShm->VP9HDR10Info.u8ChromaSitingHorz = stVP9HDR10Info->u8ChromaSitingHorz;
5870 pShm->VP9HDR10Info.u8ChromaSitingVert = stVP9HDR10Info->u8ChromaSitingVert;
5871 pShm->VP9HDR10Info.u8ColorRange = stVP9HDR10Info->u8ColorRange;
5872 pShm->VP9HDR10Info.u8TransferCharacteristics = stVP9HDR10Info->u8TransferCharacteristics;
5873 pShm->VP9HDR10Info.u8ColourPrimaries = stVP9HDR10Info->u8ColourPrimaries;
5874 pShm->VP9HDR10Info.u16MaxCLL = stVP9HDR10Info->u16MaxCLL;
5875 pShm->VP9HDR10Info.u16MaxFALL = stVP9HDR10Info->u16MaxFALL;
5876 pShm->VP9HDR10Info.u32MaxLuminance = stVP9HDR10Info->u32MaxLuminance;
5877 pShm->VP9HDR10Info.u32MinLuminance = stVP9HDR10Info->u32MinLuminance;
5878
5879 for(i=0;i<2;i++)
5880 {
5881 pShm->VP9HDR10Info.u16WhitePoint[i] = stVP9HDR10Info->u16WhitePoint[i];
5882 }
5883
5884 for(i=0;i<3;i++)
5885 {
5886 for(j=0;j<2;j++)
5887 {
5888 pShm->VP9HDR10Info.u16Primaries[i][j] = stVP9HDR10Info->u16Primaries[i][j];
5889 }
5890 }
5891 pShm->u8VP9HDR10InfoVaild = TRUE;
5892 break;
5893 }
5894 default:
5895 break;
5896 }
5897
5898 HAL_HVD_EX_FlushMemory();
5899
5900 return eRet;
5901 }
5902
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)5903 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
5904 {
5905 MS_S64 s64Ret = 0;
5906 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5907 if(!pShm) {
5908 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
5909 return 0;
5910 }
5911
5912 HAL_HVD_EX_ReadMemory();
5913
5914 switch (eType)
5915 {
5916 case E_HVD_GDATA_PTS_STC_DIFF:
5917 s64Ret = pShm->s64PtsStcDiff;
5918 break;
5919 case E_HVD_GDATA_TS_SEAMLESS_TARGET_PTS:
5920 s64Ret = (MS_S64)(pShm->u64SeamlessTargetPTS); //33bit PTS is compatible in S64
5921 break;
5922 default:
5923 break;
5924 }
5925
5926 return s64Ret;
5927 }
5928
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)5929 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
5930 {
5931 MS_VIRT u32Ret = 0;
5932 //static MS_U64 u64pts_real = 0;
5933 MS_U64 u64pts_low = 0;
5934 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5935 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5936
5937 HAL_HVD_EX_ReadMemory();
5938
5939 if(pShm == NULL)
5940 {
5941 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
5942 HVD_PRINT("########## VDEC patch for Debug ###########\n");
5943 return 0x0;
5944 }
5945
5946 switch (eType)
5947 {
5948 // share memory
5949 // switch
5950 case E_HVD_GDATA_DISP_INFO_ADDR:
5951 {
5952 u32Ret = (MS_VIRT) (&pShm->DispInfo);
5953 break;
5954 }
5955 case E_HVD_GDATA_MIU_SEL:
5956 u32Ret = pShm->u32VDEC_MIU_SEL;
5957 break;
5958 case E_HVD_GDATA_FRAMEBUF_ADDR:
5959 u32Ret = pShm->u32FrameBufAddr;
5960 break;
5961 case E_HVD_GDATA_FRAMEBUF_SIZE:
5962 u32Ret = pShm->u32FrameBufSize;
5963 break;
5964 case E_HVD_GDATA_FRAMEBUF2_ADDR:
5965 u32Ret = pShm->u32FrameBuf2Addr;
5966 break;
5967 case E_HVD_GDATA_FRAMEBUF2_SIZE:
5968 u32Ret = pShm->u32FrameBuf2Size;
5969 break;
5970 case E_HVD_GDATA_CMA_ALLOC_DONE:
5971 u32Ret = pShm->bCMA_AllocDone;
5972 break;
5973 case E_HVD_GDATA_CMA_USED:
5974 u32Ret = pShm->bCMA_Use;
5975 break;
5976 case E_HVD_GDATA_DYNMC_DISP_PATH_STATUS:
5977 u32Ret = pShm->stDynmcDispPath.u8ConnectStatus;//pShm->u8SetDynmcDispPathStatus;
5978 break;
5979 // report
5980 case E_HVD_GDATA_PTS:
5981 {
5982 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
5983 break;
5984 }
5985 case E_HVD_GDATA_U64PTS:
5986 {
5987 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
5988 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
5989 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
5990 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
5991 break;
5992 }
5993 case E_HVD_GDATA_U64PTS_PRE_PARSE:
5994 {
5995 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
5996 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
5997 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
5998 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
5999 break;
6000 }
6001 case E_HVD_GDATA_DECODE_CNT:
6002 {
6003 u32Ret = pShm->u32DecodeCnt;
6004 break;
6005 }
6006 case E_HVD_GDATA_DATA_ERROR_CNT:
6007 {
6008 u32Ret = pShm->u32DataErrCnt;
6009 break;
6010 }
6011 case E_HVD_GDATA_DEC_ERROR_CNT:
6012 {
6013 u32Ret = pShm->u32DecErrCnt;
6014 break;
6015 }
6016 case E_HVD_GDATA_ERROR_CODE:
6017 {
6018 u32Ret = (MS_U32) (pShm->u16ErrCode);
6019 break;
6020 }
6021 case E_HVD_GDATA_VPU_IDLE_CNT:
6022 {
6023 u32Ret = pShm->u32VPUIdleCnt;
6024 break;
6025 }
6026 case E_HVD_GDATA_DISP_FRM_INFO:
6027 {
6028 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
6029 break;
6030 }
6031 case E_HVD_GDATA_DEC_FRM_INFO:
6032 {
6033 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
6034 break;
6035 }
6036 case E_HVD_GDATA_ES_LEVEL:
6037 {
6038 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
6039 break;
6040 }
6041 #if HVD_ENABLE_MVC
6042 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
6043 {
6044 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
6045 break;
6046 }
6047 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
6048 {
6049 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
6050 break;
6051 }
6052 #endif
6053
6054 // user data
6055 case E_HVD_GDATA_USERDATA_WPTR:
6056 {
6057 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
6058 break;
6059 }
6060 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
6061 {
6062 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
6063 break;
6064 }
6065 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
6066 {
6067 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
6068 break;
6069 }
6070 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
6071 {
6072 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
6073 break;
6074 }
6075 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
6076 {
6077 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
6078 break;
6079 }
6080 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
6081 {
6082 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
6083 break;
6084 }
6085 // report - modes
6086 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
6087 {
6088 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
6089 break;
6090 }
6091 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
6092 {
6093 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
6094 break;
6095 }
6096 case E_HVD_GDATA_IS_ERR_CONCEAL:
6097 {
6098 u32Ret = pShm->ModeStatus.bIsErrConceal;
6099 break;
6100 }
6101 case E_HVD_GDATA_IS_SYNC_ON:
6102 {
6103 u32Ret = pShm->ModeStatus.bIsSyncOn;
6104 break;
6105 }
6106 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
6107 {
6108 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
6109 break;
6110 }
6111 case E_HVD_GDATA_SYNC_MODE:
6112 {
6113 u32Ret = pShm->ModeStatus.u8SyncType;
6114 break;
6115 }
6116 case E_HVD_GDATA_SKIP_MODE:
6117 {
6118 u32Ret = pShm->ModeStatus.u8SkipMode;
6119 break;
6120 }
6121 case E_HVD_GDATA_DROP_MODE:
6122 {
6123 u32Ret = pShm->ModeStatus.u8DropMode;
6124 break;
6125 }
6126 case E_HVD_GDATA_DISPLAY_DURATION:
6127 {
6128 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
6129 break;
6130 }
6131 case E_HVD_GDATA_FRC_MODE:
6132 {
6133 u32Ret = pShm->ModeStatus.u8FrcMode;
6134 break;
6135 }
6136 case E_HVD_GDATA_NEXT_PTS:
6137 {
6138 u32Ret = pShm->u32NextPTS;
6139 break;
6140 }
6141 case E_HVD_GDATA_DISP_Q_SIZE:
6142 {
6143 u32Ret = pShm->u16DispQSize;
6144 break;
6145 }
6146 case E_HVD_GDATA_DISP_Q_PTR:
6147 {
6148 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
6149 break;
6150 }
6151 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
6152 {
6153 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
6154 break;
6155 }
6156 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
6157 {
6158 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
6159 break;
6160 }
6161 case E_HVD_GDATA_REAL_FRAMERATE:
6162 {
6163 // return VPS/VUI timing info framerate, and 0 if timing info not exist
6164 u32Ret = pShm->u32RealFrameRate;
6165 break;
6166 }
6167 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
6168 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
6169 break;
6170 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
6171 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
6172 break;
6173 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
6174 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
6175 break;
6176 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
6177 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
6178 break;
6179 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
6180 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
6181 break;
6182 case E_HVD_GDATA_FW_STATUS_FLAG:
6183 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
6184 break;
6185
6186 // internal control
6187 case E_HVD_GDATA_IS_1ST_FRM_RDY:
6188 {
6189 u32Ret = pShm->bIs1stFrameRdy;
6190 break;
6191 }
6192 case E_HVD_GDATA_IS_I_FRM_FOUND:
6193 {
6194 u32Ret = pShm->bIsIFrmFound;
6195 break;
6196 }
6197 case E_HVD_GDATA_IS_SYNC_START:
6198 {
6199 u32Ret = pShm->bIsSyncStart;
6200 break;
6201 }
6202 case E_HVD_GDATA_IS_SYNC_REACH:
6203 {
6204 u32Ret = pShm->bIsSyncReach;
6205 break;
6206 }
6207 case E_HVD_GDATA_FW_VERSION_ID:
6208 {
6209 u32Ret = pShm->u32FWVersionID;
6210 break;
6211 }
6212 case E_HVD_GDATA_FW_IF_VERSION_ID:
6213 {
6214 u32Ret = pShm->u32FWIfVersionID;
6215 break;
6216 }
6217 case E_HVD_GDATA_BBU_Q_NUMB:
6218 {
6219 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
6220 break;
6221 }
6222 case E_HVD_GDATA_DEC_Q_NUMB:
6223 {
6224 u32Ret = pShm->u16DecQNumb;
6225 break;
6226 }
6227 case E_HVD_GDATA_DISP_Q_NUMB:
6228 {
6229 u32Ret = pShm->u16DispQNumb;
6230 break;
6231 }
6232 case E_HVD_GDATA_PTS_Q_NUMB:
6233 {
6234 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
6235 break;
6236 }
6237 case E_HVD_GDATA_FW_INIT_DONE:
6238 {
6239 u32Ret = pShm->bInitDone;
6240 break;
6241 }
6242 // debug
6243 case E_HVD_GDATA_SKIP_CNT:
6244 {
6245 u32Ret = pShm->u32SkipCnt;
6246 break;
6247 }
6248 case E_HVD_GDATA_GOP_CNT:
6249 {
6250 u32Ret = pShm->u32DropCnt;
6251 break;
6252 }
6253 case E_HVD_GDATA_DISP_CNT:
6254 {
6255 u32Ret = pShm->u32DispCnt;
6256 break;
6257 }
6258 case E_HVD_GDATA_DROP_CNT:
6259 {
6260 u32Ret = pShm->u32DropCnt;
6261 break;
6262 }
6263 case E_HVD_GDATA_DISP_STC:
6264 {
6265 u32Ret = pShm->u32DispSTC;
6266 break;
6267 }
6268 case E_HVD_GDATA_VSYNC_CNT:
6269 {
6270 u32Ret = pShm->u32VsyncCnt;
6271 break;
6272 }
6273 case E_HVD_GDATA_MAIN_LOOP_CNT:
6274 {
6275 u32Ret = pShm->u32MainLoopCnt;
6276 break;
6277 }
6278
6279 // AVC
6280 case E_HVD_GDATA_AVC_LEVEL_IDC:
6281 {
6282 u32Ret = pShm->u16AVC_SPS_LevelIDC;
6283 break;
6284 }
6285 case E_HVD_GDATA_AVC_LOW_DELAY:
6286 {
6287 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
6288 break;
6289 }
6290 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
6291 {
6292 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
6293 break;
6294 }
6295 case E_HVD_GDATA_FW_FLUSH_STATUS:
6296 {
6297 u32Ret = (MS_U32) (pShm->u8FlushStatus);
6298 break;
6299 }
6300 case E_HVD_GDATA_FW_CODEC_TYPE:
6301 {
6302 u32Ret = pShm->u32CodecType;
6303 break;
6304 }
6305 case E_HVD_GDATA_FW_ES_BUF_STATUS:
6306 {
6307 u32Ret = (MS_U32)pShm->u8ESBufStatus;
6308 break;
6309 }
6310 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
6311 {
6312 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
6313 {
6314 u32Ret = 1;
6315 }
6316 else
6317 {
6318 u32Ret = 0;
6319 }
6320 break;
6321 }
6322
6323 // SRAM
6324
6325 // Mailbox
6326 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
6327 {
6328 u32Ret = pShm->u32FwState;
6329 break;
6330 }
6331 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
6332 {
6333 u32Ret = pShm->bSpsChange;
6334 break;
6335 }
6336 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
6337 {
6338 u32Ret = pShm->bSpsChange;
6339
6340 if (pShm->bSpsChange &&
6341 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
6342 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
6343 {
6344 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
6345 }
6346
6347 break;
6348 }
6349 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
6350 {
6351 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6352
6353 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
6354 {
6355 u32Ret = pShm->u32FwInfo;
6356 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
6357 }
6358 break;
6359 }
6360 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
6361 {
6362 if (pShm->bIsTrigDisp) // not clear yet
6363 {
6364 u32Ret = FALSE;
6365 }
6366 else
6367 {
6368 u32Ret = TRUE;
6369 }
6370 break;
6371 }
6372 case E_HVD_GDATA_ES_READ_PTR:
6373 {
6374 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
6375 break;
6376 }
6377 case E_HVD_GDATA_ES_WRITE_PTR:
6378 {
6379 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
6380 break;
6381 }
6382 case E_HVD_GDATA_BBU_READ_PTR:
6383 {
6384 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
6385 break;
6386 }
6387 case E_HVD_GDATA_BBU_WRITE_PTR:
6388 {
6389 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6390 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6391 {
6392 u32Ret = pHVDHalContext->u32VP8BBUWptr;
6393 }
6394 else
6395 {
6396 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
6397 }
6398 break;
6399 }
6400 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
6401 {
6402 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6403
6404 u32Ret = pCtrl->u32BBUWptr_Fired;
6405
6406 break;
6407 }
6408 case E_HVD_GDATA_VPU_PC_CNT:
6409 {
6410 u32Ret = _HVD_EX_GetPC();
6411 break;
6412 }
6413 case E_HVD_GDATA_ES_QUANTITY:
6414 {
6415 u32Ret=_HVD_EX_GetESQuantity(u32Id);
6416 break;
6417 }
6418
6419
6420 // FW def
6421 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
6422 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
6423 break;
6424
6425 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
6426 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
6427 break;
6428 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
6429 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
6430 break;
6431 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
6432 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
6433 break;
6434 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
6435 u32Ret = MAX_PTS_TABLE_SIZE;
6436 break;
6437 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
6438 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
6439 break;
6440 case E_HVD_GDATA_FW_DS_BUF_ADDR:
6441 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
6442 break;
6443 case E_HVD_GDATA_FW_DS_BUF_SIZE:
6444 u32Ret = pShm->u32DSBuffSize; //3k or 6k
6445 break;
6446 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
6447 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
6448 break;
6449 case E_HVD_GDATA_FW_DS_INFO_ADDR:
6450 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
6451 break;
6452 case E_HVD_GDATA_FW_DS_IS_ENABLED:
6453 {
6454 if (pShm->bDSIsRunning)
6455 {
6456 u32Ret = TRUE;
6457 }
6458 else
6459 {
6460 u32Ret = FALSE;
6461 }
6462 break;
6463 }
6464 #if 0//(HVD_ENABLE_IQMEM)
6465 case E_HVD_GDATA_FW_IQMEM_CTRL:
6466 {
6467
6468 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
6469
6470 break;
6471 }
6472 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
6473 {
6474 if(pShm->bIsIQMEMSupport){
6475 u32Ret = TRUE;
6476 }
6477 else{
6478
6479 u32Ret = FALSE;
6480 }
6481
6482 break;
6483 }
6484 #endif
6485 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
6486 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
6487 break;
6488 case E_HVD_GDATA_FIELD_PIC_FLAG:
6489 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
6490 break;
6491 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
6492 u32Ret = pShm->u32SeamlessTSStatus;
6493 break;
6494 case E_HVD_GDATA_TS_SEAMLESS_TARGET_POC:
6495 u32Ret = pShm->u32SeamlessTargetPOC;
6496 break;
6497 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
6498 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
6499 break;
6500 #ifdef VDEC3
6501 case E_HVD_GDATA_FW_VBBU_ADDR:
6502 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
6503 break;
6504 #endif
6505 case E_HVD_GDATA_GET_NOT_SUPPORT_INFO:
6506 u32Ret = pShm->u32NotSupportInfo;
6507 break;
6508 case E_HVD_GDATA_GET_MIN_TSP_DATA_SIZE:
6509 u32Ret = pShm->u32CurMinTspDataSize;
6510 break;
6511 default:
6512 break;
6513 }
6514 return u32Ret;
6515 }
6516
HAL_HVD_EX_Get_DV_Support_Profiles(void)6517 MS_U32 HAL_HVD_EX_Get_DV_Support_Profiles(void)
6518 {
6519 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
6520 }
6521
HAL_HVD_EX_Get_DV_Support_Highest_Level(DV_Stream_Profile pDV_Stream_Profile)6522 DV_Stream_Level HAL_HVD_EX_Get_DV_Support_Highest_Level(DV_Stream_Profile pDV_Stream_Profile)
6523 {
6524 switch (pDV_Stream_Profile)
6525 {
6526 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
6527 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
6528
6529 #if 0// unsupported profile
6530 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
6531 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
6532 #endif
6533
6534 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
6535 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
6536
6537 #if 0// unsupported profile
6538 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
6539 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
6540 #endif
6541
6542 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
6543 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
6544
6545 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
6546 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
6547
6548 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
6549 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
6550
6551 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
6552 default:
6553 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
6554 }
6555 }
6556
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)6557 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
6558 {
6559 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
6560 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
6561 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6562
6563 _HAL_HVD_Entry();
6564
6565 // check if old SVD cmds
6566 if (u32Cmd < E_HVD_CMD_SVD_BASE)
6567 {
6568 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
6569
6570 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
6571 }
6572
6573 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
6574 {
6575 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
6576 }
6577
6578 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
6579 {
6580 if (u32Cmd == E_HVD_CMD_FLUSH)
6581 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
6582 }
6583
6584 if (u32Cmd == E_HVD_CMD_FLUSH &&
6585 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
6586 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
6587 {
6588 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
6589 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
6590 {
6591 _HAL_HVD_Release();
6592 HVD_Delay_ms(1);
6593 _HAL_HVD_Entry();
6594 }
6595 }
6596
6597 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
6598
6599 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
6600
6601 _HAL_HVD_Return(eRet);
6602 }
6603
HAL_HVD_EX_DeInit(MS_U32 u32Id)6604 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
6605 {
6606 HVD_Return eRet = E_HVD_RETURN_FAIL;
6607 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6608 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6609 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
6610 MS_U8 u8MiuSel;
6611 MS_U32 u32StartOffset;
6612 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6613 if(!pShm) {
6614 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
6615 return E_HVD_RETURN_FAIL;
6616 }
6617
6618 #if HVD_ENABLE_TIME_MEASURE
6619 MS_U32 ExitTimeCnt = 0;
6620 ExitTimeCnt = HVD_GetSysTime_ms();
6621 #endif
6622
6623 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
6624
6625 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
6626
6627 if (E_HVD_RETURN_SUCCESS != eRet)
6628 {
6629 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
6630 }
6631
6632 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
6633
6634 if (E_HVD_RETURN_SUCCESS != eRet)
6635 {
6636 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
6637 }
6638
6639 // check FW state to make sure it's STOP DONE
6640 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
6641 {
6642 if (HVD_GetSysTime_ms() > u32Timeout)
6643 {
6644 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
6645
6646 //return E_HVD_RETURN_TIMEOUT;
6647 eRet = E_HVD_RETURN_TIMEOUT;
6648 break;
6649 }
6650 }
6651
6652 if (pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt)
6653 {
6654 HVD_EX_MSG_INF("VDEC PLUS: DropRatio %d, Drop:0.%d (%d), Dec:0.%d (%d), Disp:0.%d\n",
6655 pShm->u8VdecPlusDropRatio,
6656 100*pShm->u32VdecPlusDropCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
6657 pShm->u32VdecPlusDropCnt,
6658 100*pShm->u32VdecPlusDecCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
6659 pShm->u32VdecPlusDecCnt,
6660 100*pShm->u32VdecPlusDispPicCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt));
6661 }
6662 else
6663 {
6664 HVD_EX_MSG_INF("VDEC PLUS DISABLE: DropRatio %d, Drop: %d, Dec: %d, Disp: %d\n",
6665 pShm->u8VdecPlusDropRatio,
6666 pShm->u32VdecPlusDropCnt,
6667 pShm->u32VdecPlusDecCnt,
6668 pShm->u32VdecPlusDispPicCnt);
6669 }
6670
6671 VPU_EX_FWCodeCfg fwCfg;
6672 VPU_EX_TaskInfo taskInfo;
6673 VPU_EX_NDecInitPara nDecInitPara;
6674
6675 nDecInitPara.pFWCodeCfg = &fwCfg;
6676 nDecInitPara.pTaskInfo = &taskInfo;
6677
6678 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
6679 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
6680
6681 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);//power control
6682 #if 0
6683 taskInfo.u32Id = u32Id;
6684 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
6685 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
6686 #endif
6687
6688 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6689 {
6690 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
6691 }
6692 else
6693 {
6694 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
6695 }
6696
6697 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
6698 {
6699 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
6700 }
6701
6702 /* clear es buffer */
6703 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
6704 {
6705 //HVD_PRINT("Clear ES buffer\n");
6706
6707 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
6708 }
6709
6710 //_HAL_HVD_MutexDelete();
6711
6712 #if HVD_ENABLE_TIME_MEASURE
6713 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
6714 #endif
6715
6716 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
6717 #ifndef VDEC3
6718 // reset bbu wptr
6719 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6720 {
6721 if(TRUE == HAL_VPU_EX_HVDInUsed())
6722 {
6723 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
6724 {
6725 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
6726 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
6727 }
6728 else
6729 {
6730 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
6731 {
6732 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
6733 }
6734 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
6735 }
6736 }
6737 else
6738 {
6739 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
6740 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
6741 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
6742 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6743 {
6744 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
6745 {
6746 _HVD_EX_ResetMainSubBBUWptr(u32Id);
6747 }
6748 }
6749 else
6750 {
6751 _HVD_EX_ResetMainSubBBUWptr(u32Id);
6752 }
6753 }
6754 }
6755 #endif
6756 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
6757
6758 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
6759 {
6760 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
6761 }
6762
6763 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
6764 {
6765
6766 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
6767
6768 _HAL_HVD_Entry();
6769 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
6770 _HAL_HVD_Release();
6771
6772 }
6773
6774 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
6775 HVD_EX_MSG_DBG("success\n");
6776
6777 return eRet;
6778 }
6779
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)6780 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
6781 {
6782 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
6783 MS_U32 u32Addr = 0;
6784 HVD_EX_Drv_Ctrl *pCtrl = NULL;
6785 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6786
6787 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6788
6789 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
6790 {
6791 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
6792
6793 if (E_HVD_RETURN_SUCCESS != eRet)
6794 {
6795 return eRet;
6796 }
6797 }
6798
6799 //HVD_PRINT(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
6800
6801 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
6802 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6803 {
6804 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
6805
6806 if (E_HVD_RETURN_SUCCESS != eRet)
6807 {
6808 return eRet;
6809 }
6810 }
6811
6812 u32Addr = pInfo->u32Staddr;
6813
6814 if (pInfo->bRVBrokenPacket)
6815 {
6816 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
6817 }
6818
6819 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
6820 {
6821 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
6822 }
6823 else
6824 {
6825 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
6826 }
6827
6828 if (E_HVD_RETURN_SUCCESS != eRet)
6829 {
6830 return eRet;
6831 }
6832
6833 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6834 {
6835 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
6836 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
6837
6838 if (E_HVD_RETURN_SUCCESS != eRet)
6839 {
6840 return eRet;
6841 }
6842 }
6843
6844 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
6845
6846 // do not add local pointer
6847 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
6848 {
6849 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
6850
6851 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
6852 (u32PacketStAddr <
6853 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
6854 {
6855 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
6856 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
6857 }
6858 else
6859 {
6860 //null packet
6861 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
6862 pCtrl->LastNal.u32NalSize = 0;
6863 }
6864 }
6865 else
6866 {
6867 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
6868 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
6869 }
6870
6871 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
6872 pCtrl->u32BBUPacketCnt++;
6873
6874 return eRet;
6875 }
6876
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)6877 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
6878 {
6879 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6880 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6881 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
6882 if(bCurrentStatus == bEnable)
6883 return;
6884
6885 if (bEnable)
6886 {
6887 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
6888 }
6889 else
6890 {
6891 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
6892 }
6893 }
6894
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)6895 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
6896 {
6897 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6898 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6899
6900 if (bEnable)
6901 {
6902 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
6903 }
6904 else
6905 {
6906 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
6907 }
6908 }
6909
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)6910 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
6911 {
6912 MS_U32 u32RB = 0;
6913 switch(eISRType)
6914 {
6915 case E_HWDEC_ISR_HVD:
6916 u32RB = REG_HVD_BASE;
6917 break;
6918 #if SUPPORT_EVD
6919 case E_HWDEC_ISR_EVD:
6920 u32RB = REG_EVD_BASE;
6921 break;
6922 #endif
6923 #if SUPPORT_G2VP9
6924 case E_HWDEC_ISR_G2VP9:
6925 break;
6926 #endif
6927 default:
6928 break;
6929 }
6930 if(u32RB)
6931 {
6932 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
6933 }
6934 }
6935
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)6936 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
6937 {
6938 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6939 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6940
6941 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
6942 }
6943
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)6944 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
6945 {
6946 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6947 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6948
6949 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
6950 {
6951 return FALSE;
6952 }
6953 else
6954 {
6955 return TRUE;
6956 }
6957 }
6958
HAL_HVD_EX_IsAlive(MS_U32 u32Id)6959 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
6960 {
6961 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6962
6963 if (pCtrl)
6964 {
6965 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
6966 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
6967 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
6968 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
6969 {
6970 return FALSE;
6971 }
6972 else
6973 {
6974 return TRUE;
6975 }
6976 }
6977 else
6978 {
6979 return FALSE;
6980 }
6981 }
6982
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)6983 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
6984 {
6985 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6986 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6987 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6988 if(!pShm) {
6989 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
6990 //return u32Data;
6991 }
6992
6993 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6994 {
6995 HAL_HVD_EX_ReadMemory();
6996
6997 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
6998 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
6999
7000 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
7001 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
7002 }
7003
7004 return TRUE;
7005 }
7006
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)7007 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
7008 {
7009 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7010 HVD_EX_Drv_Ctrl *pCtrl = NULL;
7011 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7012 MS_U32 u32Data;
7013 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7014 if(!pShm) {
7015 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
7016 return 0;
7017 }
7018
7019 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
7020
7021 HAL_HVD_EX_FlushMemory();
7022 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
7023 {
7024 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
7025 pCtrl->LastNal.u32NalAddr = u32Data;
7026 pCtrl->LastNal.u32NalSize = 0;
7027 }
7028
7029 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
7030 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
7031
7032 return TRUE;
7033 }
7034
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)7035 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
7036 {
7037 if (bEnable)
7038 {
7039 if (HAL_VPU_EX_IsEVDR2())
7040 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
7041 else
7042 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
7043 }
7044 else
7045 {
7046 #if defined (__aeon__)
7047 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
7048 #else // defined (__mips__)
7049 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
7050 #endif
7051 }
7052 }
7053
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)7054 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
7055 {
7056 return 0;
7057 }
7058
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)7059 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
7060 {
7061 return;
7062 }
7063
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)7064 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
7065 {
7066 //if( u16Clock == 0 )
7067 return 240; //140;
7068 //if( )
7069 }
7070
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)7071 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
7072 {
7073 //MS_BOOL bBitMIU1 = FALSE;
7074 //MS_BOOL bCodeMIU1 = FALSE;
7075 MS_U8 u8BitMiuSel = 0;
7076 MS_U8 u8CodeMiuSel = 0;
7077 MS_U32 u32BitStartOffset;
7078 MS_U32 u32CodeStartOffset;
7079 //MS_U8 u8MiuSel;
7080 //MS_U32 u32StartOffset;
7081 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7082 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7083 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7084 if(!pShm) {
7085 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
7086 return;
7087 }
7088
7089 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
7090
7091 #if HVD_ENABLE_MVC
7092 if(HAL_HVD_EX_CheckMVCID(u32Id))
7093 {
7094 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
7095 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
7096 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
7097 {
7098 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
7099 }
7100 }
7101 #endif /// HVD_ENABLE_MVC
7102
7103 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
7104 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
7105
7106
7107
7108
7109 if (u8BitMiuSel != u8CodeMiuSel)
7110 {
7111 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
7112 BDMA_Result bdmaRlt;
7113 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
7114
7115 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
7116 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
7117 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
7118
7119 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
7120
7121 if (E_BDMA_OK != bdmaRlt)
7122 {
7123 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
7124 }
7125 #else
7126 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
7127
7128 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
7129 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
7130 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
7131
7132 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
7133 #endif
7134 }
7135
7136 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
7137
7138 HAL_HVD_EX_FlushMemory();
7139
7140 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
7141 {
7142 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
7143 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
7144 }
7145 else
7146 {
7147 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
7148
7149 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
7150 }
7151 }
7152
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)7153 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
7154 {
7155 if (bEnable)
7156 {
7157 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
7158 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
7159 }
7160 else
7161 {
7162 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
7163 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
7164 }
7165 }
7166
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)7167 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
7168 {
7169 MS_U32 tmp1 = 0;
7170 MS_U32 tmp2 = 0;
7171 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7172 if(!pShm) {
7173 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
7174 return;
7175 }
7176
7177 HAL_HVD_EX_ReadMemory();
7178
7179 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
7180 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
7181
7182 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
7183 {
7184 MS_U32 u32Tmp = u32UartCtrl;
7185
7186 HVD_EX_MSG_DBG("\n");
7187 u32UartCtrl = 0; // turn off debug message to prevent other function prints
7188 HVD_PRINT("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
7189 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
7190
7191 HVD_PRINT("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
7192 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
7193 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
7194 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
7195
7196 HVD_PRINT("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
7197 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
7198 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
7199
7200 HVD_PRINT("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
7201 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
7202 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
7203 _HVD_EX_GetESLevel(u32Id));
7204
7205 HVD_PRINT("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
7206 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
7207 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
7208 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
7209 HVD_PRINT
7210 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
7211 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
7212 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
7213 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
7214 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
7215 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
7216 pShm->ModeStatus.bShowOneField);
7217
7218 u32UartCtrl = u32Tmp; // recover debug level
7219 }
7220 }
7221
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)7222 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
7223 {
7224 MS_U8 *u32Addr = NULL;
7225 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7226 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7227 if(!pShm) {
7228 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
7229 return;
7230 }
7231
7232 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
7233 {
7234 return;
7235 }
7236
7237 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
7238
7239 *u32NalSize = *(u32Addr + 2) & 0x1f;
7240 *u32NalSize <<= 8;
7241 *u32NalSize |= *(u32Addr + 1) & 0xff;
7242 *u32NalSize <<= 8;
7243 *u32NalSize |= *(u32Addr) & 0xff;
7244
7245 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
7246 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
7247 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
7248 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
7249 }
7250
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)7251 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
7252 {
7253 MS_U32 u32CurIdx = 0;
7254 MS_BOOL bFinished = FALSE;
7255 MS_U32 u32NalOffset = 0;
7256 MS_U32 u32NalSize = 0;
7257 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7258
7259 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
7260 {
7261 return;
7262 }
7263
7264 u32CurIdx = u32StartIdx;
7265
7266 do
7267 {
7268 if (u32CurIdx == u32EndIdx)
7269 {
7270 bFinished = TRUE;
7271 }
7272
7273 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
7274
7275 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
7276 {
7277 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
7278 }
7279
7280 u32CurIdx++;
7281
7282 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
7283 {
7284 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
7285 }
7286 } while (bFinished == TRUE);
7287 }
7288
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)7289 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
7290 {
7291 MS_U32 i = 0;
7292 MS_U32 value = 0;
7293
7294 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
7295 {
7296 HVD_EX_MSG_DBG("\n");
7297
7298 for (i = 0; i <= u32Num; i++)
7299 {
7300 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
7301 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
7302 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
7303
7304 if (value == 0)
7305 {
7306 break;
7307 }
7308
7309 HVD_PRINT(" %08x", value);
7310
7311 if (((i % 8) + 1) == 8)
7312 {
7313 HVD_PRINT(" |%u\n", i + 1);
7314 }
7315 }
7316
7317 HVD_PRINT("\nHVD Dump HW status End: total number:%u\n", i);
7318 }
7319 }
7320
HAL_HVD_EX_GetDVSupportProfiles(void)7321 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
7322 {
7323 #if 0 // wait avc finish DV dual job
7324 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
7325 #else
7326 return E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
7327 #endif
7328 }
7329
7330
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)7331 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
7332 {
7333 switch (u32DV_Stream_Profile)
7334 {
7335 #if 0 // wait avc finish DV dual job
7336 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
7337 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
7338 #endif
7339
7340 #if 0 // unsupported profile
7341 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
7342 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
7343 #endif
7344
7345 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
7346 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
7347
7348 #if 0 // unsupported profile
7349 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
7350 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
7351 #endif
7352
7353 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
7354 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
7355
7356 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
7357 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
7358
7359 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
7360 return E_DV_STREAM_LEVEL_ID_UHD48;// level 8
7361
7362 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
7363 default:
7364 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
7365 }
7366 }
7367
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)7368 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
7369 {
7370 if (pDrvCtrl)
7371 {
7372 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
7373 }
7374 }
7375
7376 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)7377 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
7378 {
7379 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
7380 }
7381
HAL_HVD_EX_GetView(MS_U32 u32Id)7382 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
7383 {
7384 if( (0xFF & (u32Id >> 8)) == 0x10)
7385 return E_VDEC_EX_MAIN_VIEW;
7386 else
7387 return E_VDEC_EX_SUB_VIEW;
7388 }
7389 #endif ///HVD_ENABLE_MVC
7390
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)7391 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
7392 {
7393 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
7394 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
7395 return;
7396 }
7397
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)7398 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
7399 {
7400 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
7401 return;
7402 }
7403
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)7404 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
7405 {
7406 MS_U64 _hw_max_pixel = 0;
7407 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
7408
7409 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
7410 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
7411 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
7412 }
7413
7414
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)7415 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
7416 {
7417 #if 1
7418 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7419 if(!pShm) {
7420 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
7421 return 0;
7422 }
7423
7424 MS_U16 u16QNum = pShm->u16DispQNumb;
7425 MS_U16 u16QPtr = pShm->u16DispQPtr;
7426 // MS_U16 u16QSize = pShm->u16DispQSize;
7427 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
7428 MS_U32 u32DispQNum = 0;
7429 #if HVD_ENABLE_MVC
7430 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
7431
7432 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7433 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
7434
7435 if(bMVC || bDolbyVision)
7436 {
7437 #if 0
7438 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
7439 {
7440 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
7441 }
7442 #endif
7443
7444 //HVD_PRINT("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
7445 //search the next frame to display
7446 while (u16QNum > 0)
7447 {
7448 //HVD_PRINT("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
7449 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
7450 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
7451
7452 //HVD_PRINT("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
7453 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
7454 {
7455 /// For MVC. Output views after the pair of (base and depend) views were decoded.
7456 /// Check the depned view was initial when Output the base view.
7457 if((u16QPtr%2) == 0)
7458 {
7459 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
7460 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
7461 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
7462 {
7463 ///HVD_PRINT("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
7464 ///HVD_PRINT("Return NULL.\n");
7465 continue;
7466 }
7467 }
7468 u32DispQNum++;
7469 }
7470
7471 u16QNum--;
7472 //go to next frame in the dispQ
7473 u16QPtr++;
7474
7475 if (u16QPtr >= pShm->u16DispQSize)
7476 {
7477 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
7478 }
7479 }
7480 }
7481 else
7482 #endif ///HVD_ENABLE_MVC
7483 {
7484 #if 0
7485 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
7486 {
7487 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
7488 }
7489 #endif
7490 // HVD_PRINT("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
7491 //search the next frame to display
7492 while (u16QNum != 0)
7493 {
7494 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
7495
7496 // HVD_PRINT("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
7497 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
7498 {
7499 u32DispQNum++;
7500 }
7501
7502 u16QNum--;
7503 //go to next frame in the dispQ
7504 u16QPtr++;
7505
7506 if (u16QPtr == pShm->u16DispQSize)
7507 {
7508 u16QPtr = 0; //wrap to the begin
7509 }
7510 }
7511 }
7512
7513 //HVD_PRINT("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
7514 return u32DispQNum;
7515 #else
7516 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
7517 return pShm->u16DispQNumb;
7518 #endif
7519 }
7520
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)7521 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
7522 {
7523 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7524 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
7525 (u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
7526 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
7527 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
7528 #if SUPPORT_G2VP9 && defined(VDEC3)
7529 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
7530 #else // Not using G2 VP9 implies using Mstar EVD VP9
7531 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
7532 #endif
7533 else
7534 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
7535 }
7536
7537 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)7538 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
7539 {
7540 #ifdef CONFIG_MSTAR_CLKM
7541 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD, bEnable);
7542 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_PPU, bEnable);
7543 #else
7544 if (bEnable)
7545 {
7546 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
7547 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
7548 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
7549 }
7550 else
7551 {
7552 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
7553 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
7554 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
7555 }
7556
7557 switch (pHVDHalContext->u32EVDClockType)
7558 {
7559 // 576, 532, 456, 480 can't use for decode(Ask for HW).
7560 case 576:
7561 {
7562 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
7563 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
7564 break;
7565 }
7566 case 532:
7567 {
7568 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
7569 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
7570 break;
7571 }
7572 case 456:
7573 {
7574 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
7575 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
7576 _HVD_WriteWordMask(REG_EVDPLL_LOOP_DIV_SECOND, REG_EVDPLL_LOOP_DIV_SECOND_456MHZ, REG_EVDPLL_LOOP_DIV_SECOND_MASK);
7577 }
7578 case 480:
7579 {
7580 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
7581 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
7582 break;
7583 }
7584 case 240:
7585 {
7586 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
7587 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
7588 break;
7589 }
7590 case 216:
7591 {
7592 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_216MHZ, TOP_CKG_EVD_PPU_MASK);
7593 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_216MHZ, TOP_CKG_EVD_MASK);
7594 break;
7595 }
7596 case 192:
7597 {
7598 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
7599 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
7600 break;
7601 }
7602 case 172:
7603 {
7604 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_172MHZ, TOP_CKG_EVD_PPU_MASK);
7605 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_172MHZ, TOP_CKG_EVD_MASK);
7606 break;
7607 }
7608 default:
7609 {
7610 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
7611 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
7612 break;
7613 }
7614 }
7615 #endif
7616 #ifdef CONFIG_MSTAR_SRAMPD
7617 if (bEnable)
7618 {
7619 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
7620 HVD_Delay_ms(1);
7621 }
7622 else
7623 {
7624 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
7625 HVD_Delay_ms(1);
7626 }
7627 #endif
7628 return;
7629 }
7630
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)7631 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
7632 {
7633 #ifndef VDEC3
7634 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
7635 #endif
7636 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7637
7638 #ifdef VDEC3
7639 if (0 == pCtrl->u32BBUId)
7640 #else
7641 if (0 == u8TaskId)
7642 #endif
7643 {
7644 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
7645 }
7646 #ifdef VDEC3
7647 else if (1 == pCtrl->u32BBUId)
7648 #else
7649 else if (1 == u8TaskId)
7650 #endif
7651 {
7652 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
7653 }
7654 #ifdef VDEC3
7655 else if (2 == pCtrl->u32BBUId)
7656 #else
7657 else if (2 == u8TaskId)
7658 #endif
7659 {
7660 _HVD_Write2Byte(EVD_BBU23_SETTING, (_HVD_Read2Byte(EVD_BBU23_SETTING) & ~REG_TSP2EVD_EN_BS3)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for bbu3-DTV mode
7661 }
7662 else
7663 {
7664 #ifdef VDEC3
7665 if (pCtrl->u32BBUId > 3)
7666 HVD_PRINT("Error bbu_id = %d , %s:%d\n",pCtrl->u32BBUId,__FUNCTION__,__LINE__);
7667 #else
7668 if (u8TaskId > 3)
7669 HVD_PRINT("Error u8TaskId = %d , %s:%d\n",u8TaskId,__FUNCTION__,__LINE__);
7670 #endif
7671 _HVD_Write2Byte(EVD_BBU23_SETTING, (_HVD_Read2Byte(EVD_BBU23_SETTING) & ~REG_TSP2EVD_EN_BS4)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for bbu4-DTV mode
7672 }
7673 return;
7674 }
7675
HAL_EVD_EX_DeinitHW(MS_U32 u32Id)7676 MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id)
7677 {
7678 MS_U16 u16Timeout = 1000;
7679 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7680 MS_BOOL isVP8Used = FALSE;
7681 MS_BOOL isAECUsed = FALSE;
7682 MS_BOOL isAVCUsed = FALSE;
7683 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
7684
7685 if(TRUE == HAL_VPU_EX_EVDInUsed())
7686 {
7687 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
7688 {
7689 HAL_AEC_PowerCtrl(FALSE);
7690 }
7691 return FALSE;
7692 }
7693 else if(!isAVCUsed)
7694 {
7695 _HVD_EX_SetMIUProtectMask(TRUE);
7696 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
7697
7698 while (u16Timeout)
7699 {
7700 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
7701 {
7702 break;
7703 }
7704 u16Timeout--;
7705 }
7706 #ifdef CONFIG_MSTAR_CLKM
7707 HAL_EVD_EX_PowerCtrl_CLKM(u32Id, FALSE);
7708 #else
7709 HAL_EVD_EX_PowerCtrl(u32Id, FALSE);
7710 #endif
7711
7712 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
7713 {
7714 HAL_AEC_PowerCtrl(FALSE);
7715 }
7716
7717 _HVD_EX_SetMIUProtectMask(FALSE);
7718 return TRUE;
7719 }
7720
7721 return FALSE;
7722 }
7723 #endif
7724
7725 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)7726 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
7727 {
7728 if (bEnable)
7729 {
7730 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
7731 }
7732 else
7733 {
7734 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
7735 }
7736
7737 switch (pHVDHalContext->u32VP9ClockType)
7738 {
7739 case 432:
7740 {
7741 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
7742 break;
7743 }
7744 case 384:
7745 {
7746 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
7747 break;
7748 }
7749 case 345:
7750 {
7751 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
7752 break;
7753 }
7754 case 320:
7755 {
7756 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
7757 break;
7758 }
7759 case 288:
7760 {
7761 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
7762 break;
7763 }
7764 case 240:
7765 {
7766 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
7767 break;
7768 }
7769 case 216:
7770 {
7771 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
7772 break;
7773 }
7774 case 172:
7775 {
7776 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
7777 break;
7778 }
7779 default:
7780 {
7781 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
7782 break;
7783 }
7784 }
7785
7786 return;
7787 }
7788
HAL_VP9_EX_DeinitHW(void)7789 MS_BOOL HAL_VP9_EX_DeinitHW(void)
7790 {
7791 MS_U16 u16Timeout = 1000;
7792
7793 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
7794
7795 while (u16Timeout)
7796 {
7797 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
7798 {
7799 break;
7800 }
7801 u16Timeout--;
7802 }
7803
7804 HAL_VP9_EX_PowerCtrl(FALSE);
7805
7806 return TRUE;
7807 }
7808 #endif
7809
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)7810 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
7811 {
7812 return TRUE;
7813 }
7814
HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)7815 void HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)
7816 {
7817 MS_VIRT u32StAddr = 0;
7818 MS_U8 u8BitMiuSel = 0;
7819 MS_U8 u8CodeMiuSel = 0;
7820 MS_U8 u8TmpMiuSel = 0;
7821 MS_U32 u32BitStartOffset;
7822 MS_U32 u32CodeStartOffset;
7823
7824 #ifndef VDEC3
7825 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
7826 #endif
7827 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7828 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
7829 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
7830 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
7831 if(!pShm) {
7832 HVD_PRINT("%s:%d pShm==NULL, return error!!!\n", __FUNCTION__, __LINE__);
7833 return;
7834 }
7835
7836 _HAL_HVD_Entry();
7837
7838 if (pCtrl == NULL)
7839 {
7840 _HAL_HVD_Return();
7841 }
7842
7843 MS_BOOL bNalTblAlreadySet = FALSE;
7844 VPU_EX_TaskInfo taskInfo;
7845 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
7846 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
7847
7848 bNalTblAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
7849
7850
7851
7852 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
7853 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
7854
7855 if (u8BitMiuSel != u8CodeMiuSel)
7856 {
7857 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
7858 }
7859 else
7860 {
7861 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
7862 }
7863
7864 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
7865 {
7866 #ifdef VDEC3
7867 if (!_HAL_EX_BBU_VP8_InUsed())
7868 #endif
7869 {
7870 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
7871
7872 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
7873 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
7874 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7875
7876 u32StAddr += VP8_BBU_TBL_SIZE;
7877
7878 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
7879 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
7880 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7881 }
7882
7883 _HAL_HVD_Return();
7884 }
7885
7886 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
7887
7888 #ifdef VDEC3
7889 if (!bNalTblAlreadySet)
7890 {
7891 _HVD_Write2Byte(_HVD_EX_Get_NAL_TBL_ST_ADDR_L(u32Id), (MS_U16) (u32StAddr >> 3));
7892 _HVD_Write2Byte(_HVD_EX_Get_NAL_TBL_ST_ADDR_H(u32Id), (MS_U16) (u32StAddr >> 19));
7893 // -1 is for NAL_TAB_LEN counts from zero.
7894 _HVD_Write2Byte(_HVD_EX_Get_NAL_TAB_LEN(u32Id), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7895 }
7896 #else
7897 if (0 == u8TaskId)
7898 {
7899 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
7900 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
7901 // -1 is for NAL_TAB_LEN counts from zero.
7902 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7903 }
7904 else
7905 {
7906 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
7907 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
7908 // -1 is for NAL_TAB_LEN counts from zero.
7909 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
7910 }
7911 #endif
7912
7913
7914 #if (HVD_ENABLE_MVC)
7915 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
7916 {
7917 /// Used sub stream to record sub view data.
7918 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
7919 //HVD_PRINT("**************** Buffer setting for MVC dual-BBU *************\n");
7920
7921 if (u8BitMiuSel != u8CodeMiuSel)
7922 {
7923 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
7924 }
7925 else
7926 {
7927 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
7928 }
7929
7930 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
7931 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
7932 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
7933 // -1 is for NAL_TAB_LEN counts from zero.
7934 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
7935 }
7936 #endif
7937
7938 if (!bNalTblAlreadySet)
7939 {
7940 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
7941 }
7942
7943 _HAL_HVD_Return();
7944 }
7945
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)7946 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
7947 {
7948 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
7949
7950 if(pCtrl->InitParams.u16ChipECONum == 0)
7951 return FALSE;
7952 else
7953 return TRUE;
7954 }
7955
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)7956 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
7957 {
7958
7959 }
7960
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)7961 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
7962 {
7963
7964 }
7965 #endif
7966