1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126 #define RV_VLC_TABLE_SIZE 0x20000
127 /* Add for Mobile Platform by Ted Sun */
128 //#define HVD_DISPQ_PREFETCH_COUNT 2
129 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
130 #define VPU_QMEM_BASE 0x20000000UL
131
132 //max support pixel(by chip capacity)
133 #define HVD_HW_MAX_PIXEL (3840*2160*31000ULL) // 4kx2k@30p
134 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
135 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
136
137 #if 0
138 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
139 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
140 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
141 static MS_U16 _u16DispQPtr = 0;
142 #endif
143
144 #define IS_TASK_ALIVE(id) ((id) != -1)
145 #ifndef UNUSED
146 #define UNUSED(x) (void)(x)
147 #endif
148
149
150 //---------------------------------- Mutex settings -----------------------------------------
151 #if HAL_HVD_ENABLE_MUTEX_PROTECT
152 #define _HAL_HVD_MutexCreate() \
153 do \
154 { \
155 if (s32HVDMutexID < 0) \
156 { \
157 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
158 } \
159 } while (0)
160
161 #define _HAL_HVD_MutexDelete() \
162 do \
163 { \
164 if (s32HVDMutexID >= 0) \
165 { \
166 OSAL_HVD_MutexDelete(s32HVDMutexID); \
167 s32HVDMutexID = -1; \
168 } \
169 } while (0)
170
171 #define _HAL_HVD_Entry() \
172 do \
173 { \
174 if (s32HVDMutexID >= 0) \
175 { \
176 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
177 { \
178 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
179 } \
180 } \
181 } while (0)
182
183 #define _HAL_HVD_Return(_ret_) \
184 do \
185 { \
186 if (s32HVDMutexID >= 0) \
187 { \
188 OSAL_HVD_MutexRelease(s32HVDMutexID); \
189 } \
190 return _ret_; \
191 } while(0)
192
193 #define _HAL_HVD_Release() \
194 do \
195 { \
196 if (s32HVDMutexID >= 0) \
197 { \
198 OSAL_HVD_MutexRelease(s32HVDMutexID); \
199 } \
200 } while (0)
201 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
202
203 #define _HAL_HVD_MutexCreate()
204 #define _HAL_HVD_MutexDelete()
205 #define _HAL_HVD_Entry()
206 #define _HAL_HVD_Return(_ret) {return _ret;}
207 #define _HAL_HVD_Release()
208
209 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
210
211 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
212 #define IS_TASK_ALIVE(id) ((id) != -1)
213 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
214
215 //------------------------------ MIU SETTINGS ----------------------------------
216 #define _MaskMiuReq_MVD_RW_0( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
217 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
218 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
222
223 #define _MaskMiu1Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
224 #define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
225 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
226 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
227 #define _MaskMiu1Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(3))
228 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(0))
229
230 #define _MaskMiu2Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU2_REG_RQ2_MASK, m, BIT(4))
231 #define _MaskMiu2Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(6))
232 #define _MaskMiu2Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ0_MASK+1, m, BIT(4))
233 #define _MaskMiu2Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(2))
234 #define _MaskMiu2Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(3))
235 #define _MaskMiu2Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(0))
236
237
238 #define HVD_MVD_RW_0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == 0))
239 #define HVD_MVD_RW_1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == 0))
240 #define HVD_MVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == 0))
241 #define HVD_HVD_RW_MIF0_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == 0))
242 #define HVD_HVD_RW_MIF1_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == 0))
243 #define HVD_HVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == 0))
244
245 #define HVD_MVD_RW_0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == BIT(4)) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == 0))
246 #define HVD_MVD_RW_1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == 0))
247 #define HVD_MVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12)) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == 0))
248 #define HVD_HVD_RW_MIF0_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == 0))
249 #define HVD_HVD_RW_MIF1_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == 0))
250 #define HVD_HVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == 0))
251
252 #define HVD_MVD_RW_0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL2) & BIT(4)) == BIT(4)))
253 #define HVD_MVD_RW_1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(6)) == BIT(6)))
254 #define HVD_MVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL0) & BIT(12)) == BIT(12)))
255 #define HVD_HVD_RW_MIF0_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(2)) == BIT(2)))
256 #define HVD_HVD_RW_MIF1_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(3)) == BIT(3)))
257 #define HVD_HVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(0)) == BIT(0)))
258
259
260 #if SUPPORT_EVD
261 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
262 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(7))
263 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
264 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(7))
265 #define _MaskMiu2Req_EVD_RW( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
266 #define _MaskMiu2Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU2_REG_RQ4_MASK, m, BIT(7))
267
268
269
270
271 #define HVD_EVD_RW_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
272 #define HVD_EVD_BBU_R_ON_MIU0 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
273 #define HVD_EVD_RW_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
274 #define HVD_EVD_BBU_R_ON_MIU1 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == BIT(7)) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == 0))
275 #define HVD_EVD_RW_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == BIT(7)))
276 #define HVD_EVD_BBU_R_ON_MIU2 (((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(7)) == 0) && ((_HVD_Read2Byte(MIU2_REG_SEL4) & BIT(7)) == BIT(7)))
277 #endif
278
279 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
280 do \
281 { \
282 if (HVD_##miu_clients##_ON_MIU0 == 1) \
283 { \
284 _MaskMiuReq_##miu_clients(mask); \
285 } \
286 else \
287 { \
288 if (HVD_##miu_clients##_ON_MIU1 == 1) \
289 { \
290 _MaskMiu1Req_##miu_clients(mask); \
291 } \
292 else if (HVD_##miu_clients##_ON_MIU2 == 1) \
293 { \
294 _MaskMiu2Req_##miu_clients(mask); \
295 } \
296 } \
297 } while (0)
298
299 // check RM is supported or not
300 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
301 #ifdef VDEC3
302 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
303 #else
304 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
305 #endif
306 //-------------------------------------------------------------------------------------------------
307 // Local Structures
308 //-------------------------------------------------------------------------------------------------
309
310 //-------------------------------------------------------------------------------------------------
311 // Local Functions Prototype
312 //-------------------------------------------------------------------------------------------------
313 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
314 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
315 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
316 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
317 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
318 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
319 static MS_U32 _HVD_EX_GetPC(void);
320 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
321 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
322 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
323 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
324 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
325 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
326 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
327 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
328 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
329 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
330 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
331 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
332 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
333 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
334 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
335 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
336 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
337 #if SUPPORT_EVD
338 static void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable);
339 static MS_BOOL HAL_EVD_EX_DeinitHW(void);
340 #endif
341 #if SUPPORT_G2VP9 && defined(VDEC3)
342 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
343 #endif
344 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
345 #if SUPPORT_G2VP9 && defined(VDEC3)
346 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
347 #endif
348 //-------------------------------------------------------------------------------------------------
349 // Global Variables
350 //-------------------------------------------------------------------------------------------------
351 #if defined (__aeon__)
352 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
353 #else
354 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
355 #endif
356 #if HAL_HVD_ENABLE_MUTEX_PROTECT
357 MS_S32 s32HVDMutexID = -1;
358 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
359 #endif
360
361
362 #define HVD_EX_STACK_SIZE 4096
363 //-------------------------------------------------------------------------------------------------
364 // Local Variables
365 //-------------------------------------------------------------------------------------------------
366 typedef struct
367 {
368
369 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
370 MS_U8 g_hvd_nal_fill_pair[2][8];
371 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
372 MS_U16 _u16DispQPtr;
373 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
374
375 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
376 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
377 MS_U32 u32VPUClockType;
378 MS_U32 u32HVDClockType;//160
379 #if SUPPORT_EVD
380 MS_U32 u32EVDClockType;
381 #endif
382 #if SUPPORT_G2VP9 && defined(VDEC3)
383 MS_U32 u32VP9ClockType;
384 #endif
385 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
386
387 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
388 MS_BOOL g_RstFlag;
389 MS_U64 u64pts_real;
390 MS_PHY u32VP8BBUWptr;
391 MS_PHY u32EVDBBUWptr;
392 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
393 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
394 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
395 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
396 //pre_set
397 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
398 } HVD_Hal_CTX;
399
400 HVD_Hal_CTX* pHVDHalContext = NULL;
401 HVD_Hal_CTX gHVDHalContext;
402 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
403
404 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
405 {
406 {FALSE},
407 {FALSE},
408 {FALSE},
409 #ifdef VDEC3
410 {FALSE},
411 #endif
412 };
413
414 //-------------------------------------------------------------------------------------------------
415 // Debug Functions
416 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)417 void HVD_EX_SetRstFlag(MS_BOOL bRst)
418 {
419 pHVDHalContext->g_RstFlag = bRst;
420 }
HVD_EX_GetRstFlag(void)421 MS_BOOL HVD_EX_GetRstFlag(void)
422 {
423 return pHVDHalContext->g_RstFlag;
424 }
425
426 //-------------------------------------------------------------------------------------------------
427 // Local Functions
428 //-------------------------------------------------------------------------------------------------
429
430 #ifdef VDEC3
431 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
432 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)433 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
434 {
435
436 MS_U32 ret = TRUE;
437 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
438
439 if(pCtrl == NULL || pstTaskInfo == NULL)
440 return FALSE;
441
442 pstTaskInfo->u32Id = u32Id;
443
444 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
445 {
446 case E_HVD_INIT_HW_RM:
447 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
448 break;
449 case E_HVD_INIT_HW_VP8:
450 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
451 break;
452 case E_HVD_INIT_HW_MVC:
453 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
454 break;
455 case E_HVD_INIT_HW_HEVC:
456 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
457 break;
458 #if SUPPORT_MSVP9
459 case E_HVD_INIT_HW_VP9:
460 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
461 break;
462 #endif
463 #if SUPPORT_G2VP9
464 case E_HVD_INIT_HW_VP9:
465 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
466 break;
467 #endif
468 default:
469 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
470 break;
471 }
472
473 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
474
475 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
476 {
477 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
478 }
479 else
480 {
481 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
482 }
483
484 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
485
486 #ifdef SUPPORT_EVD
487 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
488 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
489 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
490 #endif
491 return ret;
492
493 }
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)494 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
495 {
496 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
497 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
498 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
499 _HAL_HVD_Entry();
500
501 if(pCtrl == NULL)
502 _HAL_HVD_Return(ret);
503
504 VPU_EX_TaskInfo taskInfo;
505 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
506
507 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
508
509 taskInfo.u8HalId = u8Idx;
510 ret = HAL_VPU_EX_GetBBUId(u32Id,&taskInfo, pCtrl->bNStreamMode);
511
512 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
513 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
514
515 _HAL_HVD_Return(ret);
516 }
517
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)518 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
519 {
520 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
521 MS_BOOL ret = FALSE;
522 _HAL_HVD_Entry();
523
524 if(pCtrl == NULL)
525 _HAL_HVD_Return(ret);
526 VPU_EX_TaskInfo taskInfo;
527 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
528
529 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
530
531 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
532
533 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
534 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
535
536 _HAL_HVD_Return(ret);
537 }
538 #endif
539
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)540 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
541 {
542 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
543 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
544 pstHVDStream->s32HvdPpTaskId = -1;
545 }
546
_HVD_EX_Context_Init_HAL(void)547 static void _HVD_EX_Context_Init_HAL(void)
548 {
549 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
550 pHVDHalContext->u32VPUClockType = 432;
551 pHVDHalContext->u32HVDClockType = 384;
552 #if SUPPORT_EVD
553 pHVDHalContext->u32EVDClockType = 480;
554 #endif
555 #if SUPPORT_G2VP9 && defined(VDEC3)
556 pHVDHalContext->u32VP9ClockType = 384;
557 #endif
558 #ifdef VDEC3
559 MS_U8 i;
560
561 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
562 {
563 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
564 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
565 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
566 }
567 #else
568 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
569 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
570 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
571 #endif
572 }
573
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)574 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
575 {
576 MS_U16 u16Ret = 0;
577 #if (HVD_ENABLE_MVC || (!VDEC3))
578 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
579 #endif
580 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
581 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
582 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
583 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
584
585 #if HVD_ENABLE_MVC
586 if(HAL_HVD_EX_CheckMVCID(u32Id))
587 {
588 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
589 }
590 #endif /// HVD_ENABLE_MVC
591
592 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
593 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
594
595 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
596 {
597 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
598 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
599 }
600 else
601 #ifdef VDEC3
602 if (0 == pCtrl->u32BBUId)
603 #else
604 if (0 == u8TaskId)
605 #endif
606 {
607 //if(pCtrl->InitParams.bColocateBBUMode)
608 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
609 u16Ret = pShm->u32ColocateBBUReadPtr;
610 else
611 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
612 }
613 else
614 {
615 //if(pCtrl->InitParams.bColocateBBUMode)
616 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
617 u16Ret = pShm->u32ColocateBBUReadPtr;
618 else
619 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
620 }
621
622 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
623 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
624
625 return u16Ret;
626 }
627
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)628 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
629 {
630 MS_U16 u16Ret = 0;
631 #if (HVD_ENABLE_MVC || (!VDEC3))
632 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
633 #endif
634 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
635 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
636 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
637 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
638
639 #if HVD_ENABLE_MVC
640 if (HAL_HVD_EX_CheckMVCID(u32Id))
641 {
642 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
643 }
644 #endif /// HVD_ENABLE_MVC
645 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
646 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
647
648 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
649 {
650 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
651 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
652 }
653 else
654 #ifdef VDEC3
655 if (0 == pDrvCtrl->u32BBUId)
656 #else
657 if (0 == u8TaskId)
658 #endif
659 {
660 //if(pDrvCtrl->InitParams.bColocateBBUMode)
661 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
662 u16Ret = pShm->u32ColocateBBUWritePtr;
663 else
664 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
665 }
666 else
667 {
668 //if(pDrvCtrl->InitParams.bColocateBBUMode)
669 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
670 u16Ret = pShm->u32ColocateBBUWritePtr;
671 else
672 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
673 }
674
675 return u16Ret;
676 }
677
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)678 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
679 {
680 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
681 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
682
683 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
684 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
685 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
686 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
687 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
688 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
689 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
690 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
691 }
692
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)693 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
694 {
695 #if (HVD_ENABLE_MVC || (!VDEC3))
696 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
697 #endif
698 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
699 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
700 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
701 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
702
703 #if HVD_ENABLE_MVC
704 if (HAL_HVD_EX_CheckMVCID(u32Id))
705 {
706 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
707 }
708 #endif /// HVD_ENABLE_MVC
709
710 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
711 {
712 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
713 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
714 }
715 else
716 #ifdef VDEC3
717 if (0 == pCtrl->u32BBUId)
718 #else
719 if (0 == u8TaskId)
720 #endif
721 {
722 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
723 //if(pCtrl->InitParams.bColocateBBUMode)
724 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
725 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
726 }
727 else
728 {
729 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
730 //if(pCtrl->InitParams.bColocateBBUMode)
731 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
732 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
733 }
734
735 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
736 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
737
738 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
739 }
740
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)741 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
742 {
743 MS_BOOL bResult = TRUE;
744 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
745 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
746
747 switch (u8MBox)
748 {
749 case E_HVD_HI_0:
750 {
751 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
752 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
753 break;
754 }
755 case E_HVD_HI_1:
756 {
757 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
758 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
759 break;
760 }
761 case E_HVD_VPU_HI_0:
762 {
763 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
764 break;
765 }
766 case E_HVD_VPU_HI_1:
767 {
768 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
769 break;
770 }
771 default:
772 {
773 bResult = FALSE;
774 break;
775 }
776 }
777
778 return bResult;
779 }
780
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)781 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
782 {
783 MS_BOOL bResult = TRUE;
784 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
785 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
786
787 switch (u8MBox)
788 {
789 case E_HVD_HI_0:
790 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
791 break;
792 case E_HVD_HI_1:
793 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
794 break;
795 case E_HVD_RISC_0:
796 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
797 break;
798 case E_HVD_RISC_1:
799 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
800 break;
801 case E_HVD_VPU_HI_0:
802 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
803 break;
804 case E_HVD_VPU_HI_1:
805 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
806 break;
807 case E_HVD_VPU_RISC_0:
808 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
809 break;
810 case E_HVD_VPU_RISC_1:
811 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
812 break;
813 default:
814 break;
815 }
816
817 return bResult;
818 }
819
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)820 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
821 {
822 MS_BOOL bResult = TRUE;
823 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
824 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
825
826 switch (u8MBox)
827 {
828 case E_HVD_HI_0:
829 {
830 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
831 break;
832 }
833 case E_HVD_HI_1:
834 {
835 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
836 break;
837 }
838 case E_HVD_RISC_0:
839 {
840 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
841 break;
842 }
843 case E_HVD_RISC_1:
844 {
845 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
846 break;
847 }
848 case E_HVD_VPU_RISC_0:
849 {
850 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
851 break;
852 }
853 case E_HVD_VPU_RISC_1:
854 {
855 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
856 break;
857 }
858 default:
859 {
860 bResult = FALSE;
861 break;
862 }
863 }
864
865 return bResult;
866 }
867
868 #if 0
869 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
870 {
871 switch (u8MBox)
872 {
873 case E_HVD_RISC_0:
874 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
875 break;
876 case E_HVD_RISC_1:
877 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
878 break;
879 case E_HVD_VPU_RISC_0:
880 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
881 break;
882 case E_HVD_VPU_RISC_1:
883 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
884 break;
885 default:
886 break;
887 }
888 }
889 #endif
890
_HVD_EX_GetPC(void)891 static MS_U32 _HVD_EX_GetPC(void)
892 {
893 MS_U32 u32PC = 0;
894 u32PC = HAL_VPU_EX_GetProgCnt();
895 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
896 return u32PC;
897 }
898
_HVD_EX_GetESWritePtr(MS_U32 u32Id)899 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
900 {
901 MS_U32 u32Data = 0;
902 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
903 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
904
905 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
906 {
907 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
908
909 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
910 {
911 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
912
913 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
914 }
915 }
916 else
917 {
918 #if HVD_ENABLE_MVC
919 MS_U8 u8ViewIdx = 0;
920 if(HAL_HVD_EX_CheckMVCID(u32Id))
921 {
922 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
923 }
924 if(u8ViewIdx != 0) /// 2nd ES ptr.
925 {
926 u32Data = pShm->u32ES2WritePtr;
927 }
928 else
929 {
930 u32Data = pShm->u32ESWritePtr;
931 }
932 #else
933 u32Data = pShm->u32ESWritePtr;
934 #endif
935 }
936
937 return u32Data;
938 }
939
940 #define NAL_UNIT_LEN_BITS 21
941 #define NAL_UNIT_OFT_BITS 30
942 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
943 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
944 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
945
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)946 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
947 {
948 MS_U32 u32Data = 0;
949 MS_U8 u8TaskId = 0;
950 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
951 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
952 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
953 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
954 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
955
956 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
957 #if HVD_ENABLE_MVC
958 if(HAL_HVD_EX_CheckMVCID(u32Id))
959 {
960 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
961 }
962 #endif /// HVD_ENABLE_MVC
963
964 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
965 {
966 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
967 {
968 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
969 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
970 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
971 MS_U32 *u32Adr;
972 MS_U32 u32Tmp;
973
974 if (u16ReadPtr == u16WritePtr)
975 {
976 u32Data = _HVD_EX_GetESWritePtr(u32Id);
977 }
978 else
979 {
980 if (u16ReadPtr)
981 u16ReadPtr--;
982 else
983 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
984
985 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
986
987 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
988 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
989 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
990 u32Data = u32Data | u32Tmp;
991
992 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
993 //while(1);
994 }
995 goto EXIT;
996 }
997 // set reg_poll_nal_rptr 0
998 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
999 // set reg_poll_nal_rptr 1
1000 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
1001
1002 // read reg_nal_rptr_hi
1003 #ifdef VDEC3
1004 if (0 == pCtrl->u32BBUId)
1005 #else
1006 if (0 == u8TaskId)
1007 #endif
1008 {
1009 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
1010 u32Data >>= 6;
1011 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
1012 }
1013 else
1014 {
1015 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
1016 u32Data >>= 6;
1017 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
1018 }
1019
1020 u32Data <<= 3; // unit
1021
1022 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1023 {
1024 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1025
1026 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1027 {
1028 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1029 u32Data = u32ESWptr;
1030 }
1031 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1032 {
1033 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1034 u32Data = u32ESWptr;
1035 }
1036 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1037 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1038 {
1039 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1040 u32Data = u32ESWptr;
1041 }
1042 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1043 && ((u32Data - u32ESWptr) < 32)
1044 && (pCtrl->u32FlushRstPtr == 1))
1045 {
1046 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1047 u32Data = u32ESWptr;
1048 }
1049 }
1050
1051 // remove illegal pointer
1052 #if 1
1053 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1054 {
1055 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1056
1057 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1058 (u32PacketStaddr <
1059 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1060 {
1061 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1062 u32Data = pCtrl->u32LastESRptr;
1063 }
1064 }
1065 #endif
1066 }
1067 else
1068 {
1069 #if HVD_ENABLE_MVC
1070 MS_U8 u8ViewIdx = 0;
1071 if(HAL_HVD_EX_CheckMVCID(u32Id))
1072 {
1073 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1074 }
1075 if(u8ViewIdx != 0) /// 2nd ES ptr.
1076 {
1077 u32Data = pShm->u32ES2ReadPtr;
1078 }
1079 else
1080 {
1081 u32Data = pShm->u32ESReadPtr;
1082 }
1083 #else
1084 u32Data = pShm->u32ESReadPtr;
1085 #endif
1086 }
1087
1088 EXIT:
1089
1090 pCtrl->u32LastESRptr = u32Data;
1091
1092 return u32Data;
1093 }
1094
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1095 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1096 {
1097 MS_U16 u16TimeOut = 0xFFFF;
1098 MS_BOOL bResult = FALSE;
1099
1100 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
1101
1102 while (--u16TimeOut)
1103 {
1104 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1105 {
1106 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1107 break;
1108 }
1109 }
1110
1111 return bResult;
1112 }
1113
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1114 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1115 {
1116 MS_U16 u16TimeOut = 0xFFFF;
1117 MS_BOOL bResult = FALSE;
1118 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1119
1120 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
1121
1122 #if HVD_ENABLE_MVC
1123 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1124 {
1125 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1126 }
1127 #endif /// HVD_ENABLE_MVC
1128
1129 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1130
1131 while (--u16TimeOut)
1132 {
1133 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1134 {
1135 u32Cmd |= (u8TaskId << 24);
1136 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1137 break;
1138 }
1139 }
1140 return bResult;
1141 }
1142
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)1143 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
1144 {
1145 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1146 #ifdef VDEC3
1147 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1148 MS_BOOL IsSent = FALSE;
1149 MS_BOOL IsMailBox = FALSE;
1150 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1151
1152 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
1153 {
1154 do {
1155 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1156 if (!SentRet)
1157 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1158 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1159 break;
1160 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1161 IsSent = TRUE;
1162 break;
1163 }
1164 else if (HVD_GetSysTime_ms() > u32timeout)
1165 {
1166 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1167 break;
1168 }
1169 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1170 }
1171 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
1172 {
1173 do {
1174 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1175 if (!SentRet)
1176 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1177 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1178 break;
1179 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1180 IsSent = TRUE;
1181 break;
1182 }
1183 else if (HVD_GetSysTime_ms() > u32timeout)
1184 {
1185 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1186 break;
1187 }
1188 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1189 }
1190 if (!IsSent) {
1191 IsMailBox = TRUE;
1192 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1193 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1194 #else
1195 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1196 #endif
1197 {
1198 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1199 if (HVD_GetSysTime_ms() > u32timeout)
1200 {
1201 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1202 return E_HVD_RETURN_TIMEOUT;
1203 }
1204 #endif
1205
1206 #if 0
1207 if (u32Cmd == E_HVD_CMD_STOP)
1208 {
1209 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1210 #if HVD_ENABLE_MVC
1211 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1212 {
1213 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1214 }
1215 #endif /// HVD_ENABLE_MVC
1216 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1217
1218 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1219 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1220
1221 return E_HVD_RETURN_SUCCESS;
1222 }
1223 #endif
1224
1225 if(u32Cmd < E_DUAL_CMD_BASE)
1226 {
1227 //_HVD_EX_GetPC();
1228 HAL_HVD_EX_Dump_FW_Status(u32Id);
1229 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1230 }
1231 }
1232
1233 #ifdef VDEC3
1234 }
1235 IsSent = FALSE;
1236 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1237 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
1238 {
1239 do {
1240 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1241 if (!SentRet)
1242 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1243 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1244 break;
1245 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1246 IsSent = TRUE;
1247 break;
1248 }
1249 else if (HVD_GetSysTime_ms() > u32timeout)
1250 {
1251 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1252 break;
1253 }
1254 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1255 }
1256 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
1257 {
1258 do {
1259 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1260 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1261 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1262 }
1263 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1264 break;
1265 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1266 IsSent = TRUE;
1267 break;
1268 }
1269 else if (HVD_GetSysTime_ms() > u32timeout)
1270 {
1271 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1272 break;
1273 }
1274 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1275 }
1276 if (!IsSent)
1277 {
1278 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1279 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1280 #else
1281 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1282
1283 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1284 #endif
1285 {
1286 #ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1287 if (HVD_GetSysTime_ms() > u32timeout)
1288 {
1289 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
1290 return E_HVD_RETURN_TIMEOUT;
1291 }
1292 #endif
1293 if(u32Cmd < E_DUAL_CMD_BASE)
1294 {
1295 //_HVD_EX_GetPC();
1296 HAL_HVD_EX_Dump_FW_Status(u32Id);
1297 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1298 }
1299 }
1300 #ifdef VDEC3
1301 }
1302 else
1303 {
1304 HAL_HVD_EX_FlushMemory();
1305 }
1306 #endif
1307 return E_HVD_RETURN_SUCCESS;
1308 }
1309
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)1310 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
1311 {
1312 #if HAL_HVD_ENABLE_MIU_PROTECT
1313 _HVD_MIU_SetReqMask(MVD_RW_0, bEnable);
1314 _HVD_MIU_SetReqMask(MVD_RW_1, bEnable);
1315 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1316 #if SUPPORT_EVD
1317 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
1318 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1319 #endif
1320 _HVD_MIU_SetReqMask(HVD_RW_MIF0, bEnable);
1321 _HVD_MIU_SetReqMask(HVD_RW_MIF1, bEnable);
1322 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1323 HAL_VPU_EX_MIU_RW_Protect(bEnable);
1324 //HVD_Delay_ms(1);
1325 #endif
1326 return;
1327 }
1328
1329 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)1330 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
1331 {
1332 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1333
1334 if (u32CodecType == E_HVD_INIT_HW_HEVC
1335 #if SUPPORT_MSVP9
1336 || u32CodecType == E_HVD_INIT_HW_VP9
1337 #endif
1338 )
1339 return TRUE;
1340
1341 return FALSE;
1342 }
1343
_HAL_EX_IS_HVD(MS_U32 u32ModeFlag)1344 static MS_BOOL _HAL_EX_IS_HVD(MS_U32 u32ModeFlag) // VP8 isn't included
1345 {
1346 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
1347
1348 if ((u32CodecType == E_HVD_INIT_HW_MVC) ||
1349 (u32CodecType == E_HVD_INIT_HW_AVC) ||
1350 (u32CodecType == E_HVD_INIT_HW_AVS) ||
1351 (u32CodecType == E_HVD_INIT_HW_RM))
1352 return TRUE;
1353
1354 return FALSE;
1355 }
1356
_HAL_EX_BBU_EVD_InUsed(void)1357 static MS_BOOL _HAL_EX_BBU_EVD_InUsed(void)
1358 {
1359 if (!pHVDHalContext)
1360 return FALSE;
1361
1362 MS_U32 i;
1363 MS_BOOL bRet = FALSE;
1364
1365 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1366 {
1367 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1368 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_HEVC)
1369 #if SUPPORT_MSVP9
1370 ||(pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP9)
1371 #endif
1372 ))
1373 {
1374 bRet = TRUE;
1375 break;
1376 }
1377 }
1378
1379 return bRet;
1380 }
1381
_HAL_EX_BBU_HVD_InUsed(void)1382 static MS_BOOL _HAL_EX_BBU_HVD_InUsed(void) // VP8 isn't included
1383 {
1384 if (!pHVDHalContext)
1385 return FALSE;
1386
1387 MS_U32 i;
1388 MS_BOOL bRet = FALSE;
1389
1390 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1391 {
1392 if (pHVDHalContext->_stHVDStream[i].bUsed &&
1393 ((pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVC) ||
1394 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_AVS) ||
1395 (pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_RM)))
1396 {
1397 bRet = TRUE;
1398 break;
1399 }
1400 }
1401
1402 return bRet;
1403 }
1404
_HAL_EX_BBU_VP8_InUsed(void)1405 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
1406 {
1407 if (!pHVDHalContext)
1408 return FALSE;
1409
1410 MS_U32 i;
1411 MS_BOOL bRet = FALSE;
1412
1413 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
1414 {
1415 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
1416 {
1417 bRet = TRUE;
1418 break;
1419 }
1420 }
1421
1422 return bRet;
1423 }
1424
1425 #endif
1426
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1427 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1428 {
1429 MS_U16 u16Reg = 0;
1430 MS_VIRT u32StAddr = 0;
1431 #ifdef VDEC3
1432 MS_U32 u32Length = 0;
1433 #endif
1434 //MS_BOOL bBitMIU1 = FALSE;
1435 //MS_BOOL bCodeMIU1 = FALSE;
1436 MS_U8 u8BitMiuSel = 0;
1437 MS_U8 u8CodeMiuSel = 0;
1438 MS_U8 u8FBMiuSel = 0;
1439 MS_U32 u32BitStartOffset;
1440 MS_U32 u32CodeStartOffset;
1441 MS_U32 u32FBStartOffset;
1442
1443 MS_U8 u8TaskId = 0;
1444 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1445 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1446 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1447 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1448
1449 // MS_U32 u32TmpStartOffset;
1450 MS_U8 u8TmpMiuSel;
1451
1452
1453
1454 if(pCtrl == NULL) return;
1455
1456 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1457 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1458 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1459
1460 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1461 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1462 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1463 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1464 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1465 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1466 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1467 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1468 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1469 (u8FBMiuSel << VDEC_PPIN_MIUSEL));
1470
1471 if (u8BitMiuSel != u8CodeMiuSel)
1472 {
1473 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
1474 }
1475 else
1476 {
1477 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
1478 }
1479
1480 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1481 {
1482 #ifdef VDEC3
1483 if (!_HAL_EX_BBU_VP8_InUsed())
1484 #endif
1485 {
1486 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1487
1488 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
1489 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
1490 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1491
1492 u32StAddr += 0x2000;
1493
1494 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
1495 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
1496 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1497 }
1498
1499 // ES buffer
1500 #ifdef VDEC3
1501 if(pCtrl->bNStreamMode)
1502 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1503 else
1504 #endif
1505 u32StAddr = u32BitStartOffset;
1506
1507 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1508
1509 #ifdef VDEC3
1510 if (!_HAL_EX_BBU_VP8_InUsed())
1511 #endif
1512 {
1513 HVD_EX_MSG_ERR("ESB start addr=%lx\n", (unsigned long)u32StAddr);
1514
1515 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1516 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1517
1518 #ifdef VDEC3
1519 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1520 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1521 #else
1522 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1523 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1524 #endif
1525
1526 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1527 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1528 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1529 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1530 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1531 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1532 }
1533
1534 return;
1535 }
1536
1537 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1538
1539 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
1540
1541 #ifdef VDEC3
1542 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1543 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1544 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1545 {
1546 if (pCtrl->u32BBUId == 0)
1547 {
1548 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1549 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1550 // -1 is for NAL_TAB_LEN counts from zero.
1551 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1552 }
1553 else
1554 {
1555 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1556 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1557 // -1 is for NAL_TAB_LEN counts from zero.
1558 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1559 }
1560 }
1561 #else
1562 if (0 == u8TaskId)
1563 {
1564 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
1565 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
1566 // -1 is for NAL_TAB_LEN counts from zero.
1567 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1568 }
1569 else
1570 {
1571 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
1572 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
1573 // -1 is for NAL_TAB_LEN counts from zero.
1574 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
1575 }
1576 #endif
1577
1578 // ES buffer
1579 #ifdef VDEC3
1580 if(!pCtrl->bNStreamMode || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1581 {
1582 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1583 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1584 }
1585 else
1586 {
1587 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1588 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1589 }
1590 #else
1591 u32StAddr = u32BitStartOffset;
1592 #endif
1593
1594 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1595
1596 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1597
1598 #ifdef VDEC3
1599 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1600 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1601 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1602 {
1603 if (pCtrl->u32BBUId == 0)
1604 {
1605 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1606 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1607
1608 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1609 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1610 }
1611 else
1612 {
1613 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1614 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1615
1616 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1617 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1618 }
1619 }
1620 #else
1621 if (0 == u8TaskId)
1622 {
1623 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1624 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1625
1626 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1627 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1628 }
1629 else
1630 {
1631 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1632 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1633
1634 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1635 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1636 }
1637 #endif
1638
1639 // others
1640 #ifdef VDEC3
1641 if (!pCtrl->bNStreamMode || ((_HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_EVD_InUsed()) ||
1642 (_HAL_EX_IS_HVD(pCtrl->InitParams.u32ModeFlag) && !_HAL_EX_BBU_HVD_InUsed()) ||
1643 (E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))))
1644 {
1645 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1646
1647 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1648 {
1649 if (pCtrl->u32BBUId == 0)
1650 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1651 else
1652 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1653 }
1654 else
1655 {
1656 if (pCtrl->u32BBUId == 0)
1657 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1658 else
1659 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1660 }
1661
1662 if (pCtrl->u32BBUId == 0)
1663 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1664 else
1665 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1666
1667 if (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // RM
1668 {
1669 if (pCtrl->u32BBUId == 0) // force BBU to remove nothing, RM only
1670 u16Reg |= HVD_REG_BBU_PASER_DISABLE;
1671 else
1672 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2;
1673 }
1674 #if SUPPORT_MSVP9
1675 else if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1676 {
1677 if (pCtrl->u32BBUId == 0)
1678 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03;
1679 else
1680 u16Reg &= ~HVD_REG_BBU_PASER_ENABLE_03_BS2;
1681 }
1682 #endif
1683 else // AVS or AVC or HEVC
1684 {
1685 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1686 {
1687 if (pCtrl->u32BBUId == 0)
1688 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1689 else
1690 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1691 }
1692 else // start code remained
1693 {
1694 if (pCtrl->u32BBUId == 0)
1695 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1696 else
1697 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1698 }
1699 }
1700
1701 if (pCtrl->u32BBUId == 0)
1702 {
1703 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1704 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1705 }
1706 else
1707 {
1708 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1709 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1710 }
1711 }
1712 #else
1713 if (0 == u8TaskId)
1714 {
1715 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1716
1717 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1718 {
1719 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1720 }
1721 else
1722 {
1723 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1724 }
1725
1726 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1727
1728 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1729 {
1730 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1731 }
1732 else // AVS or AVC
1733 {
1734 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1735 {
1736 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1737 }
1738 else // start code remained
1739 {
1740 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1741 }
1742 }
1743
1744 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1745
1746 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1747 }
1748 else
1749 {
1750 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1751
1752 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1753 {
1754 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1755 }
1756 else
1757 {
1758 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1759 }
1760
1761 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1762
1763 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1764 {
1765 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1766 }
1767 else // AVS or AVC
1768 {
1769 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1770 {
1771 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1772 }
1773 else // start code remained
1774 {
1775 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1776 }
1777 }
1778
1779 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1780
1781 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1782 }
1783 #endif
1784
1785 #if (HVD_ENABLE_MVC)
1786 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1787 {
1788 /// Used sub stream to record sub view data.
1789 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1790 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1791
1792 if (u8BitMiuSel != u8CodeMiuSel)
1793 {
1794 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
1795 }
1796 else
1797 {
1798 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
1799 }
1800
1801
1802 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
1803 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
1804 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
1805 // -1 is for NAL_TAB_LEN counts from zero.
1806 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
1807
1808 // ES buffer
1809 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1810
1811 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1812 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1813 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1814
1815 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1816 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1817
1818 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1819 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1820 {
1821 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1822 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1823 }
1824 else
1825 {
1826 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1827 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1828 }
1829 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1830 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1831 {
1832 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1833 }
1834 else // AVS or AVC
1835 {
1836 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1837 {
1838 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1839 }
1840 else // start code remained
1841 {
1842 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1843 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1844 }
1845 }
1846 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1847 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1848 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1849 }
1850 #endif
1851
1852 // MIF offset
1853 #if 0
1854 {
1855 MS_U16 offaddr = 0;
1856 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1857 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1858 {
1859 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1860 }
1861 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1862 offaddr = (MS_U16) ((u32StAddr) >> 20);
1863 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1864 //0x1FF; // 9 bits(L + H)
1865 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1866 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1867 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1868 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1869 {
1870 u16Reg |= HVD_REG_MIF_OFFSET_H;
1871 }
1872 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1873 }
1874 #endif
1875 }
1876
1877 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1878 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1879 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1880 {
1881 MS_U16 u16Reg = 0;
1882 MS_U32 u32StAddr = 0;
1883 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1884 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1885 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1886
1887 if(pCtrl == NULL) return;
1888
1889 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1890 {
1891 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1892
1893 // ES buffer
1894 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1895
1896 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1897 {
1898 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1899 }
1900
1901 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1902 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1903
1904 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1905 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1906
1907 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1908 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1909 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1910 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1911 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1912 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1913
1914 return;
1915 }
1916
1917 // ES buffer
1918 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1919
1920 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1921 {
1922 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1923 }
1924
1925 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1926
1927 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1928 {
1929 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1930 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1931
1932 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1933 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1934 }
1935 else
1936 {
1937 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1938 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1939
1940 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1941 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1942 }
1943 }
1944 #endif
1945
_HVD_EX_GetESLevel(MS_U32 u32Id)1946 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1947 {
1948 MS_U32 u32Wptr = 0;
1949 MS_U32 u32Rptr = 0;
1950 MS_U32 u32CurMBX = 0;
1951 MS_U32 u32ESsize = 0;
1952 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1953 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1954
1955 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1956 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1957 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1958
1959 if (u32Rptr >= u32Wptr)
1960 {
1961 u32CurMBX = u32Rptr - u32Wptr;
1962 }
1963 else
1964 {
1965 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1966 }
1967
1968 if (u32CurMBX == 0)
1969 {
1970 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1971 }
1972 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1973 {
1974 u32Ret = E_HVD_ESB_LEVEL_OVER;
1975 }
1976 else
1977 {
1978 u32CurMBX = u32ESsize - u32CurMBX;
1979 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1980 {
1981 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1982 }
1983 }
1984
1985 return u32Ret;
1986 }
1987
_HVD_EX_GetESQuantity(MS_U32 u32Id)1988 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1989 {
1990 MS_U32 u32Wptr = 0;
1991 MS_U32 u32Rptr = 0;
1992 MS_U32 u32ESsize = 0;
1993 MS_U32 u32Ret = 0;
1994 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1995
1996 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1997 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1998 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1999
2000
2001 if(u32Wptr >= u32Rptr)
2002 {
2003 u32Ret = u32Wptr - u32Rptr;
2004 }
2005 else
2006 {
2007 u32Ret = u32ESsize - u32Rptr + u32Wptr;
2008 }
2009 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
2010 return u32Ret;
2011 }
2012
2013 #if (HVD_ENABLE_IQMEM)
HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)2014 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
2015 {
2016
2017 MS_U32 u32Timeout = 20000;
2018
2019 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
2020 {
2021
2022 HAL_VPU_EX_IQMemSetDAMode(TRUE);
2023
2024 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
2025
2026
2027 while (u32Timeout)
2028 {
2029
2030 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
2031 {
2032 break;
2033 }
2034 u32Timeout--;
2035 HVD_Delay_ms(1);
2036 }
2037
2038 HAL_VPU_EX_IQMemSetDAMode(FALSE);
2039
2040 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
2041
2042 if (u32Timeout==0)
2043 {
2044 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
2045 return FALSE;
2046 }
2047
2048
2049 }
2050 return TRUE;
2051 }
2052
2053 #endif
2054
2055 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)2056 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
2057 #else
2058 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
2059 #endif
2060 {
2061 MS_U32 u32FirmVer = 0;
2062 MS_U32 u32Timeout = 20000;
2063 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2064
2065 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
2066
2067 #if HVD_ENABLE_TIME_MEASURE
2068 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2069 #endif
2070
2071 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
2072
2073 VPU_EX_FWCodeCfg fwCfg;
2074 VPU_EX_TaskInfo taskInfo;
2075 VPU_EX_VLCTblCfg vlcCfg;
2076 #ifdef VDEC3
2077 VPU_EX_FBCfg fbCfg;
2078 #endif
2079 VPU_EX_NDecInitPara nDecInitPara;
2080
2081 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
2082 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
2083 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
2084 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
2085 #ifdef VDEC3_FB
2086 nDecInitPara.pVLCCfg = NULL;
2087 #else
2088 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2089 {
2090 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
2091 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2092 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2093 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
2094 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
2095 nDecInitPara.pVLCCfg = &vlcCfg;
2096 }
2097 #endif
2098 nDecInitPara.pFWCodeCfg = &fwCfg;
2099 nDecInitPara.pTaskInfo = &taskInfo;
2100 #ifdef VDEC3
2101 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
2102 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
2103
2104 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
2105 {
2106 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
2107 }
2108
2109 nDecInitPara.pFBCfg = &fbCfg;
2110 #endif
2111
2112 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
2113 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
2114 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
2115 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
2116 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
2117
2118 taskInfo.u32Id = u32Id;
2119
2120 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
2121 {
2122 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
2123 }
2124 #ifdef VDEC3
2125 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
2126 {
2127 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2128 }
2129 #if SUPPORT_MSVP9
2130 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2131 {
2132 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
2133 }
2134 #endif
2135 #if SUPPORT_G2VP9
2136 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
2137 {
2138 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
2139 }
2140 #endif
2141 #endif
2142 else
2143 {
2144 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
2145 }
2146
2147 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
2148
2149 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
2150 {
2151 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
2152 }
2153 else
2154 {
2155 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
2156 }
2157 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
2158
2159 #ifdef SUPPORT_EVD
2160 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2161 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2162 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2163 #endif
2164
2165 if(TRUE == HVD_EX_GetRstFlag())
2166 {
2167 //Delete task for Rst
2168 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2169 {
2170 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2171 }
2172 HVD_EX_SetRstFlag(FALSE);
2173 }
2174
2175 #if (HVD_ENABLE_IQMEM)
2176 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2177 #endif
2178
2179 #ifdef VDEC3
2180 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2181 #else
2182 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2183 #endif
2184 {
2185 HVD_EX_MSG_ERR("Task create fail!\n");
2186
2187 return FALSE;
2188 }
2189
2190 while (u32Timeout)
2191 {
2192 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2193
2194 if (u32FirmVer != 0)
2195 {
2196 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2197 break;
2198 }
2199 u32Timeout--;
2200 HVD_Delay_ms(1);
2201 }
2202
2203 #ifdef VDEC3_FB
2204 #if HVD_ENABLE_RV_FEATURE
2205 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2206
2207 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2208 {
2209 if(pShm->u32RM_VLCTableAddr == 0) {
2210 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2211 }
2212 else
2213 {
2214 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2215 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2216 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2217 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2218 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2219 nDecInitPara.pVLCCfg = &vlcCfg;
2220 }
2221 }
2222
2223 if (nDecInitPara.pVLCCfg)
2224 {
2225 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2226 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2227 {
2228 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2229 return FALSE;
2230 }
2231 }
2232 #endif
2233 #endif
2234 if (u32Timeout > 0)
2235 {
2236 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2237
2238 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2239
2240 #ifdef VDEC3
2241 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2242 {
2243 case E_HVD_INIT_HW_AVC:
2244 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2245 break;
2246 case E_HVD_INIT_HW_AVS:
2247 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2248 break;
2249 case E_HVD_INIT_HW_RM:
2250 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2251 break;
2252 case E_HVD_INIT_HW_MVC:
2253 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2254 break;
2255 case E_HVD_INIT_HW_VP8:
2256 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2257 break;
2258 case E_HVD_INIT_HW_MJPEG:
2259 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2260 break;
2261 case E_HVD_INIT_HW_VP6:
2262 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2263 break;
2264 case E_HVD_INIT_HW_HEVC:
2265 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2266 break;
2267 case E_HVD_INIT_HW_VP9:
2268 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2269 break;
2270 default:
2271 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2272 break;
2273 }
2274 #endif
2275
2276 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2277 }
2278 else
2279 {
2280 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2281 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2282
2283 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2284 {
2285 HVD_EX_MSG_ERR("Task delete fail!\n");
2286 }
2287
2288 return FALSE;
2289 }
2290
2291
2292
2293 #if (HVD_ENABLE_IQMEM)
2294
2295 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
2296 {
2297
2298 HAL_HVD_EX_IQMem_Init(u32Id);
2299 }
2300 else{
2301 HVD_EX_MSG_DBG("not support IQMEM\n");
2302 }
2303 #endif
2304
2305
2306
2307
2308
2309
2310 #if HVD_ENABLE_TIME_MEASURE
2311 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2312 #endif
2313
2314 return TRUE;
2315 }
2316
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2317 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2318 {
2319 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2320 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2321 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2322 {
2323 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2324 }
2325 else
2326 {
2327 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2328 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2329 }
2330 }
2331
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2332 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2333 {
2334 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2335 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2336
2337 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2338 {
2339 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2340 }
2341 else
2342 {
2343 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2344 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2345 }
2346 }
2347
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2348 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2349 {
2350 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2351 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2352
2353 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2354 {
2355 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2356 {
2357 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2358 }
2359 }
2360 else
2361 {
2362 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2363 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2364 }
2365 }
2366
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2367 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2368 {
2369 MS_VIRT u32PTSWptr = HVD_U32_MAX;
2370 MS_VIRT u32PTSRptr = HVD_U32_MAX;
2371 MS_VIRT u32DestAddr = 0;
2372 HVD_PTS_Entry PTSEntry;
2373 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2374 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2375 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2376
2377 // update R & W ptr
2378 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2379
2380 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
2381
2382 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2383 {
2384 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
2385 (MS_U32) MAX_PTS_TABLE_SIZE);
2386 return E_HVD_RETURN_FAIL;
2387 }
2388
2389 // check queue is full or not
2390 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2391 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2392
2393 if (u32PTSWptr == u32PTSRptr)
2394 {
2395 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
2396 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2397 return E_HVD_RETURN_FAIL;
2398 }
2399
2400 // add one PTS entry
2401 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2402 PTSEntry.u32ID_L = pInfo->u32ID_L;
2403 PTSEntry.u32ID_H = pInfo->u32ID_H;
2404 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2405
2406 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2407
2408 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
2409
2410 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2411
2412 HAL_HVD_EX_FlushMemory();
2413
2414 // update Write ptr
2415 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2416
2417 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2418
2419 return E_HVD_RETURN_SUCCESS;
2420 }
2421
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2422 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2423 {
2424 //---------------------------------------------------
2425 // item format in nal table:
2426 // reserved |borken| u32NalOffset | u32NalLen
2427 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2428 //---------------------------------------------------
2429 MS_VIRT u32Adr = 0;
2430 MS_U32 u32BBUNewWptr = 0;
2431 MS_U8 item[8];
2432 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2433 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2434 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2435 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2436
2437 #if HVD_ENABLE_MVC
2438 if(HAL_HVD_EX_CheckMVCID(u32Id))
2439 {
2440 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2441 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2442 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2443 {
2444 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2445 }
2446 }
2447 #endif /// HVD_ENABLE_MVC
2448
2449 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2450 {
2451 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
2452 }
2453 else
2454 {
2455 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2456 }
2457 u32BBUNewWptr++;
2458 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
2459
2460 // prepare nal entry
2461
2462 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2463 {
2464 // NAL len 22 bits , HEVC level5 constrain
2465 item[0] = u32NalLen & 0xff;
2466 item[1] = (u32NalLen >> 8) & 0xff;
2467 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2468 item[3] = (u32NalOffset >> 2) & 0xff;
2469 item[4] = (u32NalOffset >> 10) & 0xff;
2470 item[5] = (u32NalOffset >> 18) & 0xff;
2471 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2472 item[7] = 0;
2473 }
2474 else
2475 {
2476 item[0] = u32NalLen & 0xff;
2477 item[1] = (u32NalLen >> 8) & 0xff;
2478 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2479 item[3] = (u32NalOffset >> 3) & 0xff;
2480 item[4] = (u32NalOffset >> 11) & 0xff;
2481 item[5] = (u32NalOffset >> 19) & 0xff;
2482 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2483 item[7] = 0;
2484 }
2485
2486 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2487 {
2488 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
2489 }
2490 else
2491 {
2492 // add nal entry
2493 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2494 }
2495
2496 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2497
2498 HAL_HVD_EX_FlushMemory();
2499
2500 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2501
2502 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2503 {
2504 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
2505 }
2506 else
2507 {
2508 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2509 }
2510
2511 return E_HVD_RETURN_SUCCESS;
2512 }
2513
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2514 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2515 {
2516 MS_U8 item[8];
2517 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2518 MS_VIRT u32Adr = 0;
2519 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2520 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2521 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2522
2523 /*
2524 printf("nal2 offset=0x%x, len=0x%x\n",
2525 u32NalOffset2, u32NalLen2);
2526 */
2527
2528 item[0] = u32NalLen2 & 0xff;
2529 item[1] = (u32NalLen2 >> 8) & 0xff;
2530 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2531 item[3] = (u32NalOffset2 >> 3) & 0xff;
2532 item[4] = (u32NalOffset2 >> 11) & 0xff;
2533 item[5] = (u32NalOffset2 >> 19) & 0xff;
2534 item[6] = (u32NalOffset2 >> 27) & 0x07;
2535 item[7] = 0;
2536
2537 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2538 {
2539 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
2540 }
2541 else
2542 {
2543 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2544 }
2545
2546 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2547
2548 HAL_HVD_EX_FlushMemory();
2549
2550 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2551 }
2552
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2553 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2554 {
2555 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2556 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2557
2558 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2559 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
2560 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
2561 {
2562 MS_U16 i;
2563 MS_PHY u32VUIAddr;
2564 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
2565
2566 HAL_HVD_EX_ReadMemory();
2567 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2568
2569 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2570 {
2571 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2572 {
2573 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2574 }
2575 else
2576 {
2577 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2578 }
2579 pData++;
2580 }
2581 }
2582 else
2583 {
2584 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2585 }
2586
2587 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
2588 }
2589
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2590 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2591 {
2592 MS_U32 u32ReadPtr = 0;
2593 MS_U32 eRet = 0;
2594 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2595 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2596
2597 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2598 MS_U32 u32WritePtr = 0;
2599
2600 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2601 {
2602 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
2603 }
2604 else
2605 {
2606 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2607 }
2608
2609 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
2610
2611 if (u32WritePtr >= u32ReadPtr)
2612 {
2613 eRet = u32WritePtr - u32ReadPtr;
2614 }
2615 else
2616 {
2617 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2618 }
2619
2620 #if 0
2621 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2622 {
2623 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2624 }
2625 else
2626 {
2627 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2628 }
2629
2630 #endif
2631 return eRet;
2632 }
2633
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2634 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2635 {
2636 MS_U32 u32ReadPtr = 0;
2637 MS_U32 eRet = 0;
2638 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2639
2640 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2641
2642 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2643 {
2644 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
2645 (MS_U32) MAX_PTS_TABLE_SIZE);
2646 return 0;
2647 }
2648
2649 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2650
2651 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2652 {
2653 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2654 }
2655 else
2656 {
2657 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2658 }
2659
2660 return eRet;
2661 }
2662
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)2663 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
2664 {
2665 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2666
2667 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
2668 }
2669
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2670 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2671 {
2672 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2673 MS_U16 u16QNum = pShm->u16DispQNumb;
2674 MS_U16 u16QPtr = pShm->u16DispQPtr;
2675 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2676
2677 #if (HVD_ENABLE_MVC)
2678 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2679
2680 if (bMVC)
2681 {
2682 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2683 {
2684 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
2685 MS_U16 u16UsedFrm = 0;
2686
2687 if (u16RealQPtr != u16QPtr)
2688 {
2689 if (u16RealQPtr > u16QPtr)
2690 {
2691 u16UsedFrm = u16RealQPtr - u16QPtr;
2692 }
2693 else
2694 {
2695 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2696 }
2697 }
2698
2699 if (u16QNum > u16UsedFrm)
2700 {
2701 volatile HVD_Frm_Information *pHvdFrm;
2702
2703 u16QNum -= u16UsedFrm;
2704 u16QPtr = u16RealQPtr;
2705 pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2706
2707 if ((u16QPtr%2) == 0) //For MVC mode, we must check the pair of display entry is ready or not
2708 {
2709 volatile HVD_Frm_Information *pHvdFrmNext = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr+1];
2710
2711 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2712 {
2713 return NULL;
2714 }
2715 }
2716
2717 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2718 {
2719 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2720 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2721
2722 if ((u16QPtr%2) == 0)
2723 {
2724 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2725 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2726 }
2727 else
2728 {
2729 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2730 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
2731 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2732 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2733 }
2734
2735 u16QPtr++;
2736 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2737 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2738
2739 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2740 }
2741 }
2742
2743 return NULL;
2744 }
2745
2746 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2747 //search the next frame to display
2748 while (u16QNum > 0)
2749 {
2750 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2751 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2752 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2753
2754 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2755 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2756 {
2757 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2758 /// Check the depned view was initial when Output the base view.
2759 if((u16QPtr%2) == 0)
2760 {
2761 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2762 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2763 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2764 {
2765 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2766 ///printf("Return NULL.\n");
2767 return NULL;
2768 }
2769 }
2770
2771 //printf("V:%d.\n",u16QPtr);
2772 pHVDHalContext->_u16DispQPtr = u16QPtr;
2773 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2774 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2775 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2776 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2777 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2778 }
2779
2780 u16QNum--;
2781 //go to next frame in the dispQ
2782 u16QPtr++;
2783
2784 if (u16QPtr >= pShm->u16DispQSize)
2785 {
2786 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2787 }
2788 }
2789 }
2790 else
2791 #endif ///HVD_ENABLE_MVC
2792 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
2793 if (_HVD_EX_IsHevcInterlaceField(u32Id))
2794 {
2795 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
2796 volatile HVD_Frm_Information *pHvdFrm_first = NULL;
2797
2798 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
2799 return NULL;
2800 }
2801
2802 while (u16QNum != 0)
2803 {
2804 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2805 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2806 {
2807 if (!first_field) // second get frame, we will check at least one paired in disp queue.
2808 {
2809 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2810 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2811 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
2812
2813 if(pHvdFrm->u8FieldType == EVD_TOP_FIELD || pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
2814 pHvdFrm->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
2815 else
2816 pHvdFrm->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
2817 return pHvdFrm;
2818 }
2819 else // first get frame, we will check at least one paired in disp queue.
2820 {
2821 if (pHvdFrm_first == NULL)
2822 {
2823 pHvdFrm_first = pHvdFrm;
2824 }
2825 else
2826 {
2827 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2828 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
2829
2830 //After flush, we cannot get the correct field type of first field from sei, so we use second field type to decide first field type.
2831 if (pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 0xff)
2832 {
2833 if (pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV)
2834 pHvdFrm_first->u8FieldType = EVD_BOTTOM_WITH_NEXT;
2835 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_PREV)
2836 pHvdFrm_first->u8FieldType = EVD_TOP_WITH_NEXT;
2837 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_PREV)
2838 pHvdFrm_first->u8FieldType = EVD_TOP_WITH_NEXT;
2839 else if (pHvdFrm->u8FieldType == EVD_TOP_FIELD)
2840 pHvdFrm_first->u8FieldType = EVD_BOTTOM_FIELD;
2841 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_FIELD)
2842 pHvdFrm_first->u8FieldType = EVD_TOP_FIELD;
2843 else
2844 {
2845 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2846 return NULL;
2847 }
2848 if ((pHvdFrm_first->u32ID_L >> 16) & 0x1)
2849 pHvdFrm_first->u32ID_L |= (1 << 16);
2850 else
2851 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2852 }
2853 else if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV)
2854 {
2855 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV && pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_NEXT)
2856 {
2857 pHvdFrm_first->u32ID_L |= (1 << 16);
2858 pHvdFrm->u32ID_L |= (1 << 16);
2859 }
2860 else if (pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV && pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
2861 {
2862 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2863 pHvdFrm->u32ID_L &= (~(1 << 16));
2864 }
2865 else
2866 {
2867 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2868 return NULL;
2869 }
2870 }
2871 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
2872 if (pHvdFrm_first->u8FieldType == EVD_TOP_FIELD || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_NEXT)
2873 pHvdFrm_first->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
2874 else
2875 pHvdFrm_first->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
2876 return pHvdFrm_first;
2877 }
2878 }
2879 }
2880 u16QNum--;
2881 //go to next frame in the dispQ
2882 u16QPtr++;
2883
2884 if (u16QPtr == pShm->u16DispQSize)
2885 {
2886 u16QPtr = 0; //wrap to the begin
2887 }
2888
2889 }
2890 return NULL;
2891 }
2892 else
2893 {
2894 volatile HVD_Frm_Information *pHvdFrm = (volatile HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2895
2896 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2897 {
2898
2899 while (u16QNum != 0)
2900 {
2901 pHvdFrm = (volatile HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
2902
2903 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2904 {
2905 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2906 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2907 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2908 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2909 }
2910 u16QNum--;
2911 //go to next frame in the dispQ
2912 u16QPtr++;
2913
2914 if (u16QPtr == pShm->u16DispQSize)
2915 {
2916 u16QPtr = 0; //wrap to the begin
2917 }
2918 }
2919
2920 return NULL;
2921 }
2922
2923 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2924 //search the next frame to display
2925 while (u16QNum != 0)
2926 {
2927 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2928
2929 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2930 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2931 {
2932 pHVDHalContext->_u16DispQPtr = u16QPtr;
2933 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2934 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2935 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2936 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2937 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2938 }
2939
2940 u16QNum--;
2941 //go to next frame in the dispQ
2942 u16QPtr++;
2943
2944 if (u16QPtr == pShm->u16DispQSize)
2945 {
2946 u16QPtr = 0; //wrap to the begin
2947 }
2948 }
2949 }
2950
2951 return NULL;
2952 }
2953
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2954 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2955 {
2956 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2957 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2958 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2959 {
2960 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2961 if(pVsyncBridgeExt != NULL)
2962 {
2963 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
2964 }
2965 }
2966 return pFrmInfoExt;
2967 }
2968
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)2969 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
2970 {
2971 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2972 MS_U64 u64Ret = 0;
2973 #if SUPPORT_EVD
2974 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2975 #if SUPPORT_MSVP9
2976 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2977 #endif
2978 #endif
2979
2980 #if SUPPORT_EVD
2981 if (isEVD)
2982 {
2983 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
2984 }
2985 else
2986 #endif
2987 #if SUPPORT_G2VP9
2988 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2989 {
2990 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
2991 }
2992 else
2993 #endif
2994 {
2995 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
2996 }
2997
2998 return u64Ret;
2999 }
3000
3001 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)3002 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
3003 {
3004 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3005 MS_U16 u16QNum = pShm->u16DispQNumb;
3006 MS_U16 u16QPtr = pShm->u16DispQPtr;
3007 static volatile HVD_Frm_Information *pHvdFrm = NULL;
3008 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3009 MS_BOOL bMVC = FALSE;
3010 #if HVD_ENABLE_MVC
3011 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
3012 #endif
3013
3014
3015 if (bMVC || _HVD_EX_IsHevcInterlaceField(u32Id))
3016 {
3017 if (u16QNum == 1) return TRUE;
3018 }
3019
3020 while (u16QNum != 0)
3021 {
3022 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
3023 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
3024 {
3025 return FALSE;
3026 }
3027 u16QNum--;
3028 u16QPtr++;
3029 if (u16QPtr == pShm->u16DispQSize)
3030 {
3031 u16QPtr = 0; //wrap to the begin
3032 }
3033 }
3034
3035 return TRUE;
3036 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)3037 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
3038 {
3039 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3040
3041 return &(_pHVDCtrls[u8DrvId]);
3042 }
3043
_HVD_EX_GetStreamIdx(MS_U32 u32Id)3044 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
3045 {
3046 MS_U8 u8OffsetIdx = 0;
3047 MS_U8 u8SidBaseMask = 0xF0;
3048 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
3049
3050 switch (eSidBase)
3051 {
3052 case E_HAL_HVD_MAIN_STREAM_BASE:
3053 {
3054 u8OffsetIdx = 0;
3055 break;
3056 }
3057 case E_HAL_VPU_SUB_STREAM_BASE:
3058 {
3059 u8OffsetIdx = 1;
3060 break;
3061 }
3062 case E_HAL_VPU_MVC_STREAM_BASE:
3063 {
3064 u8OffsetIdx = 0;
3065 break;
3066 }
3067 #ifdef VDEC3
3068 case E_HAL_VPU_N_STREAM_BASE:
3069 {
3070 u8OffsetIdx = (u32Id>>8) & 0xF;
3071 break;
3072 }
3073 #endif
3074 default:
3075 {
3076 u8OffsetIdx = 0;
3077 break;
3078 }
3079 }
3080
3081 return u8OffsetIdx;
3082 }
3083 /*
3084 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
3085 {
3086 MS_U32 i = 0;
3087 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
3088 {
3089 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
3090 {
3091 return TRUE;
3092 }
3093 }
3094 return FALSE;
3095 }
3096 */
3097
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)3098 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
3099 {
3100 MS_PHY u32PhyAddr = 0x0;
3101 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3102
3103 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3104 {
3105 return 0;
3106 }
3107
3108 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3109
3110 if (u32PhyAddr == 0xFFFFFFFF) //boris
3111 {
3112 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3113 }
3114 else
3115 {
3116 #if defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3117 //u32PhyAddr += 0; // if define HVD_OLD_LAYOUT_SHARE_MEM_BIAS under SUPPORT_NEW_MEM_LAYOUT, then we could refine the codes here
3118 #else
3119 u32PhyAddr += HVD_OLD_LAYOUT_SHARE_MEM_BIAS;
3120 #endif
3121 }
3122
3123 return MsOS_PA2KSEG1(u32PhyAddr);
3124 }
3125
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3126 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3127 {
3128 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3129 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3130
3131 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3132 {
3133 return 0;
3134 }
3135
3136 MS_PHY u32PhyAddr = 0x0;
3137 #if 0
3138 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3139
3140 if (u32PhyAddr == 0xFFFFFFFF)
3141 {
3142 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3143 }
3144 #endif
3145 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3146 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3147
3148 return MsOS_PA2KSEG1(u32PhyAddr);
3149 }
3150
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3151 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3152 {
3153
3154 if (u8MiuSel == E_CHIP_MIU_0)
3155 {
3156 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3157 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3158 }
3159 else if (u8MiuSel == E_CHIP_MIU_1)
3160 {
3161 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3162 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, 0, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3163 }
3164 else // 2
3165 {
3166 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3167 _HVD_WriteWordMask(MIU2_CLIENT_SELECT_GP4, MIU2_CLIENT_SELECT_GP4_HVD_MIF1, MIU2_CLIENT_SELECT_GP4_HVD_MIF1);
3168 }
3169
3170 }
3171
3172 #if SUPPORT_G2VP9 && defined(VDEC3)
3173 #ifdef __ARM_NEON__
3174 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3175 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3176 {
3177 uint32x4x4_t data, data2;
3178 MS_U8* raster2 = raster + tile_w * 4;
3179
3180 data = vld4q_u32((const uint32_t *)tile);
3181 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3182
3183 vst1q_u32((uint32_t *)raster, data.val[0]);
3184 raster += stride;
3185 vst1q_u32((uint32_t *)raster, data.val[1]);
3186 raster += stride;
3187 vst1q_u32((uint32_t *)raster, data.val[2]);
3188 raster += stride;
3189 vst1q_u32((uint32_t *)raster, data.val[3]);
3190
3191
3192 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3193 raster2 += stride;
3194 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3195 raster2 += stride;
3196 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3197 raster2 += stride;
3198 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3199 }
3200 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3201 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3202 {
3203 MS_U8* tile0 = tile;
3204 MS_U8* tile1 = tile+16;
3205 MS_U8* tile2 = tile+32;
3206 MS_U8* tile3 = tile+48;
3207 int i;
3208
3209 for (i=0; i<4; i++) {
3210 raster[i] = tile0[i];
3211 raster[4+i] = tile1[i];
3212 raster[8+i] = tile2[i];
3213 raster[12+i] = tile3[i];
3214 }
3215
3216 for (i=0; i<4; i++) {
3217 raster[stride+i] = tile0[4+i];
3218 raster[stride+4+i] = tile1[4+i];
3219 raster[stride+8+i] = tile2[4+i];
3220 raster[stride+12+i] = tile3[4+i];
3221 }
3222
3223 for (i=0; i<4; i++) {
3224 raster[2*stride+i] = tile0[8+i];
3225 raster[2*stride+4+i] = tile1[8+i];
3226 raster[2*stride+8+i] = tile2[8+i];
3227 raster[2*stride+12+i] = tile3[8+i];
3228 }
3229
3230 for (i=0; i<4; i++) {
3231 raster[3*stride+i] = tile0[12+i];
3232 raster[3*stride+4+i] = tile1[12+i];
3233 raster[3*stride+8+i] = tile2[12+i];
3234 raster[3*stride+12+i] = tile3[12+i];
3235 }
3236 }
3237 #endif // #ifdef __ARM_NEON__
3238
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)3239 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
3240 {
3241 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
3242 u32Id,
3243 E_TASK_PRI_MEDIUM,
3244 TRUE,
3245 NULL,
3246 32, // stack size..
3247 "HVD_PostProcess_task");
3248
3249 if (s32HvdPpTaskId < 0)
3250 {
3251 HVD_EX_MSG_ERR("Pp Task create failed\n");
3252
3253 return FALSE;
3254 }
3255
3256 HVD_EX_MSG_DBG("Pp Task create success\n");
3257 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
3258
3259 return TRUE;
3260 }
3261
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3262 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3263 {
3264 return y * stride * h + x * w * h;
3265 }
3266
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3267 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3268 {
3269 return y * stride * h + x * w;
3270 }
3271
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3272 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3273 {
3274 raster[0] = tile[0];
3275 raster[1] = tile[1];
3276 raster[2] = tile[2];
3277 raster[3] = tile[3];
3278 raster[stride] = tile[4];
3279 raster[stride + 1] = tile[5];
3280 raster[stride + 2] = tile[6];
3281 raster[stride + 3] = tile[7];
3282 raster[2 * stride] = tile[8];
3283 raster[2 * stride + 1] = tile[9];
3284 raster[2 * stride + 2] = tile[10];
3285 raster[2 * stride + 3] = tile[11];
3286 raster[3 * stride] = tile[12];
3287 raster[3 * stride + 1] = tile[13];
3288 raster[3 * stride + 2] = tile[14];
3289 raster[3 * stride + 3] = tile[15];
3290 }
3291
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3292 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3293 {
3294 const MS_U32 tile_w = 4;
3295 const MS_U32 tile_h = 4;
3296 MS_U32 tile_stride = w;
3297 MS_U32 x, y;
3298 MS_U8 *dst1, *dst2;
3299 MS_U8 *src1, *src2;
3300
3301 #ifdef __ARM_NEON__
3302 // To overlap load and store, handle two blocks at the same time.
3303 dst1 = dst;
3304 src1 = src;
3305 for (y = 0; y < h / tile_h; y++)
3306 {
3307 dst2 = dst1;
3308 src2 = src1;
3309 for (x = 0; x <= (w/tile_w - 8); x+=8)
3310 {
3311 tile4x4_to_raster_8(
3312 dst2,
3313 src2,
3314 raster_stride, tile_w, tile_h);
3315 dst2 += tile_w * 8;
3316 src2 += tile_w * tile_h * 8;
3317 }
3318 dst1 += raster_stride * tile_h;
3319 src1 += tile_stride * tile_h;
3320 for (; x < w / tile_w; x++)
3321 {
3322 tile4x4_to_raster(
3323 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3324 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3325 raster_stride);
3326 }
3327 }
3328 #else
3329 dst1 = NULL;
3330 src1 = NULL;
3331 dst2 = NULL;
3332 src2 = NULL;
3333
3334 for (y = 0; y < h / tile_h; y++)
3335 {
3336 for (x = 0; x <= (w/tile_w - 4); x+=4)
3337 {
3338 tile4x4_to_raster_4(
3339 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3340 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3341 raster_stride);
3342 }
3343 for (; x < w / tile_w; x++)
3344 {
3345 tile4x4_to_raster(
3346 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3347 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3348 raster_stride);
3349 }
3350 }
3351 #endif
3352 }
3353
3354 #define FLUSH_CACHE_SIZE (256 * 1024)
3355
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3356 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3357 {
3358 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
3359 if (u32Size > FLUSH_CACHE_SIZE)
3360 u32Size = FLUSH_CACHE_SIZE;
3361
3362 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
3363 }
3364
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3365 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3366 {
3367 MS_U32 u32SkipSize = 0;
3368
3369 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3370 if (u32Size > FLUSH_CACHE_SIZE)
3371 {
3372 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3373 u32Size = FLUSH_CACHE_SIZE;
3374 }
3375
3376 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
3377 }
3378
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3379 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3380 {
3381 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
3382 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3383 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3384 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3385
3386 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3387
3388 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3389
3390 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3391 {
3392 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3393 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3394
3395 HVD_Delay_ms(1); // FIXME
3396
3397 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3398 continue;
3399
3400 HAL_HVD_EX_ReadMemory();
3401
3402 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3403 {
3404 MS_U8 *pSrcVA, *pDstVA;
3405 MS_U32 u32SrcPA, u32DstPA;
3406 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3407 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3408
3409 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3410 {
3411 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3412
3413 u16Width = pFrmInfo->u16Width;
3414 u16Height = pFrmInfo->u16Height;
3415 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3416 }
3417
3418 // Luma
3419 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3420 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3421
3422 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3423 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3424
3425 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3426 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3427
3428 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3429
3430 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3431
3432 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3433
3434 // Chroma
3435 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3436 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3437
3438 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3439 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3440
3441 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3442 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3443
3444 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3445
3446 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3447
3448 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3449
3450 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3451 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3452 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3453
3454 HAL_HVD_EX_FlushMemory();
3455
3456 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3457 break;
3458
3459 HAL_HVD_EX_ReadMemory();
3460 }
3461 }
3462
3463 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3464
3465 return TRUE;
3466 }
3467 #endif
3468
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3469 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3470 {
3471 #ifndef VDEC3
3472 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3473 #endif
3474 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3475 // MS_U8 u8MiuSel;
3476 // MS_U32 u32StartOffset;
3477
3478 #if SUPPORT_EVD
3479 MS_BOOL isEVD = (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3480 #if SUPPORT_MSVP9
3481 isEVD = isEVD || (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3482 #endif
3483 #endif
3484 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
3485 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3486
3487 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3488 // re-setup clock.
3489 #if SUPPORT_G2VP9 && defined(VDEC3)
3490 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3491 #endif
3492
3493
3494 if (!HAL_VPU_EX_HVDInUsed())
3495 {
3496 printf("HVD power on\n");
3497 HAL_HVD_EX_PowerCtrl(TRUE);
3498 }
3499
3500 #if SUPPORT_EVD
3501 if (isEVD) /// Disable it for disable H264 IMI
3502 {
3503 #ifdef VDEC3
3504 if (!HAL_VPU_EX_EVDInUsed())
3505 #endif
3506 {
3507 printf("EVD power on\n");
3508 HAL_EVD_EX_PowerCtrl(TRUE);
3509 }
3510 }
3511 #endif
3512
3513 #if SUPPORT_G2VP9 && defined(VDEC3)
3514 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3515 {
3516 if (!HAL_VPU_EX_G2VP9InUsed())
3517 {
3518 printf("G2 VP9 power on\n");
3519 HAL_VP9_EX_PowerCtrl(TRUE);
3520 }
3521 }
3522 #endif
3523
3524 if ((!HAL_VPU_EX_HVDInUsed()) )
3525 {
3526 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3527 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3528 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3529 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3530
3531 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3532
3533 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
3534 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
3535 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256);
3536 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256);
3537 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128);
3538 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128);
3539
3540 #if 0
3541 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
3542 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3543 {
3544 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
3545
3546 _HAL_HVD_Entry();
3547 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
3548 _HAL_HVD_Release();
3549
3550 }
3551 #endif
3552 }
3553
3554 #if SUPPORT_EVD
3555 if (isEVD)
3556 {
3557 #ifdef VDEC3
3558 if (!HAL_VPU_EX_EVDInUsed())
3559 #endif
3560 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3561 }
3562 #endif
3563
3564 #if SUPPORT_G2VP9 && defined(VDEC3)
3565 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3566 {
3567 if (!HAL_VPU_EX_G2VP9InUsed())
3568 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3569 }
3570 #endif
3571
3572
3573 if(pCtrl == NULL)
3574 {
3575 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
3576 //return FALSE;
3577 goto RESET;
3578 }
3579
3580 #if SUPPORT_EVD
3581 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
3582 {
3583 #ifdef VDEC3
3584 if (!HAL_VPU_EX_EVDInUsed())
3585 #endif
3586 {
3587 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3588 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3589 }
3590
3591 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3592 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3593 {
3594 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN);
3595 }
3596 goto RESET;
3597 }
3598 #endif
3599
3600 // HVD4, from JANUS and later chip
3601 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3602 {
3603 case E_HVD_INIT_HW_AVS:
3604 {
3605 #ifdef VDEC3
3606 if (0 == pCtrl->u32BBUId)
3607 #else
3608 if (0 == u8TaskId)
3609 #endif
3610 {
3611 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3612 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3613 }
3614 else
3615 {
3616 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3617 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3618 }
3619
3620 break;
3621 }
3622 case E_HVD_INIT_HW_RM:
3623 {
3624 #ifdef VDEC3
3625 if (0 == pCtrl->u32BBUId)
3626 #else
3627 if (0 == u8TaskId)
3628 #endif
3629 {
3630 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3631 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3632
3633 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3634 {
3635 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3636 }
3637 else // RV 8
3638 {
3639 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3640 }
3641 }
3642 else
3643 {
3644 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3645 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3646
3647 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3648 {
3649 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3650 }
3651 else // RV 8
3652 {
3653 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3654 }
3655
3656 }
3657
3658 break;
3659 }
3660 default:
3661 {
3662 #ifdef VDEC3
3663 if (0 == pCtrl->u32BBUId)
3664 #else
3665 if (0 == u8TaskId)
3666 #endif
3667 {
3668 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3669 }
3670 else
3671 {
3672 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3673 }
3674 break;
3675 }
3676 }
3677
3678 RESET:
3679
3680 #if 0 //Manhattan: use miu256bit
3681 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3682
3683 if (!HAL_VPU_EX_HVDInUsed())
3684 {
3685 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3686 }
3687
3688 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3689 #endif
3690
3691 #if SUPPORT_EVD
3692 if (isEVD)
3693 {
3694 #ifdef VDEC3
3695 if (!HAL_VPU_EX_EVDInUsed())
3696 #endif
3697 {
3698 printf("EVD miu 256 bits\n");
3699 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_128 & ~EVD_REG_RESET_MIU1_128));
3700 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_256 | EVD_REG_RESET_MIU1_256));
3701 }
3702 }
3703 #endif
3704 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3705 // Only ES buffer addrress needs to be set for VP8
3706 _HVD_EX_SetESBufferAddr(u32Id);
3707 #else
3708 if(DecoderType != E_VPU_EX_DECODER_MVD)
3709 {
3710 _HVD_EX_SetBufferAddr(u32Id);
3711 }
3712 #endif
3713 if (!HAL_VPU_EX_HVDInUsed())
3714 {
3715 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3716 }
3717
3718 #if SUPPORT_EVD
3719 if (isEVD)
3720 {
3721 #ifdef VDEC3
3722 if (!HAL_VPU_EX_EVDInUsed())
3723 #endif
3724 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
3725 }
3726 #endif
3727
3728 #if SUPPORT_G2VP9 && defined(VDEC3)
3729 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3730 {
3731 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3732
3733 if (!HAL_VPU_EX_G2VP9InUsed())
3734 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3735
3736 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3737 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
3738 }
3739 #endif
3740
3741 return TRUE;
3742 }
3743
HAL_HVD_EX_DeinitHW(void)3744 MS_BOOL HAL_HVD_EX_DeinitHW(void)
3745 {
3746 MS_U16 u16Timeout = 1000;
3747
3748 _HVD_EX_SetMIUProtectMask(TRUE);
3749
3750 #if SUPPORT_EVD //EVD using HVD DIU, it should be turn off EVD first
3751 //We assume HEVC belong to HVD, so we can disable EVD_REG_RESET_HK_TSP2EVD_EN in DeinitHW.
3752 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser
3753 HAL_EVD_EX_DeinitHW();
3754 #endif
3755
3756 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3757
3758 while (u16Timeout)
3759 {
3760 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
3761 {
3762 break;
3763 }
3764 u16Timeout--;
3765 }
3766
3767 HAL_HVD_EX_PowerCtrl(FALSE);
3768
3769 _HVD_EX_SetMIUProtectMask(FALSE);
3770
3771 return TRUE;
3772 }
3773
HAL_HVD_EX_FlushMemory(void)3774 void HAL_HVD_EX_FlushMemory(void)
3775 {
3776 MsOS_FlushMemory();
3777 }
3778
HAL_HVD_EX_ReadMemory(void)3779 void HAL_HVD_EX_ReadMemory(void)
3780 {
3781 MsOS_ReadMemory();
3782 }
3783
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)3784 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
3785 {
3786 _pHVDCtrls = pHVDCtrlsBase;
3787 }
3788
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)3789 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
3790 {
3791 return;
3792 }
3793
HAL_HVD_EX_GetHWVersionID(void)3794 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
3795 {
3796 return _HVD_Read2Byte(HVD_REG_REV_ID);
3797 }
3798
3799
HAL_HVD_EX_Init_Share_Mem(void)3800 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
3801 {
3802 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
3803 #if !defined(SUPPORT_X_MODEL_FEATURE)
3804 MS_U32 u32ShmId;
3805 MS_VIRT u32Addr;
3806 MS_U32 u32BufSize;
3807
3808
3809 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
3810 sizeof(HVD_Hal_CTX),
3811 &u32ShmId,
3812 &u32Addr,
3813 &u32BufSize,
3814 MSOS_SHM_QUERY))
3815 {
3816 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
3817 sizeof(HVD_Hal_CTX),
3818 &u32ShmId,
3819 &u32Addr,
3820 &u32BufSize,
3821 MSOS_SHM_CREATE))
3822 {
3823 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
3824 if(pHVDHalContext == NULL)
3825 {
3826 pHVDHalContext = &gHVDHalContext;
3827 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3828 _HVD_EX_Context_Init_HAL();
3829 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
3830 }
3831 else
3832 {
3833 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
3834 }
3835 //return FALSE;
3836 }
3837 else
3838 {
3839 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
3840 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
3841 _HVD_EX_Context_Init_HAL();
3842 }
3843 }
3844 else
3845 {
3846 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
3847 }
3848 #else
3849 if(pHVDHalContext == NULL)
3850 {
3851 pHVDHalContext = &gHVDHalContext;
3852 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3853 _HVD_EX_Context_Init_HAL();
3854 }
3855 #endif
3856 _HAL_HVD_MutexCreate();
3857 #else
3858 if(pHVDHalContext == NULL)
3859 {
3860 pHVDHalContext = &gHVDHalContext;
3861 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3862 _HVD_EX_Context_Init_HAL();
3863 }
3864 #endif
3865
3866 return TRUE;
3867 }
3868
3869
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)3870 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
3871 {
3872 MS_U32 i = 0;
3873
3874 if (eStreamType == E_HAL_HVD_MVC_STREAM)
3875 {
3876 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
3877 return pHVDHalContext->_stHVDStream[0].eStreamId;
3878 }
3879 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
3880 {
3881 for (i = 0;
3882 i <
3883 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3884 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3885 {
3886 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3887 {
3888 return pHVDHalContext->_stHVDStream[i].eStreamId;
3889 }
3890 }
3891 }
3892 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
3893 {
3894 for (i = 0;
3895 i <
3896 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3897 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3898 {
3899 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3900 {
3901 return pHVDHalContext->_stHVDStream[i].eStreamId;
3902 }
3903 }
3904 }
3905 #ifdef VDEC3
3906 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
3907 {
3908 i = eStreamType - E_HAL_HVD_N_STREAM;
3909 if (!pHVDHalContext->_stHVDStream[i].bUsed)
3910 return pHVDHalContext->_stHVDStream[i].eStreamId;
3911 }
3912 #endif
3913
3914 return E_HAL_HVD_STREAM_NONE;
3915 }
3916
HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)3917 void HAL_HVD_EX_PowerCtrl(MS_BOOL bEnable)
3918 {
3919 if (bEnable)
3920 {
3921 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3922 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3923 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3924 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
3925 }
3926 else
3927 {
3928 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
3929 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3930 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3931 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
3932 }
3933
3934 // fix to not inverse
3935 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
3936
3937 switch (pHVDHalContext->u32HVDClockType)
3938 {
3939 #if 0 //for overclocking
3940 case 432:
3941 {
3942 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
3943 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3944 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_320MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3945 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK);
3946 break;
3947 }
3948 #endif
3949 case 384:
3950 {
3951 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
3952 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3953 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3954 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3955 break;
3956 }
3957 case 345:
3958 {
3959 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_345MHZ, TOP_CKG_HVD_CLK_MASK);
3960 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3961 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3962 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3963 break;
3964 }
3965 case 320:
3966 {
3967 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_320MHZ, TOP_CKG_HVD_CLK_MASK);
3968 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_345MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3969 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3970 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3971 break;
3972 }
3973 case 288:
3974 {
3975 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
3976 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_320MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3977 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3978 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3979 break;
3980 }
3981 case 240:
3982 {
3983 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
3984 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3985 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3986 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
3987 break;
3988 }
3989 case 216:
3990 {
3991 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
3992 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_240MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
3993 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3994 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3995 break;
3996 }
3997 case 172:
3998 {
3999 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
4000 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_216MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4001 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4002 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
4003 break;
4004 }
4005
4006 default:
4007 {
4008 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4009 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4010 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4011 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
4012 break;
4013 }
4014 }
4015
4016 return;
4017 }
4018
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)4019 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
4020 {
4021 u32HVDRegOSBase = u32RegBase;
4022 HAL_VPU_EX_InitRegBase(u32RegBase);
4023 }
4024
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)4025 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
4026 {
4027 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
4028 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4029 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
4030 }
4031
HAL_HVD_EX_InitVariables(MS_U32 u32Id)4032 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
4033 {
4034 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4035 HVD_ShareMem *pShm = NULL;
4036 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4037 #if HVD_ENABLE_MVC
4038 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4039 #endif ///HVD_ENABLE_MVC
4040
4041 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4042 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4043 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4044 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
4045 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4046 int i;
4047 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
4048 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
4049 #if HVD_ENABLE_MVC
4050 if(bMVC)
4051 {
4052 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
4053 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
4054 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
4055 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
4056 }
4057 #endif ///HVD_ENABLE_MVC
4058
4059 // set a local copy of FW code address; assuming there is only one copy of FW,
4060 // no matter how many task will be created.
4061
4062 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4063
4064 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
4065
4066 // global variables
4067 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
4068
4069
4070 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4071 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4072 // Create mutex
4073 //_HAL_HVD_MutexCreate();
4074
4075 // fill HVD init variables
4076 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4077 {
4078 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
4079 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
4080 }
4081 else
4082 #if HVD_ENABLE_RV_FEATURE
4083 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4084 {
4085 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
4086 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
4087 #ifdef VDEC3_FB
4088 pHVDHalContext->u32RV_VLCTableAddr = 0;
4089 #else
4090 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
4091 {
4092 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
4093 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
4094 }
4095 else
4096 {
4097 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
4098 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
4099 return E_HVD_RETURN_INVALID_PARAMETER;
4100 }
4101 #endif
4102 }
4103 else
4104 #endif
4105 {
4106 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
4107 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
4108 #if HVD_ENABLE_MVC
4109 if(bMVC)
4110 {
4111 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
4112 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
4113 }
4114 #endif /// HVD_ENABLE_MVC
4115 pHVDHalContext->u32RV_VLCTableAddr = 0;
4116 }
4117
4118 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
4119 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
4120 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
4121 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
4122 {
4123 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4124 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4125 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4126 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4127 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4128 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4129 #if HVD_ENABLE_MVC
4130 if(bMVC)
4131 {
4132 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
4133 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
4134 {
4135 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
4136 }
4137 }
4138 #endif /// HVD_ENABLE_MVC
4139
4140 return E_HVD_RETURN_SUCCESS;
4141 }
4142 else
4143 {
4144 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4145 (unsigned long)MS_VA2PA((MS_VIRT)pShm),
4146 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4147 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4148 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4149 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4150 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4151 return E_HVD_RETURN_INVALID_PARAMETER;
4152 }
4153 }
4154
4155 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)4156 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
4157 #else
4158 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
4159 #endif
4160 {
4161 MS_U32 u32Addr = 0;
4162 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4163 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4164 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4165
4166 MS_U32 u32TmpStartOffset;
4167 MS_U8 u8TmpMiuSel;
4168
4169
4170 memset(pShm, 0, sizeof(HVD_ShareMem));
4171
4172 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
4173
4174 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
4175 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
4176 #ifdef VDEC3
4177 if (bFWdecideFB || bCMAUsed)
4178 {
4179 pShm->u32FrameBufAddr = 0;
4180 pShm->u32FrameBufSize = 0;
4181 }
4182 else
4183 #endif
4184 {
4185 pShm->u32FrameBufAddr = u32Addr;
4186 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
4187 }
4188
4189 pShm->DispInfo.u16DispWidth = 1;
4190 pShm->DispInfo.u16DispHeight = 1;
4191 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
4192 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
4193 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
4194 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4195 //Chip info
4196 pShm->u16ChipID = E_MSTAR_CHIP_MANHATTAN;
4197 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4198 // PreSetControl
4199 if (pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->bOnePendingBuffer)
4200 {
4201 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4202 }
4203 pShm->bUseTSPInBBUMode = FALSE;
4204
4205
4206 if ((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
4207 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4208 {
4209 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4210
4211 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
4212
4213 pShm->u32IapGnBufAddr = u32Addr;
4214 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufSize;
4215
4216 }
4217
4218 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
4219 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
4220 {
4221 case E_HVD_DEF_MFCODEC_DEFAULT:
4222 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4223 break;
4224 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
4225 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
4226 break;
4227 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
4228 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
4229 break;
4230 default:
4231 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4232 }
4233
4234 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
4235 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
4236 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
4237 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
4238 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
4239 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
4240
4241 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4242 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4243 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4244 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4245 else
4246 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4247 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4248 {
4249 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4250 {
4251 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4252 }
4253 else
4254 {
4255 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4256 }
4257 }
4258 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4259 {
4260 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4261 {
4262 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4263 }
4264 else
4265 {
4266 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4267 }
4268 }
4269 else
4270 {
4271 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4272 }
4273
4274 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4275 {
4276 pShm->bHVDIMIEnable = FALSE;
4277 }
4278
4279 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4280 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4281 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4282 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4283 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4284 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4285 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4286 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4287 {
4288 pShm->bUseWbMvop = 1;
4289 }
4290 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4291
4292 #if (VPU_FORCE_MIU_MODE)
4293 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4294
4295 pShm->u32FWBaseAddr = u32TmpStartOffset;
4296
4297 #else
4298 ///TODO:
4299 /*
4300 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4301
4302 if(u8TmpMiuSel == E_CHIP_MIU_0)
4303 {
4304 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4305 }
4306 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4307 {
4308 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4309 }
4310 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4311 {
4312 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4313 }
4314 */
4315 #endif
4316 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4317 #else
4318 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4319 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4320 {
4321 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4322 }
4323 pShm->u32FWBaseAddr = u32Addr;
4324 #endif
4325
4326 // RM only
4327 #if HVD_ENABLE_RV_FEATURE
4328 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4329 && (pCtrl->InitParams.pRVFileInfo != NULL))
4330 {
4331 MS_U32 i = 0;
4332
4333 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4334 {
4335 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4336 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4337 }
4338
4339 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4340 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4341 #ifdef VDEC3_FB
4342 pShm->u32RM_VLCTableAddr = 0;
4343 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4344 #else
4345 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
4346
4347 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4348 u32Addr = u32TmpStartOffset;
4349
4350 pShm->u32RM_VLCTableAddr = u32Addr;
4351 #endif
4352 }
4353 #endif
4354
4355 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4356 && (pCtrl->InitParams.pRVFileInfo != NULL))
4357 {
4358 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4359 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4360 }
4361
4362 //if(pCtrl->InitParams.bColocateBBUMode)
4363 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4364 {
4365 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4366 }
4367
4368 #if SUPPORT_G2VP9
4369 // Enable SW detile support for G2 VP9
4370 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4371 {
4372 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4373 }
4374 #endif
4375
4376 HAL_HVD_EX_FlushMemory();
4377
4378 return E_HVD_RETURN_SUCCESS;
4379 }
4380 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4381 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4382 #else
4383 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4384 #endif
4385 {
4386 MS_BOOL bInitRet = FALSE;
4387
4388 #if 0
4389 // check MVD power on
4390 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4391 {
4392 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4393 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4394 HVD_Delay_ms(1);
4395 }
4396 // Check VPU power on
4397 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4398 {
4399 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4400 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4401 HVD_Delay_ms(1);
4402 }
4403 // check HVD power on
4404 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4405 {
4406 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4407 HAL_HVD_EX_PowerCtrl(TRUE);
4408 HVD_Delay_ms(1);
4409 }
4410 #endif
4411 #ifdef VDEC3
4412 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4413 #else
4414 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4415 #endif
4416 if (!bInitRet)
4417 {
4418 return E_HVD_RETURN_FAIL;
4419 }
4420
4421 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4422
4423 if (!bInitRet)
4424 {
4425 return E_HVD_RETURN_FAIL;
4426 }
4427
4428 return E_HVD_RETURN_SUCCESS;
4429 }
4430
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4431 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4432 {
4433 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4434
4435 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4436
4437 return E_HVD_RETURN_SUCCESS;
4438 }
4439
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)4440 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
4441 {
4442 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4443 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4444 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4445 MS_BOOL bMVC = FALSE;
4446 #if HVD_ENABLE_MVC
4447 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4448 #endif
4449
4450 switch (u32type)
4451 {
4452 // share memory
4453 // switch
4454 case E_HVD_SDATA_FRAMEBUF_ADDR:
4455 {
4456 pShm->u32FrameBufAddr = u32Data;
4457 break;
4458 }
4459 case E_HVD_SDATA_FRAMEBUF_SIZE:
4460 {
4461 pShm->u32FrameBufSize = u32Data;
4462 break;
4463 }
4464 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4465 {
4466 pShm->u32FrameBuf2Addr = u32Data;
4467 break;
4468 }
4469 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4470 {
4471 pShm->u32FrameBuf2Size = u32Data;
4472 break;
4473 }
4474 case E_HVD_SDATA_CMA_USED:
4475 {
4476 pShm->bCMA_Use = u32Data;
4477 break;
4478 }
4479 case E_HVD_SDATA_CMA_ALLOC_DONE:
4480 {
4481 pShm->bCMA_AllocDone = u32Data;
4482 break;
4483 }
4484 case E_HVD_SDATA_CMA_TWO_MIU:
4485 {
4486 pShm->bCMA_TwoMIU = u32Data;
4487 break;
4488 }
4489 case E_HVD_SDATA_RM_PICTURE_SIZES:
4490 {
4491 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4492 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4493 break;
4494 }
4495 case E_HVD_SDATA_ERROR_CODE:
4496 {
4497 pShm->u16ErrCode = (MS_U16) u32Data;
4498 break;
4499 }
4500 case E_HVD_SDATA_DISP_INFO_TH:
4501 {
4502 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4503 sizeof(HVD_DISP_THRESHOLD));
4504 break;
4505 }
4506 case E_HVD_SDATA_FW_FLUSH_STATUS:
4507 {
4508 pShm->u8FlushStatus = (MS_U8)u32Data;
4509 break;
4510 }
4511 case E_HVD_SDATA_DMX_FRAMERATE:
4512 {
4513 pShm->u32DmxFrameRate = u32Data;
4514 break;
4515 }
4516 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4517 {
4518 pShm->u32DmxFrameRateBase = u32Data;
4519 break;
4520 }
4521 case E_HVD_SDATA_MIU_SEL:
4522 {
4523 pShm->u32VDEC_MIU_SEL = u32Data;
4524 break;
4525 }
4526 // SRAM
4527
4528 // Mailbox
4529 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4530 {
4531 if (u32Data != 0)
4532 {
4533 pShm->bEnableDispCtrl = TRUE;
4534 pShm->bIsTrigDisp = TRUE;
4535 }
4536 else
4537 {
4538 pShm->bEnableDispCtrl = FALSE;
4539 }
4540
4541 break;
4542 }
4543 case E_HVD_SDATA_GET_DISP_INFO_START:
4544 {
4545 pShm->bSpsChange = FALSE;
4546 break;
4547 }
4548 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4549 {
4550 pShm->u32VirtualBoxWidth = u32Data;
4551 break;
4552 }
4553 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4554 {
4555 pShm->u32VirtualBoxHeight = u32Data;
4556 break;
4557 }
4558 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4559 {
4560 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4561 {
4562 //printf("DispFrame DqPtr: %d\n", u32Data);
4563 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4564 }
4565 break;
4566 }
4567 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4568 {
4569 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
4570 {
4571 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4572 {
4573 //printf("DispFrame DqPtr: %ld\n", u32Data);
4574 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4575 }
4576 }
4577 break;
4578 }
4579 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4580 {
4581 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4582 {
4583 if (bMVC)
4584 {
4585 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4586 {
4587 //ALOGE("R1: %x", u32Data);
4588 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
4589 }
4590 else
4591 {
4592 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4593 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4594 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
4595 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4596 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4597 }
4598 }
4599 else
4600 {
4601 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4602 }
4603 }
4604 else
4605 {
4606 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4607 {
4608 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4609 }
4610 }
4611 break;
4612 }
4613 #if (HVD_ENABLE_IQMEM)
4614 case E_HVD_SDATA_FW_IQMEM_CTRL:
4615 {
4616 pShm->u8IQmemCtrl= (MS_U8)u32Data;
4617 break;
4618
4619 }
4620 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
4621 {
4622 if (u32Data != 0)
4623 {
4624 pShm->bIQmemEnableIfSupport= TRUE;
4625 }
4626 else
4627 {
4628 pShm->bIQmemEnableIfSupport= FALSE;
4629 }
4630
4631
4632 break;
4633
4634 }
4635 #endif
4636
4637 default:
4638 break;
4639 }
4640
4641 HAL_HVD_EX_FlushMemory();
4642
4643 return eRet;
4644 }
4645
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4646 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4647 {
4648 MS_S64 s64Ret = 0;
4649 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4650
4651 HAL_HVD_EX_ReadMemory();
4652
4653 switch (eType)
4654 {
4655 case E_HVD_GDATA_PTS_STC_DIFF:
4656 s64Ret = pShm->s64PtsStcDiff;
4657 break;
4658 default:
4659 break;
4660 }
4661
4662 return s64Ret;
4663 }
4664
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4665 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4666 {
4667 MS_VIRT u32Ret = 0;
4668 //static MS_U64 u64pts_real = 0;
4669 MS_U64 u64pts_low = 0;
4670 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4671 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4672
4673 HAL_HVD_EX_ReadMemory();
4674
4675 if(pShm == NULL)
4676 {
4677 printf("########## VDEC patch for Debug ###########\n");
4678 return 0x0;
4679 }
4680
4681 switch (eType)
4682 {
4683 // share memory
4684 // switch
4685 case E_HVD_GDATA_DISP_INFO_ADDR:
4686 {
4687 u32Ret = (MS_VIRT) (&pShm->DispInfo);
4688 break;
4689 }
4690 case E_HVD_GDATA_MIU_SEL:
4691 u32Ret = pShm->u32VDEC_MIU_SEL;
4692 break;
4693 case E_HVD_GDATA_FRAMEBUF_ADDR:
4694 u32Ret = pShm->u32FrameBufAddr;
4695 break;
4696 case E_HVD_GDATA_FRAMEBUF_SIZE:
4697 u32Ret = pShm->u32FrameBufSize;
4698 break;
4699 case E_HVD_GDATA_FRAMEBUF2_ADDR:
4700 u32Ret = pShm->u32FrameBuf2Addr;
4701 break;
4702 case E_HVD_GDATA_FRAMEBUF2_SIZE:
4703 u32Ret = pShm->u32FrameBuf2Size;
4704 break;
4705 case E_HVD_GDATA_CMA_ALLOC_DONE:
4706 u32Ret = pShm->bCMA_AllocDone;
4707 break;
4708 case E_HVD_GDATA_CMA_USED:
4709 u32Ret = pShm->bCMA_Use;
4710 break;
4711 // report
4712 case E_HVD_GDATA_PTS:
4713 {
4714 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
4715 break;
4716 }
4717 case E_HVD_GDATA_U64PTS:
4718 {
4719 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
4720 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
4721 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4722 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4723 break;
4724 }
4725 case E_HVD_GDATA_U64PTS_PRE_PARSE:
4726 {
4727 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
4728 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
4729 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4730 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4731 break;
4732 }
4733 case E_HVD_GDATA_DECODE_CNT:
4734 {
4735 u32Ret = pShm->u32DecodeCnt;
4736 break;
4737 }
4738 case E_HVD_GDATA_DATA_ERROR_CNT:
4739 {
4740 u32Ret = pShm->u32DataErrCnt;
4741 break;
4742 }
4743 case E_HVD_GDATA_DEC_ERROR_CNT:
4744 {
4745 u32Ret = pShm->u32DecErrCnt;
4746 break;
4747 }
4748 case E_HVD_GDATA_ERROR_CODE:
4749 {
4750 u32Ret = (MS_U32) (pShm->u16ErrCode);
4751 break;
4752 }
4753 case E_HVD_GDATA_VPU_IDLE_CNT:
4754 {
4755 u32Ret = pShm->u32VPUIdleCnt;
4756 break;
4757 }
4758 case E_HVD_GDATA_DISP_FRM_INFO:
4759 {
4760 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
4761 break;
4762 }
4763 case E_HVD_GDATA_DEC_FRM_INFO:
4764 {
4765 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
4766 break;
4767 }
4768 case E_HVD_GDATA_ES_LEVEL:
4769 {
4770 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
4771 break;
4772 }
4773 #if HVD_ENABLE_MVC
4774 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
4775 {
4776 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
4777 break;
4778 }
4779 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
4780 {
4781 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
4782 break;
4783 }
4784 #endif
4785
4786 // user data
4787 case E_HVD_GDATA_USERDATA_WPTR:
4788 {
4789 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
4790 break;
4791 }
4792 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
4793 {
4794 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
4795 break;
4796 }
4797 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
4798 {
4799 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
4800 break;
4801 }
4802 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
4803 {
4804 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
4805 break;
4806 }
4807 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
4808 {
4809 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
4810 break;
4811 }
4812 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
4813 {
4814 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
4815 break;
4816 }
4817 // report - modes
4818 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
4819 {
4820 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
4821 break;
4822 }
4823 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
4824 {
4825 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
4826 break;
4827 }
4828 case E_HVD_GDATA_IS_ERR_CONCEAL:
4829 {
4830 u32Ret = pShm->ModeStatus.bIsErrConceal;
4831 break;
4832 }
4833 case E_HVD_GDATA_IS_SYNC_ON:
4834 {
4835 u32Ret = pShm->ModeStatus.bIsSyncOn;
4836 break;
4837 }
4838 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
4839 {
4840 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
4841 break;
4842 }
4843 case E_HVD_GDATA_SYNC_MODE:
4844 {
4845 u32Ret = pShm->ModeStatus.u8SyncType;
4846 break;
4847 }
4848 case E_HVD_GDATA_SKIP_MODE:
4849 {
4850 u32Ret = pShm->ModeStatus.u8SkipMode;
4851 break;
4852 }
4853 case E_HVD_GDATA_DROP_MODE:
4854 {
4855 u32Ret = pShm->ModeStatus.u8DropMode;
4856 break;
4857 }
4858 case E_HVD_GDATA_DISPLAY_DURATION:
4859 {
4860 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
4861 break;
4862 }
4863 case E_HVD_GDATA_FRC_MODE:
4864 {
4865 u32Ret = pShm->ModeStatus.u8FrcMode;
4866 break;
4867 }
4868 case E_HVD_GDATA_NEXT_PTS:
4869 {
4870 u32Ret = pShm->u32NextPTS;
4871 break;
4872 }
4873 case E_HVD_GDATA_DISP_Q_SIZE:
4874 {
4875 u32Ret = pShm->u16DispQSize;
4876 break;
4877 }
4878 case E_HVD_GDATA_DISP_Q_PTR:
4879 {
4880 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
4881 break;
4882 }
4883 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
4884 {
4885 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
4886 break;
4887 }
4888 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
4889 {
4890 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
4891 break;
4892 }
4893 case E_HVD_GDATA_REAL_FRAMERATE:
4894 {
4895 // return VPS/VUI timing info framerate, and 0 if timing info not exist
4896 u32Ret = pShm->u32RealFrameRate;
4897 break;
4898 }
4899 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
4900 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
4901 break;
4902 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
4903 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
4904 break;
4905 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
4906 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
4907 break;
4908 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
4909 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
4910 break;
4911 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
4912 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
4913 break;
4914 case E_HVD_GDATA_FW_STATUS_FLAG:
4915 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
4916 break;
4917
4918 // internal control
4919 case E_HVD_GDATA_IS_1ST_FRM_RDY:
4920 {
4921 u32Ret = pShm->bIs1stFrameRdy;
4922 break;
4923 }
4924 case E_HVD_GDATA_IS_I_FRM_FOUND:
4925 {
4926 u32Ret = pShm->bIsIFrmFound;
4927 break;
4928 }
4929 case E_HVD_GDATA_IS_SYNC_START:
4930 {
4931 u32Ret = pShm->bIsSyncStart;
4932 break;
4933 }
4934 case E_HVD_GDATA_IS_SYNC_REACH:
4935 {
4936 u32Ret = pShm->bIsSyncReach;
4937 break;
4938 }
4939 case E_HVD_GDATA_FW_VERSION_ID:
4940 {
4941 u32Ret = pShm->u32FWVersionID;
4942 break;
4943 }
4944 case E_HVD_GDATA_FW_IF_VERSION_ID:
4945 {
4946 u32Ret = pShm->u32FWIfVersionID;
4947 break;
4948 }
4949 case E_HVD_GDATA_BBU_Q_NUMB:
4950 {
4951 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
4952 break;
4953 }
4954 case E_HVD_GDATA_DEC_Q_NUMB:
4955 {
4956 u32Ret = pShm->u16DecQNumb;
4957 break;
4958 }
4959 case E_HVD_GDATA_DISP_Q_NUMB:
4960 {
4961 u32Ret = pShm->u16DispQNumb;
4962 break;
4963 }
4964 case E_HVD_GDATA_PTS_Q_NUMB:
4965 {
4966 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
4967 break;
4968 }
4969 case E_HVD_GDATA_FW_INIT_DONE:
4970 {
4971 u32Ret = pShm->bInitDone;
4972 break;
4973 }
4974 // debug
4975 case E_HVD_GDATA_SKIP_CNT:
4976 {
4977 u32Ret = pShm->u32SkipCnt;
4978 break;
4979 }
4980 case E_HVD_GDATA_GOP_CNT:
4981 {
4982 u32Ret = pShm->u32DropCnt;
4983 break;
4984 }
4985 case E_HVD_GDATA_DISP_CNT:
4986 {
4987 u32Ret = pShm->u32DispCnt;
4988 break;
4989 }
4990 case E_HVD_GDATA_DROP_CNT:
4991 {
4992 u32Ret = pShm->u32DropCnt;
4993 break;
4994 }
4995 case E_HVD_GDATA_DISP_STC:
4996 {
4997 u32Ret = pShm->u32DispSTC;
4998 break;
4999 }
5000 case E_HVD_GDATA_VSYNC_CNT:
5001 {
5002 u32Ret = pShm->u32VsyncCnt;
5003 break;
5004 }
5005 case E_HVD_GDATA_MAIN_LOOP_CNT:
5006 {
5007 u32Ret = pShm->u32MainLoopCnt;
5008 break;
5009 }
5010
5011 // AVC
5012 case E_HVD_GDATA_AVC_LEVEL_IDC:
5013 {
5014 u32Ret = pShm->u16AVC_SPS_LevelIDC;
5015 break;
5016 }
5017 case E_HVD_GDATA_AVC_LOW_DELAY:
5018 {
5019 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
5020 break;
5021 }
5022 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
5023 {
5024 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
5025 break;
5026 }
5027 case E_HVD_GDATA_FW_FLUSH_STATUS:
5028 {
5029 u32Ret = (MS_U32) (pShm->u8FlushStatus);
5030 break;
5031 }
5032 case E_HVD_GDATA_FW_CODEC_TYPE:
5033 {
5034 u32Ret = pShm->u32CodecType;
5035 break;
5036 }
5037 case E_HVD_GDATA_FW_ES_BUF_STATUS:
5038 {
5039 u32Ret = (MS_U32)pShm->u8ESBufStatus;
5040 break;
5041 }
5042 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
5043 {
5044 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
5045 {
5046 u32Ret = 1;
5047 }
5048 else
5049 {
5050 u32Ret = 0;
5051 }
5052 break;
5053 }
5054
5055 // SRAM
5056
5057 // Mailbox
5058 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
5059 {
5060 u32Ret = pShm->u32FwState;
5061 break;
5062 }
5063 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
5064 {
5065 u32Ret = pShm->bSpsChange;
5066 break;
5067 }
5068 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
5069 {
5070 u32Ret = pShm->bSpsChange;
5071
5072 if (pShm->bSpsChange &&
5073 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
5074 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
5075 {
5076 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
5077 }
5078
5079 break;
5080 }
5081 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
5082 {
5083 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5084
5085 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
5086 {
5087 u32Ret = pShm->u32FwInfo;
5088 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
5089 }
5090 break;
5091 }
5092 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
5093 {
5094 if (pShm->bIsTrigDisp) // not clear yet
5095 {
5096 u32Ret = FALSE;
5097 }
5098 else
5099 {
5100 u32Ret = TRUE;
5101 }
5102 break;
5103 }
5104 case E_HVD_GDATA_ES_READ_PTR:
5105 {
5106 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5107 break;
5108 }
5109 case E_HVD_GDATA_ES_WRITE_PTR:
5110 {
5111 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
5112 break;
5113 }
5114 case E_HVD_GDATA_BBU_READ_PTR:
5115 {
5116 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
5117 break;
5118 }
5119 case E_HVD_GDATA_BBU_WRITE_PTR:
5120 {
5121 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5122 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5123 {
5124 u32Ret = pHVDHalContext->u32VP8BBUWptr;
5125 }
5126 else
5127 {
5128 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5129 }
5130 break;
5131 }
5132 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
5133 {
5134 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5135
5136 u32Ret = pCtrl->u32BBUWptr_Fired;
5137
5138 break;
5139 }
5140 case E_HVD_GDATA_VPU_PC_CNT:
5141 {
5142 u32Ret = _HVD_EX_GetPC();
5143 break;
5144 }
5145 case E_HVD_GDATA_ES_QUANTITY:
5146 {
5147 u32Ret=_HVD_EX_GetESQuantity(u32Id);
5148 break;
5149 }
5150
5151
5152 // FW def
5153 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
5154 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
5155 break;
5156
5157 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
5158 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
5159 break;
5160 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
5161 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
5162 break;
5163 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
5164 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5165 break;
5166 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
5167 u32Ret = MAX_PTS_TABLE_SIZE;
5168 break;
5169 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
5170 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
5171 break;
5172 case E_HVD_GDATA_FW_DS_BUF_ADDR:
5173 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
5174 break;
5175 case E_HVD_GDATA_FW_DS_BUF_SIZE:
5176 u32Ret = pShm->u32DSBuffSize; //3k or 6k
5177 break;
5178 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
5179 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
5180 break;
5181 case E_HVD_GDATA_FW_DS_INFO_ADDR:
5182 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
5183 break;
5184 case E_HVD_GDATA_FW_DS_IS_ENABLED:
5185 {
5186 if (pShm->bDSIsRunning)
5187 {
5188 u32Ret = TRUE;
5189 }
5190 else
5191 {
5192 u32Ret = FALSE;
5193 }
5194 break;
5195 }
5196 #if (HVD_ENABLE_IQMEM)
5197 case E_HVD_GDATA_FW_IQMEM_CTRL:
5198 {
5199
5200 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
5201
5202 break;
5203 }
5204 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
5205 {
5206 if(pShm->bIsIQMEMSupport){
5207 u32Ret = TRUE;
5208 }
5209 else{
5210
5211 u32Ret = FALSE;
5212 }
5213
5214 break;
5215 }
5216 #endif
5217 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
5218 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
5219 break;
5220 case E_HVD_GDATA_FIELD_PIC_FLAG:
5221 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
5222 break;
5223 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
5224 u32Ret = pShm->u32SeamlessTSStatus;
5225 break;
5226 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
5227 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
5228 break;
5229 #ifdef VDEC3
5230 case E_HVD_GDATA_FW_VBBU_ADDR:
5231 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
5232 break;
5233 #endif
5234 default:
5235 break;
5236 }
5237 return u32Ret;
5238 }
5239
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)5240 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
5241 {
5242 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5243 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
5244 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5245
5246 _HAL_HVD_Entry();
5247
5248 // check if old SVD cmds
5249 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5250 {
5251 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
5252
5253 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5254 }
5255
5256 if(u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5257 {
5258 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5259 }
5260
5261 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5262 {
5263 if (u32Cmd == E_HVD_CMD_FLUSH)
5264 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5265 }
5266
5267 if (u32Cmd == E_HVD_CMD_FLUSH &&
5268 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5269 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5270 {
5271 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5272 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5273 {
5274 _HAL_HVD_Release();
5275 HVD_Delay_ms(1);
5276 _HAL_HVD_Entry();
5277 }
5278 }
5279
5280 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
5281
5282 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5283
5284 _HAL_HVD_Return(eRet);
5285 }
5286
HAL_HVD_EX_DeInit(MS_U32 u32Id)5287 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5288 {
5289 HVD_Return eRet = E_HVD_RETURN_FAIL;
5290 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5291 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5292 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5293 MS_U8 u8MiuSel;
5294 MS_U32 u32StartOffset;
5295
5296
5297 #if HVD_ENABLE_TIME_MEASURE
5298 MS_U32 ExitTimeCnt = 0;
5299 ExitTimeCnt = HVD_GetSysTime_ms();
5300 #endif
5301
5302 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
5303
5304 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5305
5306 if (E_HVD_RETURN_SUCCESS != eRet)
5307 {
5308 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5309 }
5310
5311 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5312
5313 if (E_HVD_RETURN_SUCCESS != eRet)
5314 {
5315 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5316 }
5317
5318 // check FW state to make sure it's STOP DONE
5319 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5320 {
5321 if (HVD_GetSysTime_ms() > u32Timeout)
5322 {
5323 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
5324
5325 //return E_HVD_RETURN_TIMEOUT;
5326 eRet = E_HVD_RETURN_TIMEOUT;
5327 break;
5328 }
5329 }
5330
5331 VPU_EX_FWCodeCfg fwCfg;
5332 VPU_EX_TaskInfo taskInfo;
5333 VPU_EX_NDecInitPara nDecInitPara;
5334
5335 nDecInitPara.pFWCodeCfg = &fwCfg;
5336 nDecInitPara.pTaskInfo = &taskInfo;
5337
5338 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5339 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5340
5341 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);//power control
5342 #if 0
5343 taskInfo.u32Id = u32Id;
5344 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5345 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5346 #endif
5347
5348 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5349 {
5350 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5351 }
5352 else
5353 {
5354 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5355 }
5356
5357 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5358 {
5359 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5360 }
5361
5362 /* clear es buffer */
5363 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5364 {
5365 //printf("Clear ES buffer\n");
5366
5367 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5368 }
5369
5370 //_HAL_HVD_MutexDelete();
5371
5372 #if HVD_ENABLE_TIME_MEASURE
5373 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5374 #endif
5375
5376 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
5377 #ifndef VDEC3
5378 // reset bbu wptr
5379 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5380 {
5381 if(TRUE == HAL_VPU_EX_HVDInUsed())
5382 {
5383 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5384 {
5385 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5386 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5387 }
5388 else
5389 {
5390 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5391 {
5392 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5393 }
5394 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5395 }
5396 }
5397 else
5398 {
5399 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
5400 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
5401 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
5402 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5403 {
5404 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5405 {
5406 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5407 }
5408 }
5409 else
5410 {
5411 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5412 }
5413 }
5414 }
5415 #endif
5416 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5417
5418 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5419 {
5420 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
5421 }
5422
5423 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
5424 {
5425
5426 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
5427
5428 _HAL_HVD_Entry();
5429 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
5430 _HAL_HVD_Release();
5431
5432 }
5433
5434 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
5435 HVD_EX_MSG_DBG("success\n");
5436
5437 return eRet;
5438 }
5439
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5440 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5441 {
5442 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5443 MS_U32 u32Addr = 0;
5444 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5445 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5446
5447 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5448
5449 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5450 {
5451 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5452
5453 if (E_HVD_RETURN_SUCCESS != eRet)
5454 {
5455 return eRet;
5456 }
5457 }
5458
5459 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5460
5461 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5462 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5463 {
5464 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5465
5466 if (E_HVD_RETURN_SUCCESS != eRet)
5467 {
5468 return eRet;
5469 }
5470 }
5471
5472 u32Addr = pInfo->u32Staddr;
5473
5474 if (pInfo->bRVBrokenPacket)
5475 {
5476 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5477 }
5478
5479 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5480 {
5481 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5482 }
5483 else
5484 {
5485 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5486 }
5487
5488 if (E_HVD_RETURN_SUCCESS != eRet)
5489 {
5490 return eRet;
5491 }
5492
5493 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5494 {
5495 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5496 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5497
5498 if (E_HVD_RETURN_SUCCESS != eRet)
5499 {
5500 return eRet;
5501 }
5502 }
5503
5504 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5505
5506 // do not add local pointer
5507 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5508 {
5509 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5510
5511 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5512 (u32PacketStAddr <
5513 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5514 {
5515 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5516 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5517 }
5518 else
5519 {
5520 //null packet
5521 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5522 pCtrl->LastNal.u32NalSize = 0;
5523 }
5524 }
5525 else
5526 {
5527 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5528 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5529 }
5530
5531 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5532 pCtrl->u32BBUPacketCnt++;
5533
5534 return eRet;
5535 }
5536
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5537 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5538 {
5539 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5540 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5541 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
5542 if(bCurrentStatus == bEnable)
5543 return;
5544
5545 if (bEnable)
5546 {
5547 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5548 }
5549 else
5550 {
5551 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5552 }
5553 }
5554
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5555 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5556 {
5557 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5558 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5559
5560 if (bEnable)
5561 {
5562 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5563 }
5564 else
5565 {
5566 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5567 }
5568 }
5569
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)5570 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
5571 {
5572 MS_U32 u32RB = 0;
5573 switch(eISRType)
5574 {
5575 case E_HWDEC_ISR_HVD:
5576 u32RB = REG_HVD_BASE;
5577 break;
5578 #if SUPPORT_EVD
5579 case E_HWDEC_ISR_EVD:
5580 u32RB = REG_EVD_BASE;
5581 break;
5582 #endif
5583 #if SUPPORT_G2VP9
5584 case E_HWDEC_ISR_G2VP9:
5585 break;
5586 #endif
5587 default:
5588 break;
5589 }
5590 if(u32RB)
5591 {
5592 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5593 }
5594 }
5595
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5596 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5597 {
5598 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5599 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5600
5601 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5602 }
5603
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)5604 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
5605 {
5606 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5607 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5608
5609 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
5610 {
5611 return FALSE;
5612 }
5613 else
5614 {
5615 return TRUE;
5616 }
5617 }
5618
HAL_HVD_EX_IsAlive(MS_U32 u32Id)5619 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
5620 {
5621 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5622
5623 if (pCtrl)
5624 {
5625 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
5626 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
5627 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
5628 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
5629 {
5630 return FALSE;
5631 }
5632 else
5633 {
5634 return TRUE;
5635 }
5636 }
5637 else
5638 {
5639 return FALSE;
5640 }
5641 }
5642
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)5643 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
5644 {
5645 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5646 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5647 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5648
5649 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5650 {
5651 HAL_HVD_EX_ReadMemory();
5652
5653 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
5654 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
5655
5656 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
5657 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
5658 }
5659
5660 return TRUE;
5661 }
5662
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)5663 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
5664 {
5665 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5666 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5667 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5668 MS_U32 u32Data;
5669 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5670
5671 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
5672
5673 HAL_HVD_EX_FlushMemory();
5674 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5675 {
5676 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5677 pCtrl->LastNal.u32NalAddr = u32Data;
5678 pCtrl->LastNal.u32NalSize = 0;
5679 }
5680
5681 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5682 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
5683
5684 return TRUE;
5685 }
5686
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)5687 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
5688 {
5689 if (bEnable)
5690 {
5691 if (HAL_VPU_EX_IsEVDR2())
5692 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5693 else
5694 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
5695 }
5696 else
5697 {
5698 #if defined (__aeon__)
5699 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
5700 #else // defined (__mips__)
5701 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
5702 #endif
5703 }
5704 }
5705
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)5706 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
5707 {
5708 return 0;
5709 }
5710
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)5711 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
5712 {
5713 return;
5714 }
5715
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)5716 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
5717 {
5718 //if( u16Clock == 0 )
5719 return 216; //140;
5720 //if( )
5721 }
5722
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)5723 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
5724 {
5725 //MS_BOOL bBitMIU1 = FALSE;
5726 //MS_BOOL bCodeMIU1 = FALSE;
5727 MS_U8 u8BitMiuSel = 0;
5728 MS_U8 u8CodeMiuSel = 0;
5729 MS_U32 u32BitStartOffset;
5730 MS_U32 u32CodeStartOffset;
5731 //MS_U8 u8MiuSel;
5732 //MS_U32 u32StartOffset;
5733 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5734 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5735 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5736 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
5737
5738 #if HVD_ENABLE_MVC
5739 if(HAL_HVD_EX_CheckMVCID(u32Id))
5740 {
5741 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
5742 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
5743 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
5744 {
5745 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
5746 }
5747 }
5748 #endif /// HVD_ENABLE_MVC
5749
5750 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
5751 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
5752
5753
5754
5755
5756 if (u8BitMiuSel != u8CodeMiuSel)
5757 {
5758 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
5759 BDMA_Result bdmaRlt;
5760 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5761
5762 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5763 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
5764 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5765
5766 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
5767
5768 if (E_BDMA_OK != bdmaRlt)
5769 {
5770 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
5771 }
5772 #else
5773 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
5774
5775 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
5776 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
5777 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
5778
5779 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
5780 #endif
5781 }
5782
5783 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
5784
5785 HAL_HVD_EX_FlushMemory();
5786
5787 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5788 {
5789 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
5790 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
5791 }
5792 else
5793 {
5794 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
5795
5796 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5797 }
5798 }
5799
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)5800 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
5801 {
5802 if (bEnable)
5803 {
5804 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
5805 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
5806 }
5807 else
5808 {
5809 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
5810 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
5811 }
5812 }
5813
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)5814 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
5815 {
5816 MS_U32 tmp1 = 0;
5817 MS_U32 tmp2 = 0;
5818 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5819
5820 HAL_HVD_EX_ReadMemory();
5821
5822 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
5823 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
5824
5825 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
5826 {
5827 MS_U32 u32Tmp = u32UartCtrl;
5828
5829 HVD_EX_MSG_DBG("\n");
5830 u32UartCtrl = 0; // turn off debug message to prevent other function prints
5831 printf("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
5832 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
5833
5834 printf("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
5835 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
5836 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
5837 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
5838
5839 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
5840 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
5841 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
5842
5843 printf("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
5844 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
5845 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
5846 _HVD_EX_GetESLevel(u32Id));
5847
5848 printf("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
5849 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
5850 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
5851 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
5852 printf
5853 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
5854 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
5855 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
5856 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
5857 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
5858 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
5859 pShm->ModeStatus.bShowOneField);
5860
5861 u32UartCtrl = u32Tmp; // recover debug level
5862 }
5863 }
5864
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)5865 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
5866 {
5867 MS_U8 *u32Addr = NULL;
5868 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5869 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5870
5871 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
5872 {
5873 return;
5874 }
5875
5876 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
5877
5878 *u32NalSize = *(u32Addr + 2) & 0x1f;
5879 *u32NalSize <<= 8;
5880 *u32NalSize |= *(u32Addr + 1) & 0xff;
5881 *u32NalSize <<= 8;
5882 *u32NalSize |= *(u32Addr) & 0xff;
5883
5884 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
5885 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
5886 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
5887 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
5888 }
5889
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)5890 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
5891 {
5892 MS_U32 u32CurIdx = 0;
5893 MS_BOOL bFinished = FALSE;
5894 MS_U32 u32NalOffset = 0;
5895 MS_U32 u32NalSize = 0;
5896 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5897
5898 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
5899 {
5900 return;
5901 }
5902
5903 u32CurIdx = u32StartIdx;
5904
5905 do
5906 {
5907 if (u32CurIdx == u32EndIdx)
5908 {
5909 bFinished = TRUE;
5910 }
5911
5912 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
5913
5914 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
5915 {
5916 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
5917 }
5918
5919 u32CurIdx++;
5920
5921 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
5922 {
5923 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5924 }
5925 } while (bFinished == TRUE);
5926 }
5927
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)5928 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
5929 {
5930 MS_U32 i = 0;
5931 MS_U32 value = 0;
5932
5933 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
5934 {
5935 HVD_EX_MSG_DBG("\n");
5936
5937 for (i = 0; i <= u32Num; i++)
5938 {
5939 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
5940 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
5941 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
5942
5943 if (value == 0)
5944 {
5945 break;
5946 }
5947
5948 printf(" %08x", value);
5949
5950 if (((i % 8) + 1) == 8)
5951 {
5952 printf(" |%u\n", i + 1);
5953 }
5954 }
5955
5956 printf("\nHVD Dump HW status End: total number:%u\n", i);
5957 }
5958 }
5959
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)5960 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
5961 {
5962 if (pDrvCtrl)
5963 {
5964 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
5965 }
5966 }
5967
5968 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)5969 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
5970 {
5971 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
5972 }
5973
HAL_HVD_EX_GetView(MS_U32 u32Id)5974 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
5975 {
5976 if( (0xFF & (u32Id >> 8)) == 0x10)
5977 return E_VDEC_EX_MAIN_VIEW;
5978 else
5979 return E_VDEC_EX_SUB_VIEW;
5980 }
5981 #endif ///HVD_ENABLE_MVC
5982
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)5983 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
5984 {
5985 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
5986 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
5987 return;
5988 }
5989
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)5990 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
5991 {
5992 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
5993 return;
5994 }
5995
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)5996 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
5997 {
5998 MS_U64 _hw_max_pixel = 0;
5999 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
6000
6001 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
6002 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
6003 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
6004 }
6005
6006
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)6007 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
6008 {
6009 #if 1
6010 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6011 MS_U16 u16QNum = pShm->u16DispQNumb;
6012 MS_U16 u16QPtr = pShm->u16DispQPtr;
6013 // MS_U16 u16QSize = pShm->u16DispQSize;
6014 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
6015 MS_U32 u32DispQNum = 0;
6016 #if HVD_ENABLE_MVC
6017 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
6018
6019 if(bMVC)
6020 {
6021 #if 0
6022 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
6023 {
6024 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
6025 }
6026 #endif
6027
6028 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
6029 //search the next frame to display
6030 while (u16QNum > 0)
6031 {
6032 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
6033 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
6034 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6035
6036 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
6037 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6038 {
6039 /// For MVC. Output views after the pair of (base and depend) views were decoded.
6040 /// Check the depned view was initial when Output the base view.
6041 if((u16QPtr%2) == 0)
6042 {
6043 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
6044 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
6045 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
6046 {
6047 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
6048 ///printf("Return NULL.\n");
6049 continue;
6050 }
6051 }
6052 u32DispQNum++;
6053 }
6054
6055 u16QNum--;
6056 //go to next frame in the dispQ
6057 u16QPtr++;
6058
6059 if (u16QPtr >= pShm->u16DispQSize)
6060 {
6061 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
6062 }
6063 }
6064 }
6065 else
6066 #endif ///HVD_ENABLE_MVC
6067 {
6068 #if 0
6069 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
6070 {
6071 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
6072 }
6073 #endif
6074 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
6075 //search the next frame to display
6076 while (u16QNum != 0)
6077 {
6078 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6079
6080 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
6081 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6082 {
6083 u32DispQNum++;
6084 }
6085
6086 u16QNum--;
6087 //go to next frame in the dispQ
6088 u16QPtr++;
6089
6090 if (u16QPtr == pShm->u16DispQSize)
6091 {
6092 u16QPtr = 0; //wrap to the begin
6093 }
6094 }
6095 }
6096
6097 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
6098 return u32DispQNum;
6099 #else
6100 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
6101 return pShm->u16DispQNumb;
6102 #endif
6103 }
6104
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)6105 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
6106 {
6107 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6108 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC)
6109 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6110 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
6111 #if SUPPORT_G2VP9 && defined(VDEC3)
6112 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
6113 #else // Not using G2 VP9 implies using Mstar EVD VP9
6114 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6115 #endif
6116 else
6117 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
6118 }
6119
6120 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)6121 void HAL_EVD_EX_PowerCtrl(MS_BOOL bEnable)
6122 {
6123 if (bEnable)
6124 {
6125 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6126 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6127 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6128 }
6129 else
6130 {
6131 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6132 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6133 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6134 }
6135
6136 switch (pHVDHalContext->u32EVDClockType)
6137 {
6138 case 576:
6139 {
6140 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6141 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6142 break;
6143 }
6144 case 532:
6145 {
6146 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
6147 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
6148 break;
6149 }
6150 case 456:
6151 {
6152 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6153 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6154 _HVD_WriteWordMask(REG_EVDPLL_LOOP_DIV_SECOND, REG_EVDPLL_LOOP_DIV_SECOND_456MHZ, REG_EVDPLL_LOOP_DIV_SECOND_MASK);
6155 }
6156 case 466:
6157 {
6158 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6159 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
6160 break;
6161 }
6162 case 480:
6163 {
6164 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
6165 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6166 break;
6167 }
6168 case 384:
6169 {
6170 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
6171 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
6172 break;
6173 }
6174 case 320:
6175 {
6176 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
6177 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
6178 break;
6179 }
6180 case 240:
6181 {
6182 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
6183 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6184 break;
6185 }
6186 case 192:
6187 {
6188 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
6189 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
6190 break;
6191 }
6192 default:
6193 {
6194 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6195 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6196 break;
6197 }
6198 }
6199
6200 return;
6201 }
6202
HAL_EVD_EX_DeinitHW(void)6203 static MS_BOOL HAL_EVD_EX_DeinitHW(void)
6204 {
6205 MS_U16 u16Timeout = 1000;
6206
6207 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
6208
6209 while (u16Timeout)
6210 {
6211 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
6212 {
6213 break;
6214 }
6215 u16Timeout--;
6216 }
6217
6218 HAL_EVD_EX_PowerCtrl(FALSE);
6219
6220 return TRUE;
6221 }
6222 #endif
6223
6224 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)6225 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
6226 {
6227 if (bEnable)
6228 {
6229 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6230 }
6231 else
6232 {
6233 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6234 }
6235
6236 switch (pHVDHalContext->u32VP9ClockType)
6237 {
6238 case 432:
6239 {
6240 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6241 break;
6242 }
6243 case 384:
6244 {
6245 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6246 break;
6247 }
6248 case 345:
6249 {
6250 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6251 break;
6252 }
6253 case 320:
6254 {
6255 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6256 break;
6257 }
6258 case 288:
6259 {
6260 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6261 break;
6262 }
6263 case 240:
6264 {
6265 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6266 break;
6267 }
6268 case 216:
6269 {
6270 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6271 break;
6272 }
6273 case 172:
6274 {
6275 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
6276 break;
6277 }
6278 default:
6279 {
6280 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6281 break;
6282 }
6283 }
6284
6285 return;
6286 }
6287
HAL_VP9_EX_DeinitHW(void)6288 MS_BOOL HAL_VP9_EX_DeinitHW(void)
6289 {
6290 MS_U16 u16Timeout = 1000;
6291
6292 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6293
6294 while (u16Timeout)
6295 {
6296 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6297 {
6298 break;
6299 }
6300 u16Timeout--;
6301 }
6302
6303 HAL_VP9_EX_PowerCtrl(FALSE);
6304
6305 return TRUE;
6306 }
6307 #endif
6308
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6309 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6310 {
6311 return TRUE;
6312 }
HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)6313 void HAL_HVD_EX_SetBufferAddr(MS_U32 u32Id)
6314 {
6315 _HVD_EX_SetBufferAddr(u32Id);
6316 }
6317
6318
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)6319 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6320 {
6321 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6322
6323 if(pCtrl->InitParams.u16ChipECONum == 0)
6324 return FALSE;
6325 else
6326 return TRUE;
6327
6328 }
6329
6330
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6331 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6332 {
6333
6334 }
6335
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6336 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6337 {
6338
6339 }
6340 #endif
6341