1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126 #define RV_VLC_TABLE_SIZE 0x20000
127 /* Add for Mobile Platform by Ted Sun */
128 //#define HVD_DISPQ_PREFETCH_COUNT 2
129 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
130 #define VPU_QMEM_BASE 0x20000000UL
131
132 //max support pixel(by chip capacity)
133 #define HVD_HW_MAX_PIXEL (3840*2160*31000ULL) // 4kx2k@30p
134 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
135 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
136
137 #if 0
138 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
139 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
140 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
141 static MS_U16 _u16DispQPtr = 0;
142 #endif
143
144 #define IS_TASK_ALIVE(id) ((id) != -1)
145 #ifndef UNUSED
146 #define UNUSED(x) (void)(x)
147 #endif
148
149
150 //---------------------------------- Mutex settings -----------------------------------------
151 #if HAL_HVD_ENABLE_MUTEX_PROTECT
152 #define _HAL_HVD_MutexCreate() \
153 do \
154 { \
155 if (s32HVDMutexID < 0) \
156 { \
157 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
158 } \
159 } while (0)
160
161 #define _HAL_HVD_MutexDelete() \
162 do \
163 { \
164 if (s32HVDMutexID >= 0) \
165 { \
166 OSAL_HVD_MutexDelete(s32HVDMutexID); \
167 s32HVDMutexID = -1; \
168 } \
169 } while (0)
170
171 #define _HAL_HVD_Entry() \
172 do \
173 { \
174 if (s32HVDMutexID >= 0) \
175 { \
176 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
177 { \
178 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
179 } \
180 } \
181 } while (0)
182
183 #define _HAL_HVD_Return(_ret_) \
184 do \
185 { \
186 if (s32HVDMutexID >= 0) \
187 { \
188 OSAL_HVD_MutexRelease(s32HVDMutexID); \
189 } \
190 return _ret_; \
191 } while(0)
192
193 #define _HAL_HVD_Release() \
194 do \
195 { \
196 if (s32HVDMutexID >= 0) \
197 { \
198 OSAL_HVD_MutexRelease(s32HVDMutexID); \
199 } \
200 } while (0)
201 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
202
203 #define _HAL_HVD_MutexCreate()
204 #define _HAL_HVD_MutexDelete()
205 #define _HAL_HVD_Entry()
206 #define _HAL_HVD_Return(_ret) {return _ret;}
207 #define _HAL_HVD_Release()
208
209 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
210
211 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
212 #define IS_TASK_ALIVE(id) ((id) != -1)
213 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
214
215 //------------------------------ MIU SETTINGS ----------------------------------
216 #define _MaskMiuReq_MVD_RW_0( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
217 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
218 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
222
223 #define _MaskMiu1Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
224 #define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
225 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
226 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
227 #define _MaskMiu1Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(3))
228 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(0))
229
230
231 #define HVD_MVD_RW_0_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0)
232 #define HVD_MVD_RW_1_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0)
233 #define HVD_MVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0)
234 #define HVD_HVD_RW_MIF0_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0)
235 #define HVD_HVD_RW_MIF1_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0)
236 #define HVD_HVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0)
237
238 #define HVD_MVD_RW_0_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == BIT(4))
239 #define HVD_MVD_RW_1_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6))
240 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
241 #define HVD_HVD_RW_MIF0_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2))
242 #define HVD_HVD_RW_MIF1_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3))
243 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0))
244
245 #if SUPPORT_EVD
246 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
247 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
248 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(4))
249 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(4))
250
251 #define HVD_EVD_RW_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0)
252 #define HVD_EVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0)
253 #define HVD_EVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4))
254 #define HVD_EVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4))
255 #endif
256
257 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
258 do \
259 { \
260 if (HVD_##miu_clients##_ON_MIU0 == 1) \
261 { \
262 _MaskMiuReq_##miu_clients(mask); \
263 } \
264 else \
265 { \
266 if (HVD_##miu_clients##_ON_MIU1 == 1) \
267 { \
268 _MaskMiu1Req_##miu_clients(mask); \
269 } \
270 } \
271 } while (0)
272
273 // check RM is supported or not
274 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
275 #ifdef VDEC3
276 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
277 #else
278 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
279 #endif
280
281 #define DIFF(a, b) (a > b ? (a-b) : (b-a)) // abs diff
282
283 //-------------------------------------------------------------------------------------------------
284 // Local Structures
285 //-------------------------------------------------------------------------------------------------
286
287 //-------------------------------------------------------------------------------------------------
288 // Local Functions Prototype
289 //-------------------------------------------------------------------------------------------------
290 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
291 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
292 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
293 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
294 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
295 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
296 static MS_U32 _HVD_EX_GetPC(void);
297 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
298 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
299 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
300 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
301 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
302 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
303 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
304 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
305 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
306 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
307 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
308 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
309 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
310 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
311 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
312 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
313 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
314 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed, MS_BOOL *isAVCUsed);
315 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable);
316 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable);
317 #if SUPPORT_EVD
318 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable);
319 #endif
320 #if SUPPORT_G2VP9 && defined(VDEC3)
321 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
322 #endif
323 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
324 #if SUPPORT_G2VP9 && defined(VDEC3)
325 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
326 #endif
327
328 //-------------------------------------------------------------------------------------------------
329 // Global Variables
330 //-------------------------------------------------------------------------------------------------
331 #if defined (__aeon__)
332 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
333 #else
334 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
335 #endif
336 #if HAL_HVD_ENABLE_MUTEX_PROTECT
337 MS_S32 s32HVDMutexID = -1;
338 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
339 #endif
340
341
342 #define HVD_EX_STACK_SIZE 4096
343 //-------------------------------------------------------------------------------------------------
344 // Local Variables
345 //-------------------------------------------------------------------------------------------------
346 typedef struct
347 {
348
349 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
350 MS_U8 g_hvd_nal_fill_pair[2][8];
351 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
352 MS_U16 _u16DispQPtr;
353 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
354
355 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
356 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
357 MS_U32 u32VPUClockType;
358 MS_U32 u32HVDClockType;//160
359 #if SUPPORT_EVD
360 MS_U32 u32EVDClockType;
361 #endif
362 #if SUPPORT_G2VP9 && defined(VDEC3)
363 MS_U32 u32VP9ClockType;
364 #endif
365 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
366
367 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
368 MS_BOOL g_RstFlag;
369 MS_U64 u64pts_real;
370 MS_PHY u32VP8BBUWptr;
371 MS_PHY u32EVDBBUWptr;
372 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
373 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
374 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
375 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
376 //pre_set
377 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
378 } HVD_Hal_CTX;
379
380 HVD_Hal_CTX* pHVDHalContext = NULL;
381 HVD_Hal_CTX gHVDHalContext;
382 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
383
384 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
385 {
386 {FALSE},
387 {FALSE},
388 {FALSE},
389 #ifdef VDEC3
390 {FALSE},
391 #endif
392 };
393
394 //-------------------------------------------------------------------------------------------------
395 // Debug Functions
396 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)397 void HVD_EX_SetRstFlag(MS_BOOL bRst)
398 {
399 pHVDHalContext->g_RstFlag = bRst;
400 }
HVD_EX_GetRstFlag(void)401 MS_BOOL HVD_EX_GetRstFlag(void)
402 {
403 return pHVDHalContext->g_RstFlag;
404 }
405
406 //-------------------------------------------------------------------------------------------------
407 // Local Functions
408 //-------------------------------------------------------------------------------------------------
409 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)410 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
411 {
412 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
413
414 if (u32CodecType == E_HVD_INIT_HW_HEVC || u32CodecType == E_HVD_INIT_HW_HEVC_DV
415 #if SUPPORT_MSVP9
416 || u32CodecType == E_HVD_INIT_HW_VP9
417 #endif
418 )
419 return TRUE;
420
421 return FALSE;
422 }
423
_HAL_EX_BBU_VP8_InUsed(void)424 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
425 {
426 if (!pHVDHalContext)
427 return FALSE;
428
429 MS_U32 i;
430 MS_BOOL bRet = FALSE;
431
432 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
433 {
434 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
435 {
436 bRet = TRUE;
437 break;
438 }
439 }
440
441 return bRet;
442 }
443
444 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
445 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)446 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
447 {
448
449 MS_U32 ret = TRUE;
450 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
451
452 if(pCtrl == NULL || pstTaskInfo == NULL)
453 return FALSE;
454
455 pstTaskInfo->u32Id = u32Id;
456
457 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
458 {
459 case E_HVD_INIT_HW_RM:
460 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
461 break;
462 case E_HVD_INIT_HW_VP8:
463 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
464 break;
465 case E_HVD_INIT_HW_MVC:
466 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
467 break;
468 case E_HVD_INIT_HW_HEVC:
469 case E_HVD_INIT_HW_HEVC_DV:
470 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
471 break;
472 #if SUPPORT_MSVP9
473 case E_HVD_INIT_HW_VP9:
474 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
475 break;
476 #endif
477 #if SUPPORT_G2VP9
478 case E_HVD_INIT_HW_VP9:
479 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
480 break;
481 #endif
482 default:
483 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
484 break;
485 }
486
487 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
488
489 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
490 {
491 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
492 }
493 else
494 {
495 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
496 }
497
498 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
499
500 #ifdef SUPPORT_EVD
501 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
502 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
503 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
504 #endif
505 return ret;
506
507 }
508
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)509 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
510 {
511 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
512 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
513 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
514 _HAL_HVD_Entry();
515
516 if(pCtrl == NULL)
517 _HAL_HVD_Return(ret);
518
519 VPU_EX_TaskInfo taskInfo;
520 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
521
522 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
523
524 taskInfo.u8HalId = u8Idx;
525 ret = HAL_VPU_EX_GetBBUId(u32Id, &taskInfo, pCtrl->bShareBBU);
526
527 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
528 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
529
530 _HAL_HVD_Return(ret);
531 }
532
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)533 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
534 {
535 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
536 MS_BOOL ret = FALSE;
537 _HAL_HVD_Entry();
538
539 if(pCtrl == NULL)
540 _HAL_HVD_Return(ret);
541 VPU_EX_TaskInfo taskInfo;
542 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
543
544 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
545
546 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
547
548 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
549 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
550
551 _HAL_HVD_Return(ret);
552 }
553
HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId)554 MS_BOOL HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId)
555 {
556 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
557 MS_BOOL ret = FALSE;
558 _HAL_HVD_Entry();
559
560 if(pCtrl == NULL)
561 _HAL_HVD_Return(ret);
562 VPU_EX_TaskInfo taskInfo;
563 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
564
565 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
566
567 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, taskInfo.eDecType);
568
569 _HAL_HVD_Return(TRUE);
570 }
571 #endif
572
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)573 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
574 {
575 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
576 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
577 pstHVDStream->s32HvdPpTaskId = -1;
578 }
579
_HVD_EX_Context_Init_HAL(void)580 static void _HVD_EX_Context_Init_HAL(void)
581 {
582 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
583 pHVDHalContext->u32VPUClockType = 432;
584 pHVDHalContext->u32HVDClockType = 384;
585 #if SUPPORT_EVD
586 pHVDHalContext->u32EVDClockType = 576;
587 #endif
588 #if SUPPORT_G2VP9 && defined(VDEC3)
589 pHVDHalContext->u32VP9ClockType = 384;
590 #endif
591 #ifdef VDEC3
592 MS_U8 i;
593
594 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
595 {
596 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
597 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
598 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
599 }
600 #else
601 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
602 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
603 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
604 #endif
605 }
606
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)607 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
608 {
609 MS_U16 u16Ret = 0;
610 #if (HVD_ENABLE_MVC || (!VDEC3))
611 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
612 #endif
613 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
614 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
615 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
616 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
617
618 #if HVD_ENABLE_MVC
619 if(HAL_HVD_EX_CheckMVCID(u32Id))
620 {
621 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
622 }
623 #endif /// HVD_ENABLE_MVC
624
625 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
626 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
627
628 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
629 {
630 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
631 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
632 }
633 else
634 #ifdef VDEC3
635 if (0 == pCtrl->u32BBUId)
636 #else
637 if (0 == u8TaskId)
638 #endif
639 {
640 //if(pCtrl->InitParams.bColocateBBUMode)
641 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
642 u16Ret = pShm->u32ColocateBBUReadPtr;
643 else
644 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
645 }
646 else
647 {
648 //if(pCtrl->InitParams.bColocateBBUMode)
649 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
650 u16Ret = pShm->u32ColocateBBUReadPtr;
651 else
652 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
653 }
654
655 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
656 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
657
658 return u16Ret;
659 }
660
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)661 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
662 {
663 MS_U16 u16Ret = 0;
664 #if (HVD_ENABLE_MVC || (!VDEC3))
665 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
666 #endif
667 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
668 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
669 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
670 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
671
672 #if HVD_ENABLE_MVC
673 if (HAL_HVD_EX_CheckMVCID(u32Id))
674 {
675 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
676 }
677 #endif /// HVD_ENABLE_MVC
678 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
679 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
680
681 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
682 {
683 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
684 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
685 }
686 else
687 #ifdef VDEC3
688 if (0 == pDrvCtrl->u32BBUId)
689 #else
690 if (0 == u8TaskId)
691 #endif
692 {
693 //if(pDrvCtrl->InitParams.bColocateBBUMode)
694 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
695 u16Ret = pShm->u32ColocateBBUWritePtr;
696 else
697 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
698 }
699 else
700 {
701 //if(pDrvCtrl->InitParams.bColocateBBUMode)
702 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
703 u16Ret = pShm->u32ColocateBBUWritePtr;
704 else
705 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
706 }
707
708 return u16Ret;
709 }
710
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)711 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
712 {
713 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
714 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
715
716 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
717 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
718 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
719 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
720 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
721 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
722 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
723 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
724 }
725
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)726 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
727 {
728 #if (HVD_ENABLE_MVC || (!VDEC3))
729 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
730 #endif
731 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
732 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
733 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
734 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
735
736 #if HVD_ENABLE_MVC
737 if (HAL_HVD_EX_CheckMVCID(u32Id))
738 {
739 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
740 }
741 #endif /// HVD_ENABLE_MVC
742
743 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
744 {
745 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
746 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
747 }
748 else
749 #ifdef VDEC3
750 if (0 == pCtrl->u32BBUId)
751 #else
752 if (0 == u8TaskId)
753 #endif
754 {
755 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
756 //if(pCtrl->InitParams.bColocateBBUMode)
757 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
758 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
759 }
760 else
761 {
762 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
763 //if(pCtrl->InitParams.bColocateBBUMode)
764 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
765 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
766 }
767
768 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
769 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
770
771 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
772 }
773
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)774 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
775 {
776 MS_BOOL bResult = TRUE;
777 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
778 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
779
780 switch (u8MBox)
781 {
782 case E_HVD_HI_0:
783 {
784 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
785 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
786 break;
787 }
788 case E_HVD_HI_1:
789 {
790 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
791 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
792 break;
793 }
794 case E_HVD_VPU_HI_0:
795 {
796 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
797 break;
798 }
799 case E_HVD_VPU_HI_1:
800 {
801 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
802 break;
803 }
804 default:
805 {
806 bResult = FALSE;
807 break;
808 }
809 }
810
811 return bResult;
812 }
813
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)814 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
815 {
816 MS_BOOL bResult = TRUE;
817 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
818 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
819
820 switch (u8MBox)
821 {
822 case E_HVD_HI_0:
823 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
824 break;
825 case E_HVD_HI_1:
826 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
827 break;
828 case E_HVD_RISC_0:
829 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
830 break;
831 case E_HVD_RISC_1:
832 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
833 break;
834 case E_HVD_VPU_HI_0:
835 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
836 break;
837 case E_HVD_VPU_HI_1:
838 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
839 break;
840 case E_HVD_VPU_RISC_0:
841 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
842 break;
843 case E_HVD_VPU_RISC_1:
844 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
845 break;
846 default:
847 break;
848 }
849
850 return bResult;
851 }
852
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)853 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
854 {
855 MS_BOOL bResult = TRUE;
856 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
857 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
858
859 switch (u8MBox)
860 {
861 case E_HVD_HI_0:
862 {
863 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
864 break;
865 }
866 case E_HVD_HI_1:
867 {
868 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
869 break;
870 }
871 case E_HVD_RISC_0:
872 {
873 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
874 break;
875 }
876 case E_HVD_RISC_1:
877 {
878 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
879 break;
880 }
881 case E_HVD_VPU_RISC_0:
882 {
883 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
884 break;
885 }
886 case E_HVD_VPU_RISC_1:
887 {
888 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
889 break;
890 }
891 default:
892 {
893 bResult = FALSE;
894 break;
895 }
896 }
897
898 return bResult;
899 }
900
901 #if 0
902 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
903 {
904 switch (u8MBox)
905 {
906 case E_HVD_RISC_0:
907 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
908 break;
909 case E_HVD_RISC_1:
910 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
911 break;
912 case E_HVD_VPU_RISC_0:
913 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
914 break;
915 case E_HVD_VPU_RISC_1:
916 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
917 break;
918 default:
919 break;
920 }
921 }
922 #endif
923
_HVD_EX_GetPC(void)924 static MS_U32 _HVD_EX_GetPC(void)
925 {
926 MS_U32 u32PC = 0;
927 u32PC = HAL_VPU_EX_GetProgCnt();
928 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
929 return u32PC;
930 }
931
_HVD_EX_GetESWritePtr(MS_U32 u32Id)932 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
933 {
934 MS_U32 u32Data = 0;
935 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
936 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
937
938 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
939 {
940 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
941
942 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
943 {
944 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
945
946 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
947 }
948 }
949 else
950 {
951 #if HVD_ENABLE_MVC
952 MS_U8 u8ViewIdx = 0;
953 if(HAL_HVD_EX_CheckMVCID(u32Id))
954 {
955 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
956 }
957 if(u8ViewIdx != 0) /// 2nd ES ptr.
958 {
959 u32Data = pShm->u32ES2WritePtr;
960 }
961 else
962 {
963 u32Data = pShm->u32ESWritePtr;
964 }
965 #else
966 u32Data = pShm->u32ESWritePtr;
967 #endif
968 }
969
970 return u32Data;
971 }
972
973 #define NAL_UNIT_LEN_BITS 21
974 #define NAL_UNIT_OFT_BITS 30
975 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
976 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
977 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
978
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)979 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
980 {
981 MS_U32 u32Data = 0;
982 MS_U8 u8TaskId = 0;
983 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
984 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
985 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
986 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
987 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
988
989 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
990 #if HVD_ENABLE_MVC
991 if(HAL_HVD_EX_CheckMVCID(u32Id))
992 {
993 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
994 }
995 #endif /// HVD_ENABLE_MVC
996
997 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
998 {
999 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
1000 {
1001 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1002 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
1003 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
1004 MS_U32 *u32Adr;
1005 MS_U32 u32Tmp;
1006
1007 if (u16ReadPtr == u16WritePtr)
1008 {
1009 u32Data = _HVD_EX_GetESWritePtr(u32Id);
1010 }
1011 else
1012 {
1013 if (u16ReadPtr)
1014 u16ReadPtr--;
1015 else
1016 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
1017
1018 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
1019
1020 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
1021 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
1022 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
1023 u32Data = u32Data | u32Tmp;
1024
1025 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
1026 //while(1);
1027 }
1028 goto EXIT;
1029 }
1030 // set reg_poll_nal_rptr 0
1031 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
1032 // set reg_poll_nal_rptr 1
1033 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
1034
1035 // read reg_nal_rptr_hi
1036 #ifdef VDEC3
1037 if (0 == pCtrl->u32BBUId)
1038 #else
1039 if (0 == u8TaskId)
1040 #endif
1041 {
1042 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
1043 u32Data >>= 6;
1044 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
1045 }
1046 else
1047 {
1048 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
1049 u32Data >>= 6;
1050 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
1051 }
1052
1053 u32Data <<= 3; // unit
1054
1055 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1056 {
1057 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1058
1059 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1060 {
1061 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1062 u32Data = u32ESWptr;
1063 }
1064 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1065 {
1066 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1067 u32Data = u32ESWptr;
1068 }
1069 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1070 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1071 {
1072 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1073 u32Data = u32ESWptr;
1074 }
1075 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1076 && ((u32Data - u32ESWptr) < 32)
1077 && (pCtrl->u32FlushRstPtr == 1))
1078 {
1079 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1080 u32Data = u32ESWptr;
1081 }
1082 }
1083
1084 // remove illegal pointer
1085 #if 1
1086 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1087 {
1088 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1089
1090 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1091 (u32PacketStaddr <
1092 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1093 {
1094 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1095 u32Data = pCtrl->u32LastESRptr;
1096 }
1097 }
1098 #endif
1099 }
1100 else
1101 {
1102 #if HVD_ENABLE_MVC
1103 MS_U8 u8ViewIdx = 0;
1104 if(HAL_HVD_EX_CheckMVCID(u32Id))
1105 {
1106 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1107 }
1108 if(u8ViewIdx != 0) /// 2nd ES ptr.
1109 {
1110 u32Data = pShm->u32ES2ReadPtr;
1111 }
1112 else
1113 {
1114 u32Data = pShm->u32ESReadPtr;
1115 }
1116 #else
1117 u32Data = pShm->u32ESReadPtr;
1118 #endif
1119 }
1120
1121 EXIT:
1122
1123 pCtrl->u32LastESRptr = u32Data;
1124
1125 return u32Data;
1126 }
1127
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1128 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1129 {
1130 MS_U16 u16TimeOut = 0xFFFF;
1131 MS_BOOL bResult = FALSE;
1132
1133 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
1134
1135 while (--u16TimeOut)
1136 {
1137 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1138 {
1139 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1140 break;
1141 }
1142 }
1143
1144 return bResult;
1145 }
1146
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1147 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1148 {
1149 MS_U16 u16TimeOut = 0xFFFF;
1150 MS_BOOL bResult = FALSE;
1151 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1152
1153 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
1154
1155 #if HVD_ENABLE_MVC
1156 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1157 {
1158 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1159 }
1160 #endif /// HVD_ENABLE_MVC
1161
1162 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1163
1164 while (--u16TimeOut)
1165 {
1166 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1167 {
1168 u32Cmd |= (u8TaskId << 24);
1169 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1170 break;
1171 }
1172 }
1173 return bResult;
1174 }
1175
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)1176 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
1177 {
1178 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1179 #ifdef VDEC3
1180 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1181 MS_BOOL IsSent = FALSE;
1182 MS_BOOL IsMailBox = FALSE;
1183 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1184
1185 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
1186 {
1187 do {
1188 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1189 if (!SentRet)
1190 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1191 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1192 break;
1193 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1194 IsSent = TRUE;
1195 break;
1196 }
1197 else if (HVD_GetSysTime_ms() > u32timeout)
1198 {
1199 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1200 break;
1201 }
1202 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1203 }
1204 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
1205 {
1206 do {
1207 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1208 if (!SentRet)
1209 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1210 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1211 break;
1212 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1213 IsSent = TRUE;
1214 break;
1215 }
1216 else if (HVD_GetSysTime_ms() > u32timeout)
1217 {
1218 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1219 break;
1220 }
1221 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1222 }
1223 if (!IsSent)
1224 {
1225 IsMailBox = TRUE;
1226 u32timeout = HVD_GetSysTime_ms() + HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT;//pHVDHalContext->u32HVDCmdTimeout;
1227 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1228 #else
1229 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1230 #endif
1231 {
1232 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1233 if (HVD_GetSysTime_ms() > u32timeout)
1234 {
1235 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1236 return E_HVD_RETURN_TIMEOUT;
1237 }
1238 //#endif
1239
1240 #if 0
1241 if (u32Cmd == E_HVD_CMD_STOP)
1242 {
1243 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1244 #if HVD_ENABLE_MVC
1245 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1246 {
1247 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1248 }
1249 #endif /// HVD_ENABLE_MVC
1250 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1251
1252 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1253 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1254
1255 return E_HVD_RETURN_SUCCESS;
1256 }
1257 #endif
1258
1259 if(u32Cmd < E_DUAL_CMD_BASE)
1260 {
1261 //_HVD_EX_GetPC();
1262 HAL_HVD_EX_Dump_FW_Status(u32Id);
1263 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1264 }
1265 }
1266
1267 #ifdef VDEC3
1268 }
1269 IsSent = FALSE;
1270 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1271 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
1272 {
1273 do {
1274 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1275 if (!SentRet)
1276 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1277 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1278 break;
1279 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1280 IsSent = TRUE;
1281 break;
1282 }
1283 else if (HVD_GetSysTime_ms() > u32timeout)
1284 {
1285 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1286 break;
1287 }
1288 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1289 }
1290 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
1291 {
1292 do {
1293 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1294 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1295 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1296 }
1297 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1298 break;
1299 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1300 IsSent = TRUE;
1301 break;
1302 }
1303 else if (HVD_GetSysTime_ms() > u32timeout)
1304 {
1305 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1306 break;
1307 }
1308 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1309 }
1310 if (!IsSent)
1311 {
1312 u32timeout = HVD_GetSysTime_ms() + HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT;//pHVDHalContext->u32HVDCmdTimeout;
1313 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1314 #else
1315 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1316
1317 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1318 #endif
1319 {
1320 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1321 if (HVD_GetSysTime_ms() > u32timeout)
1322 {
1323 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
1324 return E_HVD_RETURN_TIMEOUT;
1325 }
1326 //#endif
1327 if(u32Cmd < E_DUAL_CMD_BASE)
1328 {
1329 //_HVD_EX_GetPC();
1330 HAL_HVD_EX_Dump_FW_Status(u32Id);
1331 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1332 }
1333 }
1334 #ifdef VDEC3
1335 }
1336 else
1337 {
1338 HAL_HVD_EX_FlushMemory();
1339 }
1340 #endif
1341 return E_HVD_RETURN_SUCCESS;
1342 }
1343
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)1344 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
1345 {
1346 #if HAL_HVD_ENABLE_MIU_PROTECT
1347 _HVD_MIU_SetReqMask(MVD_RW_0, bEnable);
1348 _HVD_MIU_SetReqMask(MVD_RW_1, bEnable);
1349 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1350 #if SUPPORT_EVD
1351 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
1352 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1353 #endif
1354 _HVD_MIU_SetReqMask(HVD_RW_MIF0, bEnable);
1355 _HVD_MIU_SetReqMask(HVD_RW_MIF1, bEnable);
1356 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1357 HAL_VPU_EX_MIU_RW_Protect(bEnable);
1358 //HVD_Delay_ms(1);
1359 #endif
1360 return;
1361 }
1362
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1363 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1364 {
1365 MS_U16 u16Reg = 0;
1366 MS_VIRT u32StAddr = 0;
1367 #ifdef VDEC3
1368 MS_U32 u32Length = 0;
1369 #endif
1370 MS_U8 u8BitMiuSel = 0;
1371 MS_U8 u8CodeMiuSel = 0;
1372 MS_U8 u8FBMiuSel = 0;
1373 MS_U8 u8TmpMiuSel = 0;
1374
1375 MS_U32 u32BitStartOffset;
1376 MS_U32 u32CodeStartOffset;
1377 MS_U32 u32FBStartOffset;
1378
1379 #ifndef VDEC3
1380 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1381 #endif
1382 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1383 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1384 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1385
1386 _HAL_HVD_Entry();
1387
1388 if (pCtrl == NULL)
1389 {
1390 _HAL_HVD_Return();
1391 }
1392
1393 MS_BOOL bESBufferAlreadySet = FALSE;
1394 VPU_EX_TaskInfo taskInfo;
1395 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1396
1397 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
1398
1399 bESBufferAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
1400
1401
1402
1403 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1404 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1405 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1406
1407 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1408 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1409 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1410 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1411 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1412 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1413 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1414 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1415 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1416 (u8FBMiuSel << VDEC_PPIN_MIUSEL) |
1417 (u8FBMiuSel << VDEC_XCSHM_MIUSEL));
1418
1419 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1420 {
1421 // ES buffer
1422 #ifdef VDEC3
1423 if(pCtrl->bShareBBU)
1424 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1425 else
1426 #endif
1427 u32StAddr = u32BitStartOffset;
1428
1429 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1430
1431 #ifdef VDEC3
1432 if (!_HAL_EX_BBU_VP8_InUsed())
1433 #endif
1434 {
1435 HVD_EX_MSG_DBG("ESB start addr=%lx\n", (unsigned long)u32StAddr);
1436
1437 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1438 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1439
1440 #ifdef VDEC3
1441 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1442 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1443 #else
1444 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1445 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1446 #endif
1447
1448 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1449 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1450 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1451 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1452 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1453 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1454 }
1455
1456 _HAL_HVD_Return();
1457 }
1458
1459 // ES buffer
1460 #ifdef VDEC3
1461 if(!pCtrl->bShareBBU || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1462 {
1463 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1464 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1465 }
1466 else
1467 {
1468 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1469 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1470 }
1471 #else
1472 u32StAddr = u32BitStartOffset;
1473 #endif
1474
1475 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1476
1477 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1478
1479 #ifdef VDEC3
1480 if (!bESBufferAlreadySet)
1481 {
1482 if (pCtrl->u32BBUId == 0)
1483 {
1484 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1485 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1486
1487 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1488 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1489 }
1490 else
1491 {
1492 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1493 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1494
1495 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1496 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1497 }
1498 }
1499 #else
1500 if (0 == u8TaskId)
1501 {
1502 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1503 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1504
1505 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1506 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1507 }
1508 else
1509 {
1510 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1511 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1512
1513 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1514 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1515 }
1516 #endif
1517
1518 // others
1519 #ifdef VDEC3
1520 if (!bESBufferAlreadySet)
1521 {
1522 if (pCtrl->u32BBUId == 0)
1523 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1524 else
1525 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1526
1527 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1528 {
1529 if (pCtrl->u32BBUId == 0)
1530 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1531 else
1532 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1533 }
1534 else
1535 {
1536 if (pCtrl->u32BBUId == 0)
1537 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1538 else
1539 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1540 }
1541
1542 // do not set parsing setting in DRV, and we set it in FW (hvd_switch_bbu)
1543 if (pCtrl->u32BBUId == 0)
1544 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1545 else
1546 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1547
1548 if (pCtrl->u32BBUId == 0)
1549 {
1550 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1551 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1552 }
1553 else
1554 {
1555 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1556 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1557 }
1558 }
1559 #else
1560 if (0 == u8TaskId)
1561 {
1562 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1563
1564 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1565 {
1566 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1567 }
1568 else
1569 {
1570 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1571 }
1572
1573 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1574
1575 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1576 {
1577 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1578 }
1579 else // AVS or AVC
1580 {
1581 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1582 {
1583 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1584 }
1585 else // start code remained
1586 {
1587 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1588 }
1589 }
1590
1591 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1592
1593 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1594 }
1595 else
1596 {
1597 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1598
1599 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1600 {
1601 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1602 }
1603 else
1604 {
1605 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1606 }
1607
1608 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1609
1610 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1611 {
1612 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1613 }
1614 else // AVS or AVC
1615 {
1616 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1617 {
1618 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1619 }
1620 else // start code remained
1621 {
1622 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1623 }
1624 }
1625
1626 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1627
1628 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1629 }
1630 #endif
1631
1632 #if (HVD_ENABLE_MVC)
1633 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1634 {
1635 /// Used sub stream to record sub view data.
1636 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1637 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1638
1639 // ES buffer
1640 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1641
1642 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1643 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1644 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1645
1646 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1647 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1648
1649 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1650 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1651 {
1652 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1653 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1654 }
1655 else
1656 {
1657 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1658 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1659 }
1660 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1661 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1662 {
1663 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1664 }
1665 else // AVS or AVC
1666 {
1667 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1668 {
1669 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1670 }
1671 else // start code remained
1672 {
1673 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1674 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1675 }
1676 }
1677 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1678 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1679 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1680 }
1681 #endif
1682
1683 // MIF offset
1684 #if 0
1685 {
1686 MS_U16 offaddr = 0;
1687 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1688 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1689 {
1690 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1691 }
1692 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1693 offaddr = (MS_U16) ((u32StAddr) >> 20);
1694 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1695 //0x1FF; // 9 bits(L + H)
1696 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1697 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1698 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1699 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1700 {
1701 u16Reg |= HVD_REG_MIF_OFFSET_H;
1702 }
1703 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1704 }
1705 #endif
1706
1707 if (!bESBufferAlreadySet)
1708 {
1709 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
1710 }
1711
1712 _HAL_HVD_Return();
1713 }
1714
1715 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1716 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1717 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1718 {
1719 MS_U16 u16Reg = 0;
1720 MS_U32 u32StAddr = 0;
1721 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1722 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1723 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1724
1725 if(pCtrl == NULL) return;
1726
1727 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1728 {
1729 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1730
1731 // ES buffer
1732 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1733
1734 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1735 {
1736 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1737 }
1738
1739 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1740 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1741
1742 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1743 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1744
1745 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1746 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1747 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1748 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1749 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1750 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1751
1752 return;
1753 }
1754
1755 // ES buffer
1756 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1757
1758 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1759 {
1760 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1761 }
1762
1763 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1764
1765 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1766 {
1767 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1768 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1769
1770 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1771 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1772 }
1773 else
1774 {
1775 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1776 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1777
1778 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1779 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1780 }
1781 }
1782 #endif
1783
_HVD_EX_GetESLevel(MS_U32 u32Id)1784 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1785 {
1786 MS_U32 u32Wptr = 0;
1787 MS_U32 u32Rptr = 0;
1788 MS_U32 u32CurMBX = 0;
1789 MS_U32 u32ESsize = 0;
1790 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1791 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1792
1793 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1794 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1795 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1796
1797 if (u32Rptr >= u32Wptr)
1798 {
1799 u32CurMBX = u32Rptr - u32Wptr;
1800 }
1801 else
1802 {
1803 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1804 }
1805
1806 if (u32CurMBX == 0)
1807 {
1808 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1809 }
1810 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1811 {
1812 u32Ret = E_HVD_ESB_LEVEL_OVER;
1813 }
1814 else
1815 {
1816 u32CurMBX = u32ESsize - u32CurMBX;
1817 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1818 {
1819 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1820 }
1821 }
1822
1823 return u32Ret;
1824 }
1825
_HVD_EX_GetESQuantity(MS_U32 u32Id)1826 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1827 {
1828 MS_U32 u32Wptr = 0;
1829 MS_U32 u32Rptr = 0;
1830 MS_U32 u32ESsize = 0;
1831 MS_U32 u32Ret = 0;
1832 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1833
1834 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1835 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1836 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1837
1838
1839 if(u32Wptr >= u32Rptr)
1840 {
1841 u32Ret = u32Wptr - u32Rptr;
1842 }
1843 else
1844 {
1845 u32Ret = u32ESsize - u32Rptr + u32Wptr;
1846 }
1847 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
1848 return u32Ret;
1849 }
1850
1851 #if (HVD_ENABLE_IQMEM)
HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)1852 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
1853 {
1854
1855 MS_U32 u32Timeout = 20000;
1856
1857 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
1858 {
1859
1860 HAL_VPU_EX_IQMemSetDAMode(TRUE);
1861
1862 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
1863
1864
1865 while (u32Timeout)
1866 {
1867
1868 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
1869 {
1870 break;
1871 }
1872 u32Timeout--;
1873 HVD_Delay_ms(1);
1874 }
1875
1876 HAL_VPU_EX_IQMemSetDAMode(FALSE);
1877
1878 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
1879
1880 if (u32Timeout==0)
1881 {
1882 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
1883 return FALSE;
1884 }
1885
1886
1887 }
1888 return TRUE;
1889 }
1890
1891 #endif
1892
1893 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)1894 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
1895 #else
1896 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
1897 #endif
1898 {
1899 MS_U32 u32FirmVer = 0;
1900 MS_U32 u32Timeout = 20000;
1901 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1902
1903 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
1904
1905 #if HVD_ENABLE_TIME_MEASURE
1906 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
1907 #endif
1908
1909 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
1910
1911 VPU_EX_FWCodeCfg fwCfg;
1912 VPU_EX_TaskInfo taskInfo;
1913 VPU_EX_VLCTblCfg vlcCfg;
1914 #ifdef VDEC3
1915 VPU_EX_FBCfg fbCfg;
1916 #endif
1917 VPU_EX_NDecInitPara nDecInitPara;
1918
1919 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
1920 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1921 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
1922 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
1923 #ifdef VDEC3_FB
1924 nDecInitPara.pVLCCfg = NULL;
1925 #else
1926 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
1927 {
1928 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
1929 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
1930 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
1931 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
1932 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
1933 nDecInitPara.pVLCCfg = &vlcCfg;
1934 }
1935 #endif
1936 nDecInitPara.pFWCodeCfg = &fwCfg;
1937 nDecInitPara.pTaskInfo = &taskInfo;
1938 #ifdef VDEC3
1939 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
1940 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
1941
1942 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1943 {
1944 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1945 }
1946
1947 nDecInitPara.pFBCfg = &fbCfg;
1948 #endif
1949
1950 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
1951 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
1952 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
1953 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
1954 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
1955
1956 taskInfo.u32Id = u32Id;
1957
1958 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1959 {
1960 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
1961 }
1962 #ifdef VDEC3
1963 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
1964 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
1965 {
1966 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
1967 }
1968 #if SUPPORT_MSVP9
1969 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
1970 {
1971 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
1972 }
1973 #endif
1974 #if SUPPORT_G2VP9
1975 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
1976 {
1977 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
1978 }
1979 #endif
1980 #endif
1981 else
1982 {
1983 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
1984 }
1985
1986 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
1987
1988 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1989 {
1990 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
1991 }
1992 else
1993 {
1994 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
1995 }
1996 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
1997
1998 #ifdef SUPPORT_EVD
1999 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2000 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2001 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2002 #endif
2003
2004 if(TRUE == HVD_EX_GetRstFlag())
2005 {
2006 //Delete task for Rst
2007 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2008 {
2009 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2010 }
2011 HVD_EX_SetRstFlag(FALSE);
2012 }
2013
2014 #if (HVD_ENABLE_IQMEM)
2015 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2016 #endif
2017
2018 #ifdef VDEC3
2019 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2020 #else
2021 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2022 #endif
2023 {
2024 HVD_EX_MSG_ERR("Task create fail!\n");
2025
2026 return FALSE;
2027 }
2028
2029 while (u32Timeout)
2030 {
2031 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2032
2033 if (u32FirmVer != 0)
2034 {
2035 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2036 break;
2037 }
2038 u32Timeout--;
2039 HVD_Delay_ms(1);
2040 }
2041
2042 #ifdef VDEC3_FB
2043 #if HVD_ENABLE_RV_FEATURE
2044 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2045
2046 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2047 {
2048 if(pShm->u32RM_VLCTableAddr == 0) {
2049 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2050 }
2051 else
2052 {
2053 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2054 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2055 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2056 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2057 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2058 nDecInitPara.pVLCCfg = &vlcCfg;
2059 }
2060 }
2061
2062 if (nDecInitPara.pVLCCfg)
2063 {
2064 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2065 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2066 {
2067 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2068 return FALSE;
2069 }
2070 }
2071 #endif
2072 #endif
2073 if (u32Timeout > 0)
2074 {
2075 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2076
2077 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2078
2079 #ifdef VDEC3
2080 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2081 {
2082 case E_HVD_INIT_HW_AVC:
2083 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2084 break;
2085 case E_HVD_INIT_HW_AVS:
2086 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2087 break;
2088 case E_HVD_INIT_HW_RM:
2089 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2090 break;
2091 case E_HVD_INIT_HW_MVC:
2092 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2093 break;
2094 case E_HVD_INIT_HW_VP8:
2095 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2096 break;
2097 case E_HVD_INIT_HW_MJPEG:
2098 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2099 break;
2100 case E_HVD_INIT_HW_VP6:
2101 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2102 break;
2103 case E_HVD_INIT_HW_HEVC:
2104 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2105 break;
2106 case E_HVD_INIT_HW_VP9:
2107 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2108 break;
2109 case E_HVD_INIT_HW_HEVC_DV:
2110 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC_DV;
2111 break;
2112 default:
2113 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2114 break;
2115 }
2116 #endif
2117
2118 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2119 }
2120 else
2121 {
2122 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2123 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2124
2125 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2126 {
2127 HVD_EX_MSG_ERR("Task delete fail!\n");
2128 }
2129
2130 return FALSE;
2131 }
2132
2133
2134
2135 #if (HVD_ENABLE_IQMEM)
2136
2137 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
2138 {
2139
2140 HAL_HVD_EX_IQMem_Init(u32Id);
2141 }
2142 else{
2143 HVD_EX_MSG_DBG("not support IQMEM\n");
2144 }
2145 #endif
2146
2147
2148
2149
2150
2151
2152 #if HVD_ENABLE_TIME_MEASURE
2153 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2154 #endif
2155
2156 return TRUE;
2157 }
2158
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2159 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2160 {
2161 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2162 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2163 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2164 {
2165 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2166 }
2167 else
2168 {
2169 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2170 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2171 }
2172 }
2173
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2174 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2175 {
2176 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2177 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2178
2179 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2180 {
2181 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2182 }
2183 else
2184 {
2185 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2186 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2187 }
2188 }
2189
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2190 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2191 {
2192 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2193 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2194
2195 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2196 {
2197 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2198 {
2199 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2200 }
2201 }
2202 else
2203 {
2204 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2205 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2206 }
2207 }
2208
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2209 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2210 {
2211 MS_VIRT u32PTSWptr = HVD_U32_MAX;
2212 MS_VIRT u32PTSRptr = HVD_U32_MAX;
2213 MS_VIRT u32DestAddr = 0;
2214 HVD_PTS_Entry PTSEntry;
2215 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2216 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2217 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2218
2219 // update R & W ptr
2220 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2221
2222 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
2223
2224 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2225 {
2226 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
2227 (MS_U32) MAX_PTS_TABLE_SIZE);
2228 return E_HVD_RETURN_FAIL;
2229 }
2230
2231 // check queue is full or not
2232 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2233 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2234
2235 if (u32PTSWptr == u32PTSRptr)
2236 {
2237 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
2238 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2239 return E_HVD_RETURN_FAIL;
2240 }
2241
2242 // add one PTS entry
2243 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2244 PTSEntry.u32ID_L = pInfo->u32ID_L;
2245 PTSEntry.u32ID_H = pInfo->u32ID_H;
2246 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2247
2248 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2249
2250 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
2251
2252 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2253
2254 HAL_HVD_EX_FlushMemory();
2255
2256 // update Write ptr
2257 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2258
2259 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2260
2261 return E_HVD_RETURN_SUCCESS;
2262 }
2263
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2264 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2265 {
2266 //---------------------------------------------------
2267 // item format in nal table:
2268 // reserved |borken| u32NalOffset | u32NalLen
2269 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2270 //---------------------------------------------------
2271 MS_VIRT u32Adr = 0;
2272 MS_U32 u32BBUNewWptr = 0;
2273 MS_U8 item[8];
2274 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2275 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2276 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2277 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2278
2279 #if HVD_ENABLE_MVC
2280 if(HAL_HVD_EX_CheckMVCID(u32Id))
2281 {
2282 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2283 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2284 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2285 {
2286 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2287 }
2288 }
2289 #endif /// HVD_ENABLE_MVC
2290
2291 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2292 {
2293 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
2294 }
2295 else
2296 {
2297 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2298 }
2299 u32BBUNewWptr++;
2300 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
2301
2302 // prepare nal entry
2303
2304 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
2305 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2306 {
2307 // NAL len 22 bits , HEVC level5 constrain
2308 item[0] = u32NalLen & 0xff;
2309 item[1] = (u32NalLen >> 8) & 0xff;
2310 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2311 item[3] = (u32NalOffset >> 2) & 0xff;
2312 item[4] = (u32NalOffset >> 10) & 0xff;
2313 item[5] = (u32NalOffset >> 18) & 0xff;
2314 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2315 item[7] = 0;
2316 }
2317 else
2318 {
2319 item[0] = u32NalLen & 0xff;
2320 item[1] = (u32NalLen >> 8) & 0xff;
2321 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2322 item[3] = (u32NalOffset >> 3) & 0xff;
2323 item[4] = (u32NalOffset >> 11) & 0xff;
2324 item[5] = (u32NalOffset >> 19) & 0xff;
2325 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2326 item[7] = 0;
2327 }
2328
2329 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2330 {
2331 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
2332 }
2333 else
2334 {
2335 // add nal entry
2336 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2337 }
2338
2339 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2340
2341 HAL_HVD_EX_FlushMemory();
2342
2343 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2344
2345 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2346 {
2347 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
2348 }
2349 else
2350 {
2351 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2352 }
2353
2354 return E_HVD_RETURN_SUCCESS;
2355 }
2356
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2357 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2358 {
2359 MS_U8 item[8];
2360 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2361 MS_VIRT u32Adr = 0;
2362 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2363 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2364 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2365
2366 /*
2367 printf("nal2 offset=0x%x, len=0x%x\n",
2368 u32NalOffset2, u32NalLen2);
2369 */
2370
2371 item[0] = u32NalLen2 & 0xff;
2372 item[1] = (u32NalLen2 >> 8) & 0xff;
2373 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2374 item[3] = (u32NalOffset2 >> 3) & 0xff;
2375 item[4] = (u32NalOffset2 >> 11) & 0xff;
2376 item[5] = (u32NalOffset2 >> 19) & 0xff;
2377 item[6] = (u32NalOffset2 >> 27) & 0x07;
2378 item[7] = 0;
2379
2380 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2381 {
2382 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
2383 }
2384 else
2385 {
2386 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2387 }
2388
2389 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2390
2391 HAL_HVD_EX_FlushMemory();
2392
2393 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2394 }
2395
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2396 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2397 {
2398 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2399 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2400
2401 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2402 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
2403 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
2404 {
2405 MS_U16 i;
2406 MS_PHY u32VUIAddr;
2407 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
2408
2409 HAL_HVD_EX_ReadMemory();
2410 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2411
2412 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2413 {
2414 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2415 {
2416 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2417 }
2418 else
2419 {
2420 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2421 }
2422 pData++;
2423 }
2424 }
2425 else
2426 {
2427 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2428 }
2429
2430 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
2431 }
2432
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2433 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2434 {
2435 MS_U32 u32ReadPtr = 0;
2436 MS_U32 eRet = 0;
2437 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2438 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2439
2440 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2441 MS_U32 u32WritePtr = 0;
2442
2443 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2444 {
2445 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
2446 }
2447 else
2448 {
2449 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2450 }
2451
2452 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
2453
2454 if (u32WritePtr >= u32ReadPtr)
2455 {
2456 eRet = u32WritePtr - u32ReadPtr;
2457 }
2458 else
2459 {
2460 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2461 }
2462
2463 #if 0
2464 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2465 {
2466 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2467 }
2468 else
2469 {
2470 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2471 }
2472
2473 #endif
2474 return eRet;
2475 }
2476
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2477 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2478 {
2479 MS_U32 u32ReadPtr = 0;
2480 MS_U32 eRet = 0;
2481 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2482
2483 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2484
2485 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2486 {
2487 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
2488 (MS_U32) MAX_PTS_TABLE_SIZE);
2489 return 0;
2490 }
2491
2492 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2493
2494 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2495 {
2496 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2497 }
2498 else
2499 {
2500 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2501 }
2502
2503 return eRet;
2504 }
2505
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)2506 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
2507 {
2508 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2509
2510 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
2511 }
2512
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2513 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2514 {
2515 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2516 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2517 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2518 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2519 HAL_HVD_EX_ReadMemory();
2520 MS_U16 u16QNum = pShm->u16DispQNumb;
2521 MS_U16 u16QPtr = pShm->u16DispQPtr;
2522
2523 HVD_Frm_Information *pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2524 if (bDolbyVision)
2525 {
2526 if (pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone && u16QNum < 4) // first time we need to wait 4 pic to ensure we got the correct layer type
2527 {
2528 return NULL;
2529 }
2530 else
2531 {
2532 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = FALSE;
2533 }
2534 }
2535
2536 #if (HVD_ENABLE_MVC)
2537 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2538 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
2539 {
2540 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2541 {
2542 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
2543 MS_U16 u16UsedFrm = 0;
2544 MS_U16 u16ResvFrmNum = ((u16RealQPtr % 2) == 0) ? 1 : 0; // need to check the next frame num is exist when get first frame.
2545 if (u16RealQPtr != u16QPtr)
2546 {
2547 if (u16RealQPtr > u16QPtr)
2548 {
2549 u16UsedFrm = u16RealQPtr - u16QPtr;
2550 }
2551 else
2552 {
2553 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2554 }
2555 }
2556
2557 if (u16QNum > (u16UsedFrm + u16ResvFrmNum))
2558 {
2559 u16QNum -= u16UsedFrm;
2560 u16QPtr = u16RealQPtr;
2561 pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2562
2563 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2564 {
2565 if ((u16QPtr % 2) == 0)
2566 {
2567 HVD_Frm_Information *pHvdFrmNext = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr + 1];
2568
2569 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2570 {
2571 return NULL;
2572 }
2573
2574 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2575 if(bDolbyVision)
2576 {
2577 HVD_PRINT("BL pts: %d, u16QPtr: %d, u16QNum:%d, u32PrivateData:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2578 }
2579 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2580 }
2581 else
2582 {
2583 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2584 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
2585 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2586 HVD_Frm_Information *pHvdFrmPrv = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr - 1]; // must be odd
2587
2588 if(bDolbyVision)
2589 {
2590 HVD_PRINT("EL pts: %d, u16QPtr: %d, u16QNum:%d, uid:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2591 #if 0 // dump dolby metadata calculated by FW
2592 unsigned char *dump_addr = (unsigned char *)((void *)pShm + pShm->u32HVD_DBG_DUMP_ADDR - (u8Idx * 0x100000 + HVD_SHARE_MEM_ST_OFFSET));
2593 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2594 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2595 unsigned int i = 0;
2596 unsigned char arr[33] = {0};
2597 if(pVsyncBridgeExt != NULL)
2598 {
2599 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[u16QPtr]);
2600 }
2601 dump_addr += 32 * pFrmInfoExt->u8CurrentIndex;
2602 for (i = 0; i < 32; i++)
2603 {
2604 arr[i] = *(dump_addr + i);
2605 }
2606 HVD_PRINT("[md5]%d=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x %02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x", (unsigned int)pFrmInfoExt->u8CurrentIndex, arr[0], arr[1], arr[2], arr[3], arr[4], arr[5], arr[6], arr[7], arr[8], arr[9], arr[10], arr[11], arr[12], arr[13], arr[14], arr[15], arr[16], arr[17], arr[18], arr[19], arr[20], arr[21], arr[22], arr[23], arr[24], arr[25], arr[26], arr[27], arr[28], arr[29], arr[30], arr[31]);
2607 #endif
2608 HVD_Frm_Information *pPrevHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr - 1];//BL
2609 if(DIFF(pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp) > 1000)
2610 HVD_EX_MSG_ERR("BL pts: %d, EL pts: %d matched failed!!\n",pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp);
2611 }
2612 pHvdFrmPrv->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2613 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2614 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2615 }
2616 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2617 u16QPtr++;
2618 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2619 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2620
2621 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2622 }
2623 }
2624
2625 return NULL;
2626 }
2627
2628 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2629 //search the next frame to display
2630 while (u16QNum > 0)
2631 {
2632 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2633 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2634 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2635
2636 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2637 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2638 {
2639 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2640 /// Check the depned view was initial when Output the base view.
2641 if((u16QPtr%2) == 0)
2642 {
2643 HVD_Frm_Information *pHvdFrm_sub = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2644 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2645 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2646 {
2647 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2648 ///printf("Return NULL.\n");
2649 return NULL;
2650 }
2651 }
2652
2653 //printf("V:%d.\n",u16QPtr);
2654 pHVDHalContext->_u16DispQPtr = u16QPtr;
2655 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2656 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2657 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2658 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2659 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2660 }
2661
2662 u16QNum--;
2663 //go to next frame in the dispQ
2664 u16QPtr++;
2665
2666 if (u16QPtr >= pShm->u16DispQSize)
2667 {
2668 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2669 }
2670 }
2671 }
2672 else
2673 #endif ///HVD_ENABLE_MVC
2674 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
2675 if (_HVD_EX_IsHevcInterlaceField(u32Id))
2676 {
2677 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
2678 HVD_Frm_Information *pHvdFrm_first = NULL;
2679
2680 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
2681 return NULL;
2682 }
2683
2684 while (u16QNum != 0)
2685 {
2686 pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2687 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2688 {
2689 if (!first_field) // second get frame, we will check at least one paired in disp queue.
2690 {
2691 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2692 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2693 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
2694
2695 if(pHvdFrm->u8FieldType == EVD_TOP_FIELD || pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
2696 pHvdFrm->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
2697 else
2698 pHvdFrm->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
2699 return pHvdFrm;
2700 }
2701 else // first get frame, we will check at least one paired in disp queue.
2702 {
2703 if (pHvdFrm_first == NULL)
2704 {
2705 pHvdFrm_first = pHvdFrm;
2706 }
2707 else
2708 {
2709 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2710 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
2711
2712 //After flush, we cannot get the correct field type of first field from sei, so we use second field type to decide first field type.
2713 if (pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 0xff)
2714 {
2715 if (pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV)
2716 pHvdFrm_first->u8FieldType = EVD_BOTTOM_WITH_NEXT;
2717 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_PREV)
2718 pHvdFrm_first->u8FieldType = EVD_TOP_WITH_NEXT;
2719 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_PREV)
2720 pHvdFrm_first->u8FieldType = EVD_TOP_WITH_NEXT;
2721 else if (pHvdFrm->u8FieldType == EVD_TOP_FIELD)
2722 pHvdFrm_first->u8FieldType = EVD_BOTTOM_FIELD;
2723 else if (pHvdFrm->u8FieldType == EVD_BOTTOM_FIELD)
2724 pHvdFrm_first->u8FieldType = EVD_TOP_FIELD;
2725 else
2726 {
2727 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2728 return NULL;
2729 }
2730 if ((pHvdFrm_first->u32ID_L >> 16) & 0x1)
2731 pHvdFrm_first->u32ID_L |= (1 << 16);
2732 else
2733 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2734 }
2735 else if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV)
2736 {
2737 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV && pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_NEXT)
2738 {
2739 pHvdFrm_first->u32ID_L |= (1 << 16);
2740 pHvdFrm->u32ID_L |= (1 << 16);
2741 }
2742 else if (pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV && pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
2743 {
2744 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2745 pHvdFrm->u32ID_L &= (~(1 << 16));
2746 }
2747 else
2748 {
2749 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2750 return NULL;
2751 }
2752 }
2753 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
2754 if (pHvdFrm_first->u8FieldType == EVD_TOP_FIELD || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_NEXT)
2755 pHvdFrm_first->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
2756 else
2757 pHvdFrm_first->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
2758 return pHvdFrm_first;
2759 }
2760 }
2761 }
2762 u16QNum--;
2763 //go to next frame in the dispQ
2764 u16QPtr++;
2765
2766 if (u16QPtr == pShm->u16DispQSize)
2767 {
2768 u16QPtr = 0; //wrap to the begin
2769 }
2770
2771 }
2772 return NULL;
2773 }
2774 else
2775 {
2776 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2777 {
2778
2779 while (u16QNum != 0)
2780 {
2781 pHvdFrm = (HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
2782
2783 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2784 {
2785 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2786 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2787 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2788 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2789 }
2790 u16QNum--;
2791 //go to next frame in the dispQ
2792 if (bDolbyVision)
2793 u16QPtr += 2; // single layer must in even ptr
2794 else
2795 u16QPtr++;
2796
2797 if (u16QPtr >= pShm->u16DispQSize)
2798 {
2799 u16QPtr = 0; //wrap to the begin
2800 }
2801 }
2802
2803 return NULL;
2804 }
2805
2806 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2807 //search the next frame to display
2808 while (u16QNum != 0)
2809 {
2810 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2811
2812 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2813 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2814 {
2815 pHVDHalContext->_u16DispQPtr = u16QPtr;
2816 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2817 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2818 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2819 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2820 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2821 }
2822
2823 u16QNum--;
2824 //go to next frame in the dispQ
2825 u16QPtr++;
2826
2827 if (u16QPtr == pShm->u16DispQSize)
2828 {
2829 u16QPtr = 0; //wrap to the begin
2830 }
2831 }
2832 }
2833
2834 return NULL;
2835 }
2836
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2837 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2838 {
2839 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2840 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2841 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2842 {
2843 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2844 if(pVsyncBridgeExt != NULL)
2845 {
2846 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
2847 }
2848 }
2849 return pFrmInfoExt;
2850 }
2851
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)2852 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
2853 {
2854 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2855 MS_U64 u64Ret = 0;
2856
2857 #if SUPPORT_EVD
2858 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
2859 if (isEVD)
2860 {
2861 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
2862 }
2863 else
2864 #endif
2865 #if SUPPORT_G2VP9
2866 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2867 {
2868 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
2869 }
2870 else
2871 #endif
2872 {
2873 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
2874 }
2875
2876 return u64Ret;
2877 }
2878
2879 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)2880 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
2881 {
2882 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2883 MS_U16 u16QNum = pShm->u16DispQNumb;
2884 MS_U16 u16QPtr = pShm->u16DispQPtr;
2885 static volatile HVD_Frm_Information *pHvdFrm = NULL;
2886 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2887 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2888 MS_BOOL bMVC = FALSE;
2889 #if HVD_ENABLE_MVC
2890 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2891 #endif
2892
2893
2894 if (bMVC || (bDolbyVision && !pShm->bSingleLayer) || _HVD_EX_IsHevcInterlaceField(u32Id))
2895 {
2896 if (u16QNum == 1) return TRUE;
2897 }
2898
2899 while (u16QNum != 0)
2900 {
2901 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2902 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2903 {
2904 return FALSE;
2905 }
2906 u16QNum--;
2907
2908 if (bDolbyVision)
2909 u16QPtr += 2; // single layer must in even ptr
2910 else
2911 u16QPtr++;
2912
2913 if (u16QPtr >= pShm->u16DispQSize)
2914 {
2915 u16QPtr = 0; //wrap to the begin
2916 }
2917 }
2918
2919 return TRUE;
2920 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)2921 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
2922 {
2923 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
2924
2925 return &(_pHVDCtrls[u8DrvId]);
2926 }
2927
_HVD_EX_GetStreamIdx(MS_U32 u32Id)2928 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
2929 {
2930 MS_U8 u8OffsetIdx = 0;
2931 MS_U8 u8SidBaseMask = 0xF0;
2932 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
2933
2934 switch (eSidBase)
2935 {
2936 case E_HAL_HVD_MAIN_STREAM_BASE:
2937 {
2938 u8OffsetIdx = 0;
2939 break;
2940 }
2941 case E_HAL_VPU_SUB_STREAM_BASE:
2942 {
2943 u8OffsetIdx = 1;
2944 break;
2945 }
2946 case E_HAL_VPU_MVC_STREAM_BASE:
2947 {
2948 u8OffsetIdx = 0;
2949 break;
2950 }
2951 #ifdef VDEC3
2952 case E_HAL_VPU_N_STREAM_BASE:
2953 {
2954 u8OffsetIdx = (u32Id>>8) & 0xF;
2955 break;
2956 }
2957 #endif
2958 default:
2959 {
2960 u8OffsetIdx = 0;
2961 break;
2962 }
2963 }
2964
2965 return u8OffsetIdx;
2966 }
2967 /*
2968 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
2969 {
2970 MS_U32 i = 0;
2971 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
2972 {
2973 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
2974 {
2975 return TRUE;
2976 }
2977 }
2978 return FALSE;
2979 }
2980 */
2981
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)2982 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
2983 {
2984 MS_PHY u32PhyAddr = 0x0;
2985 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2986
2987 if (pCtrl->MemMap.u32CodeBufAddr == 0)
2988 {
2989 return 0;
2990 }
2991
2992 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
2993
2994 if (u32PhyAddr == 0xFFFFFFFF) //boris
2995 {
2996 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
2997 }
2998 else
2999 {
3000 // TEE, common + share_info
3001 u32PhyAddr += COMMON_AREA_SIZE;
3002 }
3003
3004 return MsOS_PA2KSEG1(u32PhyAddr);
3005 }
3006
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3007 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3008 {
3009 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3010 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3011
3012 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3013 {
3014 return 0;
3015 }
3016
3017 MS_PHY u32PhyAddr = 0x0;
3018 #if 0
3019 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3020
3021 if (u32PhyAddr == 0xFFFFFFFF)
3022 {
3023 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3024 }
3025 #endif
3026 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3027 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3028
3029 return MsOS_PA2KSEG1(u32PhyAddr);
3030 }
3031
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3032 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3033 {
3034
3035 if (u8MiuSel == E_CHIP_MIU_0)
3036 {
3037 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3038 }
3039 else if (u8MiuSel == E_CHIP_MIU_1)
3040 {
3041 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3042 }
3043 }
3044
3045 #if SUPPORT_G2VP9 && defined(VDEC3)
3046 #ifdef __ARM_NEON__
3047 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3048 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3049 {
3050 uint32x4x4_t data, data2;
3051 MS_U8* raster2 = raster + tile_w * 4;
3052
3053 data = vld4q_u32((const uint32_t *)tile);
3054 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3055
3056 vst1q_u32((uint32_t *)raster, data.val[0]);
3057 raster += stride;
3058 vst1q_u32((uint32_t *)raster, data.val[1]);
3059 raster += stride;
3060 vst1q_u32((uint32_t *)raster, data.val[2]);
3061 raster += stride;
3062 vst1q_u32((uint32_t *)raster, data.val[3]);
3063
3064
3065 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3066 raster2 += stride;
3067 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3068 raster2 += stride;
3069 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3070 raster2 += stride;
3071 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3072 }
3073 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3074 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3075 {
3076 MS_U8* tile0 = tile;
3077 MS_U8* tile1 = tile+16;
3078 MS_U8* tile2 = tile+32;
3079 MS_U8* tile3 = tile+48;
3080 int i;
3081
3082 for (i=0; i<4; i++) {
3083 raster[i] = tile0[i];
3084 raster[4+i] = tile1[i];
3085 raster[8+i] = tile2[i];
3086 raster[12+i] = tile3[i];
3087 }
3088
3089 for (i=0; i<4; i++) {
3090 raster[stride+i] = tile0[4+i];
3091 raster[stride+4+i] = tile1[4+i];
3092 raster[stride+8+i] = tile2[4+i];
3093 raster[stride+12+i] = tile3[4+i];
3094 }
3095
3096 for (i=0; i<4; i++) {
3097 raster[2*stride+i] = tile0[8+i];
3098 raster[2*stride+4+i] = tile1[8+i];
3099 raster[2*stride+8+i] = tile2[8+i];
3100 raster[2*stride+12+i] = tile3[8+i];
3101 }
3102
3103 for (i=0; i<4; i++) {
3104 raster[3*stride+i] = tile0[12+i];
3105 raster[3*stride+4+i] = tile1[12+i];
3106 raster[3*stride+8+i] = tile2[12+i];
3107 raster[3*stride+12+i] = tile3[12+i];
3108 }
3109 }
3110 #endif // #ifdef __ARM_NEON__
3111
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)3112 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
3113 {
3114 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
3115 u32Id,
3116 E_TASK_PRI_MEDIUM,
3117 TRUE,
3118 NULL,
3119 32, // stack size..
3120 "HVD_PostProcess_task");
3121
3122 if (s32HvdPpTaskId < 0)
3123 {
3124 HVD_EX_MSG_ERR("Pp Task create failed\n");
3125
3126 return FALSE;
3127 }
3128
3129 HVD_EX_MSG_DBG("Pp Task create success\n");
3130 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
3131
3132 return TRUE;
3133 }
3134
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3135 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3136 {
3137 return y * stride * h + x * w * h;
3138 }
3139
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3140 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3141 {
3142 return y * stride * h + x * w;
3143 }
3144
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3145 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3146 {
3147 raster[0] = tile[0];
3148 raster[1] = tile[1];
3149 raster[2] = tile[2];
3150 raster[3] = tile[3];
3151 raster[stride] = tile[4];
3152 raster[stride + 1] = tile[5];
3153 raster[stride + 2] = tile[6];
3154 raster[stride + 3] = tile[7];
3155 raster[2 * stride] = tile[8];
3156 raster[2 * stride + 1] = tile[9];
3157 raster[2 * stride + 2] = tile[10];
3158 raster[2 * stride + 3] = tile[11];
3159 raster[3 * stride] = tile[12];
3160 raster[3 * stride + 1] = tile[13];
3161 raster[3 * stride + 2] = tile[14];
3162 raster[3 * stride + 3] = tile[15];
3163 }
3164
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3165 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3166 {
3167 const MS_U32 tile_w = 4;
3168 const MS_U32 tile_h = 4;
3169 MS_U32 tile_stride = w;
3170 MS_U32 x, y;
3171 MS_U8 *dst1, *dst2;
3172 MS_U8 *src1, *src2;
3173
3174 #ifdef __ARM_NEON__
3175 // To overlap load and store, handle two blocks at the same time.
3176 dst1 = dst;
3177 src1 = src;
3178 for (y = 0; y < h / tile_h; y++)
3179 {
3180 dst2 = dst1;
3181 src2 = src1;
3182 for (x = 0; x <= (w/tile_w - 8); x+=8)
3183 {
3184 tile4x4_to_raster_8(
3185 dst2,
3186 src2,
3187 raster_stride, tile_w, tile_h);
3188 dst2 += tile_w * 8;
3189 src2 += tile_w * tile_h * 8;
3190 }
3191 dst1 += raster_stride * tile_h;
3192 src1 += tile_stride * tile_h;
3193 for (; x < w / tile_w; x++)
3194 {
3195 tile4x4_to_raster(
3196 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3197 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3198 raster_stride);
3199 }
3200 }
3201 #else
3202 dst1 = NULL;
3203 src1 = NULL;
3204 dst2 = NULL;
3205 src2 = NULL;
3206
3207 for (y = 0; y < h / tile_h; y++)
3208 {
3209 for (x = 0; x <= (w/tile_w - 4); x+=4)
3210 {
3211 tile4x4_to_raster_4(
3212 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3213 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3214 raster_stride);
3215 }
3216 for (; x < w / tile_w; x++)
3217 {
3218 tile4x4_to_raster(
3219 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3220 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3221 raster_stride);
3222 }
3223 }
3224 #endif
3225 }
3226
3227 #define FLUSH_CACHE_SIZE (256 * 1024)
3228
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3229 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3230 {
3231 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
3232 if (u32Size > FLUSH_CACHE_SIZE)
3233 u32Size = FLUSH_CACHE_SIZE;
3234
3235 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
3236 }
3237
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3238 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3239 {
3240 MS_U32 u32SkipSize = 0;
3241
3242 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3243 if (u32Size > FLUSH_CACHE_SIZE)
3244 {
3245 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3246 u32Size = FLUSH_CACHE_SIZE;
3247 }
3248
3249 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
3250 }
3251
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3252 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3253 {
3254 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
3255 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3256 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3257 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3258
3259 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3260
3261 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3262
3263 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3264 {
3265 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3266 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3267
3268 HVD_Delay_ms(1); // FIXME
3269
3270 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3271 continue;
3272
3273 HAL_HVD_EX_ReadMemory();
3274
3275 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3276 {
3277 MS_U8 *pSrcVA, *pDstVA;
3278 MS_U32 u32SrcPA, u32DstPA;
3279 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3280 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3281
3282 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3283 {
3284 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3285
3286 u16Width = pFrmInfo->u16Width;
3287 u16Height = pFrmInfo->u16Height;
3288 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3289 }
3290
3291 // Luma
3292 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3293 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3294
3295 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3296 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3297
3298 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3299 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3300
3301 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3302
3303 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3304
3305 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3306
3307 // Chroma
3308 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3309 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3310
3311 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3312 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3313
3314 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3315 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3316
3317 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3318
3319 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3320
3321 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3322
3323 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3324 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3325 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3326
3327 HAL_HVD_EX_FlushMemory();
3328
3329 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3330 break;
3331
3332 HAL_HVD_EX_ReadMemory();
3333 }
3334 }
3335
3336 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3337
3338 return TRUE;
3339 }
3340 #endif
3341
HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id,MS_BOOL * isVP8Used,MS_BOOL * isAECUsed,MS_BOOL * isAVCUsed)3342 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed , MS_BOOL *isAVCUsed)
3343 {
3344 MS_U8 i ;
3345 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3346
3347 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM ; i++)
3348 {
3349 if( _pHVDCtrls[i].bUsed && (i != u8DrvId))
3350 {
3351 MS_U32 u32TempModeFlag = (_pHVDCtrls[i].InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ;
3352 if((E_HVD_INIT_HW_VP8 == u32TempModeFlag))
3353 {
3354 *isVP8Used = TRUE ;
3355 }
3356 else if((E_HVD_INIT_HW_VP9 == u32TempModeFlag) || (E_HVD_INIT_HW_AVS == u32TempModeFlag))
3357 {
3358 *isAECUsed = TRUE ;
3359 }
3360 else if((E_HVD_INIT_HW_AVC == u32TempModeFlag))
3361 {
3362 *isAVCUsed = TRUE ;
3363 }
3364 }
3365 }
3366 }
3367
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3368 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3369 {
3370 #ifndef VDEC3
3371 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3372 #endif
3373 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3374 MS_BOOL isVP8Used = FALSE;
3375 MS_BOOL isAECUsed = FALSE;
3376 MS_BOOL isAVCUsed = FALSE;
3377 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
3378 // MS_U8 u8MiuSel;
3379 // MS_U32 u32StartOffset;
3380
3381 #if SUPPORT_EVD
3382 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
3383 #else
3384 MS_BOOL isEVD = FALSE;
3385 #endif
3386 MS_BOOL isHVD = !isEVD;
3387
3388 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
3389 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3390
3391 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3392 // re-setup clock.
3393 #if SUPPORT_G2VP9 && defined(VDEC3)
3394 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3395 #endif
3396
3397
3398 if (isHVD)
3399 {
3400 if (!HAL_VPU_EX_HVDInUsed())
3401 {
3402 printf("HVD power on\n");
3403 HAL_HVD_EX_PowerCtrl(u32Id, TRUE);
3404 }
3405
3406 if(!isVP8Used && (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3407 {
3408 HAL_VP8_PowerCtrl(TRUE);
3409 }
3410 else if(!isAECUsed && (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3411 {
3412 HAL_AEC_PowerCtrl(TRUE);
3413 }
3414
3415 #ifdef CONFIG_MSTAR_SRAMPD
3416 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3417 HVD_Delay_ms(1);
3418 #endif
3419 }
3420
3421 #if SUPPORT_EVD
3422 #ifdef VDEC3
3423 if (isEVD) /// Disable it for disable H264 IMI
3424 {
3425 if (!HAL_VPU_EX_EVDInUsed())
3426 {
3427 printf("EVD power on\n");
3428 HAL_EVD_EX_PowerCtrl(u32Id, TRUE);
3429 }
3430 if(!isAECUsed && (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3431 {
3432 HAL_AEC_PowerCtrl(TRUE);
3433 }
3434 }
3435 #endif
3436 #endif
3437
3438 #if SUPPORT_G2VP9 && defined(VDEC3)
3439 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3440 {
3441 if (!HAL_VPU_EX_G2VP9InUsed())
3442 {
3443 printf("G2 VP9 power on\n");
3444 HAL_VP9_EX_PowerCtrl(TRUE);
3445 }
3446 }
3447 #endif
3448
3449 if ((!HAL_VPU_EX_HVDInUsed()) )
3450 {
3451 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3452 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3453 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3454 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3455
3456 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3457
3458 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
3459 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
3460 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256);
3461 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256);
3462 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128);
3463 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128);
3464
3465 #if 0
3466 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
3467 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3468 {
3469 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
3470
3471 _HAL_HVD_Entry();
3472 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
3473 _HAL_HVD_Release();
3474
3475 }
3476 #endif
3477 }
3478
3479 #if SUPPORT_EVD
3480 if (isEVD)
3481 {
3482 #ifdef VDEC3
3483 if (!HAL_VPU_EX_EVDInUsed())
3484 #endif
3485 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3486 }
3487 #endif
3488
3489 #if SUPPORT_G2VP9 && defined(VDEC3)
3490 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3491 {
3492 if (!HAL_VPU_EX_G2VP9InUsed())
3493 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3494 }
3495 #endif
3496
3497
3498 if(pCtrl == NULL)
3499 {
3500 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
3501 //return FALSE;
3502 goto RESET;
3503 }
3504
3505 #if SUPPORT_EVD
3506 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
3507 {
3508 #ifdef VDEC3
3509 if (!HAL_VPU_EX_EVDInUsed())
3510 #endif
3511 {
3512 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3513 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3514 }
3515
3516 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3517 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3518 {
3519 #ifdef VDEC3
3520 if (0 == pCtrl->u32BBUId)
3521 #else
3522 if (0 == u8TaskId)
3523 #endif
3524 {
3525 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
3526 }
3527 else
3528 {
3529 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
3530 }
3531
3532 }
3533 goto RESET;
3534 }
3535 #endif
3536
3537 // HVD4, from JANUS and later chip
3538 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3539 {
3540 case E_HVD_INIT_HW_AVS:
3541 {
3542 #ifdef VDEC3
3543 if (0 == pCtrl->u32BBUId)
3544 #else
3545 if (0 == u8TaskId)
3546 #endif
3547 {
3548 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3549 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3550 }
3551 else
3552 {
3553 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3554 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3555 }
3556
3557 break;
3558 }
3559 case E_HVD_INIT_HW_RM:
3560 {
3561 #ifdef VDEC3
3562 if (0 == pCtrl->u32BBUId)
3563 #else
3564 if (0 == u8TaskId)
3565 #endif
3566 {
3567 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3568 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3569
3570 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3571 {
3572 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3573 }
3574 else // RV 8
3575 {
3576 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3577 }
3578 }
3579 else
3580 {
3581 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3582 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3583
3584 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3585 {
3586 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3587 }
3588 else // RV 8
3589 {
3590 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3591 }
3592
3593 }
3594
3595 break;
3596 }
3597 default:
3598 {
3599 #ifdef VDEC3
3600 if (0 == pCtrl->u32BBUId)
3601 #else
3602 if (0 == u8TaskId)
3603 #endif
3604 {
3605 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3606 }
3607 else
3608 {
3609 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3610 }
3611 break;
3612 }
3613 }
3614
3615 RESET:
3616
3617 #if 0 //use miu256bit
3618 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3619
3620 if (!HAL_VPU_EX_HVDInUsed())
3621 {
3622 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3623 }
3624
3625 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3626 #endif
3627
3628 #if SUPPORT_EVD
3629 if (isEVD)
3630 {
3631 #ifdef VDEC3
3632 if (!HAL_VPU_EX_EVDInUsed())
3633 #endif
3634 {
3635 printf("EVD miu 256 bits\n");
3636 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_128 & ~EVD_REG_RESET_MIU1_128));
3637 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_256 | EVD_REG_RESET_MIU1_256));
3638 _HVD_Write2Byte(REG_CLK_EVD, (_HVD_Read2Byte(REG_CLK_EVD) & ~REG_CLK_EVD_SW_OV_EN & ~REG_CLK_EVD_PPU_SW_OV_EN));//set 0 firmware
3639 //_HVD_Write2Byte(REG_CLK_EVD, (_HVD_Read2Byte(REG_CLK_EVD) | REG_CLK_EVD_SW_OV_EN | REG_CLK_EVD_PPU_SW_OV_EN));//set 1 driver
3640 printf("EVD BBU 256 bits\n");
3641 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) & ~REG_BBU_MIU_128));
3642 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) | REG_BBU_MIU_256));
3643 }
3644 }
3645 #endif
3646 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3647 // Only ES buffer addrress needs to be set for VP8
3648 _HVD_EX_SetESBufferAddr(u32Id);
3649 #else
3650 if(DecoderType != E_VPU_EX_DECODER_MVD)
3651 {
3652 _HVD_EX_SetBufferAddr(u32Id);
3653 }
3654 #endif
3655 if (!HAL_VPU_EX_HVDInUsed())
3656 {
3657 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3658 }
3659
3660 #if SUPPORT_EVD
3661 if (isEVD)
3662 {
3663 #ifdef VDEC3
3664 if (!HAL_VPU_EX_EVDInUsed())
3665 #endif
3666 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
3667 }
3668 #endif
3669
3670 #if SUPPORT_G2VP9 && defined(VDEC3)
3671 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3672 {
3673 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3674
3675 if (!HAL_VPU_EX_G2VP9InUsed())
3676 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3677
3678 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3679 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
3680 }
3681 #endif
3682
3683 return TRUE;
3684 }
3685
HAL_HVD_EX_DeinitHW(MS_U32 u32Id)3686 MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id)
3687 {
3688 MS_U16 u16Timeout = 1000;
3689 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3690 MS_BOOL isVP8Used = FALSE;
3691 MS_BOOL isAECUsed = FALSE;
3692 MS_BOOL isAVCUsed = FALSE;
3693 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed , &isAVCUsed);
3694
3695 #if SUPPORT_EVD
3696 if(!isAVCUsed && E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) && !HAL_VPU_EX_EVDInUsed())
3697 {
3698 HAL_EVD_EX_DeinitHW(u32Id);//no AVC/EVD use , close EVD power
3699 }
3700 #endif
3701
3702 if(TRUE == HAL_VPU_EX_HVDInUsed())
3703 {
3704 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3705 {
3706 HAL_VP8_PowerCtrl(FALSE);
3707 }
3708 else if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3709 {
3710 HAL_AEC_PowerCtrl(FALSE);
3711 }
3712 return FALSE;
3713 }
3714 else
3715 {
3716 _HVD_EX_SetMIUProtectMask(TRUE);
3717
3718 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3719
3720 while (u16Timeout)
3721 {
3722 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
3723 {
3724 break;
3725 }
3726 u16Timeout--;
3727 }
3728
3729 HAL_HVD_EX_PowerCtrl(u32Id, FALSE);
3730
3731 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3732 {
3733 HAL_VP8_PowerCtrl(FALSE);
3734 }
3735 else if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3736 {
3737 HAL_AEC_PowerCtrl(FALSE);
3738 }
3739
3740 #ifdef CONFIG_MSTAR_SRAMPD
3741 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3742 HVD_Delay_ms(1);
3743 #endif
3744
3745 _HVD_EX_SetMIUProtectMask(FALSE);
3746
3747 return TRUE;
3748 }
3749
3750 return FALSE;
3751 }
3752
HAL_HVD_EX_FlushMemory(void)3753 void HAL_HVD_EX_FlushMemory(void)
3754 {
3755 MsOS_FlushMemory();
3756 }
3757
HAL_HVD_EX_ReadMemory(void)3758 void HAL_HVD_EX_ReadMemory(void)
3759 {
3760 MsOS_ReadMemory();
3761 }
3762
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)3763 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
3764 {
3765 _pHVDCtrls = pHVDCtrlsBase;
3766 }
3767
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)3768 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
3769 {
3770 return;
3771 }
3772
HAL_HVD_EX_GetHWVersionID(void)3773 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
3774 {
3775 return _HVD_Read2Byte(HVD_REG_REV_ID);
3776 }
3777
3778
HAL_HVD_EX_Init_Share_Mem(void)3779 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
3780 {
3781 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
3782 #if !defined(SUPPORT_X_MODEL_FEATURE)
3783 MS_U32 u32ShmId;
3784 MS_VIRT u32Addr;
3785 MS_U32 u32BufSize;
3786
3787
3788 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
3789 sizeof(HVD_Hal_CTX),
3790 &u32ShmId,
3791 &u32Addr,
3792 &u32BufSize,
3793 MSOS_SHM_QUERY))
3794 {
3795 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
3796 sizeof(HVD_Hal_CTX),
3797 &u32ShmId,
3798 &u32Addr,
3799 &u32BufSize,
3800 MSOS_SHM_CREATE))
3801 {
3802 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
3803 if(pHVDHalContext == NULL)
3804 {
3805 pHVDHalContext = &gHVDHalContext;
3806 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3807 _HVD_EX_Context_Init_HAL();
3808 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
3809 }
3810 else
3811 {
3812 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
3813 }
3814 //return FALSE;
3815 }
3816 else
3817 {
3818 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
3819 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
3820 _HVD_EX_Context_Init_HAL();
3821 }
3822 }
3823 else
3824 {
3825 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
3826 }
3827 #else
3828 if(pHVDHalContext == NULL)
3829 {
3830 pHVDHalContext = &gHVDHalContext;
3831 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3832 _HVD_EX_Context_Init_HAL();
3833 }
3834 #endif
3835 _HAL_HVD_MutexCreate();
3836 #else
3837 if(pHVDHalContext == NULL)
3838 {
3839 pHVDHalContext = &gHVDHalContext;
3840 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3841 _HVD_EX_Context_Init_HAL();
3842 }
3843 #endif
3844
3845 return TRUE;
3846 }
3847
3848
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)3849 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
3850 {
3851 MS_U32 i = 0;
3852
3853 if (eStreamType == E_HAL_HVD_MVC_STREAM)
3854 {
3855 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
3856 return pHVDHalContext->_stHVDStream[0].eStreamId;
3857 }
3858 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
3859 {
3860 for (i = 0;
3861 i <
3862 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3863 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3864 {
3865 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3866 {
3867 return pHVDHalContext->_stHVDStream[i].eStreamId;
3868 }
3869 }
3870 }
3871 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
3872 {
3873 for (i = 0;
3874 i <
3875 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3876 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3877 {
3878 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3879 {
3880 return pHVDHalContext->_stHVDStream[i].eStreamId;
3881 }
3882 }
3883 }
3884 #ifdef VDEC3
3885 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
3886 {
3887 i = eStreamType - E_HAL_HVD_N_STREAM;
3888 if (!pHVDHalContext->_stHVDStream[i].bUsed)
3889 return pHVDHalContext->_stHVDStream[i].eStreamId;
3890 }
3891 #endif
3892
3893 return E_HAL_HVD_STREAM_NONE;
3894 }
3895
HAL_VP8_PowerCtrl(MS_BOOL bEnable)3896 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable)
3897 {
3898 if (bEnable)
3899 {
3900 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3901
3902 switch (pHVDHalContext->u32HVDClockType)
3903 {
3904 case 384:
3905 {
3906 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3907 break;
3908 }
3909 case 345:
3910 {
3911 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3912 break;
3913 }
3914 case 320:
3915 {
3916 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3917 break;
3918 }
3919 case 288:
3920 {
3921 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3922 break;
3923 }
3924 case 240:
3925 {
3926 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
3927 break;
3928 }
3929 case 216:
3930 {
3931 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3932 break;
3933 }
3934 case 172:
3935 {
3936 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3937 break;
3938 }
3939 default:
3940 {
3941 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3942 break;
3943 }
3944 }
3945 }
3946 else
3947 {
3948 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3949 }
3950
3951 }
3952
HAL_AEC_PowerCtrl(MS_BOOL bEnable)3953 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable)
3954 {
3955 if (bEnable)
3956 {
3957 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3958
3959 switch (pHVDHalContext->u32HVDClockType)
3960 {
3961 case 384:
3962 {
3963 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3964 break;
3965 }
3966 case 345:
3967 {
3968 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3969 break;
3970 }
3971 case 320:
3972 {
3973 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3974 break;
3975 }
3976 case 288:
3977 {
3978 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3979 break;
3980 }
3981 case 240:
3982 {
3983 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3984 break;
3985 }
3986 case 216:
3987 {
3988 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3989 break;
3990 }
3991 case 172:
3992 {
3993 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3994 break;
3995 }
3996 default:
3997 {
3998 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3999 break;
4000 }
4001 }
4002 }
4003 else
4004 {
4005 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4006 }
4007
4008 }
4009
HAL_HVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)4010 void HAL_HVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
4011 {
4012 if (bEnable)
4013 {
4014 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4015 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4016 }
4017 else
4018 {
4019 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4020 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4021 }
4022
4023 // fix to not inverse
4024 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
4025
4026 switch (pHVDHalContext->u32HVDClockType)
4027 {
4028 #if 0 //for overclocking
4029 case 432:
4030 {
4031 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
4032 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4033 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_320MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4034 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK);
4035 break;
4036 }
4037 #endif
4038 case 384:
4039 {
4040 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4041 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4042 break;
4043 }
4044 case 345:
4045 {
4046 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_345MHZ, TOP_CKG_HVD_CLK_MASK);
4047 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4048 break;
4049 }
4050 case 320:
4051 {
4052 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_320MHZ, TOP_CKG_HVD_CLK_MASK);
4053 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_345MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4054 break;
4055 }
4056 case 288:
4057 {
4058 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
4059 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_320MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4060 break;
4061 }
4062 case 240:
4063 {
4064 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
4065 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4066 break;
4067 }
4068 case 216:
4069 {
4070 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
4071 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_240MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4072 break;
4073 }
4074 case 172:
4075 {
4076 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
4077 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_216MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4078 break;
4079 }
4080
4081 default:
4082 {
4083 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4084 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4085 break;
4086 }
4087 }
4088
4089 return;
4090 }
4091
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)4092 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
4093 {
4094 u32HVDRegOSBase = u32RegBase;
4095 HAL_VPU_EX_InitRegBase(u32RegBase);
4096 }
4097
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)4098 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
4099 {
4100 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
4101 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4102 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
4103 }
4104
HAL_HVD_EX_InitVariables(MS_U32 u32Id)4105 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
4106 {
4107 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4108 HVD_ShareMem *pShm = NULL;
4109 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4110 #if HVD_ENABLE_MVC
4111 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4112 #endif ///HVD_ENABLE_MVC
4113
4114 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4115 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4116 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4117 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
4118 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4119 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = TRUE;
4120 int i;
4121 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
4122 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
4123 #if HVD_ENABLE_MVC
4124 if(bMVC)
4125 {
4126 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
4127 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
4128 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
4129 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
4130 }
4131 #endif ///HVD_ENABLE_MVC
4132
4133 // set a local copy of FW code address; assuming there is only one copy of FW,
4134 // no matter how many task will be created.
4135
4136 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4137
4138 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
4139
4140 // global variables
4141 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
4142
4143
4144 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4145 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4146 // Create mutex
4147 //_HAL_HVD_MutexCreate();
4148
4149 // fill HVD init variables
4150 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4151 {
4152 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
4153 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
4154 }
4155 else
4156 #if HVD_ENABLE_RV_FEATURE
4157 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4158 {
4159 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
4160 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
4161 #ifdef VDEC3_FB
4162 pHVDHalContext->u32RV_VLCTableAddr = 0;
4163 #else
4164 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
4165 {
4166 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
4167 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
4168 }
4169 else
4170 {
4171 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
4172 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
4173 return E_HVD_RETURN_INVALID_PARAMETER;
4174 }
4175 #endif
4176 }
4177 else
4178 #endif
4179 {
4180 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
4181 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
4182 #if HVD_ENABLE_MVC
4183 if(bMVC)
4184 {
4185 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
4186 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
4187 }
4188 #endif /// HVD_ENABLE_MVC
4189 pHVDHalContext->u32RV_VLCTableAddr = 0;
4190 }
4191
4192 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
4193 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
4194 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
4195 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
4196 {
4197 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4198 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4199 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4200 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4201 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4202 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4203 #if HVD_ENABLE_MVC
4204 if(bMVC)
4205 {
4206 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
4207 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
4208 {
4209 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
4210 }
4211 }
4212 #endif /// HVD_ENABLE_MVC
4213
4214 return E_HVD_RETURN_SUCCESS;
4215 }
4216 else
4217 {
4218 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4219 (unsigned long)MS_VA2PA((MS_VIRT)pShm),
4220 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4221 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4222 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4223 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4224 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4225 return E_HVD_RETURN_INVALID_PARAMETER;
4226 }
4227 }
4228
4229 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)4230 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
4231 #else
4232 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
4233 #endif
4234 {
4235 MS_U32 u32Addr = 0;
4236 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4237 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4238 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4239
4240 MS_U32 u32TmpStartOffset;
4241 MS_U8 u8TmpMiuSel;
4242
4243
4244 memset(pShm, 0, sizeof(HVD_ShareMem));
4245
4246 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
4247
4248 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
4249 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
4250 #ifdef VDEC3
4251 if (bFWdecideFB || bCMAUsed)
4252 {
4253 pShm->u32FrameBufAddr = 0;
4254 pShm->u32FrameBufSize = 0;
4255 }
4256 else
4257 #endif
4258 {
4259 pShm->u32FrameBufAddr = u32Addr;
4260 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
4261 }
4262
4263 // FIXME: need to use the avaliable task resource instead of using next task resource
4264 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
4265 pShm->u8ExternalHeapIdx = u8Idx + 1;
4266 else
4267 pShm->u8ExternalHeapIdx = 0xFF;
4268 pShm->DispInfo.u16DispWidth = 1;
4269 pShm->DispInfo.u16DispHeight = 1;
4270 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
4271 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
4272 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
4273 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4274 //Chip info
4275 pShm->u16ChipID = E_MSTAR_CHIP_MAXIM;
4276 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4277 // PreSetControl
4278 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bOnePendingBuffer)
4279 {
4280 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4281 }
4282
4283 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bCalFrameRate)
4284 {
4285 pShm->u32PreSetControl |= PRESET_CAL_FRAMERATE;
4286 }
4287
4288 pShm->bUseTSPInBBUMode = FALSE;
4289
4290
4291 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable) &&
4292 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4293 {
4294 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4295
4296 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufAddr);
4297
4298 pShm->u32IapGnBufAddr = u32Addr;
4299 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufSize;
4300
4301 }
4302
4303 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
4304 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
4305 {
4306 case E_HVD_DEF_MFCODEC_DEFAULT:
4307 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4308 break;
4309 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
4310 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
4311 break;
4312 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
4313 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
4314 break;
4315 default:
4316 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4317 }
4318
4319 pShm->u8CodecFeature &= ~E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4320 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bDVSingleLayerMode)
4321 pShm->u8CodecFeature |= E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4322
4323 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
4324 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
4325 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
4326 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
4327 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
4328 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
4329
4330 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.bEnable))
4331 {
4332 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4333
4334 pShm->stDynmcDispPath.u8Connect = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.bConnect;
4335 pShm->stDynmcDispPath.u8DispPath = (MS_U8)(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.eMvopPath);
4336 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4337
4338 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, pShm->stDynmcDispPath.u8DispPath);
4339 }
4340 else
4341 {
4342 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4343
4344 MS_U8 u8Connect = FALSE;
4345 MS_U8 u8Path = E_CTL_DISPLAY_PATH_NONE;
4346 switch (pCtrl->eStream)
4347 {
4348 case E_HVD_ORIGINAL_MAIN_STREAM:
4349 u8Connect = TRUE;
4350 u8Path = E_CTL_DISPLAY_PATH_MVOP_0;
4351 break;
4352 case E_HVD_ORIGINAL_SUB_STREAM:
4353 u8Connect = TRUE;
4354 u8Path = E_CTL_DISPLAY_PATH_MVOP_1;
4355 break;
4356 case E_HVD_ORIGINAL_N_STREAM:
4357 default:
4358 u8Connect = FALSE;
4359 u8Path = E_CTL_DISPLAY_PATH_NONE;
4360 break;
4361 }
4362
4363 pShm->stDynmcDispPath.u8Connect = u8Connect;
4364 pShm->stDynmcDispPath.u8DispPath = u8Path;
4365 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4366
4367 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, u8Path);
4368 }
4369
4370 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
4371 {
4372 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.bEnable))
4373 {
4374 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
4375 pShm->u8InputTSP = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.u8InputTsp;
4376
4377 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
4378 }
4379 else
4380 {
4381 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
4382
4383 MS_U8 u8Input = E_CTL_INPUT_TSP_NONE;
4384 switch (pCtrl->eStream)
4385 {
4386 case E_HVD_ORIGINAL_MAIN_STREAM:
4387 u8Input = E_CTL_INPUT_TSP_0;
4388 break;
4389 case E_HVD_ORIGINAL_SUB_STREAM:
4390 u8Input = E_CTL_INPUT_TSP_1;
4391 break;
4392 case E_HVD_ORIGINAL_N_STREAM:
4393 default:
4394 u8Input = E_CTL_INPUT_TSP_NONE;
4395 break;
4396 }
4397
4398 pShm->u8InputTSP = u8Input;
4399
4400 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
4401 }
4402 }
4403 else
4404 {
4405 HVD_EX_MSG_DBG("[NDec][0x%x][%d] not TSP input, ignore PRESET_CONNECT_INPUT_TSP \n", u32Id, u8Idx);
4406 }
4407
4408 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4409 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4410 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4411 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4412 else
4413 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4414 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4415 {
4416 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4417 {
4418 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4419 }
4420 else
4421 {
4422 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4423 }
4424 }
4425 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4426 {
4427 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4428 {
4429 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4430 }
4431 else
4432 {
4433 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4434 }
4435 }
4436 else
4437 {
4438 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4439 }
4440
4441 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4442 {
4443 pShm->bHVDIMIEnable = TRUE; //AVC FW enable IMI only for 4k2k
4444 }
4445
4446 #if 0
4447 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bEnableDynamicCMA)
4448 {
4449 pShm->u8CodecFeature |= E_VDEC_DYNAMIC_CMA_MODE;
4450 }
4451 #endif
4452
4453 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4454 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4455 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4456 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4457 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4458 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4459 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4460 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4461 (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4462 {
4463 pShm->bUseWbMvop = 1;
4464 }
4465
4466 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
4467 || E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4468 {
4469 if(!(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & E_HVD_DEF_FEATURE_DISABLE_TEMPORAL_SCALABILITY))
4470 pShm->u8CodecFeature |= E_VDEC_TEMPORAL_SCALABILITY_MODE;
4471 }
4472
4473 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4474
4475 #if (VPU_FORCE_MIU_MODE)
4476 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4477
4478 pShm->u32FWBaseAddr = u32TmpStartOffset;
4479
4480 #else
4481 ///TODO:
4482 /*
4483 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4484
4485 if(u8TmpMiuSel == E_CHIP_MIU_0)
4486 {
4487 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4488 }
4489 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4490 {
4491 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4492 }
4493 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4494 {
4495 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4496 }
4497 */
4498 #endif
4499 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4500 #else
4501 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4502 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4503 {
4504 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4505 }
4506 pShm->u32FWBaseAddr = u32Addr;
4507 #endif
4508
4509 // RM only
4510 #if HVD_ENABLE_RV_FEATURE
4511 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4512 && (pCtrl->InitParams.pRVFileInfo != NULL))
4513 {
4514 MS_U32 i = 0;
4515
4516 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4517 {
4518 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4519 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4520 }
4521
4522 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4523 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4524 #ifdef VDEC3_FB
4525 pShm->u32RM_VLCTableAddr = 0;
4526 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4527 #else
4528 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
4529
4530 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4531 u32Addr = u32TmpStartOffset;
4532
4533 pShm->u32RM_VLCTableAddr = u32Addr;
4534 #endif
4535 }
4536 #endif
4537
4538 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4539 && (pCtrl->InitParams.pRVFileInfo != NULL))
4540 {
4541 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4542 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4543 }
4544
4545 //if(pCtrl->InitParams.bColocateBBUMode)
4546 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4547 {
4548 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4549 }
4550
4551 #if SUPPORT_G2VP9
4552 // Enable SW detile support for G2 VP9
4553 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4554 {
4555 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4556 }
4557 #endif
4558
4559 HAL_HVD_EX_FlushMemory();
4560
4561 return E_HVD_RETURN_SUCCESS;
4562 }
4563 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4564 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4565 #else
4566 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4567 #endif
4568 {
4569 MS_BOOL bInitRet = FALSE;
4570
4571 #if 0
4572 // check MVD power on
4573 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4574 {
4575 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4576 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4577 HVD_Delay_ms(1);
4578 }
4579 // Check VPU power on
4580 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4581 {
4582 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4583 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4584 HVD_Delay_ms(1);
4585 }
4586 // check HVD power on
4587 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4588 {
4589 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4590 HAL_HVD_EX_PowerCtrl(TRUE);
4591 HVD_Delay_ms(1);
4592 }
4593 #endif
4594 #ifdef VDEC3
4595 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4596 #else
4597 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4598 #endif
4599 if (!bInitRet)
4600 {
4601 return E_HVD_RETURN_FAIL;
4602 }
4603
4604 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4605
4606 if (!bInitRet)
4607 {
4608 return E_HVD_RETURN_FAIL;
4609 }
4610
4611 return E_HVD_RETURN_SUCCESS;
4612 }
4613
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4614 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4615 {
4616 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4617
4618 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4619
4620 return E_HVD_RETURN_SUCCESS;
4621 }
4622
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)4623 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
4624 {
4625 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4626 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4627 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4628 MS_BOOL bMVC = FALSE;
4629 #if HVD_ENABLE_MVC
4630 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4631 #endif
4632
4633 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4634 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
4635
4636 switch (u32type)
4637 {
4638 // share memory
4639 // switch
4640 case E_HVD_SDATA_FRAMEBUF_ADDR:
4641 {
4642 pShm->u32FrameBufAddr = u32Data;
4643 break;
4644 }
4645 case E_HVD_SDATA_FRAMEBUF_SIZE:
4646 {
4647 pShm->u32FrameBufSize = u32Data;
4648 break;
4649 }
4650 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4651 {
4652 pShm->u32FrameBuf2Addr = u32Data;
4653 break;
4654 }
4655 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4656 {
4657 pShm->u32FrameBuf2Size = u32Data;
4658 break;
4659 }
4660 case E_HVD_SDATA_MAX_CMA_SIZE:
4661 {
4662 pShm->u32MaxCMAFrameBufSize = u32Data;
4663 break;
4664 }
4665 case E_HVD_SDATA_MAX_CMA_SIZE2:
4666 {
4667 pShm->u32MaxCMAFrameBuf2Size = u32Data;
4668 break;
4669 }
4670 case E_HVD_SDATA_CMA_USED:
4671 {
4672 pShm->bCMA_Use = u32Data;
4673 break;
4674 }
4675 case E_HVD_SDATA_CMA_ALLOC_DONE:
4676 {
4677 pShm->bCMA_AllocDone = u32Data;
4678 break;
4679 }
4680 case E_HVD_SDATA_CMA_TWO_MIU:
4681 {
4682 pShm->bCMA_TwoMIU = u32Data;
4683 break;
4684 }
4685 case E_HVD_SDATA_RM_PICTURE_SIZES:
4686 {
4687 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4688 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4689 break;
4690 }
4691 case E_HVD_SDATA_ERROR_CODE:
4692 {
4693 pShm->u16ErrCode = (MS_U16) u32Data;
4694 break;
4695 }
4696 case E_HVD_SDATA_DISP_INFO_TH:
4697 {
4698 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4699 sizeof(HVD_DISP_THRESHOLD));
4700 break;
4701 }
4702 case E_HVD_SDATA_FW_FLUSH_STATUS:
4703 {
4704 pShm->u8FlushStatus = (MS_U8)u32Data;
4705 break;
4706 }
4707 case E_HVD_SDATA_DMX_FRAMERATE:
4708 {
4709 pShm->u32DmxFrameRate = u32Data;
4710 break;
4711 }
4712 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4713 {
4714 pShm->u32DmxFrameRateBase = u32Data;
4715 break;
4716 }
4717 case E_HVD_SDATA_MIU_SEL:
4718 {
4719 pShm->u32VDEC_MIU_SEL = u32Data;
4720 break;
4721 }
4722 case E_HVD_SDATA_DV_XC_SHM_SIZE:
4723 {
4724 pShm->u32DolbyVisionXCShmSize = u32Data;
4725 break;
4726 }
4727 // SRAM
4728
4729 // Mailbox
4730 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4731 {
4732 if (u32Data != 0)
4733 {
4734 pShm->bEnableDispCtrl = TRUE;
4735 pShm->bIsTrigDisp = TRUE;
4736 }
4737 else
4738 {
4739 pShm->bEnableDispCtrl = FALSE;
4740 }
4741
4742 break;
4743 }
4744 case E_HVD_SDATA_GET_DISP_INFO_START:
4745 {
4746 pShm->bSpsChange = FALSE;
4747 break;
4748 }
4749 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4750 {
4751 pShm->u32VirtualBoxWidth = u32Data;
4752 break;
4753 }
4754 case E_HVD_SDATA_DV_INFO:
4755 {
4756 pShm->u8DVLevelFromDriverAPI = (MS_U8)(u32Data & 0xff);
4757 pShm->u8DVProfileFromDriverAPI = (MS_U8)((u32Data >> 8) & 0xff);
4758 pShm->u8DolbyMetaReorder = (MS_U8)((u32Data >> 16) & 0xff);
4759 break;
4760 }
4761 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4762 {
4763 pShm->u32VirtualBoxHeight = u32Data;
4764 break;
4765 }
4766 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4767 {
4768 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4769 {
4770 //printf("DispFrame DqPtr: %d\n", u32Data);
4771 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4772 }
4773 break;
4774 }
4775 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4776 {
4777 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
4778 {
4779 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4780 {
4781 //printf("DispFrame DqPtr: %ld\n", u32Data);
4782 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4783 }
4784 }
4785 break;
4786 }
4787 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4788 {
4789 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4790 {
4791 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
4792 {
4793 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4794 {
4795 //ALOGE("R1: %x", u32Data);
4796 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
4797 }
4798 else
4799 {
4800 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4801 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4802 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
4803 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4804 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4805 }
4806 }
4807 else
4808 {
4809 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4810 }
4811 }
4812 else
4813 {
4814 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4815 {
4816 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4817 }
4818 }
4819 break;
4820 }
4821 case E_HVD_SDATA_HDR_PERFRAME:
4822 {
4823 if (u32Data != 0)
4824 {
4825 pShm->u8IsDoblyHDR10 = TRUE;
4826 }
4827 else
4828 {
4829 pShm->u8IsDoblyHDR10 = FALSE;
4830 }
4831 break;
4832 }
4833 #if (HVD_ENABLE_IQMEM)
4834 case E_HVD_SDATA_FW_IQMEM_CTRL:
4835 {
4836 pShm->u8IQmemCtrl= (MS_U8)u32Data;
4837 break;
4838
4839 }
4840 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
4841 {
4842 if (u32Data != 0)
4843 {
4844 pShm->bIQmemEnableIfSupport= TRUE;
4845 }
4846 else
4847 {
4848 pShm->bIQmemEnableIfSupport= FALSE;
4849 }
4850
4851
4852 break;
4853
4854 }
4855 #endif
4856 case E_HVD_SDATA_DYNMC_DISP_PATH_STATUS:
4857 {
4858 pShm->stDynmcDispPath.u8ConnectStatus = u32Data;
4859 break;
4860 }
4861
4862 default:
4863 break;
4864 }
4865
4866 HAL_HVD_EX_FlushMemory();
4867
4868 return eRet;
4869 }
4870
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4871 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4872 {
4873 MS_S64 s64Ret = 0;
4874 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4875
4876 HAL_HVD_EX_ReadMemory();
4877
4878 switch (eType)
4879 {
4880 case E_HVD_GDATA_PTS_STC_DIFF:
4881 s64Ret = pShm->s64PtsStcDiff;
4882 break;
4883 default:
4884 break;
4885 }
4886
4887 return s64Ret;
4888 }
4889
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4890 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4891 {
4892 MS_VIRT u32Ret = 0;
4893 //static MS_U64 u64pts_real = 0;
4894 MS_U64 u64pts_low = 0;
4895 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4896 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4897
4898 HAL_HVD_EX_ReadMemory();
4899
4900 if(pShm == NULL)
4901 {
4902 printf("########## VDEC patch for Debug ###########\n");
4903 return 0x0;
4904 }
4905
4906 switch (eType)
4907 {
4908 // share memory
4909 // switch
4910 case E_HVD_GDATA_DISP_INFO_ADDR:
4911 {
4912 u32Ret = (MS_VIRT) (&pShm->DispInfo);
4913 break;
4914 }
4915 case E_HVD_GDATA_MIU_SEL:
4916 u32Ret = pShm->u32VDEC_MIU_SEL;
4917 break;
4918 case E_HVD_GDATA_FRAMEBUF_ADDR:
4919 u32Ret = pShm->u32FrameBufAddr;
4920 break;
4921 case E_HVD_GDATA_FRAMEBUF_SIZE:
4922 u32Ret = pShm->u32FrameBufSize;
4923 break;
4924 case E_HVD_GDATA_FRAMEBUF2_ADDR:
4925 u32Ret = pShm->u32FrameBuf2Addr;
4926 break;
4927 case E_HVD_GDATA_FRAMEBUF2_SIZE:
4928 u32Ret = pShm->u32FrameBuf2Size;
4929 break;
4930 case E_HVD_GDATA_CMA_ALLOC_DONE:
4931 u32Ret = pShm->bCMA_AllocDone;
4932 break;
4933 case E_HVD_GDATA_CMA_USED:
4934 u32Ret = pShm->bCMA_Use;
4935 break;
4936 case E_HVD_GDATA_DYNMC_DISP_PATH_STATUS:
4937 u32Ret = pShm->stDynmcDispPath.u8ConnectStatus;//pShm->u8SetDynmcDispPathStatus;
4938 break;
4939 // report
4940 case E_HVD_GDATA_PTS:
4941 {
4942 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
4943 break;
4944 }
4945 case E_HVD_GDATA_U64PTS:
4946 {
4947 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
4948 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
4949 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4950 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4951 break;
4952 }
4953 case E_HVD_GDATA_U64PTS_PRE_PARSE:
4954 {
4955 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
4956 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
4957 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
4958 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
4959 break;
4960 }
4961 case E_HVD_GDATA_DECODE_CNT:
4962 {
4963 u32Ret = pShm->u32DecodeCnt;
4964 break;
4965 }
4966 case E_HVD_GDATA_DATA_ERROR_CNT:
4967 {
4968 u32Ret = pShm->u32DataErrCnt;
4969 break;
4970 }
4971 case E_HVD_GDATA_DEC_ERROR_CNT:
4972 {
4973 u32Ret = pShm->u32DecErrCnt;
4974 break;
4975 }
4976 case E_HVD_GDATA_ERROR_CODE:
4977 {
4978 u32Ret = (MS_U32) (pShm->u16ErrCode);
4979 break;
4980 }
4981 case E_HVD_GDATA_VPU_IDLE_CNT:
4982 {
4983 u32Ret = pShm->u32VPUIdleCnt;
4984 break;
4985 }
4986 case E_HVD_GDATA_DISP_FRM_INFO:
4987 {
4988 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
4989 break;
4990 }
4991 case E_HVD_GDATA_DEC_FRM_INFO:
4992 {
4993 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
4994 break;
4995 }
4996 case E_HVD_GDATA_ES_LEVEL:
4997 {
4998 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
4999 break;
5000 }
5001 #if HVD_ENABLE_MVC
5002 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
5003 {
5004 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
5005 break;
5006 }
5007 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
5008 {
5009 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
5010 break;
5011 }
5012 #endif
5013
5014 // user data
5015 case E_HVD_GDATA_USERDATA_WPTR:
5016 {
5017 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
5018 break;
5019 }
5020 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
5021 {
5022 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
5023 break;
5024 }
5025 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
5026 {
5027 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
5028 break;
5029 }
5030 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
5031 {
5032 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
5033 break;
5034 }
5035 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
5036 {
5037 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
5038 break;
5039 }
5040 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
5041 {
5042 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
5043 break;
5044 }
5045 // report - modes
5046 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
5047 {
5048 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
5049 break;
5050 }
5051 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
5052 {
5053 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
5054 break;
5055 }
5056 case E_HVD_GDATA_IS_ERR_CONCEAL:
5057 {
5058 u32Ret = pShm->ModeStatus.bIsErrConceal;
5059 break;
5060 }
5061 case E_HVD_GDATA_IS_SYNC_ON:
5062 {
5063 u32Ret = pShm->ModeStatus.bIsSyncOn;
5064 break;
5065 }
5066 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
5067 {
5068 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
5069 break;
5070 }
5071 case E_HVD_GDATA_SYNC_MODE:
5072 {
5073 u32Ret = pShm->ModeStatus.u8SyncType;
5074 break;
5075 }
5076 case E_HVD_GDATA_SKIP_MODE:
5077 {
5078 u32Ret = pShm->ModeStatus.u8SkipMode;
5079 break;
5080 }
5081 case E_HVD_GDATA_DROP_MODE:
5082 {
5083 u32Ret = pShm->ModeStatus.u8DropMode;
5084 break;
5085 }
5086 case E_HVD_GDATA_DISPLAY_DURATION:
5087 {
5088 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
5089 break;
5090 }
5091 case E_HVD_GDATA_FRC_MODE:
5092 {
5093 u32Ret = pShm->ModeStatus.u8FrcMode;
5094 break;
5095 }
5096 case E_HVD_GDATA_NEXT_PTS:
5097 {
5098 u32Ret = pShm->u32NextPTS;
5099 break;
5100 }
5101 case E_HVD_GDATA_DISP_Q_SIZE:
5102 {
5103 u32Ret = pShm->u16DispQSize;
5104 break;
5105 }
5106 case E_HVD_GDATA_DISP_Q_PTR:
5107 {
5108 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
5109 break;
5110 }
5111 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
5112 {
5113 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
5114 break;
5115 }
5116 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
5117 {
5118 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
5119 break;
5120 }
5121 case E_HVD_GDATA_REAL_FRAMERATE:
5122 {
5123 // return VPS/VUI timing info framerate, and 0 if timing info not exist
5124 u32Ret = pShm->u32RealFrameRate;
5125 break;
5126 }
5127 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
5128 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
5129 break;
5130 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
5131 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
5132 break;
5133 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
5134 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
5135 break;
5136 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
5137 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
5138 break;
5139 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
5140 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
5141 break;
5142 case E_HVD_GDATA_FW_STATUS_FLAG:
5143 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
5144 break;
5145
5146 // internal control
5147 case E_HVD_GDATA_IS_1ST_FRM_RDY:
5148 {
5149 u32Ret = pShm->bIs1stFrameRdy;
5150 break;
5151 }
5152 case E_HVD_GDATA_IS_I_FRM_FOUND:
5153 {
5154 u32Ret = pShm->bIsIFrmFound;
5155 break;
5156 }
5157 case E_HVD_GDATA_IS_SYNC_START:
5158 {
5159 u32Ret = pShm->bIsSyncStart;
5160 break;
5161 }
5162 case E_HVD_GDATA_IS_SYNC_REACH:
5163 {
5164 u32Ret = pShm->bIsSyncReach;
5165 break;
5166 }
5167 case E_HVD_GDATA_FW_VERSION_ID:
5168 {
5169 u32Ret = pShm->u32FWVersionID;
5170 break;
5171 }
5172 case E_HVD_GDATA_FW_IF_VERSION_ID:
5173 {
5174 u32Ret = pShm->u32FWIfVersionID;
5175 break;
5176 }
5177 case E_HVD_GDATA_BBU_Q_NUMB:
5178 {
5179 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
5180 break;
5181 }
5182 case E_HVD_GDATA_DEC_Q_NUMB:
5183 {
5184 u32Ret = pShm->u16DecQNumb;
5185 break;
5186 }
5187 case E_HVD_GDATA_DISP_Q_NUMB:
5188 {
5189 u32Ret = pShm->u16DispQNumb;
5190 break;
5191 }
5192 case E_HVD_GDATA_PTS_Q_NUMB:
5193 {
5194 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
5195 break;
5196 }
5197 case E_HVD_GDATA_FW_INIT_DONE:
5198 {
5199 u32Ret = pShm->bInitDone;
5200 break;
5201 }
5202 // debug
5203 case E_HVD_GDATA_SKIP_CNT:
5204 {
5205 u32Ret = pShm->u32SkipCnt;
5206 break;
5207 }
5208 case E_HVD_GDATA_GOP_CNT:
5209 {
5210 u32Ret = pShm->u32DropCnt;
5211 break;
5212 }
5213 case E_HVD_GDATA_DISP_CNT:
5214 {
5215 u32Ret = pShm->u32DispCnt;
5216 break;
5217 }
5218 case E_HVD_GDATA_DROP_CNT:
5219 {
5220 u32Ret = pShm->u32DropCnt;
5221 break;
5222 }
5223 case E_HVD_GDATA_DISP_STC:
5224 {
5225 u32Ret = pShm->u32DispSTC;
5226 break;
5227 }
5228 case E_HVD_GDATA_VSYNC_CNT:
5229 {
5230 u32Ret = pShm->u32VsyncCnt;
5231 break;
5232 }
5233 case E_HVD_GDATA_MAIN_LOOP_CNT:
5234 {
5235 u32Ret = pShm->u32MainLoopCnt;
5236 break;
5237 }
5238
5239 // AVC
5240 case E_HVD_GDATA_AVC_LEVEL_IDC:
5241 {
5242 u32Ret = pShm->u16AVC_SPS_LevelIDC;
5243 break;
5244 }
5245 case E_HVD_GDATA_AVC_LOW_DELAY:
5246 {
5247 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
5248 break;
5249 }
5250 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
5251 {
5252 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
5253 break;
5254 }
5255 case E_HVD_GDATA_FW_FLUSH_STATUS:
5256 {
5257 u32Ret = (MS_U32) (pShm->u8FlushStatus);
5258 break;
5259 }
5260 case E_HVD_GDATA_FW_CODEC_TYPE:
5261 {
5262 u32Ret = pShm->u32CodecType;
5263 break;
5264 }
5265 case E_HVD_GDATA_FW_ES_BUF_STATUS:
5266 {
5267 u32Ret = (MS_U32)pShm->u8ESBufStatus;
5268 break;
5269 }
5270 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
5271 {
5272 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
5273 {
5274 u32Ret = 1;
5275 }
5276 else
5277 {
5278 u32Ret = 0;
5279 }
5280 break;
5281 }
5282
5283 // SRAM
5284
5285 // Mailbox
5286 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
5287 {
5288 u32Ret = pShm->u32FwState;
5289 break;
5290 }
5291 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
5292 {
5293 u32Ret = pShm->bSpsChange;
5294 break;
5295 }
5296 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
5297 {
5298 u32Ret = pShm->bSpsChange;
5299
5300 if (pShm->bSpsChange &&
5301 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
5302 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
5303 {
5304 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
5305 }
5306
5307 break;
5308 }
5309 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
5310 {
5311 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5312
5313 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
5314 {
5315 u32Ret = pShm->u32FwInfo;
5316 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
5317 }
5318 break;
5319 }
5320 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
5321 {
5322 if (pShm->bIsTrigDisp) // not clear yet
5323 {
5324 u32Ret = FALSE;
5325 }
5326 else
5327 {
5328 u32Ret = TRUE;
5329 }
5330 break;
5331 }
5332 case E_HVD_GDATA_ES_READ_PTR:
5333 {
5334 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5335 break;
5336 }
5337 case E_HVD_GDATA_ES_WRITE_PTR:
5338 {
5339 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
5340 break;
5341 }
5342 case E_HVD_GDATA_BBU_READ_PTR:
5343 {
5344 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
5345 break;
5346 }
5347 case E_HVD_GDATA_BBU_WRITE_PTR:
5348 {
5349 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5350 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5351 {
5352 u32Ret = pHVDHalContext->u32VP8BBUWptr;
5353 }
5354 else
5355 {
5356 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5357 }
5358 break;
5359 }
5360 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
5361 {
5362 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5363
5364 u32Ret = pCtrl->u32BBUWptr_Fired;
5365
5366 break;
5367 }
5368 case E_HVD_GDATA_VPU_PC_CNT:
5369 {
5370 u32Ret = _HVD_EX_GetPC();
5371 break;
5372 }
5373 case E_HVD_GDATA_ES_QUANTITY:
5374 {
5375 u32Ret=_HVD_EX_GetESQuantity(u32Id);
5376 break;
5377 }
5378
5379
5380 // FW def
5381 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
5382 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
5383 break;
5384
5385 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
5386 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
5387 break;
5388 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
5389 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
5390 break;
5391 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
5392 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5393 break;
5394 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
5395 u32Ret = MAX_PTS_TABLE_SIZE;
5396 break;
5397 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
5398 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
5399 break;
5400 case E_HVD_GDATA_FW_DS_BUF_ADDR:
5401 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
5402 break;
5403 case E_HVD_GDATA_FW_DS_BUF_SIZE:
5404 u32Ret = pShm->u32DSBuffSize; //3k or 6k
5405 break;
5406 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
5407 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
5408 break;
5409 case E_HVD_GDATA_FW_DS_INFO_ADDR:
5410 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
5411 break;
5412 case E_HVD_GDATA_FW_DS_IS_ENABLED:
5413 {
5414 if (pShm->bDSIsRunning)
5415 {
5416 u32Ret = TRUE;
5417 }
5418 else
5419 {
5420 u32Ret = FALSE;
5421 }
5422 break;
5423 }
5424 #if (HVD_ENABLE_IQMEM)
5425 case E_HVD_GDATA_FW_IQMEM_CTRL:
5426 {
5427
5428 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
5429
5430 break;
5431 }
5432 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
5433 {
5434 if(pShm->bIsIQMEMSupport){
5435 u32Ret = TRUE;
5436 }
5437 else{
5438
5439 u32Ret = FALSE;
5440 }
5441
5442 break;
5443 }
5444 #endif
5445 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
5446 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
5447 break;
5448 case E_HVD_GDATA_FIELD_PIC_FLAG:
5449 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
5450 break;
5451 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
5452 u32Ret = pShm->u32SeamlessTSStatus;
5453 break;
5454 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
5455 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
5456 break;
5457 #ifdef VDEC3
5458 case E_HVD_GDATA_FW_VBBU_ADDR:
5459 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
5460 break;
5461 #endif
5462 case E_HVD_GDATA_SEQ_CHANGE_INFO:
5463 u32Ret = (MS_U32)pShm->u32SeqChangeInfo;
5464 break;
5465 default:
5466 break;
5467 }
5468 return u32Ret;
5469 }
5470
HAL_HVD_EX_GetDVSupportProfiles(void)5471 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
5472 {
5473 #if 0 // wait avc finish DV dual job
5474 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5475 #else
5476 return E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5477 #endif
5478 }
5479
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)5480 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
5481 {
5482 switch (u32DV_Stream_Profile)
5483 {
5484 #if 0 // wait avc finish DV dual job
5485 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
5486 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
5487 #endif
5488
5489 #if 0 // unsupported profile
5490 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
5491 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5492 #endif
5493
5494 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
5495 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5496
5497 #if 0 // unsupported profile
5498 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
5499 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5500 #endif
5501
5502 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
5503 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5504
5505 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
5506 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5507
5508 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
5509 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5510
5511 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
5512 default:
5513 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5514 }
5515 }
5516
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)5517 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
5518 {
5519 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5520 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
5521 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5522 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5523 {
5524 // skip mutex
5525 }
5526 else
5527 {
5528 _HAL_HVD_Entry();
5529 }
5530 // check if old SVD cmds
5531 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5532 {
5533 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
5534
5535 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5536 {
5537 return E_HVD_RETURN_INVALID_PARAMETER;
5538 }
5539 else
5540 {
5541 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5542 }
5543 }
5544
5545 if (u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5546 {
5547 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5548 }
5549
5550 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5551 {
5552 if (u32Cmd == E_HVD_CMD_FLUSH)
5553 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5554 }
5555
5556 if (u32Cmd == E_HVD_CMD_FLUSH &&
5557 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5558 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5559 {
5560 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5561 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5562 {
5563 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5564 {
5565 HVD_Delay_ms(1);
5566 }
5567 else
5568 {
5569 _HAL_HVD_Release();
5570 HVD_Delay_ms(1);
5571 _HAL_HVD_Entry();
5572 }
5573 }
5574 }
5575
5576 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
5577
5578 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5579 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5580 {
5581 return eRet;
5582 }
5583 else
5584 {
5585 _HAL_HVD_Return(eRet);
5586 }
5587 }
5588
HAL_HVD_EX_DeInit(MS_U32 u32Id)5589 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5590 {
5591 HVD_Return eRet = E_HVD_RETURN_FAIL;
5592 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5593 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5594 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5595 MS_U8 u8MiuSel;
5596 MS_U32 u32StartOffset;
5597 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5598
5599 #if HVD_ENABLE_TIME_MEASURE
5600 MS_U32 ExitTimeCnt = 0;
5601 ExitTimeCnt = HVD_GetSysTime_ms();
5602 #endif
5603
5604 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
5605
5606 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5607
5608 if (E_HVD_RETURN_SUCCESS != eRet)
5609 {
5610 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5611 }
5612
5613 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5614
5615 if (E_HVD_RETURN_SUCCESS != eRet)
5616 {
5617 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5618 }
5619
5620 // check FW state to make sure it's STOP DONE
5621 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5622 {
5623 if (HVD_GetSysTime_ms() > u32Timeout)
5624 {
5625 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
5626
5627 //return E_HVD_RETURN_TIMEOUT;
5628 eRet = E_HVD_RETURN_TIMEOUT;
5629 break;
5630 }
5631 }
5632
5633 if (pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt)
5634 {
5635 HVD_EX_MSG_INF("VDEC PLUS: DropRatio %d, Drop:0.%d (%d), Dec:0.%d (%d), Disp:0.%d\n",
5636 pShm->u8VdecPlusDropRatio,
5637 100*pShm->u32VdecPlusDropCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5638 pShm->u32VdecPlusDropCnt,
5639 100*pShm->u32VdecPlusDecCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5640 pShm->u32VdecPlusDecCnt,
5641 100*pShm->u32VdecPlusDispPicCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt));
5642 }
5643 else
5644 {
5645 HVD_EX_MSG_INF("VDEC PLUS DISABLE: DropRatio %d, Drop: %d, Dec: %d, Disp: %d\n",
5646 pShm->u8VdecPlusDropRatio,
5647 pShm->u32VdecPlusDropCnt,
5648 pShm->u32VdecPlusDecCnt,
5649 pShm->u32VdecPlusDispPicCnt);
5650 }
5651
5652 VPU_EX_FWCodeCfg fwCfg;
5653 VPU_EX_TaskInfo taskInfo;
5654 VPU_EX_NDecInitPara nDecInitPara;
5655
5656 nDecInitPara.pFWCodeCfg = &fwCfg;
5657 nDecInitPara.pTaskInfo = &taskInfo;
5658
5659 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5660 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5661
5662 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);//power control
5663 #if 0
5664 taskInfo.u32Id = u32Id;
5665 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5666 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5667 #endif
5668
5669 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5670 {
5671 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5672 }
5673 else
5674 {
5675 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5676 }
5677
5678 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5679 {
5680 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5681 }
5682
5683 /* clear es buffer */
5684 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5685 {
5686 //printf("Clear ES buffer\n");
5687
5688 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5689 }
5690
5691 //_HAL_HVD_MutexDelete();
5692
5693 #if HVD_ENABLE_TIME_MEASURE
5694 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5695 #endif
5696
5697 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
5698 #ifndef VDEC3
5699 // reset bbu wptr
5700 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5701 {
5702 if(TRUE == HAL_VPU_EX_HVDInUsed())
5703 {
5704 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5705 {
5706 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5707 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5708 }
5709 else
5710 {
5711 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5712 {
5713 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5714 }
5715 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5716 }
5717 }
5718 else
5719 {
5720 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
5721 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
5722 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
5723 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5724 {
5725 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5726 {
5727 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5728 }
5729 }
5730 else
5731 {
5732 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5733 }
5734 }
5735 }
5736 #endif
5737 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5738
5739 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5740 {
5741 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
5742 }
5743
5744 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
5745 {
5746
5747 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
5748
5749 _HAL_HVD_Entry();
5750 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
5751 _HAL_HVD_Release();
5752
5753 }
5754
5755 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
5756 HVD_EX_MSG_DBG("success\n");
5757
5758 return eRet;
5759 }
5760
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5761 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5762 {
5763 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5764 MS_U32 u32Addr = 0;
5765 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5766 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5767
5768 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5769
5770 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5771 {
5772 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5773
5774 if (E_HVD_RETURN_SUCCESS != eRet)
5775 {
5776 return eRet;
5777 }
5778 }
5779
5780 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5781
5782 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5783 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5784 {
5785 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5786
5787 if (E_HVD_RETURN_SUCCESS != eRet)
5788 {
5789 return eRet;
5790 }
5791 }
5792
5793 u32Addr = pInfo->u32Staddr;
5794
5795 if (pInfo->bRVBrokenPacket)
5796 {
5797 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5798 }
5799
5800 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5801 {
5802 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5803 }
5804 else
5805 {
5806 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5807 }
5808
5809 if (E_HVD_RETURN_SUCCESS != eRet)
5810 {
5811 return eRet;
5812 }
5813
5814 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5815 {
5816 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5817 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5818
5819 if (E_HVD_RETURN_SUCCESS != eRet)
5820 {
5821 return eRet;
5822 }
5823 }
5824
5825 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5826
5827 // do not add local pointer
5828 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5829 {
5830 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5831
5832 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5833 (u32PacketStAddr <
5834 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5835 {
5836 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5837 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5838 }
5839 else
5840 {
5841 //null packet
5842 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5843 pCtrl->LastNal.u32NalSize = 0;
5844 }
5845 }
5846 else
5847 {
5848 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5849 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5850 }
5851
5852 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5853 pCtrl->u32BBUPacketCnt++;
5854
5855 return eRet;
5856 }
5857
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5858 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5859 {
5860 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5861 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5862 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
5863 if(bCurrentStatus == bEnable)
5864 return;
5865
5866 if (bEnable)
5867 {
5868 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5869 }
5870 else
5871 {
5872 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5873 }
5874 }
5875
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5876 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5877 {
5878 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5879 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5880
5881 if (bEnable)
5882 {
5883 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5884 }
5885 else
5886 {
5887 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5888 }
5889 }
5890
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)5891 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
5892 {
5893 MS_U32 u32RB = 0;
5894 switch(eISRType)
5895 {
5896 case E_HWDEC_ISR_HVD:
5897 u32RB = REG_HVD_BASE;
5898 break;
5899 #if SUPPORT_EVD
5900 case E_HWDEC_ISR_EVD:
5901 u32RB = REG_EVD_BASE;
5902 break;
5903 #endif
5904 #if SUPPORT_G2VP9
5905 case E_HWDEC_ISR_G2VP9:
5906 break;
5907 #endif
5908 default:
5909 break;
5910 }
5911 if(u32RB)
5912 {
5913 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5914 }
5915 }
5916
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5917 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5918 {
5919 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5920 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5921
5922 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5923 }
5924
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)5925 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
5926 {
5927 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5928 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5929
5930 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
5931 {
5932 return FALSE;
5933 }
5934 else
5935 {
5936 return TRUE;
5937 }
5938 }
5939
HAL_HVD_EX_IsAlive(MS_U32 u32Id)5940 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
5941 {
5942 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5943
5944 if (pCtrl)
5945 {
5946 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
5947 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
5948 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
5949 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
5950 {
5951 return FALSE;
5952 }
5953 else
5954 {
5955 return TRUE;
5956 }
5957 }
5958 else
5959 {
5960 return FALSE;
5961 }
5962 }
5963
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)5964 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
5965 {
5966 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5967 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5968 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5969
5970 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5971 {
5972 HAL_HVD_EX_ReadMemory();
5973
5974 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
5975 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
5976
5977 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
5978 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
5979 }
5980
5981 return TRUE;
5982 }
5983
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)5984 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
5985 {
5986 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5987 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5988 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5989 MS_U32 u32Data;
5990 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5991
5992 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
5993
5994 HAL_HVD_EX_FlushMemory();
5995 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5996 {
5997 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5998 pCtrl->LastNal.u32NalAddr = u32Data;
5999 pCtrl->LastNal.u32NalSize = 0;
6000 }
6001
6002 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
6003 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
6004
6005 return TRUE;
6006 }
6007
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)6008 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
6009 {
6010 if (bEnable)
6011 {
6012 if (HAL_VPU_EX_IsEVDR2())
6013 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6014 else
6015 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
6016 }
6017 else
6018 {
6019 #if defined (__aeon__)
6020 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6021 #else // defined (__mips__)
6022 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
6023 #endif
6024 }
6025 }
6026
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)6027 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
6028 {
6029 return 0;
6030 }
6031
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)6032 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
6033 {
6034 return;
6035 }
6036
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)6037 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
6038 {
6039 //if( u16Clock == 0 )
6040 return 216; //140;
6041 //if( )
6042 }
6043
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)6044 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
6045 {
6046 //MS_BOOL bBitMIU1 = FALSE;
6047 //MS_BOOL bCodeMIU1 = FALSE;
6048 MS_U8 u8BitMiuSel = 0;
6049 MS_U8 u8CodeMiuSel = 0;
6050 MS_U32 u32BitStartOffset;
6051 MS_U32 u32CodeStartOffset;
6052 //MS_U8 u8MiuSel;
6053 //MS_U32 u32StartOffset;
6054 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6055 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6056 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6057 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
6058
6059 #if HVD_ENABLE_MVC
6060 if(HAL_HVD_EX_CheckMVCID(u32Id))
6061 {
6062 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
6063 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
6064 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
6065 {
6066 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
6067 }
6068 }
6069 #endif /// HVD_ENABLE_MVC
6070
6071 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6072 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6073
6074
6075
6076
6077 if (u8BitMiuSel != u8CodeMiuSel)
6078 {
6079 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
6080 BDMA_Result bdmaRlt;
6081 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6082
6083 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6084 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
6085 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6086
6087 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
6088
6089 if (E_BDMA_OK != bdmaRlt)
6090 {
6091 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
6092 }
6093 #else
6094 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6095
6096 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6097 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
6098 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6099
6100 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
6101 #endif
6102 }
6103
6104 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
6105
6106 HAL_HVD_EX_FlushMemory();
6107
6108 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6109 {
6110 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
6111 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
6112 }
6113 else
6114 {
6115 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
6116
6117 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
6118 }
6119 }
6120
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)6121 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
6122 {
6123 if (bEnable)
6124 {
6125 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
6126 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
6127 }
6128 else
6129 {
6130 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
6131 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
6132 }
6133 }
6134
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)6135 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
6136 {
6137 MS_U32 tmp1 = 0;
6138 MS_U32 tmp2 = 0;
6139 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6140
6141 HAL_HVD_EX_ReadMemory();
6142
6143 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
6144 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
6145
6146 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6147 {
6148 MS_U32 u32Tmp = u32UartCtrl;
6149
6150 HVD_EX_MSG_DBG("\n");
6151 u32UartCtrl = 0; // turn off debug message to prevent other function prints
6152 printf("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
6153 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
6154
6155 printf("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
6156 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
6157 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
6158 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
6159
6160 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
6161 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
6162 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
6163
6164 printf("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
6165 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
6166 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
6167 _HVD_EX_GetESLevel(u32Id));
6168
6169 printf("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
6170 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
6171 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
6172 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
6173 printf
6174 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
6175 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
6176 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
6177 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
6178 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
6179 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
6180 pShm->ModeStatus.bShowOneField);
6181
6182 u32UartCtrl = u32Tmp; // recover debug level
6183 }
6184 }
6185
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)6186 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
6187 {
6188 MS_U8 *u32Addr = NULL;
6189 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6190 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6191
6192 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6193 {
6194 return;
6195 }
6196
6197 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
6198
6199 *u32NalSize = *(u32Addr + 2) & 0x1f;
6200 *u32NalSize <<= 8;
6201 *u32NalSize |= *(u32Addr + 1) & 0xff;
6202 *u32NalSize <<= 8;
6203 *u32NalSize |= *(u32Addr) & 0xff;
6204
6205 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
6206 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
6207 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
6208 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
6209 }
6210
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)6211 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
6212 {
6213 MS_U32 u32CurIdx = 0;
6214 MS_BOOL bFinished = FALSE;
6215 MS_U32 u32NalOffset = 0;
6216 MS_U32 u32NalSize = 0;
6217 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6218
6219 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
6220 {
6221 return;
6222 }
6223
6224 u32CurIdx = u32StartIdx;
6225
6226 do
6227 {
6228 if (u32CurIdx == u32EndIdx)
6229 {
6230 bFinished = TRUE;
6231 }
6232
6233 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
6234
6235 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
6236 {
6237 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
6238 }
6239
6240 u32CurIdx++;
6241
6242 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6243 {
6244 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
6245 }
6246 } while (bFinished == TRUE);
6247 }
6248
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)6249 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
6250 {
6251 MS_U32 i = 0;
6252 MS_U32 value = 0;
6253
6254 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6255 {
6256 HVD_EX_MSG_DBG("\n");
6257
6258 for (i = 0; i <= u32Num; i++)
6259 {
6260 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
6261 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
6262 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
6263
6264 if (value == 0)
6265 {
6266 break;
6267 }
6268
6269 printf(" %08x", value);
6270
6271 if (((i % 8) + 1) == 8)
6272 {
6273 printf(" |%u\n", i + 1);
6274 }
6275 }
6276
6277 printf("\nHVD Dump HW status End: total number:%u\n", i);
6278 }
6279 }
6280
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)6281 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
6282 {
6283 if (pDrvCtrl)
6284 {
6285 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
6286 }
6287 }
6288
6289 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)6290 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
6291 {
6292 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
6293 }
6294
HAL_HVD_EX_GetView(MS_U32 u32Id)6295 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
6296 {
6297 if( (0xFF & (u32Id >> 8)) == 0x10)
6298 return E_VDEC_EX_MAIN_VIEW;
6299 else
6300 return E_VDEC_EX_SUB_VIEW;
6301 }
6302 #endif ///HVD_ENABLE_MVC
6303
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)6304 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
6305 {
6306 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
6307 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
6308 return;
6309 }
6310
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)6311 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
6312 {
6313 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
6314 return;
6315 }
6316
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)6317 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
6318 {
6319 MS_U64 _hw_max_pixel = 0;
6320 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
6321
6322 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
6323 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
6324 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
6325 }
6326
6327
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)6328 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
6329 {
6330 #if 1
6331 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6332 MS_U16 u16QNum = pShm->u16DispQNumb;
6333 MS_U16 u16QPtr = pShm->u16DispQPtr;
6334 // MS_U16 u16QSize = pShm->u16DispQSize;
6335 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
6336 MS_U32 u32DispQNum = 0;
6337 #if HVD_ENABLE_MVC
6338 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
6339
6340 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6341 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
6342
6343 if(bMVC || bDolbyVision)
6344 {
6345 #if 0
6346 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
6347 {
6348 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
6349 }
6350 #endif
6351
6352 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
6353 //search the next frame to display
6354 while (u16QNum > 0)
6355 {
6356 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
6357 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
6358 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6359
6360 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
6361 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6362 {
6363 /// For MVC. Output views after the pair of (base and depend) views were decoded.
6364 /// Check the depned view was initial when Output the base view.
6365 if((u16QPtr%2) == 0)
6366 {
6367 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
6368 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
6369 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
6370 {
6371 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
6372 ///printf("Return NULL.\n");
6373 break;
6374 }
6375 }
6376 u32DispQNum++;
6377 }
6378
6379 u16QNum--;
6380 //go to next frame in the dispQ
6381 u16QPtr++;
6382
6383 if (u16QPtr >= pShm->u16DispQSize)
6384 {
6385 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
6386 }
6387 }
6388 }
6389 else
6390 #endif ///HVD_ENABLE_MVC
6391 {
6392 #if 0
6393 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
6394 {
6395 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
6396 }
6397 #endif
6398 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
6399 //search the next frame to display
6400 while (u16QNum != 0)
6401 {
6402 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6403
6404 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
6405 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6406 {
6407 u32DispQNum++;
6408 }
6409
6410 u16QNum--;
6411 //go to next frame in the dispQ
6412 u16QPtr++;
6413
6414 if (u16QPtr == pShm->u16DispQSize)
6415 {
6416 u16QPtr = 0; //wrap to the begin
6417 }
6418 }
6419 }
6420
6421 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
6422 return u32DispQNum;
6423 #else
6424 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
6425 return pShm->u16DispQNumb;
6426 #endif
6427 }
6428
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)6429 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
6430 {
6431 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6432 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
6433 (u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
6434 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6435 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
6436 #if SUPPORT_G2VP9 && defined(VDEC3)
6437 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
6438 #else // Not using G2 VP9 implies using Mstar EVD VP9
6439 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6440 #endif
6441 else
6442 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
6443 }
6444
6445 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)6446 void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
6447 {
6448 #ifdef CONFIG_MSTAR_CLKM
6449 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD, bEnable);
6450 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_PPU, bEnable);
6451 #else
6452 if (bEnable)
6453 {
6454 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6455 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6456 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6457 }
6458 else
6459 {
6460 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6461 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6462 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6463 }
6464
6465 switch (pHVDHalContext->u32EVDClockType)
6466 {
6467 case 576:
6468 {
6469 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6470 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6471 break;
6472 }
6473 case 532:
6474 {
6475 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
6476 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
6477 break;
6478 }
6479 case 456:
6480 {
6481 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6482 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6483 _HVD_WriteWordMask(REG_EVDPLL_LOOP_DIV_SECOND, REG_EVDPLL_LOOP_DIV_SECOND_456MHZ, REG_EVDPLL_LOOP_DIV_SECOND_MASK);
6484 break;
6485 }
6486 case 466:
6487 {
6488 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6489 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
6490 break;
6491 }
6492 case 480:
6493 {
6494 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
6495 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6496 break;
6497 }
6498 case 384:
6499 {
6500 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
6501 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
6502 break;
6503 }
6504 case 320:
6505 {
6506 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
6507 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
6508 break;
6509 }
6510 case 240:
6511 {
6512 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
6513 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6514 break;
6515 }
6516 case 192:
6517 {
6518 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
6519 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
6520 break;
6521 }
6522 default:
6523 {
6524 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6525 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6526 break;
6527 }
6528 }
6529 #endif
6530 #ifdef CONFIG_MSTAR_SRAMPD
6531 if (bEnable)
6532 {
6533 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6534 HVD_Delay_ms(1);
6535 }
6536 else
6537 {
6538 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6539 HVD_Delay_ms(1);
6540 }
6541 #endif
6542 return;
6543 }
6544
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)6545 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
6546 {
6547 #ifndef VDEC3
6548 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6549 #endif
6550 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6551 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6552 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6553
6554 #ifdef VDEC3
6555 if (0 == pCtrl->u32BBUId)
6556 #else
6557 if (0 == u8TaskId)
6558 #endif
6559 {
6560 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
6561 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6562 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)) & (~HVD_REG_BBU_TSP_INPUT));
6563 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)));
6564 }
6565 else
6566 {
6567 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
6568 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6569 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)) & (~HVD_REG_BBU_TSP_INPUT_BS2));
6570 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)));
6571 }
6572
6573 return;
6574 }
6575
HAL_EVD_EX_DeinitHW(MS_U32 u32Id)6576 MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id)
6577 {
6578 MS_U16 u16Timeout = 1000;
6579 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6580 MS_BOOL isVP8Used = FALSE;
6581 MS_BOOL isAECUsed = FALSE;
6582 MS_BOOL isAVCUsed = FALSE;
6583 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
6584
6585 if(TRUE == HAL_VPU_EX_EVDInUsed())
6586 {
6587 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6588 {
6589 HAL_AEC_PowerCtrl(FALSE);
6590 }
6591 return FALSE;
6592 }
6593 else if(!isAVCUsed)//no AVC/EVD use , close EVD power
6594 {
6595 _HVD_EX_SetMIUProtectMask(TRUE);
6596
6597 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
6598
6599 while (u16Timeout)
6600 {
6601 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
6602 {
6603 break;
6604 }
6605 u16Timeout--;
6606 }
6607
6608 HAL_EVD_EX_PowerCtrl(u32Id, FALSE);
6609
6610 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6611 {
6612 HAL_AEC_PowerCtrl(FALSE);
6613 }
6614
6615 _HVD_EX_SetMIUProtectMask(FALSE);
6616
6617 return TRUE;
6618 }
6619
6620 return FALSE;
6621 }
6622 #endif
6623
6624 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)6625 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
6626 {
6627 if (bEnable)
6628 {
6629 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6630 }
6631 else
6632 {
6633 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6634 }
6635
6636 switch (pHVDHalContext->u32VP9ClockType)
6637 {
6638 case 432:
6639 {
6640 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6641 break;
6642 }
6643 case 384:
6644 {
6645 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6646 break;
6647 }
6648 case 345:
6649 {
6650 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6651 break;
6652 }
6653 case 320:
6654 {
6655 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6656 break;
6657 }
6658 case 288:
6659 {
6660 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6661 break;
6662 }
6663 case 240:
6664 {
6665 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6666 break;
6667 }
6668 case 216:
6669 {
6670 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6671 break;
6672 }
6673 case 172:
6674 {
6675 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
6676 break;
6677 }
6678 default:
6679 {
6680 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6681 break;
6682 }
6683 }
6684
6685 return;
6686 }
6687
HAL_VP9_EX_DeinitHW(void)6688 MS_BOOL HAL_VP9_EX_DeinitHW(void)
6689 {
6690 MS_U16 u16Timeout = 1000;
6691
6692 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6693
6694 while (u16Timeout)
6695 {
6696 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6697 {
6698 break;
6699 }
6700 u16Timeout--;
6701 }
6702
6703 HAL_VP9_EX_PowerCtrl(FALSE);
6704
6705 return TRUE;
6706 }
6707 #endif
6708
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6709 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6710 {
6711 return TRUE;
6712 }
6713
HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)6714 void HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)
6715 {
6716 MS_VIRT u32StAddr = 0;
6717 MS_U8 u8BitMiuSel = 0;
6718 MS_U8 u8CodeMiuSel = 0;
6719 MS_U8 u8TmpMiuSel = 0;
6720 MS_U32 u32BitStartOffset;
6721 MS_U32 u32CodeStartOffset;
6722
6723 #ifndef VDEC3
6724 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6725 #endif
6726 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6727 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6728 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6729 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6730
6731 _HAL_HVD_Entry();
6732
6733 if (pCtrl == NULL)
6734 {
6735 _HAL_HVD_Return();
6736 }
6737
6738 MS_BOOL bNalTblAlreadySet = FALSE;
6739 VPU_EX_TaskInfo taskInfo;
6740 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
6741 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
6742
6743 bNalTblAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
6744
6745
6746
6747 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6748 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6749
6750 if (u8BitMiuSel != u8CodeMiuSel)
6751 {
6752 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
6753 }
6754 else
6755 {
6756 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
6757 }
6758
6759 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6760 {
6761 #ifdef VDEC3
6762 if (!_HAL_EX_BBU_VP8_InUsed())
6763 #endif
6764 {
6765 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
6766
6767 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
6768 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
6769 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6770
6771 u32StAddr += VP8_BBU_TBL_SIZE;
6772
6773 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
6774 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
6775 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6776 }
6777
6778 _HAL_HVD_Return();
6779 }
6780
6781 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
6782
6783 #ifdef VDEC3
6784 if (!bNalTblAlreadySet)
6785 {
6786 if (pCtrl->u32BBUId == 0)
6787 {
6788 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
6789 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
6790 // -1 is for NAL_TAB_LEN counts from zero.
6791 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6792 }
6793 else
6794 {
6795 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
6796 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
6797 // -1 is for NAL_TAB_LEN counts from zero.
6798 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6799 }
6800 }
6801 #else
6802 if (0 == u8TaskId)
6803 {
6804 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
6805 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
6806 // -1 is for NAL_TAB_LEN counts from zero.
6807 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6808 }
6809 else
6810 {
6811 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
6812 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
6813 // -1 is for NAL_TAB_LEN counts from zero.
6814 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6815 }
6816 #endif
6817
6818
6819 #if (HVD_ENABLE_MVC)
6820 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
6821 {
6822 /// Used sub stream to record sub view data.
6823 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
6824 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
6825
6826 if (u8BitMiuSel != u8CodeMiuSel)
6827 {
6828 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
6829 }
6830 else
6831 {
6832 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
6833 }
6834
6835 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
6836 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
6837 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
6838 // -1 is for NAL_TAB_LEN counts from zero.
6839 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
6840 }
6841 #endif
6842
6843 if (!bNalTblAlreadySet)
6844 {
6845 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
6846 }
6847
6848 _HAL_HVD_Return();
6849 }
6850
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)6851 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6852 {
6853 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6854
6855 if(pCtrl->InitParams.u16ChipECONum == 0)
6856 return FALSE;
6857 else
6858 return TRUE;
6859 }
6860
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6861 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6862 {
6863
6864 }
6865
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6866 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6867 {
6868
6869 }
6870 #endif
6871