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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regHVD.h 98 /// @brief HVD Module Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_HVD_H_ 103 #define _REG_HVD_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 115 //***************************************************************************** 116 // RIU macro 117 #define HVD_MACRO_START do { 118 #define HVD_MACRO_END } while (0) 119 #define HVD_RIU_BASE (u32HVDRegOSBase) 120 121 #define HVD_HIGHBYTE(u16) ((MS_U8)((u16) >> 8)) 122 #define HVD_LOWBYTE(u16) ((MS_U8)(u16)) 123 #define HVD_RIU_READ_BYTE(addr) ( READ_BYTE( HVD_RIU_BASE + (addr) ) ) 124 #define HVD_RIU_READ_WORD(addr) ( READ_WORD( HVD_RIU_BASE + (addr) ) ) 125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } 126 #define HVD_RIU_WRITE_WORD(addr, val) { WRITE_WORD( HVD_RIU_BASE+(addr), val); } 127 128 129 #define _HVD_ReadByte( u32Reg ) HVD_RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1)) 130 131 #define _HVD_Read2Byte( u32Reg ) (HVD_RIU_READ_WORD((u32Reg)<<1)) 132 133 #define _HVD_Read4Byte( u32Reg ) ( (MS_U32)HVD_RIU_READ_WORD((u32Reg)<<1) | ((MS_U32)HVD_RIU_READ_WORD(((u32Reg)+2)<<1)<<16 ) ) 134 135 #define _HVD_ReadRegBit( u32Reg, u8Mask ) (HVD_RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask)) 136 137 #define _HVD_ReadWordBit( u32Reg, u16Mask ) (_HVD_Read2Byte( u32Reg ) & (u16Mask)) 138 139 #define _HVD_WriteRegBit( u32Reg, bEnable, u8Mask ) \ 140 HVD_MACRO_START \ 141 HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \ 142 (HVD_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \ 143 HVD_MACRO_END 144 145 #define _HVD_WriteByte( u32Reg, u8Val ) \ 146 HVD_MACRO_START \ 147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \ 148 HVD_MACRO_END 149 150 #define _HVD_Write2Byte( u32Reg, u16Val ) \ 151 HVD_MACRO_START \ 152 if ( ((u32Reg) & 0x01) ) \ 153 { \ 154 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ 155 HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ 156 } \ 157 else \ 158 { \ 159 HVD_RIU_WRITE_WORD( ((u32Reg)<<1) , u16Val); \ 160 } \ 161 HVD_MACRO_END 162 163 #define _HVD_Write3Byte( u32Reg, u32Val ) \ 164 if ((u32Reg) & 0x01) \ 165 { \ 166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ 167 HVD_RIU_WRITE_WORD( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ 168 } \ 169 else \ 170 { \ 171 HVD_RIU_WRITE_WORD( (u32Reg) << 1, u32Val); \ 172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ 173 } 174 175 #define _HVD_Write4Byte( u32Reg, u32Val ) \ 176 HVD_MACRO_START \ 177 if ((u32Reg) & 0x01) \ 178 { \ 179 HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ 180 HVD_RIU_WRITE_WORD( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ 181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ 182 } \ 183 else \ 184 { \ 185 HVD_RIU_WRITE_WORD( (u32Reg) <<1 , u32Val); \ 186 HVD_RIU_WRITE_WORD( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ 187 } \ 188 HVD_MACRO_END 189 190 #define _HVD_WriteByteMask( u32Reg, u8Val, u8Msk ) \ 191 HVD_MACRO_START \ 192 HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 193 HVD_MACRO_END 194 195 #define _HVD_WriteWordMask( u32Reg, u16Val , u16Msk) \ 196 HVD_MACRO_START \ 197 if ( ((u32Reg) & 0x01) ) \ 198 { \ 199 _HVD_WriteByteMask( ((u32Reg)+1) , (((u16Val) & 0xff00)>>8) , (((u16Msk)&0xff00)>>8) ); \ 200 _HVD_WriteByteMask( (u32Reg) , ((u16Val) & 0x00ff) , ((u16Msk)&0x00ff) ); \ 201 } \ 202 else \ 203 { \ 204 HVD_RIU_WRITE_WORD( ((u32Reg)<<1) , (((u16Val) & (u16Msk)) | (_HVD_Read2Byte( u32Reg ) & (~( u16Msk )))) ); \ 205 } \ 206 HVD_MACRO_END 207 208 //------------------------------------------------------------------------------ 209 // MVD Reg 210 //------------------------------------------------------------------------------ 211 #define REG_MVD_BASE (0x1100) 212 213 #define MVD_REG_STAT_CTRL (REG_MVD_BASE) 214 #define MVD_REG_CTRL_RST BIT(0) 215 #define MVD_REG_CTRL_INIT BIT(2) 216 #define MVD_REG_DISCONNECT_MIU BIT(6) 217 218 #if 1//Note: this setting should be set according client table of each chip 219 #define MIU0_REG_BASE 0x1200 220 #define MIU1_REG_BASE 0x0600 221 222 #define MIU_CLIENT_SELECT_GP2 (MIU0_REG_BASE + (0x007A<<1)) 223 #define MIU_CLIENT_SELECT_GP2_MVD BIT(4) 224 #endif 225 226 227 228 //------------------------------------------------------------------------------ 229 // HVD Reg 230 //------------------------------------------------------------------------------ 231 #define REG_HVD_BASE (0x1B00) 232 #define REG_EVD_BASE (0x60B00) 233 #define REG_G2VP9_BASE (0x60E00) 234 235 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1)) 236 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1)) 237 #define HVD_REG_RESET_SWRST BIT(0) 238 #define HVD_REG_RESET_SWRST_FIN BIT(2) 239 #define HVD_REG_RESET_STOP_BBU BIT(3) 240 #define HVD_REG_RESET_MIU_RDY BIT(4) 241 #define HVD_REG_RESET_MIU1_128 BIT(5) 242 #define HVD_REG_RESET_MIU1_256 BIT(6) 243 #define HVD_REG_MC_MIU_256 BIT(7) 244 #define HVD_REG_RESET_HK_AVS_MODE BIT(8) 245 #define HVD_REG_RESET_HK_RM_MODE BIT(9) 246 #define HVD_REG_RESET_HK_RV9_DEC_MODE BIT(10) 247 #define HVD_REG_RESET_MIU_128 BIT(11) 248 #define HVD_REG_RESET_CPUIF_SEL BIT(12) 249 #define HVD_REG_RESET_ALL_SRAM_SD_EN BIT(13) 250 #define HVD_REG_RESET_MIU_256 BIT(14) 251 #define HVD_REG_RESET_BOND_HD BIT(15) 252 253 #define HVD_REG_ESB_ST_ADDR_L(reg_base) (reg_base + ((0x0002) << 1)) 254 #define HVD_REG_ESB_ST_ADDR_H(reg_base) (reg_base + ((0x0003) << 1)) 255 256 #define HVD_REG_ESB_LENGTH_L(reg_base) (reg_base + ((0x0004) << 1)) 257 #define HVD_REG_ESB_LENGTH_H(reg_base) (reg_base + ((0x0005) << 1)) 258 259 #define HVD_REG_ESB_RPTR(reg_base) (reg_base + ((0x0006) << 1)) 260 #define HVD_REG_ESB_RPTR_POLL BIT(0) 261 262 #define HVD_REG_ESB_RPTR_H(reg_base) (reg_base + ((0x0007) << 1)) 263 264 #define HVD_REG_MIF_BBU(reg_base) (reg_base + ((0x0008) << 1)) 265 #define HVD_REG_MIF_OFFSET_L_BITS 7 266 #define HVD_REG_MIF_OFFSET_H BIT(12) 267 #define HVD_REG_BBU_TSP_INPUT BIT(8) 268 #define HVD_REG_BBU_PASER_MASK (BIT(10) | BIT(9)) 269 #define HVD_REG_BBU_PASER_DISABLE 0 270 #define HVD_REG_BBU_PASER_ENABLE_ALL BIT(9) 271 #define HVD_REG_BBU_PASER_ENABLE_03 (BIT(9) | BIT(10)) 272 #define HVD_REG_BBU_AUTO_NAL_TAB BIT(11) 273 274 #define HVD_REG_NAL_TBL_ST_ADDR_L(reg_base) (reg_base + ((0x0009) << 1)) 275 #define HVD_REG_NAL_TBL_ST_ADDR_H(reg_base) (reg_base + ((0x000A) << 1)) 276 277 #define HVD_REG_HI_MBOX0_L(reg_base) (reg_base + ((0x000B) << 1)) 278 #define HVD_REG_HI_MBOX0_H(reg_base) (reg_base + ((0x000C) << 1)) 279 #define HVD_REG_HI_MBOX1_L(reg_base) (reg_base + ((0x000D) << 1)) 280 #define HVD_REG_HI_MBOX1_H(reg_base) (reg_base + ((0x000E) << 1)) 281 #define HVD_REG_HI_MBOX_SET(reg_base) (reg_base + ((0x000F) << 1)) 282 #define HVD_REG_HI_MBOX0_SET BIT(0) 283 #define HVD_REG_HI_MBOX1_SET BIT(8) 284 285 #define HVD_REG_RISC_MBOX_CLR(reg_base) (reg_base + ((0x0010) << 1)) 286 #define HVD_REG_RISC_MBOX0_CLR BIT(0) 287 #define HVD_REG_RISC_MBOX1_CLR BIT(1) 288 #define HVD_REG_RISC_ISR_CLR BIT(2) 289 #define HVD_REG_NAL_WPTR_SYNC BIT(3) 290 #define HVD_REG_RISC_ISR_MSK BIT(6) 291 #define HVD_REG_RISC_ISR_FORCE BIT(10) 292 293 #define HVD_REG_RISC_MBOX_RDY(reg_base) (reg_base + ((0x0011) << 1)) 294 #define HVD_REG_RISC_MBOX0_RDY BIT(0) 295 #define HVD_REG_RISC_MBOX1_RDY BIT(4) 296 #define HVD_REG_RISC_ISR_VALID BIT(8) 297 298 #define HVD_REG_HI_MBOX_RDY(reg_base) (reg_base + ((0x0012) << 1)) 299 #define HVD_REG_HI_MBOX0_RDY BIT(0) 300 #define HVD_REG_HI_MBOX1_RDY BIT(8) 301 302 #define HVD_REG_RISC_MBOX0_L(reg_base) (reg_base + ((0x0013) << 1)) 303 #define HVD_REG_RISC_MBOX0_H(reg_base) (reg_base + ((0x0014) << 1)) 304 #define HVD_REG_RISC_MBOX1_L(reg_base) (reg_base + ((0x0015) << 1)) 305 #define HVD_REG_RISC_MBOX1_H(reg_base) (reg_base + ((0x0016) << 1)) 306 307 #define HVD_REG_POLL_NAL_RPTR(reg_base) (reg_base + ((0x0017) << 1)) 308 #define HVD_REG_POLL_NAL_RPTR_BIT BIT(0) 309 #define HVD_REG_NAL_RPTR_HI(reg_base) (reg_base + ((0x0018) << 1)) 310 #define HVD_REG_NAL_WPTR_HI(reg_base) (reg_base + ((0x0019) << 1)) 311 #define HVD_REG_NAL_TAB_LEN(reg_base) (reg_base + ((0x0020) << 1)) 312 313 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1)) 314 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1)) 315 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1)) 316 317 /* Second bitstream registers definition */ 318 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1)) 319 #define HVD_REG_MODE_HK_AVS_MODE_BS2 BIT(8) 320 #define HVD_REG_MODE_HK_RM_MODE_BS2 BIT(9) 321 #define HVD_REG_MODE_HK_RV9_DEC_MODE_BS2 BIT(10) 322 323 #define HVD_REG_ESB_ST_ADDR_L_BS2(reg_base) (reg_base + ((0x0032) << 1)) 324 #define HVD_REG_ESB_ST_ADDR_H_BS2(reg_base) (reg_base + ((0x0033) << 1)) 325 326 #define HVD_REG_ESB_LENGTH_L_BS2(reg_base) (reg_base + ((0x0034) << 1)) 327 #define HVD_REG_ESB_LENGTH_H_BS2(reg_base) (reg_base + ((0x0035) << 1)) 328 329 #define HVD_REG_ESB_RPTR_L_BS2(reg_base) (reg_base + ((0x0036) << 1)) 330 #define HVD_REG_ESB_RPTR_H_BS2(reg_base) (reg_base + ((0x0037) << 1)) 331 332 #define HVD_REG_MIF_BBU_BS2(reg_base) (reg_base + ((0x0038) << 1)) 333 #define HVD_REG_MIF_OFFSET_L_BITS_BS2 7 334 #define HVD_REG_MIF_OFFSET_H_BS2 BIT(12) 335 #define HVD_REG_BBU_TSP_INPUT_BS2 BIT(8) 336 #define HVD_REG_BBU_PASER_MASK_BS2 (BIT(10) | BIT(9)) 337 #define HVD_REG_BBU_PASER_DISABLE_BS2 0 338 #define HVD_REG_BBU_PASER_ENABLE_ALL_BS2 BIT(9) 339 #define HVD_REG_BBU_PASER_ENABLE_03_BS2 (BIT(9) | BIT(10)) 340 #define HVD_REG_BBU_AUTO_NAL_TAB_BS2 BIT(11) 341 342 #define HVD_REG_NAL_TBL_ST_ADDR_L_BS2(reg_base) (reg_base + ((0x0039) << 1)) 343 #define HVD_REG_NAL_TBL_ST_ADDR_H_BS2(reg_base) (reg_base + ((0x003A) << 1)) 344 345 #define HVD_REG_NAL_RPTR_HI_BS2(reg_base) (reg_base + ((0x003B) << 1)) 346 #define HVD_REG_NAL_WPTR_HI_BS2(reg_base) (reg_base + ((0x003C) << 1)) 347 #define HVD_REG_NAL_TAB_LEN_BS2(reg_base) (reg_base + ((0x003D) << 1)) 348 349 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1)) 350 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1)) 351 352 /* VP8 Registers */ 353 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1)) 354 #define HVD_REG_HK_VP8_DEC_MODE BIT(0) 355 #define HVD_REG_HK_PLAYER_FM BIT(1) 356 357 #define HVD_REG_ESB_ST_ADR_L_BS34 (REG_HVD_BASE + ((0x0042) << 1)) 358 #define HVD_REG_ESB_ST_ADR_H_BS34 (REG_HVD_BASE + ((0x0043) << 1)) 359 #define HVD_REG_ESB_LENGTH_L_BS34 (REG_HVD_BASE + ((0x0044) << 1)) 360 #define HVD_REG_ESB_LENGTH_H_BS34 (REG_HVD_BASE + ((0x0045) << 1)) 361 362 #define HVD_REG_MIF_BS34 (REG_HVD_BASE + ((0x0048) << 1)) 363 #define HVD_REG_BS34_MIF_OFFSET_L_BITS 7 364 #define HVD_REG_BS34_MIF_OFFSET_H BIT(12) 365 #define HVD_REG_BS34_TSP_INPUT BIT(8) 366 #define HVD_REG_BS34_PASER_MASK (BIT(10) | BIT(9)) 367 #define HVD_REG_BS34_PASER_DISABLE 0 368 #define HVD_REG_BS34_PASER_ENABLE_ALL BIT(9) 369 #define HVD_REG_BS34_PASER_ENABLE_03 (BIT(9) | BIT(10)) 370 #define HVD_REG_BS34_AUTO_NAL_TAB BIT(11) 371 #define HVD_REG_BS34_NAL_BUF_SKIP BIT(13) 372 #define HVD_REG_BS34_NAL_BUF_SKIP_RDY BIT(14) 373 374 #define HVD_REG_NAL_TAB_ST_L_BS3 (REG_HVD_BASE + ((0x0049) << 1)) 375 #define HVD_REG_NAL_TAB_ST_H_BS3 (REG_HVD_BASE + ((0x004A) << 1)) 376 #define HVD_REG_NAL_RPTR_HI_BS3 (REG_HVD_BASE + ((0x004B) << 1)) 377 #define HVD_REG_NAL_WPTR_HI_BS3 (REG_HVD_BASE + ((0x004C) << 1)) 378 #define HVD_REG_NAL_TAB_LEN_BS3 (REG_HVD_BASE + ((0x004D) << 1)) 379 #define HVD_REG_NAL_TAB_ST_L_BS4 (REG_HVD_BASE + ((0x0059) << 1)) 380 #define HVD_REG_NAL_TAB_ST_H_BS4 (REG_HVD_BASE + ((0x005A) << 1)) 381 #define HVD_REG_NAL_RPTR_HI_BS4 (REG_HVD_BASE + ((0x005B) << 1)) 382 #define HVD_REG_NAL_WPTR_HI_BS4 (REG_HVD_BASE + ((0x005C) << 1)) 383 #define HVD_REG_NAL_TAB_LEN_BS4 (REG_HVD_BASE + ((0x005D) << 1)) 384 385 //------------------------------------------------------------------------------ 386 // EVD Reg 387 //------------------------------------------------------------------------------ 388 #define REG_EVDPLL_BASE (0x10B00) 389 #define REG_EVDPLL_PD (REG_EVDPLL_BASE + ((0x0041) << 1)) 390 #define REG_EVDPLL_PD_DIS BIT(8) 391 392 #define EVD_REG_RESET (REG_EVD_BASE + ((0x0001) << 1)) 393 #define EVD_REG_RESET_SWRST BIT(0) 394 #define EVD_REG_RESET_SWRST_FIN BIT(2) 395 #define EVD_REG_RESET_STOP_BBU BIT(3) 396 #define EVD_REG_RESET_MIU_RDY BIT(4) 397 #define EVD_REG_RESET_MIU1_128 BIT(5) 398 #define EVD_REG_RESET_MIU1_256 BIT(6) 399 #define EVD_REG_RESET_USE_HVD_MIU_EN BIT(7) 400 #define EVD_REG_RESET_HK_HEVC_MODE BIT(8) 401 #define EVD_REG_RESET_HK_TSP2EVD_EN BIT(9) 402 #define EVD_REG_RESET_MIU0_256 BIT(10) 403 #define EVD_REG_RESET_MIU0_128 BIT(11) 404 #define EVD_REG_RESET_CPUIF_SEL BIT(12) 405 #define EVD_REG_RESET_ALL_SRAM_SD_EN BIT(13) 406 #define EVD_REG_RESET_BOND_UHD BIT(14) 407 #define EVD_REG_RESET_BOND_HD BIT(15) 408 // If BBU has its own port, need to set bbu 128/256; otherwise, keep default value reg_bbu_miu_256 = 1 409 #define EVD_REG_BBU_MIU_WIDTH (REG_EVD_BASE + ((0x0040) << 1)) // Miami, Clippers use 128 bits BBU 410 #define EVD_REG_BBU_MIU_128 BITS(1:0,1) 411 #define EVD_REG_BBU_MIU_256 BITS(1:0,2) 412 413 //------------------------------------------------------------------------------ 414 // G2 VP9 Reg 415 //------------------------------------------------------------------------------ 416 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1)) 417 #define VP9_REG_RESET_SWRST BIT(0) 418 #define VP9_REG_RESET_SWRST_FIN BIT(2) 419 #define VP9_REG_RESET_MIU_RDY BIT(4) 420 #define VP9_REG_RESET_ALL_SRAM_SD_EN BIT(13) 421 #define VP9_REG_RESET_APB_SEL BIT(15) 422 423 #define EVD_REG_VP9_MODE (REG_EVD_BASE + ((0x001b) << 1)) 424 #define EVD_REG_SET_VP9_MODE BIT(0) 425 426 427 //------------------------------------------------------------------------------ 428 // ChipTop Reg 429 //------------------------------------------------------------------------------ 430 431 #define CHIPTOP_REG_BASE (0x1E00 ) 432 #define CLKGEN0_REG_BASE (0x0B00 ) 433 434 #define REG_TOP_PSRAM0_1_MIUMUX (CHIPTOP_REG_BASE+(0x002D<<1)) //TODO 435 #define TOP_CKG_PSRAM0_MASK BMASK(1:0) 436 #define TOP_CKG_PSRAM0_DIS BIT(0) 437 #define TOP_CKG_PSRAM0_INV BIT(1) 438 #define TOP_CKG_PSRAM1_MASK BMASK(3:2) 439 #define TOP_CKG_PSRAM1_DIS BIT(0) 440 #define TOP_CKG_PSRAM1_INV BIT(1) 441 #define TOP_MIU_MUX_G07_MASK BMASK(7:6) 442 #define TOP_MIU_MUX_G07_OD_LSB_R BITS(7:6,0) 443 #define TOP_MIU_MUX_G07_GOP2_R BITS(7:6,1) 444 #define TOP_MIU_MUX_G08_MASK BMASK(9:8) 445 #define TOP_MIU_MUX_G08_OD_LSB_W BITS(9:8,0) 446 #define TOP_MIU_MUX_G08_VE_W BITS(9:8,1) 447 #define TOP_MIU_MUX_G15_MASK BMASK(11:10) 448 #define TOP_MIU_MUX_G15_GOP2_R BITS(11:10,0) 449 #define TOP_MIU_MUX_G15_OD_LSB_R BITS(11:10,1) 450 #define TOP_MIU_MUX_G1A_MASK BMASK(13:12) 451 #define TOP_MIU_MUX_G1A_VE_W BITS(13:12,0) 452 #define TOP_MIU_MUX_G1A_OD_LSB_W BITS(13:12,1) 453 #define TOP_MIU_MUX_G26_MASK BMASK(15:14) 454 #define TOP_MIU_MUX_G26_RVD_RW BITS(15:14,0) 455 #define TOP_MIU_MUX_G26_SVD_INTP_R BITS(15:14,1) 456 #define TOP_MIU_MUX_G26_MVD_R BITS(15:14,2) 457 458 #define REG_TOP_VPU (CLKGEN0_REG_BASE+(0x0030<<1)) 459 #define TOP_CKG_VPU_MASK BMASK(4:0) 460 #define TOP_CKG_VPU_DIS BIT(0) 461 #define TOP_CKG_VPU_INV BIT(1) 462 #define TOP_CKG_VPU_CLK_MASK BMASK(4:2) 463 #define TOP_CKG_VPU_240MHZ BITS(4:2, 0) 464 #define TOP_CKG_VPU_216MHZ BITS(4:2, 1) 465 #define TOP_CKG_VPU_192MHZ BITS(4:2, 2) 466 #define TOP_CKG_VPU_12MHZ BITS(4:2, 3) 467 #define TOP_CKG_VPU_320MHZ BITS(4:2, 4) 468 #define TOP_CKG_VPU_288MHZ BITS(4:2, 5) 469 #define TOP_CKG_VPU_432MHZ BITS(4:2, 6) 470 #define TOP_CKG_VPU_384MHZ BITS(4:2, 7) 471 472 #define REG_TOP_HVD_IDB (CLKGEN0_REG_BASE+(0x0030<<1)) 473 #define TOP_CKG_HVD_IDB_CLK_MASK BMASK(10:8) 474 #define TOP_CKG_HVD_IDB_432MHZ BITS(10:8, 0) // default use this 475 #define TOP_CKG_HVD_IDB_384MHZ BITS(10:8, 1) 476 #define TOP_CKG_HVD_IDB_345MHZ BITS(10:8, 2) 477 #define TOP_CKG_HVD_IDB_480MHZ BITS(10:8, 3) // for overclocking 478 #define TOP_CKG_HVD_IDB_320MHZ BITS(10:8, 4) 479 #define TOP_CKG_HVD_IDB_288MHZ BITS(10:8, 5) 480 #define TOP_CKG_HVD_IDB_240MHZ BITS(10:8, 6) 481 #define TOP_CKG_HVD_IDB_216MHZ BITS(10:8, 7) 482 483 #define REG_TOP_HVD (CLKGEN0_REG_BASE+(0x0031<<1)) 484 #define TOP_CKG_HVD_MASK BMASK(4:0) 485 #define TOP_CKG_HVD_DIS BIT(0) 486 #define TOP_CKG_HVD_INV BIT(1) 487 #define TOP_CKG_HVD_CLK_MASK BMASK(4:2) 488 #define TOP_CKG_HVD_384MHZ BITS(4:2, 0) // default use this 489 #define TOP_CKG_HVD_345MHZ BITS(4:2, 1) 490 #define TOP_CKG_HVD_320MHZ BITS(4:2, 2) 491 #define TOP_CKG_HVD_288MHZ BITS(4:2, 3) 492 #define TOP_CKG_HVD_240MHZ BITS(4:2, 4) 493 #define TOP_CKG_HVD_216MHZ BITS(4:2, 5) 494 #define TOP_CKG_HVD_172MHZ BITS(4:2, 6) 495 #define TOP_CKG_HVD_432MHZ BITS(4:2, 7) // for overclocking 496 497 #define REG_TOP_VP8 (CLKGEN0_REG_BASE+(0x0031<<1)) 498 #define TOP_CKG_VP8_MASK BMASK(11:8) 499 #define TOP_CKG_VP8_DIS BIT(8) 500 #define TOP_CKG_VP8_INV BIT(9) 501 #define TOP_CKG_VP8_CLK_MASK BMASK(11:10) 502 #define TOP_CKG_VP8_288MHZ BITS(11:10, 0) // default use this 503 #define TOP_CKG_VP8_240MHZ BITS(11:10, 1) 504 #define TOP_CKG_VP8_216MHZ BITS(11:10, 2) 505 #define TOP_CKG_VP8_320MHZ BITS(11:10, 3) // for overclocking 506 507 #define REG_TOP_HVD_AEC (CLKGEN0_REG_BASE+(0x0034<<1)) 508 #define TOP_CKG_HVD_AEC_MASK BMASK(4:0) 509 #define TOP_CKG_HVD_AEC_DIS BIT(0) 510 #define TOP_CKG_HVD_AEC_INV BIT(1) 511 #define TOP_CKG_HVD_AEC_CLK_MASK BMASK(3:2) 512 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this 513 #define TOP_CKG_HVD_AEC_240MHZ BITS(3:2, 1) 514 #define TOP_CKG_HVD_AEC_216MHZ BITS(3:2, 2) 515 #define TOP_CKG_HVD_AEC_320MHZ BITS(3:2, 3) 516 #define TOP_CKG_HVD_AEC_CLK_FROM_HVD_AEC_P BIT(4) //no need to set; hw switch automatically 517 518 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) 519 #define TOP_CKG_VP9_MASK BMASK(8:4) 520 #define TOP_CKG_VP9_DIS BIT(4) 521 #define TOP_CKG_VP9_INV BIT(5) 522 #define TOP_CKG_VP9_CLK_MASK BMASK(8:6) 523 #define TOP_CKG_VP9_432MHZ BITS(8:6,0) 524 #define TOP_CKG_VP9_384MHZ BITS(8:6,1) 525 #define TOP_CKG_VP9_345MHZ BITS(8:6,2) 526 #define TOP_CKG_VP9_320MHZ BITS(8:6,3) 527 #define TOP_CKG_VP9_288MHZ BITS(8:6,4) 528 #define TOP_CKG_VP9_240MHZ BITS(8:6,5) 529 #define TOP_CKG_VP9_216MHZ BITS(8:6,6) 530 #define TOP_CKG_VP9_172MHZ BITS(8:6,7) 531 532 #define REG_TOP_MVD (CLKGEN0_REG_BASE+(0x0039<<1)) 533 #define TOP_CKG_MVD_MASK BMASK(4:0) 534 #define TOP_CKG_MHVD_DIS BIT(0) 535 #define TOP_CKG_MVD_INV BIT(1) 536 #define TOP_CKG_MVD_CLK_MASK BMASK(4:2) 537 #define TOP_CKG_MVD_160MHZ BITS(4:2, 0) 538 #define TOP_CKG_MVD_144MHZ BITS(4:2, 1) 539 #define TOP_CKG_MVD_RESV BITS(4:2, 2) 540 #define TOP_CKG_MVD_108MHZ BITS(4:2, 3) 541 542 #define REG_TOP_MVD2 (CLKGEN0_REG_BASE+(0x0039<<1)) 543 #define TOP_CKG_MVD2_MASK BMASK(11:8) 544 #define TOP_CKG_MHVD2_DIS BIT(8) 545 #define TOP_CKG_MVD2_INV BIT(9) 546 #define TOP_CKG_MVD2_CLK_MASK BMASK(11:10) 547 #define TOP_CKG_MVD2_170MHZ BITS(11:10, 0) 548 #define TOP_CKG_MVD2_144MHZ BITS(11:10, 1) 549 #define TOP_CKG_MVD2_160MHZ BITS(11:10, 1) 550 #define TOP_CKG_MVD2_CLK_MIU_P BITS(11:10, 1) 551 552 #define REG_TOP_CKG_EVD_PPU (CLKGEN0_REG_BASE+(0x0033<<1)) 553 #define TOP_CKG_EVD_PPU_MASK BMASK(13:10) 554 #define TOP_CKG_EVD_PPU_DIS BIT(8) 555 #define TOP_CKG_EVD_PPU_INV BIT(9) 556 #define TOP_CKG_EVD_PPU_PLL_BUF BITS(13:10, 0) //576 557 #define TOP_CKG_EVD_PPU_MIU128PLL BITS(13:10, 1) 558 #define TOP_CKG_EVD_PPU_MIU256PLL BITS(13:10, 2) 559 #define TOP_CKG_EVD_PPU_480MHZ BITS(13:10, 3) 560 #define TOP_CKG_EVD_PPU_384MHZ BITS(13:10, 4) 561 #define TOP_CKG_EVD_PPU_320MHZ BITS(13:10, 5) 562 #define TOP_CKG_EVD_PPU_240MHZ BITS(13:10, 6) 563 #define TOP_CKG_EVD_PPU_192MHZ BITS(13:10, 7) 564 565 #define REG_TOP_CKG_EVD (CLKGEN0_REG_BASE+(0x0034<<1)) 566 #define TOP_CKG_EVD_MASK BMASK(13:10) 567 #define TOP_CKG_EVD_DIS BIT(8) 568 #define TOP_CKG_EVD_INV BIT(9) 569 #define TOP_CKG_EVD_PLL_BUF BITS(13:10, 0) 570 #define TOP_CKG_EVD_MIU128PLL BITS(13:10, 1) 571 #define TOP_CKG_EVD_MIU256PLL BITS(13:10, 2) 572 #define TOP_CKG_EVD_480MHZ BITS(13:10, 3) 573 #define TOP_CKG_EVD_384MHZ BITS(13:10, 4) 574 #define TOP_CKG_EVD_320MHZ BITS(13:10, 5) 575 #define TOP_CKG_EVD_240MHZ BITS(13:10, 6) 576 #define TOP_CKG_EVD_192MHZ BITS(13:10, 7) 577 578 #define REG_TOP_UART_SEL0 (CHIPTOP_REG_BASE+(0x0053<<1)) 579 #define REG_TOP_UART_SEL_0_MASK BMASK(3:0) 580 #define REG_TOP_UART_SEL_MHEG5 BITS(3:0, 1) 581 #define REG_TOP_UART_SEL_VD_MHEG5 BITS(3:0, 2) 582 #define REG_TOP_UART_SEL_TSP BITS(3:0, 3) 583 #define REG_TOP_UART_SEL_PIU_0 BITS(3:0, 4) 584 #define REG_TOP_UART_SEL_PIU_1 BITS(3:0, 5) 585 #define REG_TOP_UART_SEL_PIU_FAST BITS(3:0, 7) 586 #define REG_TOP_UART_SEL_VD_MCU_51_TXD0 BITS(3:0, 10) 587 #define REG_TOP_UART_SEL_VD_MCU_51_TXD1 BITS(3:0, 11) 588 589 //------------------------------------------------------------------------------ 590 // MIU Reg 591 //------------------------------------------------------------------------------ 592 #define MIU0_REG_HVD_BASE (0x1200) 593 #define MIU0_REG_HVD_BASE2 (0x61500) 594 595 #define MIU1_REG_HVD_BASE (0x0600) 596 #define MIU1_REG_HVD_BASE2 (0x62200) 597 598 #define MIU2_REG_HVD_BASE (0x62000) 599 #define MIU2_REG_HVD_BASE2 (0x62300) 600 601 602 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1)) 603 #define MIU0_CLIENT_SELECT_GP4_HVD_MIF0 BIT(2) 604 #define MIU0_CLIENT_SELECT_GP4_HVD_MIF1 BIT(3) 605 #define MIU0_CLIENT_SELECT_GP4_HVD_MALI BIT(4) 606 607 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1)) 608 #define MIU2_CLIENT_SELECT_GP4_HVD_MIF0 BIT(2) 609 #define MIU2_CLIENT_SELECT_GP4_HVD_MIF1 BIT(3) 610 #define MIU2_CLIENT_SELECT_GP4_HVD_MALI BIT(4) 611 612 613 //#define MIU2_REG_HVD_BASE (0x62000) 614 //#define MIU2_REG_HVD_BASE2 (0x62300) 615 616 617 618 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1)) 619 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1)) 620 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1)) 621 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1)) 622 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) 623 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1)) 624 625 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) 626 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1)) 627 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1)) 628 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1)) 629 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1)) 630 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1)) 631 632 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) 633 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1)) 634 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) 635 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1)) 636 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) 637 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1)) 638 639 640 641 642 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1)) 643 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1)) 644 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1)) 645 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) 646 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) 647 #define MIU0_REG_SEL5 (MIU0_REG_HVD_BASE+(( 0x007D)<<1)) 648 649 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1)) 650 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1)) 651 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1)) 652 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1)) 653 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1)) 654 #define MIU2_REG_SEL5 (MIU2_REG_HVD_BASE+(( 0x007D)<<1)) 655 656 657 //#define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1)) 658 659 660 #define MIU_HVD_RW (BIT(10)|BIT(11)) 661 #define MIU_MVD_RW (BIT(5)|BIT(6)) 662 663 //------------------------------------------------------------------------------------------------- 664 // Type and Structure 665 //------------------------------------------------------------------------------------------------- 666 667 668 #endif // _REG_HVD_H_ 669 670