1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
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20 //
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75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
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91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99 // Common Definition
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #include <asm/io.h>
103 #include "chip_setup.h"
104 #include "include/mstar/mstar_chip.h"
105 #else
106 #include <string.h>
107 #endif
108
109 #include "drvHVD_Common.h"
110
111 // Internal Definition
112 #include "drvHVD_def.h"
113 #include "fwHVD_if.h"
114 #include "halVPU_EX.h"
115 #include "halHVD_EX.h"
116 #include "regHVD_EX.h"
117
118 //-------------------------------------------------------------------------------------------------
119 // Driver Compiler Options
120 //-------------------------------------------------------------------------------------------------
121 #if (!defined(MSOS_TYPE_NUTTX) && !defined(MSOS_TYPE_OPTEE)) || defined(SUPPORT_X_MODEL_FEATURE)
122
123 //-------------------------------------------------------------------------------------------------
124 // Local Defines
125 //-------------------------------------------------------------------------------------------------
126 #define RV_VLC_TABLE_SIZE 0x20000
127 /* Add for Mobile Platform by Ted Sun */
128 //#define HVD_DISPQ_PREFETCH_COUNT 2
129 #define HVD_FW_MEM_OFFSET 0x100000UL // 1M
130 #define VPU_QMEM_BASE 0x20000000UL
131
132 //max support pixel(by chip capacity)
133 #define HVD_HW_MAX_PIXEL (3840*2160*31000ULL) // 4kx2k@30p
134 #define HEVC_HW_MAX_PIXEL (4096*2160*61000ULL) // 4kx2k@60p
135 #define VP9_HW_MAX_PIXEL (4096*2304*31000ULL) // 4kx2k@30p
136
137 #if 0
138 static HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
139 static MS_U8 g_hvd_nal_fill_pair[2][8] = { {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0, 0, 0} };
140 static MS_U32 u32RV_VLCTableAddr = 0; // offset from Frame buffer start address
141 static MS_U16 _u16DispQPtr = 0;
142 #endif
143
144 #define IS_TASK_ALIVE(id) ((id) != -1)
145 #ifndef UNUSED
146 #define UNUSED(x) (void)(x)
147 #endif
148
149
150 //---------------------------------- Mutex settings -----------------------------------------
151 #if HAL_HVD_ENABLE_MUTEX_PROTECT
152 #define _HAL_HVD_MutexCreate() \
153 do \
154 { \
155 if (s32HVDMutexID < 0) \
156 { \
157 s32HVDMutexID = OSAL_HVD_MutexCreate((MS_U8*)(_u8HVD_Mutex)); \
158 } \
159 } while (0)
160
161 #define _HAL_HVD_MutexDelete() \
162 do \
163 { \
164 if (s32HVDMutexID >= 0) \
165 { \
166 OSAL_HVD_MutexDelete(s32HVDMutexID); \
167 s32HVDMutexID = -1; \
168 } \
169 } while (0)
170
171 #define _HAL_HVD_Entry() \
172 do \
173 { \
174 if (s32HVDMutexID >= 0) \
175 { \
176 if (!OSAL_HVD_MutexObtain(s32HVDMutexID, OSAL_HVD_MUTEX_TIMEOUT)) \
177 { \
178 printf("[HAL HVD][%06d] Mutex taking timeout\n", __LINE__); \
179 } \
180 } \
181 } while (0)
182
183 #define _HAL_HVD_Return(_ret_) \
184 do \
185 { \
186 if (s32HVDMutexID >= 0) \
187 { \
188 OSAL_HVD_MutexRelease(s32HVDMutexID); \
189 } \
190 return _ret_; \
191 } while(0)
192
193 #define _HAL_HVD_Release() \
194 do \
195 { \
196 if (s32HVDMutexID >= 0) \
197 { \
198 OSAL_HVD_MutexRelease(s32HVDMutexID); \
199 } \
200 } while (0)
201 #else // HAL_HVD_ENABLE_MUTEX_PROTECT
202
203 #define _HAL_HVD_MutexCreate()
204 #define _HAL_HVD_MutexDelete()
205 #define _HAL_HVD_Entry()
206 #define _HAL_HVD_Return(_ret) {return _ret;}
207 #define _HAL_HVD_Release()
208
209 #endif // HAL_HVD_ENABLE_MUTEX_PROTECT
210
211 #define INC_VALUE(value, queue_sz) { (value) = ((++(value)) >= queue_sz) ? 0 : (value); }
212 #define IS_TASK_ALIVE(id) ((id) != -1)
213 #define NEXT_MULTIPLE(value, n) (((value) + (n) - 1) & ~((n)-1))
214
215 //------------------------------ MIU SETTINGS ----------------------------------
216 #define _MaskMiuReq_MVD_RW_0( m ) _HVD_WriteRegBit(MIU0_REG_RQ2_MASK, m, BIT(4))
217 #define _MaskMiuReq_MVD_RW_1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(6))
218 #define _MaskMiuReq_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ0_MASK+1, m, BIT(4))
219 #define _MaskMiuReq_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(2))
220 #define _MaskMiuReq_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(3))
221 #define _MaskMiuReq_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(0))
222
223 #define _MaskMiu1Req_MVD_RW_0( m ) _HVD_WriteRegBit(MIU1_REG_RQ2_MASK, m, BIT(4))
224 #define _MaskMiu1Req_MVD_RW_1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(6))
225 #define _MaskMiu1Req_MVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ0_MASK+1, m, BIT(4))
226 #define _MaskMiu1Req_HVD_RW_MIF0( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(2))
227 #define _MaskMiu1Req_HVD_RW_MIF1( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(3))
228 #define _MaskMiu1Req_HVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(0))
229
230
231 #define HVD_MVD_RW_0_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == 0)
232 #define HVD_MVD_RW_1_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == 0)
233 #define HVD_MVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == 0)
234 #define HVD_HVD_RW_MIF0_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == 0)
235 #define HVD_HVD_RW_MIF1_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == 0)
236 #define HVD_HVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == 0)
237
238 #define HVD_MVD_RW_0_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL2) & BIT(4)) == BIT(4))
239 #define HVD_MVD_RW_1_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(6)) == BIT(6))
240 #define HVD_MVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL0) & BIT(12)) == BIT(12))
241 #define HVD_HVD_RW_MIF0_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(2)) == BIT(2))
242 #define HVD_HVD_RW_MIF1_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(3)) == BIT(3))
243 #define HVD_HVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(0)) == BIT(0))
244
245 #if SUPPORT_EVD
246 #define _MaskMiuReq_EVD_RW( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
247 #define _MaskMiuReq_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU0_REG_RQ4_MASK, m, BIT(4))
248 #define _MaskMiu1Req_EVD_RW( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(4))
249 #define _MaskMiu1Req_EVD_BBU_R( m ) _HVD_WriteRegBit(MIU1_REG_RQ4_MASK, m, BIT(4))
250
251 #define HVD_EVD_RW_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0)
252 #define HVD_EVD_BBU_R_ON_MIU0 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == 0)
253 #define HVD_EVD_RW_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4))
254 #define HVD_EVD_BBU_R_ON_MIU1 ((_HVD_Read2Byte(MIU0_REG_SEL4) & BIT(4)) == BIT(4))
255 #endif
256
257 #define _HVD_MIU_SetReqMask(miu_clients, mask) \
258 do \
259 { \
260 if (HVD_##miu_clients##_ON_MIU0 == 1) \
261 { \
262 _MaskMiuReq_##miu_clients(mask); \
263 } \
264 else \
265 { \
266 if (HVD_##miu_clients##_ON_MIU1 == 1) \
267 { \
268 _MaskMiu1Req_##miu_clients(mask); \
269 } \
270 } \
271 } while (0)
272
273 // check RM is supported or not
274 #define HVD_HW_RUBBER3 (HAL_HVD_EX_GetHWVersionID()& BIT(14))
275 #ifdef VDEC3
276 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 16
277 #else
278 #define HAL_HVD_EX_MAX_SUPPORT_STREAM 3
279 #endif
280
281 #define DIFF(a, b) (a > b ? (a-b) : (b-a)) // abs diff
282
283 //-------------------------------------------------------------------------------------------------
284 // Local Structures
285 //-------------------------------------------------------------------------------------------------
286
287 //-------------------------------------------------------------------------------------------------
288 // Local Functions Prototype
289 //-------------------------------------------------------------------------------------------------
290 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id);
291 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr);
292 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg);
293 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox);
294 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg);
295 //static void _HVD_EX_MBoxClear(MS_U8 u8MBox);
296 static MS_U32 _HVD_EX_GetPC(void);
297 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id);
298 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug);
299 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg);
300 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd);
301 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg);
302 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable);
303 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id);
304 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id);
305 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id);
306 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo);
307 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen);
308 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2);
309 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id);
310 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id);
311 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id);
312 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id);
313 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id);
314 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed, MS_BOOL *isAVCUsed);
315 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable);
316 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable);
317 #if SUPPORT_EVD
318 static void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable);
319 #endif
320 #if SUPPORT_G2VP9 && defined(VDEC3)
321 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable);
322 #endif
323 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id);
324 #if SUPPORT_G2VP9 && defined(VDEC3)
325 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id);
326 #endif
327
328 //-------------------------------------------------------------------------------------------------
329 // Global Variables
330 //-------------------------------------------------------------------------------------------------
331 #if defined (__aeon__)
332 static MS_VIRT u32HVDRegOSBase = 0xA0200000;
333 #else
334 static MS_VIRT u32HVDRegOSBase = 0xBF200000;
335 #endif
336 #if HAL_HVD_ENABLE_MUTEX_PROTECT
337 MS_S32 s32HVDMutexID = -1;
338 MS_U8 _u8HVD_Mutex[] = { "HVD_Mutex" };
339 #endif
340
341
342 #define HVD_EX_STACK_SIZE 4096
343 //-------------------------------------------------------------------------------------------------
344 // Local Variables
345 //-------------------------------------------------------------------------------------------------
346 typedef struct
347 {
348
349 HVD_AVC_VUI_DISP_INFO g_hvd_VUIINFO;
350 MS_U8 g_hvd_nal_fill_pair[2][8];
351 MS_VIRT u32RV_VLCTableAddr; // offset from Frame buffer start address
352 MS_U16 _u16DispQPtr;
353 MS_U16 _u16DispOutSideQPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
354
355 //HVD_EX_Drv_Ctrl *_pHVDCtrls;
356 MS_U32 u32HVDCmdTimeout;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
357 MS_U32 u32VPUClockType;
358 MS_U32 u32HVDClockType;//160
359 #if SUPPORT_EVD
360 MS_U32 u32EVDClockType;
361 #endif
362 #if SUPPORT_G2VP9 && defined(VDEC3)
363 MS_U32 u32VP9ClockType;
364 #endif
365 HVD_EX_Stream _stHVDStream[HAL_HVD_EX_MAX_SUPPORT_STREAM];
366
367 volatile HVD_Frm_Information *pHvdFrm;//_HVD_EX_GetNextDispFrame()
368 MS_BOOL g_RstFlag;
369 MS_U64 u64pts_real;
370 MS_PHY u32VP8BBUWptr;
371 MS_PHY u32EVDBBUWptr;
372 MS_BOOL bBBU_running[HAL_HVD_EX_MAX_SUPPORT_STREAM];
373 MS_U32 u32BBUReadEsPtr[HAL_HVD_EX_MAX_SUPPORT_STREAM];
374 MS_S32 _s32VDEC_BBU_TaskId[HAL_HVD_EX_MAX_SUPPORT_STREAM];
375 MS_U8 u8VdecExBBUStack[HAL_HVD_EX_MAX_SUPPORT_STREAM][HVD_EX_STACK_SIZE];
376 //pre_set
377 HVD_Pre_Ctrl *pHVDPreCtrl_Hal[HAL_HVD_EX_MAX_SUPPORT_STREAM];
378 } HVD_Hal_CTX;
379
380 HVD_Hal_CTX* pHVDHalContext = NULL;
381 HVD_Hal_CTX gHVDHalContext;
382 HVD_EX_Drv_Ctrl *_pHVDCtrls = NULL;
383
384 static HVD_EX_PreSet _stHVDPreSet[HAL_HVD_EX_MAX_SUPPORT_STREAM] =
385 {
386 {FALSE},
387 {FALSE},
388 {FALSE},
389 #ifdef VDEC3
390 {FALSE},
391 #endif
392 };
393
394 //-------------------------------------------------------------------------------------------------
395 // Debug Functions
396 //-------------------------------------------------------------------------------------------------
HVD_EX_SetRstFlag(MS_BOOL bRst)397 void HVD_EX_SetRstFlag(MS_BOOL bRst)
398 {
399 pHVDHalContext->g_RstFlag = bRst;
400 }
HVD_EX_GetRstFlag(void)401 MS_BOOL HVD_EX_GetRstFlag(void)
402 {
403 return pHVDHalContext->g_RstFlag;
404 }
405
406 //-------------------------------------------------------------------------------------------------
407 // Local Functions
408 //-------------------------------------------------------------------------------------------------
409 #ifdef VDEC3
_HAL_EX_IS_EVD(MS_U32 u32ModeFlag)410 static MS_BOOL _HAL_EX_IS_EVD(MS_U32 u32ModeFlag)
411 {
412 MS_U32 u32CodecType = u32ModeFlag & E_HVD_INIT_HW_MASK;
413
414 if (u32CodecType == E_HVD_INIT_HW_HEVC || u32CodecType == E_HVD_INIT_HW_HEVC_DV
415 #if SUPPORT_MSVP9
416 || u32CodecType == E_HVD_INIT_HW_VP9
417 #endif
418 )
419 return TRUE;
420
421 return FALSE;
422 }
423
_HAL_EX_BBU_VP8_InUsed(void)424 static MS_BOOL _HAL_EX_BBU_VP8_InUsed(void)
425 {
426 if (!pHVDHalContext)
427 return FALSE;
428
429 MS_U32 i;
430 MS_BOOL bRet = FALSE;
431
432 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
433 {
434 if (pHVDHalContext->_stHVDStream[i].bUsed && pHVDHalContext->_stHVDStream[i].u32CodecType == E_HAL_HVD_VP8)
435 {
436 bRet = TRUE;
437 break;
438 }
439 }
440
441 return bRet;
442 }
443
444 // This function will get decoder type not only MVD,HVD,EVD but more codec types.
445 // However, sometimes we don't use so deterministic infomation.
HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id,VPU_EX_TaskInfo * pstTaskInfo)446 static MS_BOOL HAL_HVD_EX_GetTaskInfo(MS_U32 u32Id, VPU_EX_TaskInfo* pstTaskInfo)
447 {
448
449 MS_U32 ret = TRUE;
450 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
451
452 if(pCtrl == NULL || pstTaskInfo == NULL)
453 return FALSE;
454
455 pstTaskInfo->u32Id = u32Id;
456
457 switch(pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
458 {
459 case E_HVD_INIT_HW_RM:
460 pstTaskInfo->eDecType = E_VPU_EX_DECODER_RVD;
461 break;
462 case E_HVD_INIT_HW_VP8:
463 pstTaskInfo->eDecType = E_VPU_EX_DECODER_VP8;
464 break;
465 case E_HVD_INIT_HW_MVC:
466 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
467 break;
468 case E_HVD_INIT_HW_HEVC:
469 case E_HVD_INIT_HW_HEVC_DV:
470 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
471 break;
472 #if SUPPORT_MSVP9
473 case E_HVD_INIT_HW_VP9:
474 pstTaskInfo->eDecType = E_VPU_EX_DECODER_EVD;
475 break;
476 #endif
477 #if SUPPORT_G2VP9
478 case E_HVD_INIT_HW_VP9:
479 pstTaskInfo->eDecType = E_VPU_EX_DECODER_G2VP9;
480 break;
481 #endif
482 default:
483 pstTaskInfo->eDecType = E_VPU_EX_DECODER_HVD;
484 break;
485 }
486
487 pstTaskInfo->eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
488
489 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
490 {
491 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_FILE;
492 }
493 else
494 {
495 pstTaskInfo->eSrcType = E_VPU_EX_INPUT_TSP;
496 }
497
498 pstTaskInfo->u32HeapSize = HVD_DRAM_SIZE;
499
500 #ifdef SUPPORT_EVD
501 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
502 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
503 pstTaskInfo->u32HeapSize = EVD_DRAM_SIZE;
504 #endif
505 return ret;
506
507 }
508
HAL_HVD_EX_GetBBUId(MS_U32 u32Id)509 MS_U32 HAL_HVD_EX_GetBBUId(MS_U32 u32Id)
510 {
511 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
512 MS_U32 ret = HAL_HVD_INVALID_BBU_ID;
513 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
514 _HAL_HVD_Entry();
515
516 if(pCtrl == NULL)
517 _HAL_HVD_Return(ret);
518
519 VPU_EX_TaskInfo taskInfo;
520 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
521
522 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
523
524 taskInfo.u8HalId = u8Idx;
525 ret = HAL_VPU_EX_GetBBUId(u32Id, &taskInfo, pCtrl->bShareBBU);
526
527 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
528 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
529
530 _HAL_HVD_Return(ret);
531 }
532
HAL_HVD_EX_FreeBBUId(MS_U32 u32Id,MS_U32 u32BBUId)533 MS_BOOL HAL_HVD_EX_FreeBBUId(MS_U32 u32Id, MS_U32 u32BBUId)
534 {
535 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
536 MS_BOOL ret = FALSE;
537 _HAL_HVD_Entry();
538
539 if(pCtrl == NULL)
540 _HAL_HVD_Return(ret);
541 VPU_EX_TaskInfo taskInfo;
542 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
543
544 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
545
546 ret = HAL_VPU_EX_FreeBBUId(u32Id,u32BBUId,&taskInfo);
547
548 HVD_EX_MSG_DBG("u32Id=0x%x eDecType=0x%x eSrcType=0x%x ret=0x%x\n", (unsigned int)taskInfo.u32Id,
549 (unsigned int)taskInfo.eDecType, (unsigned int)taskInfo.eSrcType, (unsigned int)ret);
550
551 _HAL_HVD_Return(ret);
552 }
553
HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id,MS_U32 u32BBUId)554 MS_BOOL HAL_HVD_EX_ClearBBUSetting(MS_U32 u32Id, MS_U32 u32BBUId)
555 {
556 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
557 MS_BOOL ret = FALSE;
558 _HAL_HVD_Entry();
559
560 if(pCtrl == NULL)
561 _HAL_HVD_Return(ret);
562 VPU_EX_TaskInfo taskInfo;
563 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
564
565 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);
566
567 HAL_VPU_EX_ClearBBUSetting(u32Id, u32BBUId, taskInfo.eDecType);
568
569 _HAL_HVD_Return(TRUE);
570 }
571 #endif
572
_HVD_EX_PpTask_Delete(HVD_EX_Stream * pstHVDStream)573 static void _HVD_EX_PpTask_Delete(HVD_EX_Stream *pstHVDStream)
574 {
575 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_STOP;
576 MsOS_DeleteTask(pstHVDStream->s32HvdPpTaskId);
577 pstHVDStream->s32HvdPpTaskId = -1;
578 }
579
_HVD_EX_Context_Init_HAL(void)580 static void _HVD_EX_Context_Init_HAL(void)
581 {
582 pHVDHalContext->u32HVDCmdTimeout = 100;//same as HVD_FW_CMD_TIMEOUT_DEFAULT
583 pHVDHalContext->u32VPUClockType = 432;
584 pHVDHalContext->u32HVDClockType = 384;
585 #if SUPPORT_EVD
586 pHVDHalContext->u32EVDClockType = 576;
587 #endif
588 #if SUPPORT_G2VP9 && defined(VDEC3)
589 pHVDHalContext->u32VP9ClockType = 384;
590 #endif
591 #ifdef VDEC3
592 MS_U8 i;
593
594 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
595 {
596 pHVDHalContext->_stHVDStream[i].eStreamId = E_HAL_HVD_N_STREAM0 + i;
597 pHVDHalContext->_stHVDStream[i].ePpTaskState = E_HAL_HVD_STATE_STOP;
598 pHVDHalContext->_stHVDStream[i].s32HvdPpTaskId = -1;
599 }
600 #else
601 pHVDHalContext->_stHVDStream[0].eStreamId = E_HAL_HVD_MAIN_STREAM0;
602 pHVDHalContext->_stHVDStream[1].eStreamId = E_HAL_HVD_SUB_STREAM0;
603 pHVDHalContext->_stHVDStream[2].eStreamId = E_HAL_HVD_SUB_STREAM1;
604 #endif
605 }
606
_HVD_EX_GetBBUReadptr(MS_U32 u32Id)607 static MS_U16 _HVD_EX_GetBBUReadptr(MS_U32 u32Id)
608 {
609 MS_U16 u16Ret = 0;
610 #if (HVD_ENABLE_MVC || (!VDEC3))
611 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
612 #endif
613 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
614 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
615 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
616 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
617
618 #if HVD_ENABLE_MVC
619 if(HAL_HVD_EX_CheckMVCID(u32Id))
620 {
621 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
622 }
623 #endif /// HVD_ENABLE_MVC
624
625 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
626 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
627
628 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
629 {
630 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS4);
631 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS3);
632 }
633 else
634 #ifdef VDEC3
635 if (0 == pCtrl->u32BBUId)
636 #else
637 if (0 == u8TaskId)
638 #endif
639 {
640 //if(pCtrl->InitParams.bColocateBBUMode)
641 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
642 u16Ret = pShm->u32ColocateBBUReadPtr;
643 else
644 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB));
645 }
646 else
647 {
648 //if(pCtrl->InitParams.bColocateBBUMode)
649 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
650 u16Ret = pShm->u32ColocateBBUReadPtr;
651 else
652 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB));
653 }
654
655 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
656 _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_RPTR_HI_BS2(u32RB)));
657
658 return u16Ret;
659 }
660
_HVD_EX_GetBBUWritedptr(MS_U32 u32Id)661 static MS_U16 _HVD_EX_GetBBUWritedptr(MS_U32 u32Id)
662 {
663 MS_U16 u16Ret = 0;
664 #if (HVD_ENABLE_MVC || (!VDEC3))
665 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
666 #endif
667 HVD_EX_Drv_Ctrl *pDrvCtrl = _HVD_EX_GetDrvCtrl(u32Id);
668 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
669 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
670 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
671
672 #if HVD_ENABLE_MVC
673 if (HAL_HVD_EX_CheckMVCID(u32Id))
674 {
675 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
676 }
677 #endif /// HVD_ENABLE_MVC
678 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), 0, HVD_REG_POLL_NAL_RPTR_BIT);
679 _HVD_WriteWordMask(HVD_REG_POLL_NAL_RPTR(u32RB), HVD_REG_POLL_NAL_RPTR_BIT, HVD_REG_POLL_NAL_RPTR_BIT);
680
681 if ((pDrvCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8) // VP8
682 {
683 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS4);
684 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS3);
685 }
686 else
687 #ifdef VDEC3
688 if (0 == pDrvCtrl->u32BBUId)
689 #else
690 if (0 == u8TaskId)
691 #endif
692 {
693 //if(pDrvCtrl->InitParams.bColocateBBUMode)
694 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
695 u16Ret = pShm->u32ColocateBBUWritePtr;
696 else
697 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB));
698 }
699 else
700 {
701 //if(pDrvCtrl->InitParams.bColocateBBUMode)
702 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
703 u16Ret = pShm->u32ColocateBBUWritePtr;
704 else
705 u16Ret = _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB));
706 }
707
708 return u16Ret;
709 }
710
_HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)711 static void _HVD_EX_ResetMainSubBBUWptr(MS_U32 u32Id)
712 {
713 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
714 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
715
716 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), 0);
717 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
718 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), 0);
719 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
720 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, 0);
721 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
722 _HVD_Write2Byte(HVD_REG_NAL_RPTR_HI_BS4, 0);
723 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
724 }
725
_HVD_EX_SetBBUWriteptr(MS_U32 u32Id,MS_U16 u16BBUNewWptr)726 static void _HVD_EX_SetBBUWriteptr(MS_U32 u32Id, MS_U16 u16BBUNewWptr)
727 {
728 #if (HVD_ENABLE_MVC || (!VDEC3))
729 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
730 #endif
731 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
732 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
733 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
734 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
735
736 #if HVD_ENABLE_MVC
737 if (HAL_HVD_EX_CheckMVCID(u32Id))
738 {
739 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
740 }
741 #endif /// HVD_ENABLE_MVC
742
743 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
744 {
745 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS3, u16BBUNewWptr);
746 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS4, u16BBUNewWptr);
747 }
748 else
749 #ifdef VDEC3
750 if (0 == pCtrl->u32BBUId)
751 #else
752 if (0 == u8TaskId)
753 #endif
754 {
755 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI(u32RB), u16BBUNewWptr);
756 //if(pCtrl->InitParams.bColocateBBUMode)
757 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
758 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
759 }
760 else
761 {
762 _HVD_Write2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB), u16BBUNewWptr);
763 //if(pCtrl->InitParams.bColocateBBUMode)
764 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
765 pShm->u32ColocateBBUWritePtr = u16BBUNewWptr;
766 }
767
768 HVD_EX_MSG_DBG("Task0=%d, Task1=%d\n",
769 _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI(u32RB)), _HVD_Read2Byte(HVD_REG_NAL_WPTR_HI_BS2(u32RB)));
770
771 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_NAL_WPTR_SYNC, HVD_REG_NAL_WPTR_SYNC); // set bit 3
772 }
773
_HVD_EX_MBoxSend(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 u32Msg)774 static MS_BOOL _HVD_EX_MBoxSend(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 u32Msg)
775 {
776 MS_BOOL bResult = TRUE;
777 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
778 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
779
780 switch (u8MBox)
781 {
782 case E_HVD_HI_0:
783 {
784 _HVD_Write4Byte(HVD_REG_HI_MBOX0_L(u32RB), u32Msg);
785 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX0_SET, HVD_REG_HI_MBOX0_SET);
786 break;
787 }
788 case E_HVD_HI_1:
789 {
790 _HVD_Write4Byte(HVD_REG_HI_MBOX1_L(u32RB), u32Msg);
791 _HVD_WriteWordMask(HVD_REG_HI_MBOX_SET(u32RB), HVD_REG_HI_MBOX1_SET, HVD_REG_HI_MBOX1_SET);
792 break;
793 }
794 case E_HVD_VPU_HI_0:
795 {
796 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX0, u32Msg);
797 break;
798 }
799 case E_HVD_VPU_HI_1:
800 {
801 bResult = HAL_VPU_EX_MBoxSend(VPU_HI_MBOX1, u32Msg);
802 break;
803 }
804 default:
805 {
806 bResult = FALSE;
807 break;
808 }
809 }
810
811 return bResult;
812 }
813
_HVD_EX_MBoxReady(MS_U32 u32Id,MS_U8 u8MBox)814 static MS_BOOL _HVD_EX_MBoxReady(MS_U32 u32Id, MS_U8 u8MBox)
815 {
816 MS_BOOL bResult = TRUE;
817 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
818 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
819
820 switch (u8MBox)
821 {
822 case E_HVD_HI_0:
823 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX0_RDY) ? FALSE : TRUE;
824 break;
825 case E_HVD_HI_1:
826 bResult = _HVD_ReadWordBit(HVD_REG_HI_MBOX_RDY(u32RB), HVD_REG_HI_MBOX1_RDY) ? FALSE : TRUE;
827 break;
828 case E_HVD_RISC_0:
829 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX0_RDY) ? TRUE : FALSE;
830 break;
831 case E_HVD_RISC_1:
832 bResult = _HVD_ReadWordBit(HVD_REG_RISC_MBOX_RDY(u32RB), HVD_REG_RISC_MBOX1_RDY) ? TRUE : FALSE;
833 break;
834 case E_HVD_VPU_HI_0:
835 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX0);
836 break;
837 case E_HVD_VPU_HI_1:
838 bResult = HAL_VPU_EX_MBoxRdy(VPU_HI_MBOX1);
839 break;
840 case E_HVD_VPU_RISC_0:
841 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX0);
842 break;
843 case E_HVD_VPU_RISC_1:
844 bResult = HAL_VPU_EX_MBoxRdy(VPU_RISC_MBOX1);
845 break;
846 default:
847 break;
848 }
849
850 return bResult;
851 }
852
_HVD_EX_MBoxRead(MS_U32 u32Id,MS_U8 u8MBox,MS_U32 * u32Msg)853 static MS_BOOL _HVD_EX_MBoxRead(MS_U32 u32Id, MS_U8 u8MBox, MS_U32 *u32Msg)
854 {
855 MS_BOOL bResult = TRUE;
856 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
857 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
858
859 switch (u8MBox)
860 {
861 case E_HVD_HI_0:
862 {
863 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX0_L(u32RB));
864 break;
865 }
866 case E_HVD_HI_1:
867 {
868 *u32Msg = _HVD_Read4Byte(HVD_REG_HI_MBOX1_L(u32RB));
869 break;
870 }
871 case E_HVD_RISC_0:
872 {
873 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX0_L(u32RB));
874 break;
875 }
876 case E_HVD_RISC_1:
877 {
878 *u32Msg = _HVD_Read4Byte(HVD_REG_RISC_MBOX1_L(u32RB));
879 break;
880 }
881 case E_HVD_VPU_RISC_0:
882 {
883 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX0, u32Msg);
884 break;
885 }
886 case E_HVD_VPU_RISC_1:
887 {
888 bResult = HAL_VPU_EX_MBoxRead(VPU_RISC_MBOX1, u32Msg);
889 break;
890 }
891 default:
892 {
893 bResult = FALSE;
894 break;
895 }
896 }
897
898 return bResult;
899 }
900
901 #if 0
902 static void _HVD_EX_MBoxClear(MS_U8 u8MBox)
903 {
904 switch (u8MBox)
905 {
906 case E_HVD_RISC_0:
907 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX0_CLR, HVD_REG_RISC_MBOX0_CLR);
908 break;
909 case E_HVD_RISC_1:
910 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR, HVD_REG_RISC_MBOX1_CLR, HVD_REG_RISC_MBOX1_CLR);
911 break;
912 case E_HVD_VPU_RISC_0:
913 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX0);
914 break;
915 case E_HVD_VPU_RISC_1:
916 HAL_VPU_EX_MBoxClear(VPU_RISC_MBOX1);
917 break;
918 default:
919 break;
920 }
921 }
922 #endif
923
_HVD_EX_GetPC(void)924 static MS_U32 _HVD_EX_GetPC(void)
925 {
926 MS_U32 u32PC = 0;
927 u32PC = HAL_VPU_EX_GetProgCnt();
928 // HVD_MSG_DBG("<gdbg>pc0 =0x%lx\n",u32PC);
929 return u32PC;
930 }
931
_HVD_EX_GetESWritePtr(MS_U32 u32Id)932 static MS_U32 _HVD_EX_GetESWritePtr(MS_U32 u32Id)
933 {
934 MS_U32 u32Data = 0;
935 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
936 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
937
938 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
939 {
940 u32Data = pCtrl->LastNal.u32NalAddr + pCtrl->LastNal.u32NalSize;
941
942 if (u32Data > pCtrl->MemMap.u32BitstreamBufSize)
943 {
944 u32Data -= pCtrl->MemMap.u32BitstreamBufSize;
945
946 HVD_EX_MSG_ERR("app should not put this kind of packet\n");
947 }
948 }
949 else
950 {
951 #if HVD_ENABLE_MVC
952 MS_U8 u8ViewIdx = 0;
953 if(HAL_HVD_EX_CheckMVCID(u32Id))
954 {
955 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
956 }
957 if(u8ViewIdx != 0) /// 2nd ES ptr.
958 {
959 u32Data = pShm->u32ES2WritePtr;
960 }
961 else
962 {
963 u32Data = pShm->u32ESWritePtr;
964 }
965 #else
966 u32Data = pShm->u32ESWritePtr;
967 #endif
968 }
969
970 return u32Data;
971 }
972
973 #define NAL_UNIT_LEN_BITS 21
974 #define NAL_UNIT_OFT_BITS 30
975 #define NAL_UNIT_OFT_LOW_BITS (32-NAL_UNIT_LEN_BITS)
976 #define NAL_UNIT_OFT_HIGH_BITS (NAL_UNIT_OFT_BITS-NAL_UNIT_OFT_LOW_BITS)
977 #define NAL_UNIT_OFT_LOW_MASK (((unsigned int)0xFFFFFFFF)>>(32-NAL_UNIT_OFT_LOW_BITS))
978
_HVD_EX_GetESReadPtr(MS_U32 u32Id,MS_BOOL bDbug)979 static MS_U32 _HVD_EX_GetESReadPtr(MS_U32 u32Id, MS_BOOL bDbug)
980 {
981 MS_U32 u32Data = 0;
982 MS_U8 u8TaskId = 0;
983 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
984 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
985 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
986 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
987 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS3 = pShm->u32HVD_BBU_DRAM_ST_ADDR;
988
989 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
990 #if HVD_ENABLE_MVC
991 if(HAL_HVD_EX_CheckMVCID(u32Id))
992 {
993 u8TaskId = (MS_U8) HAL_HVD_EX_GetView(u32Id);
994 }
995 #endif /// HVD_ENABLE_MVC
996
997 if (((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV) || (TRUE == bDbug))
998 {
999 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP8)
1000 {
1001 // MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1002 MS_U16 u16ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
1003 MS_U16 u16WritePtr = _HVD_EX_GetBBUWritedptr(u32Id);
1004 MS_U32 *u32Adr;
1005 MS_U32 u32Tmp;
1006
1007 if (u16ReadPtr == u16WritePtr)
1008 {
1009 u32Data = _HVD_EX_GetESWritePtr(u32Id);
1010 }
1011 else
1012 {
1013 if (u16ReadPtr)
1014 u16ReadPtr--;
1015 else
1016 u16ReadPtr = VP8_BBU_DRAM_TBL_ENTRY - 1;
1017
1018 u32Adr = (MS_U32 *)(MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS3 + (u16ReadPtr << 3)));
1019
1020 u32Data = (*u32Adr) >> NAL_UNIT_LEN_BITS;
1021 u32Tmp = (*(u32Adr+1)) & (0xffffffff>>(32-(NAL_UNIT_OFT_BITS-(32-NAL_UNIT_LEN_BITS))));
1022 u32Tmp = u32Tmp << (32-NAL_UNIT_LEN_BITS);
1023 u32Data = u32Data | u32Tmp;
1024
1025 //printf("[VP8] GetESRptr (%x,%x,%x,%x,%d,%d)\n", u32Adr, (*u32Adr), (*(u32Adr+1)) , u32Data, u16ReadPtr, u16WritePtr);
1026 //while(1);
1027 }
1028 goto EXIT;
1029 }
1030 // set reg_poll_nal_rptr 0
1031 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), 0, HVD_REG_ESB_RPTR_POLL);
1032 // set reg_poll_nal_rptr 1
1033 _HVD_WriteWordMask(HVD_REG_ESB_RPTR(u32RB), HVD_REG_ESB_RPTR_POLL, HVD_REG_ESB_RPTR_POLL);
1034
1035 // read reg_nal_rptr_hi
1036 #ifdef VDEC3
1037 if (0 == pCtrl->u32BBUId)
1038 #else
1039 if (0 == u8TaskId)
1040 #endif
1041 {
1042 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR(u32RB)) & 0xFFC0;
1043 u32Data >>= 6;
1044 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H(u32RB)) << 10;
1045 }
1046 else
1047 {
1048 u32Data = _HVD_Read2Byte(HVD_REG_ESB_RPTR_L_BS2(u32RB)) & 0xFFC0;
1049 u32Data >>= 6;
1050 u32Data |= _HVD_Read2Byte(HVD_REG_ESB_RPTR_H_BS2(u32RB)) << 10;
1051 }
1052
1053 u32Data <<= 3; // unit
1054
1055 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1056 {
1057 MS_U32 u32ESWptr = _HVD_EX_GetESWritePtr(u32Id);
1058
1059 if ((pCtrl->u32LastESRptr < u32ESWptr) && (u32Data > u32ESWptr))
1060 {
1061 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1062 u32Data = u32ESWptr;
1063 }
1064 else if ((pCtrl->u32LastESRptr == u32ESWptr) && (u32Data > u32ESWptr))
1065 {
1066 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1067 u32Data = u32ESWptr;
1068 }
1069 else if ((_HVD_EX_GetBBUQNumb(u32Id) == 0) && ((u32Data - u32ESWptr) < 32)
1070 && ((pShm->u32FwState & E_HVD_FW_STATE_MASK) == E_HVD_FW_PLAY))
1071 {
1072 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1073 u32Data = u32ESWptr;
1074 }
1075 else if (((u32Data > u32ESWptr) && (pCtrl->u32LastESRptr > u32Data))
1076 && ((u32Data - u32ESWptr) < 32)
1077 && (pCtrl->u32FlushRstPtr == 1))
1078 {
1079 //HVD_MSG_INFO("444HVD Warn: ESRptr(%lx %lx) is running over ESWptr(%lx)\n" , u32Data , pCtrl->u32LastESRptr, u32ESWptr );
1080 u32Data = u32ESWptr;
1081 }
1082 }
1083
1084 // remove illegal pointer
1085 #if 1
1086 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
1087 {
1088 MS_U32 u32PacketStaddr = u32Data + pCtrl->MemMap.u32BitstreamBufAddr;
1089
1090 if (((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStaddr) &&
1091 (u32PacketStaddr <
1092 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
1093 {
1094 //HVD_MSG_INFO("HVD Warn: ESRptr(%lx %lx) is located in drv process buffer(%lx %lx)\n" , u32Data , pCtrl->u32LastESRptr, pCtrl->MemMap.u32DrvProcessBufAddr , pCtrl->MemMap.u32DrvProcessBufSize );
1095 u32Data = pCtrl->u32LastESRptr;
1096 }
1097 }
1098 #endif
1099 }
1100 else
1101 {
1102 #if HVD_ENABLE_MVC
1103 MS_U8 u8ViewIdx = 0;
1104 if(HAL_HVD_EX_CheckMVCID(u32Id))
1105 {
1106 u8ViewIdx = (MS_U8) HAL_HVD_EX_GetView(u32Id);
1107 }
1108 if(u8ViewIdx != 0) /// 2nd ES ptr.
1109 {
1110 u32Data = pShm->u32ES2ReadPtr;
1111 }
1112 else
1113 {
1114 u32Data = pShm->u32ESReadPtr;
1115 }
1116 #else
1117 u32Data = pShm->u32ESReadPtr;
1118 #endif
1119 }
1120
1121 EXIT:
1122
1123 pCtrl->u32LastESRptr = u32Data;
1124
1125 return u32Data;
1126 }
1127
_HVD_EX_SetCMDArg(MS_U32 u32Id,MS_U32 u32Arg)1128 static MS_BOOL _HVD_EX_SetCMDArg(MS_U32 u32Id, MS_U32 u32Arg)
1129 {
1130 MS_U16 u16TimeOut = 0xFFFF;
1131 MS_BOOL bResult = FALSE;
1132
1133 HVD_EX_MSG_DBG("Send ARG 0x%x to HVD\n", u32Arg);
1134
1135 while (--u16TimeOut)
1136 {
1137 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX) && _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX))
1138 {
1139 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, u32Arg);
1140 break;
1141 }
1142 }
1143
1144 return bResult;
1145 }
1146
_HVD_EX_SetCMD(MS_U32 u32Id,MS_U32 u32Cmd)1147 static MS_BOOL _HVD_EX_SetCMD(MS_U32 u32Id, MS_U32 u32Cmd)
1148 {
1149 MS_U16 u16TimeOut = 0xFFFF;
1150 MS_BOOL bResult = FALSE;
1151 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1152
1153 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD \n", u32Cmd);
1154
1155 #if HVD_ENABLE_MVC
1156 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1157 {
1158 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1159 }
1160 #endif /// HVD_ENABLE_MVC
1161
1162 HVD_EX_MSG_DBG("Send CMD 0x%x to HVD u8TaskId = %X\n", u32Cmd,u8TaskId);
1163
1164 while (--u16TimeOut)
1165 {
1166 if (_HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX))
1167 {
1168 u32Cmd |= (u8TaskId << 24);
1169 bResult = _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmd);
1170 break;
1171 }
1172 }
1173 return bResult;
1174 }
1175
_HVD_EX_SendCmd(MS_U32 u32Id,MS_U32 u32Cmd,MS_U32 u32CmdArg)1176 static HVD_Return _HVD_EX_SendCmd(MS_U32 u32Id, MS_U32 u32Cmd, MS_U32 u32CmdArg)
1177 {
1178 MS_U32 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1179 #ifdef VDEC3
1180 HVD_DRAM_COMMAND_QUEUE_SEND_STATUS SentRet = E_HVD_COMMAND_QUEUE_SEND_FAIL;
1181 MS_BOOL IsSent = FALSE;
1182 MS_BOOL IsMailBox = FALSE;
1183 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
1184
1185 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd))
1186 {
1187 do {
1188 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1189 if (!SentRet)
1190 HVD_EX_MSG_DBG("^^^Display command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1191 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1192 break;
1193 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1194 IsSent = TRUE;
1195 break;
1196 }
1197 else if (HVD_GetSysTime_ms() > u32timeout)
1198 {
1199 HVD_EX_MSG_ERR("^^^Display command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1200 break;
1201 }
1202 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1203 }
1204 else if (!HAL_VPU_EX_IsMailBoxCMD(u32Cmd))
1205 {
1206 do {
1207 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_ARG, u32CmdArg);
1208 if (!SentRet)
1209 HVD_EX_MSG_DBG("^^^Dram command ARG return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1210 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1211 break;
1212 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1213 IsSent = TRUE;
1214 break;
1215 }
1216 else if (HVD_GetSysTime_ms() > u32timeout)
1217 {
1218 HVD_EX_MSG_ERR("^^^Dram command ARG timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1219 break;
1220 }
1221 }while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1222 }
1223 if (!IsSent)
1224 {
1225 IsMailBox = TRUE;
1226 u32timeout = HVD_GetSysTime_ms() + HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT;//pHVDHalContext->u32HVDCmdTimeout;
1227 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1228 #else
1229 while (!_HVD_EX_SetCMDArg(u32Id, u32CmdArg))
1230 #endif
1231 {
1232 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1233 if (HVD_GetSysTime_ms() > u32timeout)
1234 {
1235 HVD_EX_MSG_ERR("Timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1236 return E_HVD_RETURN_TIMEOUT;
1237 }
1238 //#endif
1239
1240 #if 0
1241 if (u32Cmd == E_HVD_CMD_STOP)
1242 {
1243 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1244 #if HVD_ENABLE_MVC
1245 if(E_HAL_VPU_MVC_STREAM_BASE == u8TaskId)
1246 {
1247 u8TaskId = E_HAL_VPU_MAIN_STREAM_BASE;
1248 }
1249 #endif /// HVD_ENABLE_MVC
1250 MS_U32 u32Cmdtmp = (u8TaskId << 24) | E_HVD_CMD_STOP;
1251
1252 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_MBOX, u32Cmdtmp);
1253 _HVD_EX_MBoxSend(u32Id, HAL_HVD_CMD_ARG_MBOX, 0);
1254
1255 return E_HVD_RETURN_SUCCESS;
1256 }
1257 #endif
1258
1259 if(u32Cmd < E_DUAL_CMD_BASE)
1260 {
1261 //_HVD_EX_GetPC();
1262 HAL_HVD_EX_Dump_FW_Status(u32Id);
1263 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1264 }
1265 }
1266
1267 #ifdef VDEC3
1268 }
1269 IsSent = FALSE;
1270 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1271 if (HAL_VPU_EX_IsDisplayQueueCMD(u32Cmd) && !IsMailBox)
1272 {
1273 do {
1274 SentRet = HAL_VPU_EX_DRAMStreamDispCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1275 if (!SentRet)
1276 HVD_EX_MSG_DBG("^^^Display command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1277 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1278 break;
1279 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1280 IsSent = TRUE;
1281 break;
1282 }
1283 else if (HVD_GetSysTime_ms() > u32timeout)
1284 {
1285 HVD_EX_MSG_ERR("^^^Display command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1286 break;
1287 }
1288 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1289 }
1290 else if(!HAL_VPU_EX_IsMailBoxCMD(u32Cmd) && !IsMailBox)
1291 {
1292 do {
1293 SentRet = HAL_VPU_EX_DRAMStreamCMDQueueSend(u32Id, &pShm->cmd_queue, E_HVD_CMDQ_CMD,u32Cmd);
1294 if (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL) {
1295 HVD_EX_MSG_ERR("^^^Dram command CMD return=0x%X cmd=0x%x arg=0x%x\n", SentRet,u32Cmd, u32CmdArg);
1296 }
1297 if (SentRet == E_HVD_COMMAND_QUEUE_NOT_INITIALED)
1298 break;
1299 else if (SentRet == E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL){
1300 IsSent = TRUE;
1301 break;
1302 }
1303 else if (HVD_GetSysTime_ms() > u32timeout)
1304 {
1305 HVD_EX_MSG_ERR("^^^Dram command CMD timeout: cmd=0x%x arg=0x%x\n", u32Cmd, u32CmdArg);
1306 break;
1307 }
1308 } while (SentRet != E_HVD_COMMAND_QUEUE_SEND_SUCCESSFUL);
1309 }
1310 if (!IsSent)
1311 {
1312 u32timeout = HVD_GetSysTime_ms() + HVD_DRV_MAILBOX_CMD_WAIT_FINISH_TIMEOUT;//pHVDHalContext->u32HVDCmdTimeout;
1313 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1314 #else
1315 u32timeout = HVD_GetSysTime_ms() + pHVDHalContext->u32HVDCmdTimeout;
1316
1317 while (!_HVD_EX_SetCMD(u32Id, u32Cmd))
1318 #endif
1319 {
1320 //#ifndef VDEC3 // FIXME: workaround fw response time is slow sometimes in multiple stream case so far
1321 if (HVD_GetSysTime_ms() > u32timeout)
1322 {
1323 HVD_EX_MSG_ERR("cmd timeout: %x\n", u32Cmd);
1324 return E_HVD_RETURN_TIMEOUT;
1325 }
1326 //#endif
1327 if(u32Cmd < E_DUAL_CMD_BASE)
1328 {
1329 //_HVD_EX_GetPC();
1330 HAL_HVD_EX_Dump_FW_Status(u32Id);
1331 HAL_HVD_EX_Dump_HW_Status(HVD_U32_MAX);
1332 }
1333 }
1334 #ifdef VDEC3
1335 }
1336 else
1337 {
1338 HAL_HVD_EX_FlushMemory();
1339 }
1340 #endif
1341 return E_HVD_RETURN_SUCCESS;
1342 }
1343
_HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)1344 static void _HVD_EX_SetMIUProtectMask(MS_BOOL bEnable)
1345 {
1346 #if HAL_HVD_ENABLE_MIU_PROTECT
1347 _HVD_MIU_SetReqMask(MVD_RW_0, bEnable);
1348 _HVD_MIU_SetReqMask(MVD_RW_1, bEnable);
1349 _HVD_MIU_SetReqMask(MVD_BBU_R, bEnable);
1350 #if SUPPORT_EVD
1351 _HVD_MIU_SetReqMask(EVD_RW, bEnable);
1352 _HVD_MIU_SetReqMask(EVD_BBU_R, bEnable);
1353 #endif
1354 _HVD_MIU_SetReqMask(HVD_RW_MIF0, bEnable);
1355 _HVD_MIU_SetReqMask(HVD_RW_MIF1, bEnable);
1356 _HVD_MIU_SetReqMask(HVD_BBU_R, bEnable);
1357 HAL_VPU_EX_MIU_RW_Protect(bEnable);
1358 //HVD_Delay_ms(1);
1359 #endif
1360 return;
1361 }
1362
_HVD_EX_SetBufferAddr(MS_U32 u32Id)1363 static void _HVD_EX_SetBufferAddr(MS_U32 u32Id)
1364 {
1365 MS_U16 u16Reg = 0;
1366 MS_VIRT u32StAddr = 0;
1367 #ifdef VDEC3
1368 MS_U32 u32Length = 0;
1369 #endif
1370 MS_U8 u8BitMiuSel = 0;
1371 MS_U8 u8CodeMiuSel = 0;
1372 MS_U8 u8FBMiuSel = 0;
1373 MS_U8 u8TmpMiuSel = 0;
1374
1375 MS_U32 u32BitStartOffset;
1376 MS_U32 u32CodeStartOffset;
1377 MS_U32 u32FBStartOffset;
1378
1379 #ifndef VDEC3
1380 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
1381 #endif
1382 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1383 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1384 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1385
1386 _HAL_HVD_Entry();
1387
1388 if (pCtrl == NULL)
1389 {
1390 _HAL_HVD_Return();
1391 }
1392
1393 MS_BOOL bESBufferAlreadySet = FALSE;
1394 VPU_EX_TaskInfo taskInfo;
1395 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1396
1397 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
1398
1399 bESBufferAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
1400
1401
1402
1403 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
1404 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
1405 _phy_to_miu_offset(u8FBMiuSel, u32FBStartOffset, pCtrl->MemMap.u32FrameBufAddr);
1406
1407 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_MIU_SEL,
1408 (u8BitMiuSel << VDEC_BS_MIUSEL) |
1409 (u8FBMiuSel << VDEC_LUMA8_MIUSEL) |
1410 (u8FBMiuSel << VDEC_LUMA2_MIUSEL) |
1411 (u8FBMiuSel << VDEC_CHROMA8_MIUSEL) |
1412 (u8FBMiuSel << VDEC_CHROMA2_MIUSEL) |
1413 (u8FBMiuSel << VDEC_HWBUF_MIUSEL) |
1414 (u8FBMiuSel << VDEC_BUF1_MIUSEL) |
1415 (u8FBMiuSel << VDEC_BUF2_MIUSEL) |
1416 (u8FBMiuSel << VDEC_PPIN_MIUSEL) |
1417 (u8FBMiuSel << VDEC_XCSHM_MIUSEL));
1418
1419 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1420 {
1421 // ES buffer
1422 #ifdef VDEC3
1423 if(pCtrl->bShareBBU)
1424 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr; // NStream will share the same ES buffer
1425 else
1426 #endif
1427 u32StAddr = u32BitStartOffset;
1428
1429 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1430
1431 #ifdef VDEC3
1432 if (!_HAL_EX_BBU_VP8_InUsed())
1433 #endif
1434 {
1435 HVD_EX_MSG_DBG("ESB start addr=%lx\n", (unsigned long)u32StAddr);
1436
1437 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1438 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1439
1440 #ifdef VDEC3
1441 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1442 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32TotalBitstreamBufSize >> 3));
1443 #else
1444 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1445 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1446 #endif
1447
1448 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1449 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1450 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1451 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1452 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1453 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1454 }
1455
1456 _HAL_HVD_Return();
1457 }
1458
1459 // ES buffer
1460 #ifdef VDEC3
1461 if(!pCtrl->bShareBBU || E_HVD_INIT_INPUT_TSP == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK))
1462 {
1463 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1464 u32Length = pCtrl->MemMap.u32BitstreamBufSize >> 3;
1465 }
1466 else
1467 {
1468 u32StAddr = pCtrl->MemMap.u32TotalBitstreamBufAddr;
1469 u32Length = pCtrl->MemMap.u32TotalBitstreamBufSize >> 3;
1470 }
1471 #else
1472 u32StAddr = u32BitStartOffset;
1473 #endif
1474
1475 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, u32StAddr);
1476
1477 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%x\n", (unsigned long)u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1478
1479 #ifdef VDEC3
1480 if (!bESBufferAlreadySet)
1481 {
1482 if (pCtrl->u32BBUId == 0)
1483 {
1484 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1485 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1486
1487 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(u32Length));
1488 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(u32Length));
1489 }
1490 else
1491 {
1492 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1493 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1494
1495 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(u32Length));
1496 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(u32Length));
1497 }
1498 }
1499 #else
1500 if (0 == u8TaskId)
1501 {
1502 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1503 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1504
1505 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1506 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1507 }
1508 else
1509 {
1510 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1511 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1512
1513 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1514 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1515 }
1516 #endif
1517
1518 // others
1519 #ifdef VDEC3
1520 if (!bESBufferAlreadySet)
1521 {
1522 if (pCtrl->u32BBUId == 0)
1523 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1524 else
1525 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1526
1527 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1528 {
1529 if (pCtrl->u32BBUId == 0)
1530 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1531 else
1532 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1533 }
1534 else
1535 {
1536 if (pCtrl->u32BBUId == 0)
1537 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1538 else
1539 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1540 }
1541
1542 // do not set parsing setting in DRV, and we set it in FW (hvd_switch_bbu)
1543 if (pCtrl->u32BBUId == 0)
1544 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1545 else
1546 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1547
1548 if (pCtrl->u32BBUId == 0)
1549 {
1550 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1551 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1552 }
1553 else
1554 {
1555 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1556 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1557 }
1558 }
1559 #else
1560 if (0 == u8TaskId)
1561 {
1562 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB));
1563
1564 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1565 {
1566 u16Reg |= HVD_REG_BBU_TSP_INPUT;
1567 }
1568 else
1569 {
1570 u16Reg &= ~HVD_REG_BBU_TSP_INPUT;
1571 }
1572
1573 u16Reg &= ~HVD_REG_BBU_PASER_MASK;
1574
1575 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1576 {
1577 u16Reg |= HVD_REG_BBU_PASER_DISABLE; // force BBU to remove nothing, RM only
1578 }
1579 else // AVS or AVC
1580 {
1581 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1582 {
1583 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03;
1584 }
1585 else // start code remained
1586 {
1587 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL;
1588 }
1589 }
1590
1591 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB;
1592
1593 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), u16Reg);
1594 }
1595 else
1596 {
1597 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1598
1599 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1600 {
1601 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1602 }
1603 else
1604 {
1605 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1606 }
1607
1608 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1609
1610 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1611 {
1612 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1613 }
1614 else // AVS or AVC
1615 {
1616 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1617 {
1618 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1619 }
1620 else // start code remained
1621 {
1622 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1623 }
1624 }
1625
1626 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1627
1628 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1629 }
1630 #endif
1631
1632 #if (HVD_ENABLE_MVC)
1633 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1634 {
1635 /// Used sub stream to record sub view data.
1636 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
1637 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
1638
1639 // ES buffer
1640 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr));
1641
1642 HVD_EX_MSG_DBG("[MVC] 2nd ES _HAL_HVD_SetBuffer2Addr: ESb StAddr:%lx, len:%lx.\n", (unsigned long) u32StAddr, (unsigned long) pDrvCtrl_Sub->MemMap.u32BitstreamBufSize);
1643 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1644 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1645
1646 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1647 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pDrvCtrl_Sub->MemMap.u32BitstreamBufSize >> 3));
1648
1649 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB));
1650 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
1651 {
1652 u16Reg |= HVD_REG_BBU_TSP_INPUT_BS2;
1653 HVD_EX_MSG_DBG("[MVC] 2nd ES, TSP mode.\n");
1654 }
1655 else
1656 {
1657 u16Reg &= ~HVD_REG_BBU_TSP_INPUT_BS2;
1658 HVD_EX_MSG_DBG("[MVC] 2nd ES, BBU mode.\n");
1659 }
1660 u16Reg &= ~HVD_REG_BBU_PASER_MASK_BS2;
1661 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) // RM
1662 {
1663 u16Reg |= HVD_REG_BBU_PASER_DISABLE_BS2; // force BBU to remove nothing, RM only
1664 }
1665 else // AVS or AVC
1666 {
1667 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_START_CODE_MASK) == E_HVD_INIT_START_CODE_REMOVED)
1668 {
1669 u16Reg |= HVD_REG_BBU_PASER_ENABLE_03_BS2;
1670 }
1671 else // start code remained
1672 {
1673 u16Reg |= HVD_REG_BBU_PASER_ENABLE_ALL_BS2;
1674 ///HVD_MSG_DBG("[MVC] BBU Paser all.\n");
1675 }
1676 }
1677 u16Reg |= HVD_REG_BBU_AUTO_NAL_TAB_BS2;
1678 ///HVD_MSG_DBG("[MVC] 2nd MIF BBU 0x%lx.\n",(MS_U32)u16Reg);
1679 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), u16Reg);
1680 }
1681 #endif
1682
1683 // MIF offset
1684 #if 0
1685 {
1686 MS_U16 offaddr = 0;
1687 u32StAddr = pCtrl->MemMap.u32CodeBufAddr;
1688 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1689 {
1690 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1691 }
1692 HVD_EX_MSG_DBG("MIF offset:%lx \n", u32StAddr);
1693 offaddr = (MS_U16) ((u32StAddr) >> 20);
1694 offaddr &= BMASK(HVD_REG_MIF_OFFSET_L_BITS:0);
1695 //0x1FF; // 9 bits(L + H)
1696 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BBU);
1697 u16Reg &= ~HVD_REG_MIF_OFFSET_H;
1698 u16Reg &= ~(BMASK(HVD_REG_MIF_OFFSET_L_BITS:0));
1699 if (offaddr & BIT(HVD_REG_MIF_OFFSET_L_BITS))
1700 {
1701 u16Reg |= HVD_REG_MIF_OFFSET_H;
1702 }
1703 _HVD_Write2Byte(HVD_REG_MIF_BBU, (u16Reg | (offaddr & BMASK(HVD_REG_MIF_OFFSET_L_BITS:0))));
1704 }
1705 #endif
1706
1707 if (!bESBufferAlreadySet)
1708 {
1709 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_ES_BUFFER);
1710 }
1711
1712 _HAL_HVD_Return();
1713 }
1714
1715 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
1716 // Note: For VP8 only. MVC ES buffer address will be set when _HVD_EX_SetBufferAddr() is called
1717 static void _HVD_EX_SetESBufferAddr(MS_U32 u32Id)
1718 {
1719 MS_U16 u16Reg = 0;
1720 MS_U32 u32StAddr = 0;
1721 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1722 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
1723 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
1724
1725 if(pCtrl == NULL) return;
1726
1727 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
1728 {
1729 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
1730
1731 // ES buffer
1732 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1733
1734 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1735 {
1736 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1737 }
1738
1739 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_L_BS34, HVD_LWORD(u32StAddr >> 3));
1740 _HVD_Write2Byte(HVD_REG_ESB_ST_ADR_H_BS34, HVD_HWORD(u32StAddr >> 3));
1741
1742 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS34, HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1743 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS34, HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1744
1745 u16Reg = _HVD_Read2Byte(HVD_REG_MIF_BS34);
1746 u16Reg &= ~HVD_REG_BS34_TSP_INPUT;
1747 u16Reg &= ~HVD_REG_BS34_PASER_MASK;
1748 u16Reg |= HVD_REG_BS34_PASER_DISABLE;
1749 u16Reg |= HVD_REG_BS34_AUTO_NAL_TAB;
1750 _HVD_Write2Byte(HVD_REG_MIF_BS34, u16Reg);
1751
1752 return;
1753 }
1754
1755 // ES buffer
1756 u32StAddr = pCtrl->MemMap.u32BitstreamBufAddr;
1757
1758 if (u32StAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1759 {
1760 u32StAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1761 }
1762
1763 HVD_EX_MSG_DBG("ESB start addr=%lx, len=%lx\n", u32StAddr, pCtrl->MemMap.u32BitstreamBufSize);
1764
1765 if (0 == HAL_VPU_EX_GetTaskId(u32Id))
1766 {
1767 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L(u32RB), HVD_LWORD(u32StAddr >> 3));
1768 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H(u32RB), HVD_HWORD(u32StAddr >> 3));
1769
1770 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1771 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1772 }
1773 else
1774 {
1775 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_L_BS2(u32RB), HVD_LWORD(u32StAddr >> 3));
1776 _HVD_Write2Byte(HVD_REG_ESB_ST_ADDR_H_BS2(u32RB), HVD_HWORD(u32StAddr >> 3));
1777
1778 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_L_BS2(u32RB), HVD_LWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1779 _HVD_Write2Byte(HVD_REG_ESB_LENGTH_H_BS2(u32RB), HVD_HWORD(pCtrl->MemMap.u32BitstreamBufSize >> 3));
1780 }
1781 }
1782 #endif
1783
_HVD_EX_GetESLevel(MS_U32 u32Id)1784 static MS_U32 _HVD_EX_GetESLevel(MS_U32 u32Id)
1785 {
1786 MS_U32 u32Wptr = 0;
1787 MS_U32 u32Rptr = 0;
1788 MS_U32 u32CurMBX = 0;
1789 MS_U32 u32ESsize = 0;
1790 MS_U32 u32Ret = E_HVD_ESB_LEVEL_NORMAL;
1791 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1792
1793 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1794 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1795 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1796
1797 if (u32Rptr >= u32Wptr)
1798 {
1799 u32CurMBX = u32Rptr - u32Wptr;
1800 }
1801 else
1802 {
1803 u32CurMBX = u32ESsize - (u32Wptr - u32Rptr);
1804 }
1805
1806 if (u32CurMBX == 0)
1807 {
1808 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1809 }
1810 else if (u32CurMBX < HVD_FW_AVC_ES_OVER_THRESHOLD)
1811 {
1812 u32Ret = E_HVD_ESB_LEVEL_OVER;
1813 }
1814 else
1815 {
1816 u32CurMBX = u32ESsize - u32CurMBX;
1817 if (u32CurMBX < HVD_FW_AVC_ES_UNDER_THRESHOLD)
1818 {
1819 u32Ret = E_HVD_ESB_LEVEL_UNDER;
1820 }
1821 }
1822
1823 return u32Ret;
1824 }
1825
_HVD_EX_GetESQuantity(MS_U32 u32Id)1826 static MS_U32 _HVD_EX_GetESQuantity(MS_U32 u32Id)
1827 {
1828 MS_U32 u32Wptr = 0;
1829 MS_U32 u32Rptr = 0;
1830 MS_U32 u32ESsize = 0;
1831 MS_U32 u32Ret = 0;
1832 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1833
1834 u32Wptr = _HVD_EX_GetESWritePtr(u32Id);
1835 u32Rptr = _HVD_EX_GetESReadPtr(u32Id, FALSE);
1836 u32ESsize = pCtrl->MemMap.u32BitstreamBufSize;
1837
1838
1839 if(u32Wptr >= u32Rptr)
1840 {
1841 u32Ret = u32Wptr - u32Rptr;
1842 }
1843 else
1844 {
1845 u32Ret = u32ESsize - u32Rptr + u32Wptr;
1846 }
1847 //printf("ES Quantity <0x%lx> W:0x%lx, R:0x%lx, Q:0x%lx.\n",u32Id,u32Wptr,u32Rptr,u32Ret);
1848 return u32Ret;
1849 }
1850
1851 #if (HVD_ENABLE_IQMEM)
HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)1852 MS_BOOL HAL_HVD_EX_IQMem_Init(MS_U32 u32Id)
1853 {
1854
1855 MS_U32 u32Timeout = 20000;
1856
1857 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_NONE)
1858 {
1859
1860 HAL_VPU_EX_IQMemSetDAMode(TRUE);
1861
1862 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_LOADING);
1863
1864
1865 while (u32Timeout)
1866 {
1867
1868 if (HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IQMEM_CTRL) == E_HVD_IQMEM_INIT_LOADED)
1869 {
1870 break;
1871 }
1872 u32Timeout--;
1873 HVD_Delay_ms(1);
1874 }
1875
1876 HAL_VPU_EX_IQMemSetDAMode(FALSE);
1877
1878 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_CTRL, E_HVD_IQMEM_INIT_FINISH);
1879
1880 if (u32Timeout==0)
1881 {
1882 HVD_EX_MSG_ERR("Wait E_HVD_IQMEM_INIT_LOADED timeout !!\n");
1883 return FALSE;
1884 }
1885
1886
1887 }
1888 return TRUE;
1889 }
1890
1891 #endif
1892
1893 #ifdef VDEC3
_HVD_EX_SetRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)1894 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
1895 #else
1896 static MS_BOOL _HVD_EX_SetRegCPU(MS_U32 u32Id)
1897 #endif
1898 {
1899 MS_U32 u32FirmVer = 0;
1900 MS_U32 u32Timeout = 20000;
1901 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
1902
1903 HVD_EX_MSG_DBG("HVD HW ver id: 0x%04x\n", HAL_HVD_EX_GetHWVersionID());
1904
1905 #if HVD_ENABLE_TIME_MEASURE
1906 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
1907 #endif
1908
1909 HAL_VPU_EX_SetFWReload(!pCtrl->bTurboFWMode);
1910
1911 VPU_EX_FWCodeCfg fwCfg;
1912 VPU_EX_TaskInfo taskInfo;
1913 VPU_EX_VLCTblCfg vlcCfg;
1914 #ifdef VDEC3
1915 VPU_EX_FBCfg fbCfg;
1916 #endif
1917 VPU_EX_NDecInitPara nDecInitPara;
1918
1919 memset(&fwCfg, 0, sizeof(VPU_EX_FWCodeCfg));
1920 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
1921 memset(&vlcCfg, 0, sizeof(VPU_EX_VLCTblCfg));
1922 memset(&nDecInitPara, 0, sizeof(VPU_EX_NDecInitPara));
1923 #ifdef VDEC3_FB
1924 nDecInitPara.pVLCCfg = NULL;
1925 #else
1926 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
1927 {
1928 vlcCfg.u32DstAddr = MsOS_PA2KSEG0(pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr);
1929 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
1930 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
1931 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr;
1932 vlcCfg.u32VLCTableOffset = pHVDHalContext->u32RV_VLCTableAddr;
1933 nDecInitPara.pVLCCfg = &vlcCfg;
1934 }
1935 #endif
1936 nDecInitPara.pFWCodeCfg = &fwCfg;
1937 nDecInitPara.pTaskInfo = &taskInfo;
1938 #ifdef VDEC3
1939 fbCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufAddr;
1940 fbCfg.u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
1941
1942 if (fbCfg.u32FrameBufAddr >= pCtrl->MemMap.u32MIU1BaseAddr)
1943 {
1944 fbCfg.u32FrameBufAddr -= pCtrl->MemMap.u32MIU1BaseAddr;
1945 }
1946
1947 nDecInitPara.pFBCfg = &fbCfg;
1948 #endif
1949
1950 fwCfg.u8SrcType = pCtrl->MemMap.eFWSourceType;
1951 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
1952 fwCfg.u32DstSize = pCtrl->MemMap.u32CodeBufSize;
1953 fwCfg.u32BinAddr = pCtrl->MemMap.u32FWBinaryVAddr;
1954 fwCfg.u32BinSize = pCtrl->MemMap.u32FWBinarySize;
1955
1956 taskInfo.u32Id = u32Id;
1957
1958 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
1959 {
1960 taskInfo.eDecType = E_VPU_EX_DECODER_HVD; //E_VPU_EX_DECODER_MVC;
1961 }
1962 #ifdef VDEC3
1963 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
1964 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
1965 {
1966 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
1967 }
1968 #if SUPPORT_MSVP9
1969 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
1970 {
1971 taskInfo.eDecType = E_VPU_EX_DECODER_EVD;
1972 }
1973 #endif
1974 #if SUPPORT_G2VP9
1975 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
1976 {
1977 taskInfo.eDecType = E_VPU_EX_DECODER_G2VP9;
1978 }
1979 #endif
1980 #endif
1981 else
1982 {
1983 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
1984 }
1985
1986 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
1987
1988 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
1989 {
1990 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
1991 }
1992 else
1993 {
1994 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
1995 }
1996 taskInfo.u32HeapSize = HVD_DRAM_SIZE;
1997
1998 #ifdef SUPPORT_EVD
1999 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
2000 (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9 )
2001 taskInfo.u32HeapSize = EVD_DRAM_SIZE;
2002 #endif
2003
2004 if(TRUE == HVD_EX_GetRstFlag())
2005 {
2006 //Delete task for Rst
2007 if(!HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2008 {
2009 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
2010 }
2011 HVD_EX_SetRstFlag(FALSE);
2012 }
2013
2014 #if (HVD_ENABLE_IQMEM)
2015 HAL_HVD_EX_SetData(u32Id, E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT, (MS_U32)1);
2016 #endif
2017
2018 #ifdef VDEC3
2019 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara, bFWdecideFB, pCtrl->u32BBUId))
2020 #else
2021 if (!HAL_VPU_EX_TaskCreate(u32Id, &nDecInitPara))
2022 #endif
2023 {
2024 HVD_EX_MSG_ERR("Task create fail!\n");
2025
2026 return FALSE;
2027 }
2028
2029 while (u32Timeout)
2030 {
2031 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_INIT_DONE);
2032
2033 if (u32FirmVer != 0)
2034 {
2035 u32FirmVer = HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID);
2036 break;
2037 }
2038 u32Timeout--;
2039 HVD_Delay_ms(1);
2040 }
2041
2042 #ifdef VDEC3_FB
2043 #if HVD_ENABLE_RV_FEATURE
2044 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2045
2046 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM) //rm
2047 {
2048 if(pShm->u32RM_VLCTableAddr == 0) {
2049 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!RM_VLCTableAddr is not ready\n");
2050 }
2051 else
2052 {
2053 vlcCfg.u32DstAddr = MsOS_PA2KSEG1(MsOS_VA2PA(nDecInitPara.pFWCodeCfg->u32DstAddr + pShm->u32RM_VLCTableAddr));
2054 vlcCfg.u32BinAddr = pCtrl->MemMap.u32VLCBinaryVAddr;
2055 vlcCfg.u32BinSize = pCtrl->MemMap.u32VLCBinarySize;
2056 vlcCfg.u32FrameBufAddr = pCtrl->MemMap.u32FrameBufVAddr; //this is frame buffer address is decided by player. In VDEC3_FB path, this variable could be zero or the start address of overall Frame buffer.
2057 vlcCfg.u32VLCTableOffset = pShm->u32RM_VLCTableAddr; // offset from FW code start address
2058 nDecInitPara.pVLCCfg = &vlcCfg;
2059 }
2060 }
2061
2062 if (nDecInitPara.pVLCCfg)
2063 {
2064 HVD_EX_MSG_DBG("[VDEC3_FB] Ready to load VLC Table DstAddr=0x%x FrameBufAddr=0x%x VLCTableOffset=0x%x\n", (unsigned int)vlcCfg.u32DstAddr, (unsigned int)vlcCfg.u32FrameBufAddr, (unsigned int)vlcCfg.u32VLCTableOffset);
2065 if (!HAL_VPU_EX_LoadVLCTable(nDecInitPara.pVLCCfg, nDecInitPara.pFWCodeCfg->u8SrcType))
2066 {
2067 HVD_EX_MSG_ERR("[VDEC3_FB] Error!!!Load VLC Table fail!\n");
2068 return FALSE;
2069 }
2070 }
2071 #endif
2072 #endif
2073 if (u32Timeout > 0)
2074 {
2075 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2076
2077 pHVDHalContext->_stHVDStream[u8Idx].bUsed = TRUE;
2078
2079 #ifdef VDEC3
2080 switch (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
2081 {
2082 case E_HVD_INIT_HW_AVC:
2083 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVC;
2084 break;
2085 case E_HVD_INIT_HW_AVS:
2086 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_AVS;
2087 break;
2088 case E_HVD_INIT_HW_RM:
2089 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_RM;
2090 break;
2091 case E_HVD_INIT_HW_MVC:
2092 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MVC;
2093 break;
2094 case E_HVD_INIT_HW_VP8:
2095 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP8;
2096 break;
2097 case E_HVD_INIT_HW_MJPEG:
2098 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_MJPEG;
2099 break;
2100 case E_HVD_INIT_HW_VP6:
2101 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP6;
2102 break;
2103 case E_HVD_INIT_HW_HEVC:
2104 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC;
2105 break;
2106 case E_HVD_INIT_HW_VP9:
2107 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_VP9;
2108 break;
2109 case E_HVD_INIT_HW_HEVC_DV:
2110 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_HEVC_DV;
2111 break;
2112 default:
2113 pHVDHalContext->_stHVDStream[u8Idx].u32CodecType = E_HAL_HVD_NONE;
2114 break;
2115 }
2116 #endif
2117
2118 HVD_EX_MSG_INF("FW version binary=0x%x, if=0x%x\n", u32FirmVer, (MS_U32) HVD_FW_VERSION);
2119 }
2120 else
2121 {
2122 HVD_EX_MSG_ERR("Cannot get FW version !!0x%x 0x%lx \n", (MS_S16) _HVD_Read2Byte(HVD_REG_RESET),
2123 (unsigned long)HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_VERSION_ID));
2124
2125 if (TRUE != HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara))
2126 {
2127 HVD_EX_MSG_ERR("Task delete fail!\n");
2128 }
2129
2130 return FALSE;
2131 }
2132
2133
2134
2135 #if (HVD_ENABLE_IQMEM)
2136
2137 if( HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_IS_IQMEM_SUPPORT))
2138 {
2139
2140 HAL_HVD_EX_IQMem_Init(u32Id);
2141 }
2142 else{
2143 HVD_EX_MSG_DBG("not support IQMEM\n");
2144 }
2145 #endif
2146
2147
2148
2149
2150
2151
2152 #if HVD_ENABLE_TIME_MEASURE
2153 HVD_EX_MSG_MUST("HVD Time Measure:%d (%s %d) \n", HVD_GetSysTime_ms() - pHVDDrvContext->u32InitSysTimeBase, __FUNCTION__, __LINE__);
2154 #endif
2155
2156 return TRUE;
2157 }
2158
_HVD_EX_GetPTSTableRptr(MS_U32 u32Id)2159 static MS_VIRT _HVD_EX_GetPTSTableRptr(MS_U32 u32Id)
2160 {
2161 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2162 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2163 if (pShm->u32PTStableRptrAddr & VPU_QMEM_BASE)
2164 {
2165 return HAL_VPU_EX_MemRead(pShm->u32PTStableRptrAddr);
2166 }
2167 else
2168 {
2169 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2170 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY) pShm->u32PTStableRptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2171 }
2172 }
2173
_HVD_EX_GetPTSTableWptr(MS_U32 u32Id)2174 static MS_VIRT _HVD_EX_GetPTSTableWptr(MS_U32 u32Id)
2175 {
2176 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2177 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2178
2179 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2180 {
2181 return HAL_VPU_EX_MemRead(pShm->u32PTStableWptrAddr);
2182 }
2183 else
2184 {
2185 //return *((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2186 return *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr));
2187 }
2188 }
2189
_HVD_EX_SetPTSTableWptr(MS_U32 u32Id,MS_U32 u32Value)2190 static void _HVD_EX_SetPTSTableWptr(MS_U32 u32Id, MS_U32 u32Value)
2191 {
2192 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2193 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2194
2195 if (pShm->u32PTStableWptrAddr & VPU_QMEM_BASE)
2196 {
2197 if (!HAL_VPU_EX_MemWrite(pShm->u32PTStableWptrAddr, u32Value))
2198 {
2199 HVD_EX_MSG_ERR("PTS table SRAM write failed\n");
2200 }
2201 }
2202 else
2203 {
2204 //*((MS_VIRT *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2205 *((MS_U32 *) MsOS_PA2KSEG1((MS_PHY)pShm->u32PTStableWptrAddr + pCtrl->MemMap.u32CodeBufAddr)) = u32Value;
2206 }
2207 }
2208
_HVD_EX_UpdatePTSTable(MS_U32 u32Id,HVD_BBU_Info * pInfo)2209 static HVD_Return _HVD_EX_UpdatePTSTable(MS_U32 u32Id, HVD_BBU_Info *pInfo)
2210 {
2211 MS_VIRT u32PTSWptr = HVD_U32_MAX;
2212 MS_VIRT u32PTSRptr = HVD_U32_MAX;
2213 MS_VIRT u32DestAddr = 0;
2214 HVD_PTS_Entry PTSEntry;
2215 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2216 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2217 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2218
2219 // update R & W ptr
2220 u32PTSRptr = _HVD_EX_GetPTSTableRptr(u32Id);
2221
2222 HVD_EX_MSG_DBG("PTS table rptr:0x%lx, wptr=0x%lx\n", (unsigned long)u32PTSRptr, (unsigned long)_HVD_EX_GetPTSTableWptr(u32Id));
2223
2224 if (u32PTSRptr >= MAX_PTS_TABLE_SIZE)
2225 {
2226 HVD_EX_MSG_ERR("PTS table Read Ptr(%lx) > max table size(%x) \n", (unsigned long)u32PTSRptr,
2227 (MS_U32) MAX_PTS_TABLE_SIZE);
2228 return E_HVD_RETURN_FAIL;
2229 }
2230
2231 // check queue is full or not
2232 u32PTSWptr = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr + 1;
2233 u32PTSWptr %= MAX_PTS_TABLE_SIZE;
2234
2235 if (u32PTSWptr == u32PTSRptr)
2236 {
2237 HVD_EX_MSG_ERR("PTS table full. Read Ptr(%lx) == new Write ptr(%lx) ,Pre Wptr(%lx) \n", (unsigned long)u32PTSRptr,
2238 (unsigned long)u32PTSWptr, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2239 return E_HVD_RETURN_FAIL;
2240 }
2241
2242 // add one PTS entry
2243 PTSEntry.u32ByteCnt = pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt & HVD_BYTE_COUNT_MASK;
2244 PTSEntry.u32ID_L = pInfo->u32ID_L;
2245 PTSEntry.u32ID_H = pInfo->u32ID_H;
2246 PTSEntry.u32PTS = pInfo->u32TimeStamp;
2247
2248 u32DestAddr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_PTS_TABLE_ST_OFFSET + (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr * sizeof(HVD_PTS_Entry)));
2249
2250 HVD_EX_MSG_DBG("PTS entry dst addr=0x%lx\n", (unsigned long)MsOS_VA2PA(u32DestAddr));
2251
2252 HVD_memcpy((void *) u32DestAddr, &PTSEntry, sizeof(HVD_PTS_Entry));
2253
2254 HAL_HVD_EX_FlushMemory();
2255
2256 // update Write ptr
2257 _HVD_EX_SetPTSTableWptr(u32Id, u32PTSWptr);
2258
2259 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = u32PTSWptr;
2260
2261 return E_HVD_RETURN_SUCCESS;
2262 }
2263
_HVD_EX_UpdateESWptr(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen)2264 static HVD_Return _HVD_EX_UpdateESWptr(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen)
2265 {
2266 //---------------------------------------------------
2267 // item format in nal table:
2268 // reserved |borken| u32NalOffset | u32NalLen
2269 // 13 bits |1bit | 29 bits | 21 bits (total 8 bytes)
2270 //---------------------------------------------------
2271 MS_VIRT u32Adr = 0;
2272 MS_U32 u32BBUNewWptr = 0;
2273 MS_U8 item[8];
2274 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2275 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2276 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2277 MS_PHY u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR;
2278
2279 #if HVD_ENABLE_MVC
2280 if(HAL_HVD_EX_CheckMVCID(u32Id))
2281 {
2282 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
2283 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
2284 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
2285 {
2286 u32BBU_DRAM_ST_ADDR = pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
2287 }
2288 }
2289 #endif /// HVD_ENABLE_MVC
2290
2291 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2292 {
2293 u32BBUNewWptr = pHVDHalContext->u32VP8BBUWptr;
2294 }
2295 else
2296 {
2297 u32BBUNewWptr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2298 }
2299 u32BBUNewWptr++;
2300 u32BBUNewWptr %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
2301
2302 // prepare nal entry
2303
2304 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ||
2305 E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2306 {
2307 // NAL len 22 bits , HEVC level5 constrain
2308 item[0] = u32NalLen & 0xff;
2309 item[1] = (u32NalLen >> 8) & 0xff;
2310 item[2] = ((u32NalLen >> 16) & 0x3f) | ((u32NalOffset << 6) & 0xc0);
2311 item[3] = (u32NalOffset >> 2) & 0xff;
2312 item[4] = (u32NalOffset >> 10) & 0xff;
2313 item[5] = (u32NalOffset >> 18) & 0xff;
2314 item[6] = (u32NalOffset >> 26) & 0x0f; //including broken bit
2315 item[7] = 0;
2316 }
2317 else
2318 {
2319 item[0] = u32NalLen & 0xff;
2320 item[1] = (u32NalLen >> 8) & 0xff;
2321 item[2] = ((u32NalLen >> 16) & 0x1f) | ((u32NalOffset << 5) & 0xe0);
2322 item[3] = (u32NalOffset >> 3) & 0xff;
2323 item[4] = (u32NalOffset >> 11) & 0xff;
2324 item[5] = (u32NalOffset >> 19) & 0xff;
2325 item[6] = (u32NalOffset >> 27) & 0x07; //including broken bit
2326 item[7] = 0;
2327 }
2328
2329 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2330 {
2331 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->u32VP8BBUWptr << 3));
2332 }
2333 else
2334 {
2335 // add nal entry
2336 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2337 }
2338
2339 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2340
2341 HAL_HVD_EX_FlushMemory();
2342
2343 HVD_EX_MSG_DBG("addr=0x%lx, bbu wptr=0x%x\n", (unsigned long)MsOS_VA2PA(u32Adr), pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2344
2345 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2346 {
2347 pHVDHalContext->u32VP8BBUWptr = u32BBUNewWptr;
2348 }
2349 else
2350 {
2351 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = u32BBUNewWptr;
2352 }
2353
2354 return E_HVD_RETURN_SUCCESS;
2355 }
2356
_HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id,MS_U32 u32NalOffset,MS_U32 u32NalLen,MS_U32 u32NalOffset2,MS_U32 u32NalLen2)2357 static HVD_Return _HVD_EX_UpdateESWptr_VP8(MS_U32 u32Id, MS_U32 u32NalOffset, MS_U32 u32NalLen, MS_U32 u32NalOffset2, MS_U32 u32NalLen2)
2358 {
2359 MS_U8 item[8];
2360 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2361 MS_VIRT u32Adr = 0;
2362 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2363 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2364 MS_PHY u32VP8_BBU_DRAM_ST_ADDR_BS4 = pShm->u32HVD_BBU2_DRAM_ST_ADDR;
2365
2366 /*
2367 printf("nal2 offset=0x%x, len=0x%x\n",
2368 u32NalOffset2, u32NalLen2);
2369 */
2370
2371 item[0] = u32NalLen2 & 0xff;
2372 item[1] = (u32NalLen2 >> 8) & 0xff;
2373 item[2] = ((u32NalLen2 >> 16) & 0x1f) | ((u32NalOffset2 << 5) & 0xe0);
2374 item[3] = (u32NalOffset2 >> 3) & 0xff;
2375 item[4] = (u32NalOffset2 >> 11) & 0xff;
2376 item[5] = (u32NalOffset2 >> 19) & 0xff;
2377 item[6] = (u32NalOffset2 >> 27) & 0x07;
2378 item[7] = 0;
2379
2380 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2381 {
2382 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->u32VP8BBUWptr << 3));
2383 }
2384 else
2385 {
2386 u32Adr = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32VP8_BBU_DRAM_ST_ADDR_BS4 + (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr << 3));
2387 }
2388
2389 HVD_memcpy((void *) u32Adr, (void *) item, 8);
2390
2391 HAL_HVD_EX_FlushMemory();
2392
2393 return _HVD_EX_UpdateESWptr(u32Id, u32NalOffset, u32NalLen);
2394 }
2395
_HVD_EX_GetVUIDispInfo(MS_U32 u32Id)2396 static MS_VIRT _HVD_EX_GetVUIDispInfo(MS_U32 u32Id)
2397 {
2398 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2399 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2400
2401 if( ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC) ||
2402 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC) ||
2403 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC) )
2404 {
2405 MS_U16 i;
2406 MS_PHY u32VUIAddr;
2407 MS_U32 *pData = (MS_U32 *) &(pHVDHalContext->g_hvd_VUIINFO);
2408
2409 HAL_HVD_EX_ReadMemory();
2410 u32VUIAddr = pShm->u32AVC_VUIDispInfo_Addr;
2411
2412 for (i = 0; i < sizeof(HVD_AVC_VUI_DISP_INFO); i += 4)
2413 {
2414 if (pShm->u32AVC_VUIDispInfo_Addr & VPU_QMEM_BASE)
2415 {
2416 *pData = HAL_VPU_EX_MemRead(u32VUIAddr + i);
2417 }
2418 else
2419 {
2420 *pData = *((MS_U32 *) MsOS_PA2KSEG1(u32VUIAddr + i + pCtrl->MemMap.u32CodeBufAddr));
2421 }
2422 pData++;
2423 }
2424 }
2425 else
2426 {
2427 memset(&(pHVDHalContext->g_hvd_VUIINFO), 0, sizeof(HVD_AVC_VUI_DISP_INFO));
2428 }
2429
2430 return (MS_VIRT) &(pHVDHalContext->g_hvd_VUIINFO);
2431 }
2432
_HVD_EX_GetBBUQNumb(MS_U32 u32Id)2433 static MS_U32 _HVD_EX_GetBBUQNumb(MS_U32 u32Id)
2434 {
2435 MS_U32 u32ReadPtr = 0;
2436 MS_U32 eRet = 0;
2437 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2438 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2439
2440 u32ReadPtr = _HVD_EX_GetBBUReadptr(u32Id);
2441 MS_U32 u32WritePtr = 0;
2442
2443 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2444 {
2445 u32WritePtr = pHVDHalContext->u32VP8BBUWptr;
2446 }
2447 else
2448 {
2449 u32WritePtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
2450 }
2451
2452 HVD_EX_MSG_DBG("idx=%x, bbu rptr=%x, bbu wptr=%x\n", u8Idx, u32ReadPtr, u32WritePtr);
2453
2454 if (u32WritePtr >= u32ReadPtr)
2455 {
2456 eRet = u32WritePtr - u32ReadPtr;
2457 }
2458 else
2459 {
2460 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - u32WritePtr);
2461 }
2462
2463 #if 0
2464 if (pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr >= u32ReadPtr)
2465 {
2466 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr - u32ReadPtr;
2467 }
2468 else
2469 {
2470 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr);
2471 }
2472
2473 #endif
2474 return eRet;
2475 }
2476
_HVD_EX_GetPTSQNumb(MS_U32 u32Id)2477 static MS_U32 _HVD_EX_GetPTSQNumb(MS_U32 u32Id)
2478 {
2479 MS_U32 u32ReadPtr = 0;
2480 MS_U32 eRet = 0;
2481 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2482
2483 u32ReadPtr = _HVD_EX_GetPTSTableRptr(u32Id);
2484
2485 if (u32ReadPtr >= MAX_PTS_TABLE_SIZE)
2486 {
2487 HVD_EX_MSG_ERR("PTS table Read Ptr(%x) > max table size(%x) \n", u32ReadPtr,
2488 (MS_U32) MAX_PTS_TABLE_SIZE);
2489 return 0;
2490 }
2491
2492 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2493
2494 if (pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr >= u32ReadPtr)
2495 {
2496 eRet = pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr - u32ReadPtr;
2497 }
2498 else
2499 {
2500 eRet = MAX_PTS_TABLE_SIZE - (u32ReadPtr - pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
2501 }
2502
2503 return eRet;
2504 }
2505
_HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)2506 static MS_BOOL _HVD_EX_IsHevcInterlaceField(MS_U32 u32Id)
2507 {
2508 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2509
2510 return pShm->u32CodecType == E_HVD_Codec_HEVC && pShm->DispInfo.u8Interlace == 1;
2511 }
2512
hevc_get_paired(HEVC_PIC_STRUCT pic_struct,int first_field)2513 static HEVC_PIC_STRUCT hevc_get_paired(HEVC_PIC_STRUCT pic_struct, int first_field)
2514 {
2515 if (pic_struct == EVD_TOP_FIELD)
2516 return EVD_BOTTOM_FIELD;
2517 else if (pic_struct == EVD_BOTTOM_FIELD)
2518 return EVD_TOP_FIELD;
2519
2520 if (first_field)
2521 {
2522 // pic_struct is the first field and must pair with the next one
2523 if (pic_struct == EVD_TOP_WITH_NEXT)
2524 return EVD_BOTTOM_WITH_PREV;
2525 else if (pic_struct == EVD_BOTTOM_WITH_NEXT)
2526 return EVD_TOP_WITH_PREV;
2527 }
2528 else
2529 {
2530 // pic_struct is the second field and must pair with the previous one
2531 if (pic_struct == EVD_TOP_WITH_PREV)
2532 return EVD_BOTTOM_WITH_NEXT;
2533 else if (pic_struct == EVD_BOTTOM_WITH_PREV)
2534 return EVD_TOP_WITH_NEXT;
2535 }
2536
2537 return EVD_UNKNOWN_TYPE;
2538 }
2539
_HVD_EX_GetNextDispFrame(MS_U32 u32Id)2540 static HVD_Frm_Information *_HVD_EX_GetNextDispFrame(MS_U32 u32Id)
2541 {
2542 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2543 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2544 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2545 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2546 HAL_HVD_EX_ReadMemory();
2547 MS_U16 u16QNum = pShm->u16DispQNumb;
2548 MS_U16 u16QPtr = pShm->u16DispQPtr;
2549
2550 HVD_Frm_Information *pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2551 if (bDolbyVision)
2552 {
2553 if (pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone && u16QNum < 4) // first time we need to wait 4 pic to ensure we got the correct layer type
2554 {
2555 return NULL;
2556 }
2557 else
2558 {
2559 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = FALSE;
2560 }
2561 }
2562
2563 #if (HVD_ENABLE_MVC)
2564 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2565 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
2566 {
2567 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2568 {
2569 MS_U16 u16RealQPtr = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex;
2570 MS_U16 u16UsedFrm = 0;
2571 MS_U16 u16ResvFrmNum = ((u16RealQPtr % 2) == 0) ? 1 : 0; // need to check the next frame num is exist when get first frame.
2572 if (u16RealQPtr != u16QPtr)
2573 {
2574 if (u16RealQPtr > u16QPtr)
2575 {
2576 u16UsedFrm = u16RealQPtr - u16QPtr;
2577 }
2578 else
2579 {
2580 u16UsedFrm = pShm->u16DispQSize - (u16QPtr - u16RealQPtr);
2581 }
2582 }
2583
2584 if (u16QNum > (u16UsedFrm + u16ResvFrmNum))
2585 {
2586 u16QNum -= u16UsedFrm;
2587 u16QPtr = u16RealQPtr;
2588 pHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr];
2589
2590 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2591 {
2592 if ((u16QPtr % 2) == 0)
2593 {
2594 HVD_Frm_Information *pHvdFrmNext = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr + 1];
2595
2596 if (pHvdFrmNext->u32Status != E_HVD_DISPQ_STATUS_INIT)
2597 {
2598 return NULL;
2599 }
2600
2601 //ALOGE("G1: %x", pHvdFrm->u32PrivateData);
2602 if(bDolbyVision)
2603 {
2604 HVD_PRINT("BL pts: %d, u16QPtr: %d, u16QNum:%d, u32PrivateData:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2605 }
2606 pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData = pHvdFrm->u32PrivateData;
2607 }
2608 else
2609 {
2610 //ALOGE("G2: %x", (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2611 //pShm->UpdateQueue[pShm->u16UpdateQWtPtr] = (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData;
2612 //pShm->u16UpdateQWtPtr = (pShm->u16UpdateQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
2613 HVD_Frm_Information *pHvdFrmPrv = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr - 1]; // must be odd
2614
2615 if(bDolbyVision)
2616 {
2617 HVD_PRINT("EL pts: %d, u16QPtr: %d, u16QNum:%d, uid:%d %d %d %d\n",pHvdFrm->u32TimeStamp, u16QPtr, u16QNum, pHvdFrm->u32PrivateData, pShm->u16DispQNumb, pShm->u16DispQPtr, u16UsedFrm);
2618 #if 0 // dump dolby metadata calculated by FW
2619 unsigned char *dump_addr = (unsigned char *)((void *)pShm + pShm->u32HVD_DBG_DUMP_ADDR - (u8Idx * 0x100000 + HVD_SHARE_MEM_ST_OFFSET));
2620 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2621 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2622 unsigned int i = 0;
2623 unsigned char arr[33] = {0};
2624 if(pVsyncBridgeExt != NULL)
2625 {
2626 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[u16QPtr]);
2627 }
2628 dump_addr += 32 * pFrmInfoExt->u8CurrentIndex;
2629 for (i = 0; i < 32; i++)
2630 {
2631 arr[i] = *(dump_addr + i);
2632 }
2633 HVD_PRINT("[md5]%d=%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x %02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x", (unsigned int)pFrmInfoExt->u8CurrentIndex, arr[0], arr[1], arr[2], arr[3], arr[4], arr[5], arr[6], arr[7], arr[8], arr[9], arr[10], arr[11], arr[12], arr[13], arr[14], arr[15], arr[16], arr[17], arr[18], arr[19], arr[20], arr[21], arr[22], arr[23], arr[24], arr[25], arr[26], arr[27], arr[28], arr[29], arr[30], arr[31]);
2634 #endif
2635 HVD_Frm_Information *pPrevHvdFrm = (HVD_Frm_Information*)&pShm->DispQueue[u16QPtr - 1];//BL
2636 if(DIFF(pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp) > 1000)
2637 HVD_EX_MSG_ERR("BL pts: %d, EL pts: %d matched failed!!\n",pPrevHvdFrm->u32TimeStamp, pHvdFrm->u32TimeStamp);
2638 }
2639 pHvdFrmPrv->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2640 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2641 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, (pHvdFrm->u32PrivateData << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32PrivateData);
2642 }
2643 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2644 u16QPtr++;
2645 if (u16QPtr == pShm->u16DispQSize) u16QPtr = 0;
2646 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = u16QPtr;
2647
2648 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2649 }
2650 }
2651
2652 return NULL;
2653 }
2654
2655 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
2656 //search the next frame to display
2657 while (u16QNum > 0)
2658 {
2659 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
2660 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
2661 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2662
2663 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2664 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2665 {
2666 /// For MVC. Output views after the pair of (base and depend) views were decoded.
2667 /// Check the depned view was initial when Output the base view.
2668 if((u16QPtr%2) == 0)
2669 {
2670 HVD_Frm_Information *pHvdFrm_sub = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
2671 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
2672 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
2673 {
2674 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
2675 ///printf("Return NULL.\n");
2676 return NULL;
2677 }
2678 }
2679
2680 //printf("V:%d.\n",u16QPtr);
2681 pHVDHalContext->_u16DispQPtr = u16QPtr;
2682 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2683 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2684 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2685 HVD_EX_MSG_INF("<<< halHVD pts,idH = %lu, %lu [%x]\n", (unsigned long) pHVDHalContext->pHvdFrm->u32TimeStamp, (unsigned long) pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2686 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2687 }
2688
2689 u16QNum--;
2690 //go to next frame in the dispQ
2691 u16QPtr++;
2692
2693 if (u16QPtr >= pShm->u16DispQSize)
2694 {
2695 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
2696 }
2697 }
2698 }
2699 else
2700 #endif ///HVD_ENABLE_MVC
2701 // pShm->DispInfo.u8Interlace : 0 = progressive, 1 = interlace field, 2 = interlace frame
2702 if (_HVD_EX_IsHevcInterlaceField(u32Id))
2703 {
2704 MS_U32 first_field = pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex == 1 ? 0 : 1;
2705 HVD_Frm_Information *pHvdFrm_first = NULL;
2706
2707 if ((first_field && u16QNum < 2) || (u16QNum == 0)) {
2708 return NULL;
2709 }
2710
2711 while (u16QNum != 0)
2712 {
2713 pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2714 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2715 {
2716 if (!first_field) // second get frame, we will check at least one paired in disp queue.
2717 {
2718 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2719 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2720 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
2721
2722 if(pHvdFrm->u8FieldType == EVD_TOP_FIELD || pHvdFrm->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
2723 pHvdFrm->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
2724 else
2725 pHvdFrm->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
2726 return pHvdFrm;
2727 }
2728 else // first get frame, we will check at least one paired in disp queue.
2729 {
2730 if (pHvdFrm_first == NULL)
2731 {
2732 pHvdFrm_first = pHvdFrm;
2733 }
2734 else
2735 {
2736 pHvdFrm_first->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2737 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm_first->u32PrivateData);
2738
2739 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV)
2740 {
2741 if (pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV && pHvdFrm->u8FieldType == EVD_BOTTOM_WITH_NEXT)
2742 {
2743 pHvdFrm_first->u32ID_L |= (1 << 16);
2744 pHvdFrm->u32ID_L |= (1 << 16);
2745 }
2746 else if (pHvdFrm_first->u8FieldType == EVD_BOTTOM_WITH_PREV && pHvdFrm->u8FieldType == EVD_TOP_WITH_NEXT)
2747 {
2748 pHvdFrm_first->u32ID_L &= (~(1 << 16));
2749 pHvdFrm->u32ID_L &= (~(1 << 16));
2750 }
2751 else
2752 {
2753 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2754 return NULL;
2755 }
2756 }
2757 else
2758 {
2759 if (hevc_get_paired(pHvdFrm->u8FieldType, 0) != pHvdFrm_first->u8FieldType)
2760 {
2761 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, pHvdFrm_first->u32PrivateData);
2762 return NULL;
2763 }
2764 }
2765
2766 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 1;
2767 if (pHvdFrm_first->u8FieldType == EVD_TOP_FIELD || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_PREV || pHvdFrm_first->u8FieldType == EVD_TOP_WITH_NEXT)
2768 pHvdFrm_first->u8FieldType = 1; // 1 = E_VDEC_EX_FIELDTYPE_TOP
2769 else
2770 pHvdFrm_first->u8FieldType = 2; // 2 = E_VDEC_EX_FIELDTYPE_BOTTOM
2771 return pHvdFrm_first;
2772 }
2773 }
2774 }
2775 u16QNum--;
2776 //go to next frame in the dispQ
2777 u16QPtr++;
2778
2779 if (u16QPtr == pShm->u16DispQSize)
2780 {
2781 u16QPtr = 0; //wrap to the begin
2782 }
2783
2784 }
2785 return NULL;
2786 }
2787 else
2788 {
2789 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2790 {
2791
2792 while (u16QNum != 0)
2793 {
2794 pHvdFrm = (HVD_Frm_Information*) &pShm->DispQueue[u16QPtr];
2795
2796 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT) // Must Be
2797 {
2798 pHVDHalContext->_u16DispOutSideQPtr[u8Idx] = u16QPtr;
2799 pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW;
2800 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_UPDATE_DISPQ, pHvdFrm->u32PrivateData);
2801 return (HVD_Frm_Information*)(MS_VIRT)pHvdFrm;
2802 }
2803 u16QNum--;
2804 //go to next frame in the dispQ
2805 if (bDolbyVision)
2806 u16QPtr += 2; // single layer must in even ptr
2807 else
2808 u16QPtr++;
2809
2810 if (u16QPtr >= pShm->u16DispQSize)
2811 {
2812 u16QPtr = 0; //wrap to the begin
2813 }
2814 }
2815
2816 return NULL;
2817 }
2818
2819 //printf("Q: %d %d\n", u16QNum, u16QPtr);
2820 //search the next frame to display
2821 while (u16QNum != 0)
2822 {
2823 pHVDHalContext->pHvdFrm = (HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2824
2825 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
2826 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2827 {
2828 pHVDHalContext->_u16DispQPtr = u16QPtr;
2829 pHVDHalContext->pHvdFrm->u32Status = E_HVD_DISPQ_STATUS_VIEW; /////Change its state!!
2830 HVD_EX_MSG_DBG("FrameDone: %d, pHvdFrm=0x%lx, timestamp=%d\n", u16QPtr,
2831 (unsigned long) pHVDHalContext->pHvdFrm, pShm->DispQueue[u16QPtr].u32TimeStamp);
2832 HVD_EX_MSG_INF("<<< halHVD pts,idH = %u, %u [%x]\n", pHVDHalContext->pHvdFrm->u32TimeStamp, pHVDHalContext->pHvdFrm->u32ID_H, u16QPtr); //STS output
2833 return (HVD_Frm_Information *)(MS_VIRT) pHVDHalContext->pHvdFrm;
2834 }
2835
2836 u16QNum--;
2837 //go to next frame in the dispQ
2838 u16QPtr++;
2839
2840 if (u16QPtr == pShm->u16DispQSize)
2841 {
2842 u16QPtr = 0; //wrap to the begin
2843 }
2844 }
2845 }
2846
2847 return NULL;
2848 }
2849
_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)2850 static HVD_Frm_Information_EXT_Entry *_HVD_EX_GetNextDispFrameExt(MS_U32 u32Id)
2851 {
2852 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
2853 HVD_Frm_Information_EXT_Entry *pFrmInfoExt = NULL;
2854 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
2855 {
2856 HVD_Frm_Information_EXT *pVsyncBridgeExt = (HVD_Frm_Information_EXT *)HAL_HVD_EX_GetDispQExtShmAddr(u32Id);
2857 if(pVsyncBridgeExt != NULL)
2858 {
2859 pFrmInfoExt = &(pVsyncBridgeExt->stEntry[pHVDHalContext->_u16DispOutSideQPtr[u8Idx]]);
2860 }
2861 }
2862 return pFrmInfoExt;
2863 }
2864
_HAL_EX_GetHwMaxPixel(MS_U32 u32Id)2865 static MS_U64 _HAL_EX_GetHwMaxPixel(MS_U32 u32Id)
2866 {
2867 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2868 MS_U64 u64Ret = 0;
2869
2870 #if SUPPORT_EVD
2871 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
2872 if (isEVD)
2873 {
2874 u64Ret = (MS_U64)HEVC_HW_MAX_PIXEL;
2875 }
2876 else
2877 #endif
2878 #if SUPPORT_G2VP9
2879 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
2880 {
2881 u64Ret = (MS_U64)VP9_HW_MAX_PIXEL;
2882 }
2883 else
2884 #endif
2885 {
2886 u64Ret = (MS_U64)HVD_HW_MAX_PIXEL;
2887 }
2888
2889 return u64Ret;
2890 }
2891
2892 MS_BOOL
HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)2893 HAL_HVD_EX_DispFrameAllViewed(MS_U32 u32Id)
2894 {
2895 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
2896 MS_U16 u16QNum = pShm->u16DispQNumb;
2897 MS_U16 u16QPtr = pShm->u16DispQPtr;
2898 static volatile HVD_Frm_Information *pHvdFrm = NULL;
2899 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2900 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
2901 MS_BOOL bMVC = FALSE;
2902 #if HVD_ENABLE_MVC
2903 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
2904 #endif
2905
2906
2907 if (bMVC || (bDolbyVision && !pShm->bSingleLayer) || _HVD_EX_IsHevcInterlaceField(u32Id))
2908 {
2909 if (u16QNum == 1) return TRUE;
2910 }
2911
2912 while (u16QNum != 0)
2913 {
2914 pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
2915 if (pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
2916 {
2917 return FALSE;
2918 }
2919 u16QNum--;
2920
2921 if (bDolbyVision)
2922 u16QPtr += 2; // single layer must in even ptr
2923 else
2924 u16QPtr++;
2925
2926 if (u16QPtr >= pShm->u16DispQSize)
2927 {
2928 u16QPtr = 0; //wrap to the begin
2929 }
2930 }
2931
2932 return TRUE;
2933 }
_HVD_EX_GetDrvCtrl(MS_U32 u32Id)2934 static HVD_EX_Drv_Ctrl *_HVD_EX_GetDrvCtrl(MS_U32 u32Id)
2935 {
2936 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
2937
2938 return &(_pHVDCtrls[u8DrvId]);
2939 }
2940
_HVD_EX_GetStreamIdx(MS_U32 u32Id)2941 MS_U8 _HVD_EX_GetStreamIdx(MS_U32 u32Id)
2942 {
2943 MS_U8 u8OffsetIdx = 0;
2944 MS_U8 u8SidBaseMask = 0xF0;
2945 HAL_HVD_StreamId eSidBase = (HAL_HVD_StreamId) (u32Id >> 8 & u8SidBaseMask);
2946
2947 switch (eSidBase)
2948 {
2949 case E_HAL_HVD_MAIN_STREAM_BASE:
2950 {
2951 u8OffsetIdx = 0;
2952 break;
2953 }
2954 case E_HAL_VPU_SUB_STREAM_BASE:
2955 {
2956 u8OffsetIdx = 1;
2957 break;
2958 }
2959 case E_HAL_VPU_MVC_STREAM_BASE:
2960 {
2961 u8OffsetIdx = 0;
2962 break;
2963 }
2964 #ifdef VDEC3
2965 case E_HAL_VPU_N_STREAM_BASE:
2966 {
2967 u8OffsetIdx = (u32Id>>8) & 0xF;
2968 break;
2969 }
2970 #endif
2971 default:
2972 {
2973 u8OffsetIdx = 0;
2974 break;
2975 }
2976 }
2977
2978 return u8OffsetIdx;
2979 }
2980 /*
2981 static MS_BOOL _HAL_HVD_EX_HVDInUsed(void)
2982 {
2983 MS_U32 i = 0;
2984 for(i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM; i++)
2985 {
2986 if(TRUE == pHVDHalContext->_stHVDStream[i].bUsed)
2987 {
2988 return TRUE;
2989 }
2990 }
2991 return FALSE;
2992 }
2993 */
2994
HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)2995 MS_VIRT HAL_HVD_EX_GetShmAddr(MS_U32 u32Id)
2996 {
2997 MS_PHY u32PhyAddr = 0x0;
2998 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
2999
3000 if (pCtrl->MemMap.u32CodeBufAddr == 0)
3001 {
3002 return 0;
3003 }
3004
3005 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3006
3007 if (u32PhyAddr == 0xFFFFFFFF) //boris
3008 {
3009 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET) + HVD_SHARE_MEM_ST_OFFSET;
3010 }
3011 else
3012 {
3013 // TEE, common + share_info
3014 u32PhyAddr += COMMON_AREA_SIZE;
3015 }
3016
3017 return MsOS_PA2KSEG1(u32PhyAddr);
3018 }
3019
HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)3020 MS_VIRT HAL_HVD_EX_GetDispQExtShmAddr(MS_U32 u32Id)
3021 {
3022 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3023 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3024
3025 if (pCtrl->MemMap.u32CodeBufAddr == 0 || pShm == NULL)
3026 {
3027 return 0;
3028 }
3029
3030 MS_PHY u32PhyAddr = 0x0;
3031 #if 0
3032 u32PhyAddr = HAL_VPU_EX_GetShareInfoAddr(u32Id);
3033
3034 if (u32PhyAddr == 0xFFFFFFFF)
3035 {
3036 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr + (HAL_VPU_EX_GetTaskId(u32Id) * HVD_FW_MEM_OFFSET);
3037 }
3038 #endif
3039 u32PhyAddr = pCtrl->MemMap.u32CodeBufAddr;
3040 u32PhyAddr += pShm->u32DISPQUEUE_EXT_ST_ADDR; //with HVD_FW_MEM_OFFSET
3041
3042 return MsOS_PA2KSEG1(u32PhyAddr);
3043 }
3044
HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)3045 void HAL_HVD_MIF1_MiuClientSel(MS_U8 u8MiuSel)
3046 {
3047
3048 if (u8MiuSel == E_CHIP_MIU_0)
3049 {
3050 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, 0, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3051 }
3052 else if (u8MiuSel == E_CHIP_MIU_1)
3053 {
3054 _HVD_WriteWordMask(MIU0_CLIENT_SELECT_GP4, MIU0_CLIENT_SELECT_GP4_HVD_MIF1, MIU0_CLIENT_SELECT_GP4_HVD_MIF1);
3055 }
3056 }
3057
3058 #if SUPPORT_G2VP9 && defined(VDEC3)
3059 #ifdef __ARM_NEON__
3060 #include <arm_neon.h>
tile4x4_to_raster_8(MS_U8 * raster,MS_U8 * tile,MS_U32 stride,MS_U32 tile_w,MS_U32 tile_h)3061 static void tile4x4_to_raster_8(MS_U8* raster, MS_U8* tile, MS_U32 stride, MS_U32 tile_w, MS_U32 tile_h)
3062 {
3063 uint32x4x4_t data, data2;
3064 MS_U8* raster2 = raster + tile_w * 4;
3065
3066 data = vld4q_u32((const uint32_t *)tile);
3067 data2 = vld4q_u32((const uint32_t *)(tile + tile_w * tile_h * 4));
3068
3069 vst1q_u32((uint32_t *)raster, data.val[0]);
3070 raster += stride;
3071 vst1q_u32((uint32_t *)raster, data.val[1]);
3072 raster += stride;
3073 vst1q_u32((uint32_t *)raster, data.val[2]);
3074 raster += stride;
3075 vst1q_u32((uint32_t *)raster, data.val[3]);
3076
3077
3078 vst1q_u32((uint32_t *)raster2, data2.val[0]);
3079 raster2 += stride;
3080 vst1q_u32((uint32_t *)raster2, data2.val[1]);
3081 raster2 += stride;
3082 vst1q_u32((uint32_t *)raster2, data2.val[2]);
3083 raster2 += stride;
3084 vst1q_u32((uint32_t *)raster2, data2.val[3]);
3085 }
3086 #else
tile4x4_to_raster_4(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3087 static void tile4x4_to_raster_4(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3088 {
3089 MS_U8* tile0 = tile;
3090 MS_U8* tile1 = tile+16;
3091 MS_U8* tile2 = tile+32;
3092 MS_U8* tile3 = tile+48;
3093 int i;
3094
3095 for (i=0; i<4; i++) {
3096 raster[i] = tile0[i];
3097 raster[4+i] = tile1[i];
3098 raster[8+i] = tile2[i];
3099 raster[12+i] = tile3[i];
3100 }
3101
3102 for (i=0; i<4; i++) {
3103 raster[stride+i] = tile0[4+i];
3104 raster[stride+4+i] = tile1[4+i];
3105 raster[stride+8+i] = tile2[4+i];
3106 raster[stride+12+i] = tile3[4+i];
3107 }
3108
3109 for (i=0; i<4; i++) {
3110 raster[2*stride+i] = tile0[8+i];
3111 raster[2*stride+4+i] = tile1[8+i];
3112 raster[2*stride+8+i] = tile2[8+i];
3113 raster[2*stride+12+i] = tile3[8+i];
3114 }
3115
3116 for (i=0; i<4; i++) {
3117 raster[3*stride+i] = tile0[12+i];
3118 raster[3*stride+4+i] = tile1[12+i];
3119 raster[3*stride+8+i] = tile2[12+i];
3120 raster[3*stride+12+i] = tile3[12+i];
3121 }
3122 }
3123 #endif // #ifdef __ARM_NEON__
3124
_HVD_EX_PpTask_Create(MS_U32 u32Id,HVD_EX_Stream * pstHVDStream)3125 static MS_BOOL _HVD_EX_PpTask_Create(MS_U32 u32Id, HVD_EX_Stream *pstHVDStream)
3126 {
3127 MS_S32 s32HvdPpTaskId = MsOS_CreateTask((TaskEntry)_HAL_HVD_EX_PostProc_Task,
3128 u32Id,
3129 E_TASK_PRI_MEDIUM,
3130 TRUE,
3131 NULL,
3132 32, // stack size..
3133 "HVD_PostProcess_task");
3134
3135 if (s32HvdPpTaskId < 0)
3136 {
3137 HVD_EX_MSG_ERR("Pp Task create failed\n");
3138
3139 return FALSE;
3140 }
3141
3142 HVD_EX_MSG_DBG("Pp Task create success\n");
3143 pstHVDStream->s32HvdPpTaskId = s32HvdPpTaskId;
3144
3145 return TRUE;
3146 }
3147
tile_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3148 static MS_U32 tile_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3149 {
3150 return y * stride * h + x * w * h;
3151 }
3152
raster_offset(MS_U32 x,MS_U32 y,MS_U32 w,MS_U32 h,MS_U32 stride)3153 static MS_U32 raster_offset(MS_U32 x, MS_U32 y, MS_U32 w, MS_U32 h, MS_U32 stride)
3154 {
3155 return y * stride * h + x * w;
3156 }
3157
tile4x4_to_raster(MS_U8 * raster,MS_U8 * tile,MS_U32 stride)3158 static void tile4x4_to_raster(MS_U8* raster, MS_U8* tile, MS_U32 stride)
3159 {
3160 raster[0] = tile[0];
3161 raster[1] = tile[1];
3162 raster[2] = tile[2];
3163 raster[3] = tile[3];
3164 raster[stride] = tile[4];
3165 raster[stride + 1] = tile[5];
3166 raster[stride + 2] = tile[6];
3167 raster[stride + 3] = tile[7];
3168 raster[2 * stride] = tile[8];
3169 raster[2 * stride + 1] = tile[9];
3170 raster[2 * stride + 2] = tile[10];
3171 raster[2 * stride + 3] = tile[11];
3172 raster[3 * stride] = tile[12];
3173 raster[3 * stride + 1] = tile[13];
3174 raster[3 * stride + 2] = tile[14];
3175 raster[3 * stride + 3] = tile[15];
3176 }
3177
tiled4x4pic_to_raster_new(MS_U8 * dst,MS_U8 * src,MS_U32 w,MS_U32 h,MS_U32 raster_stride)3178 static void tiled4x4pic_to_raster_new(MS_U8* dst, MS_U8* src, MS_U32 w, MS_U32 h, MS_U32 raster_stride)
3179 {
3180 const MS_U32 tile_w = 4;
3181 const MS_U32 tile_h = 4;
3182 MS_U32 tile_stride = w;
3183 MS_U32 x, y;
3184 MS_U8 *dst1, *dst2;
3185 MS_U8 *src1, *src2;
3186
3187 #ifdef __ARM_NEON__
3188 // To overlap load and store, handle two blocks at the same time.
3189 dst1 = dst;
3190 src1 = src;
3191 for (y = 0; y < h / tile_h; y++)
3192 {
3193 dst2 = dst1;
3194 src2 = src1;
3195 for (x = 0; x <= (w/tile_w - 8); x+=8)
3196 {
3197 tile4x4_to_raster_8(
3198 dst2,
3199 src2,
3200 raster_stride, tile_w, tile_h);
3201 dst2 += tile_w * 8;
3202 src2 += tile_w * tile_h * 8;
3203 }
3204 dst1 += raster_stride * tile_h;
3205 src1 += tile_stride * tile_h;
3206 for (; x < w / tile_w; x++)
3207 {
3208 tile4x4_to_raster(
3209 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3210 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3211 raster_stride);
3212 }
3213 }
3214 #else
3215 dst1 = NULL;
3216 src1 = NULL;
3217 dst2 = NULL;
3218 src2 = NULL;
3219
3220 for (y = 0; y < h / tile_h; y++)
3221 {
3222 for (x = 0; x <= (w/tile_w - 4); x+=4)
3223 {
3224 tile4x4_to_raster_4(
3225 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3226 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3227 raster_stride);
3228 }
3229 for (; x < w / tile_w; x++)
3230 {
3231 tile4x4_to_raster(
3232 dst + raster_offset(x, y, tile_w, tile_h, raster_stride),
3233 src + tile_offset(x, y, tile_w, tile_h, tile_stride),
3234 raster_stride);
3235 }
3236 }
3237 #endif
3238 }
3239
3240 #define FLUSH_CACHE_SIZE (256 * 1024)
3241
_HAL_HVD_EX_Inv_Cache(void * pVA,MS_U32 u32Size)3242 static void _HAL_HVD_EX_Inv_Cache(void *pVA, MS_U32 u32Size)
3243 {
3244 // To improve performance, just flush the first FLUSH_CACHE_SIZE bytes of data
3245 if (u32Size > FLUSH_CACHE_SIZE)
3246 u32Size = FLUSH_CACHE_SIZE;
3247
3248 MsOS_MPool_Dcache_Flush((MS_VIRT)pVA, u32Size);
3249 }
3250
_HAL_HVD_EX_Flush_Cache(void * pVA,MS_U32 u32Size)3251 static void _HAL_HVD_EX_Flush_Cache(void *pVA, MS_U32 u32Size)
3252 {
3253 MS_U32 u32SkipSize = 0;
3254
3255 // To improve performance, just flush the last FLUSH_CACHE_SIZE bytes of data
3256 if (u32Size > FLUSH_CACHE_SIZE)
3257 {
3258 u32SkipSize = u32Size - FLUSH_CACHE_SIZE;
3259 u32Size = FLUSH_CACHE_SIZE;
3260 }
3261
3262 MsOS_MPool_Dcache_Flush(((MS_VIRT)pVA) + u32SkipSize, u32Size);
3263 }
3264
_HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)3265 static MS_BOOL _HAL_HVD_EX_PostProc_Task(MS_U32 u32Id)
3266 {
3267 HVD_EX_Stream *pstHVDStream = pHVDHalContext->_stHVDStream + _HVD_EX_GetStreamIdx(u32Id);
3268 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3269 MS_U32 u32SrcMiuSel, u32DstMiuSel;
3270 MS_U16 u16Width = 0, u16Height = 0, u16TileWidth = 0;
3271
3272 HVD_EX_MSG_DBG("[%s-%d] Start\n", __FUNCTION__, __LINE__);
3273
3274 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_RUNNING;
3275
3276 while (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_STOP)
3277 {
3278 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3279 pstHVDStream->ePpTaskState = E_HAL_HVD_STATE_PAUSE_DONE;
3280
3281 HVD_Delay_ms(1); // FIXME
3282
3283 if (pstHVDStream->ePpTaskState != E_HAL_HVD_STATE_RUNNING)
3284 continue;
3285
3286 HAL_HVD_EX_ReadMemory();
3287
3288 while (pShm->u8PpQueueRPtr != pShm->u8PpQueueWPtr)
3289 {
3290 MS_U8 *pSrcVA, *pDstVA;
3291 MS_U32 u32SrcPA, u32DstPA;
3292 HVD_Frm_Information *pFrmInfo = (HVD_Frm_Information *)&pShm->DispQueue[pShm->u8PpQueueRPtr];
3293 //HVD_EX_MSG_DBG("[%s-%d] width: %d, height = %d, pitch = %d\n", __FUNCTION__, __LINE__, pFrmInfo->u16Width, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3294
3295 if ((u16Width != pFrmInfo->u16Width) || (u16Height != pFrmInfo->u16Height))
3296 {
3297 HVD_Display_Info *pDispInfo = (HVD_Display_Info *) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DISP_INFO_ADDR);
3298
3299 u16Width = pFrmInfo->u16Width;
3300 u16Height = pFrmInfo->u16Height;
3301 u16TileWidth = NEXT_MULTIPLE(pFrmInfo->u16Pitch - pDispInfo->u16CropRight, 8);
3302 }
3303
3304 // Luma
3305 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3306 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_LUMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3307
3308 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInLumaAddr, u32SrcPA);
3309 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32LumaAddr, u32DstPA);
3310
3311 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3312 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3313
3314 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height);
3315
3316 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height, pFrmInfo->u16Pitch);
3317
3318 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height);
3319
3320 // Chroma
3321 u32SrcMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_PPIN_MIUSEL) & VDEC_MIUSEL_MASK;
3322 u32DstMiuSel = (pShm->u32VDEC_MIU_SEL >> VDEC_CHROMA8_MIUSEL) & VDEC_MIUSEL_MASK;
3323
3324 _miu_offset_to_phy(u32SrcMiuSel, pFrmInfo->u32PpInChromaAddr, u32SrcPA);
3325 _miu_offset_to_phy(u32DstMiuSel, pFrmInfo->u32ChromaAddr, u32DstPA);
3326
3327 pSrcVA = (MS_U8*) MS_PA2KSEG0(u32SrcPA);
3328 pDstVA = (MS_U8*) MS_PA2KSEG0(u32DstPA);
3329
3330 _HAL_HVD_EX_Inv_Cache(pSrcVA, u16TileWidth * pFrmInfo->u16Height / 2);
3331
3332 tiled4x4pic_to_raster_new(pDstVA, pSrcVA, u16TileWidth, pFrmInfo->u16Height/2, pFrmInfo->u16Pitch);
3333
3334 _HAL_HVD_EX_Flush_Cache(pDstVA, pFrmInfo->u16Pitch * pFrmInfo->u16Height / 2);
3335
3336 pShm->DispQueue[pShm->u8PpQueueRPtr].u32Status = E_HVD_DISPQ_STATUS_INIT;
3337 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_INC_DISPQ_NUM, 0);
3338 INC_VALUE(pShm->u8PpQueueRPtr, pShm->u8PpQueueSize);
3339
3340 HAL_HVD_EX_FlushMemory();
3341
3342 if (pstHVDStream->ePpTaskState == E_HAL_HVD_STATE_PAUSING)
3343 break;
3344
3345 HAL_HVD_EX_ReadMemory();
3346 }
3347 }
3348
3349 HVD_EX_MSG_DBG("[%s-%d] End\n", __FUNCTION__, __LINE__);
3350
3351 return TRUE;
3352 }
3353 #endif
3354
HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id,MS_BOOL * isVP8Used,MS_BOOL * isAECUsed,MS_BOOL * isAVCUsed)3355 static void HAL_HVD_EX_VP8AECInUsed(MS_U32 u32Id, MS_BOOL *isVP8Used, MS_BOOL *isAECUsed , MS_BOOL *isAVCUsed)
3356 {
3357 MS_U8 i ;
3358 MS_U8 u8DrvId = (0xFF & (u32Id >> 16));
3359
3360 for (i = 0; i < HAL_HVD_EX_MAX_SUPPORT_STREAM ; i++)
3361 {
3362 if( _pHVDCtrls[i].bUsed && (i != u8DrvId))
3363 {
3364 MS_U32 u32TempModeFlag = (_pHVDCtrls[i].InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) ;
3365 if((E_HVD_INIT_HW_VP8 == u32TempModeFlag))
3366 {
3367 *isVP8Used = TRUE ;
3368 }
3369 else if((E_HVD_INIT_HW_VP9 == u32TempModeFlag) || (E_HVD_INIT_HW_AVS == u32TempModeFlag))
3370 {
3371 *isAECUsed = TRUE ;
3372 }
3373 else if((E_HVD_INIT_HW_AVC == u32TempModeFlag))
3374 {
3375 *isAVCUsed = TRUE ;
3376 }
3377 }
3378 }
3379 }
3380
HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)3381 MS_BOOL HAL_HVD_EX_InitHW(MS_U32 u32Id,VPU_EX_DecoderType DecoderType)
3382 {
3383 #ifndef VDEC3
3384 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
3385 #endif
3386 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3387 MS_BOOL isVP8Used = FALSE;
3388 MS_BOOL isAECUsed = FALSE;
3389 MS_BOOL isAVCUsed = FALSE;
3390 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
3391 // MS_U8 u8MiuSel;
3392 // MS_U32 u32StartOffset;
3393
3394 #if SUPPORT_EVD
3395 MS_BOOL isEVD = _HAL_EX_IS_EVD(pCtrl->InitParams.u32ModeFlag);
3396 #else
3397 MS_BOOL isEVD = FALSE;
3398 #endif
3399 MS_BOOL isHVD = !isEVD;
3400
3401 //patch for enable evd in AVC because AVC may enable mf_codec which need evd registers
3402 isEVD = isEVD || (E_HVD_INIT_HW_AVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
3403
3404 // power on / reset HVD; set nal, es rw, bbu parser, release HVD engine
3405 // re-setup clock.
3406 #if SUPPORT_G2VP9 && defined(VDEC3)
3407 if (E_HVD_INIT_HW_VP9 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3408 #endif
3409
3410
3411 if (isHVD)
3412 {
3413 if (!HAL_VPU_EX_HVDInUsed())
3414 {
3415 printf("HVD power on\n");
3416 HAL_HVD_EX_PowerCtrl(u32Id, TRUE);
3417 }
3418
3419 if(!isVP8Used && (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3420 {
3421 HAL_VP8_PowerCtrl(TRUE);
3422 }
3423 else if(!isAECUsed && (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3424 {
3425 HAL_AEC_PowerCtrl(TRUE);
3426 }
3427
3428 #ifdef CONFIG_MSTAR_SRAMPD
3429 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3430 HVD_Delay_ms(1);
3431 #endif
3432 }
3433
3434 #if SUPPORT_EVD
3435 #ifdef VDEC3
3436 if (isEVD) /// Disable it for disable H264 IMI
3437 {
3438 if (!HAL_VPU_EX_EVDInUsed())
3439 {
3440 printf("EVD power on\n");
3441 HAL_EVD_EX_PowerCtrl(u32Id, TRUE);
3442 }
3443 if(!isAECUsed && (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
3444 {
3445 HAL_AEC_PowerCtrl(TRUE);
3446 }
3447 }
3448 #endif
3449 #endif
3450
3451 #if SUPPORT_G2VP9 && defined(VDEC3)
3452 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3453 {
3454 if (!HAL_VPU_EX_G2VP9InUsed())
3455 {
3456 printf("G2 VP9 power on\n");
3457 HAL_VP9_EX_PowerCtrl(TRUE);
3458 }
3459 }
3460 #endif
3461
3462 if ((!HAL_VPU_EX_HVDInUsed()) )
3463 {
3464 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
3465 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
3466 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
3467 _HVD_EX_ResetMainSubBBUWptr(u32Id);
3468
3469 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3470
3471 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_IDB_MIU_256 , HVD_REG_RESET_IDB_MIU_256);
3472 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_MC_MIU_256 , HVD_REG_MC_MIU_256);
3473 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU_256 , HVD_REG_RESET_MIU_256);
3474 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_MIU1_256 , HVD_REG_RESET_MIU1_256);
3475 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU_128);
3476 _HVD_WriteWordMask(HVD_REG_RESET, 0 , HVD_REG_RESET_MIU1_128);
3477
3478 #if 0
3479 if((pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable) &&
3480 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
3481 {
3482 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.u32IapGnBufAddr);
3483
3484 _HAL_HVD_Entry();
3485 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
3486 _HAL_HVD_Release();
3487
3488 }
3489 #endif
3490 }
3491
3492 #if SUPPORT_EVD
3493 if (isEVD)
3494 {
3495 #ifdef VDEC3
3496 if (!HAL_VPU_EX_EVDInUsed())
3497 #endif
3498 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
3499 }
3500 #endif
3501
3502 #if SUPPORT_G2VP9 && defined(VDEC3)
3503 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3504 {
3505 if (!HAL_VPU_EX_G2VP9InUsed())
3506 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
3507 }
3508 #endif
3509
3510
3511 if(pCtrl == NULL)
3512 {
3513 HVD_EX_MSG_ERR("HAL_HVD_EX_InitHW Ctrl is NULL.\n");
3514 //return FALSE;
3515 goto RESET;
3516 }
3517
3518 #if SUPPORT_EVD
3519 if (isEVD && ((E_HVD_INIT_HW_AVC != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ))
3520 {
3521 #ifdef VDEC3
3522 if (!HAL_VPU_EX_EVDInUsed())
3523 #endif
3524 {
3525 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3526 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_HEVC_MODE, EVD_REG_RESET_HK_HEVC_MODE);
3527 }
3528
3529 if ((E_HVD_INIT_MAIN_LIVE_STREAM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK))
3530 ||(E_HVD_INIT_MAIN_FILE_TS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK)))
3531 {
3532 #ifdef VDEC3
3533 if (0 == pCtrl->u32BBUId)
3534 #else
3535 if (0 == u8TaskId)
3536 #endif
3537 {
3538 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_HK_TSP2EVD_EN, EVD_REG_RESET_HK_TSP2EVD_EN); //for main-DTV mode
3539 }
3540 else
3541 {
3542 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_USE_HVD_MIU_EN, EVD_REG_RESET_USE_HVD_MIU_EN); //for sub-DTV mode
3543 }
3544
3545 }
3546 goto RESET;
3547 }
3548 #endif
3549
3550 // HVD4, from JANUS and later chip
3551 switch ((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK)
3552 {
3553 case E_HVD_INIT_HW_AVS:
3554 {
3555 #ifdef VDEC3
3556 if (0 == pCtrl->u32BBUId)
3557 #else
3558 if (0 == u8TaskId)
3559 #endif
3560 {
3561 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3562 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3563 }
3564 else
3565 {
3566 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3567 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3568 }
3569
3570 break;
3571 }
3572 case E_HVD_INIT_HW_RM:
3573 {
3574 #ifdef VDEC3
3575 if (0 == pCtrl->u32BBUId)
3576 #else
3577 if (0 == u8TaskId)
3578 #endif
3579 {
3580 _HVD_WriteWordMask(HVD_REG_RESET, 0,
3581 HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3582
3583 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3584 {
3585 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3586 }
3587 else // RV 8
3588 {
3589 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_RV9_DEC_MODE);
3590 }
3591 }
3592 else
3593 {
3594 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0,
3595 HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3596
3597 if (pCtrl->InitParams.pRVFileInfo->RV_Version) // RV 9,10
3598 {
3599 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3600 }
3601 else // RV 8
3602 {
3603 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_RV9_DEC_MODE_BS2);
3604 }
3605
3606 }
3607
3608 break;
3609 }
3610 default:
3611 {
3612 #ifdef VDEC3
3613 if (0 == pCtrl->u32BBUId)
3614 #else
3615 if (0 == u8TaskId)
3616 #endif
3617 {
3618 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_HK_AVS_MODE | HVD_REG_RESET_HK_RM_MODE);
3619 }
3620 else
3621 {
3622 _HVD_WriteWordMask(HVD_REG_MODE_BS2, 0, HVD_REG_MODE_HK_AVS_MODE_BS2 | HVD_REG_MODE_HK_RM_MODE_BS2);
3623 }
3624 break;
3625 }
3626 }
3627
3628 RESET:
3629
3630 #if 0 //use miu256bit
3631 HVD_EX_MSG_DBG("(be)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3632
3633 if (!HAL_VPU_EX_HVDInUsed())
3634 {
3635 _HVD_Write2Byte(HVD_REG_RESET, (_HVD_Read2Byte(HVD_REG_RESET) | HVD_REG_RESET_MIU_128));
3636 }
3637
3638 HVD_EX_MSG_DBG("(af)Miu128 bits Status = %x <<<<<<<\n", _HVD_Read2Byte(HVD_REG_RESET));
3639 #endif
3640
3641 #if SUPPORT_EVD
3642 if (isEVD)
3643 {
3644 #ifdef VDEC3
3645 if (!HAL_VPU_EX_EVDInUsed())
3646 #endif
3647 {
3648 printf("EVD miu 256 bits\n");
3649 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_MIU0_128 & ~EVD_REG_RESET_MIU1_128));
3650 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) | EVD_REG_RESET_MIU0_256 | EVD_REG_RESET_MIU1_256));
3651 _HVD_Write2Byte(REG_CLK_EVD, (_HVD_Read2Byte(REG_CLK_EVD) & ~REG_CLK_EVD_SW_OV_EN & ~REG_CLK_EVD_PPU_SW_OV_EN));//set 0 firmware
3652 //_HVD_Write2Byte(REG_CLK_EVD, (_HVD_Read2Byte(REG_CLK_EVD) | REG_CLK_EVD_SW_OV_EN | REG_CLK_EVD_PPU_SW_OV_EN));//set 1 driver
3653 printf("EVD BBU 256 bits\n");
3654 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) & ~REG_BBU_MIU_128));
3655 _HVD_Write2Byte(EVD_BBU_MIU_SETTING, (_HVD_Read2Byte(EVD_BBU_MIU_SETTING) | REG_BBU_MIU_256));
3656 }
3657 }
3658 #endif
3659 #if 0 //defined(SUPPORT_NEW_MEM_LAYOUT) || defined(SUPPORT_NEW_VDEC_FLOW)
3660 // Only ES buffer addrress needs to be set for VP8
3661 _HVD_EX_SetESBufferAddr(u32Id);
3662 #else
3663 if(DecoderType != E_VPU_EX_DECODER_MVD)
3664 {
3665 _HVD_EX_SetBufferAddr(u32Id);
3666 }
3667 #endif
3668 if (!HAL_VPU_EX_HVDInUsed())
3669 {
3670 _HVD_WriteWordMask(HVD_REG_RESET, 0, HVD_REG_RESET_SWRST);
3671 }
3672
3673 #if SUPPORT_EVD
3674 if (isEVD)
3675 {
3676 #ifdef VDEC3
3677 if (!HAL_VPU_EX_EVDInUsed())
3678 #endif
3679 _HVD_WriteWordMask(EVD_REG_RESET, 0, EVD_REG_RESET_SWRST);
3680 }
3681 #endif
3682
3683 #if SUPPORT_G2VP9 && defined(VDEC3)
3684 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3685 {
3686 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
3687
3688 if (!HAL_VPU_EX_G2VP9InUsed())
3689 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST);
3690
3691 if (pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE)
3692 _HVD_EX_PpTask_Create(u32Id, &pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
3693 }
3694 #endif
3695
3696 return TRUE;
3697 }
3698
HAL_HVD_EX_DeinitHW(MS_U32 u32Id)3699 MS_BOOL HAL_HVD_EX_DeinitHW(MS_U32 u32Id)
3700 {
3701 MS_U16 u16Timeout = 1000;
3702 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
3703 MS_BOOL isVP8Used = FALSE;
3704 MS_BOOL isAECUsed = FALSE;
3705 MS_BOOL isAVCUsed = FALSE;
3706 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed , &isAVCUsed);
3707
3708 #if SUPPORT_EVD
3709 if(!isAVCUsed && E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) && !HAL_VPU_EX_EVDInUsed())
3710 {
3711 HAL_EVD_EX_DeinitHW(u32Id);//no AVC/EVD use , close EVD power
3712 }
3713 #endif
3714
3715 if(TRUE == HAL_VPU_EX_HVDInUsed())
3716 {
3717 #if 0 //Power control close Vp8 register in dynamic ,but bs4-nal-ready could be off.(Patch for maxim and maserati)
3718 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3719 {
3720 HAL_VP8_PowerCtrl(FALSE);
3721 }
3722 else
3723 #endif
3724 if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3725 {
3726 HAL_AEC_PowerCtrl(FALSE);
3727 }
3728 return FALSE;
3729 }
3730 else
3731 {
3732 _HVD_EX_SetMIUProtectMask(TRUE);
3733
3734 _HVD_WriteWordMask(HVD_REG_RESET, HVD_REG_RESET_SWRST, HVD_REG_RESET_SWRST);
3735
3736 while (u16Timeout)
3737 {
3738 if ((_HVD_Read2Byte(HVD_REG_RESET) & (HVD_REG_RESET_SWRST_FIN)) == (HVD_REG_RESET_SWRST_FIN))
3739 {
3740 break;
3741 }
3742 u16Timeout--;
3743 }
3744
3745 HAL_HVD_EX_PowerCtrl(u32Id, FALSE);
3746
3747 //Power control close Vp8 register in dynamic ,but bs4-nal-ready could be off.(Patch for maxim and maserati)
3748 HAL_VP8_PowerCtrl(FALSE);
3749 #if 0
3750 if(!isVP8Used && E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3751 {
3752 HAL_VP8_PowerCtrl(FALSE);
3753 }
3754 else
3755 #endif
3756 if(!isAECUsed && E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
3757 {
3758 HAL_AEC_PowerCtrl(FALSE);
3759 }
3760
3761 #ifdef CONFIG_MSTAR_SRAMPD
3762 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC1, HICODEC_SRAM_HICODEC1);
3763 HVD_Delay_ms(1);
3764 #endif
3765
3766 _HVD_EX_SetMIUProtectMask(FALSE);
3767
3768 return TRUE;
3769 }
3770
3771 return FALSE;
3772 }
3773
HAL_HVD_EX_FlushMemory(void)3774 void HAL_HVD_EX_FlushMemory(void)
3775 {
3776 MsOS_FlushMemory();
3777 }
3778
HAL_HVD_EX_ReadMemory(void)3779 void HAL_HVD_EX_ReadMemory(void)
3780 {
3781 MsOS_ReadMemory();
3782 }
3783
HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl * pHVDCtrlsBase)3784 void HAL_HVD_EX_SetDrvCtrlsBase(HVD_EX_Drv_Ctrl *pHVDCtrlsBase)
3785 {
3786 _pHVDCtrls = pHVDCtrlsBase;
3787 }
3788
HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)3789 void HAL_HVD_EX_CheckMIUSel(MS_BOOL bChange)
3790 {
3791 return;
3792 }
3793
HAL_HVD_EX_GetHWVersionID(void)3794 MS_U32 HAL_HVD_EX_GetHWVersionID(void)
3795 {
3796 return _HVD_Read2Byte(HVD_REG_REV_ID);
3797 }
3798
3799
HAL_HVD_EX_Init_Share_Mem(void)3800 MS_BOOL HAL_HVD_EX_Init_Share_Mem(void)
3801 {
3802 #if (defined(MSOS_TYPE_LINUX) || defined(MSOS_TYPE_ECOS) || defined(MSOS_TYPE_LINUX_KERNEL))
3803 #if !defined(SUPPORT_X_MODEL_FEATURE)
3804 MS_U32 u32ShmId;
3805 MS_VIRT u32Addr;
3806 MS_U32 u32BufSize;
3807
3808
3809 if (FALSE == MsOS_SHM_GetId( (MS_U8*)"Linux HVD HAL",
3810 sizeof(HVD_Hal_CTX),
3811 &u32ShmId,
3812 &u32Addr,
3813 &u32BufSize,
3814 MSOS_SHM_QUERY))
3815 {
3816 if (FALSE == MsOS_SHM_GetId((MS_U8*)"Linux HVD HAL",
3817 sizeof(HVD_Hal_CTX),
3818 &u32ShmId,
3819 &u32Addr,
3820 &u32BufSize,
3821 MSOS_SHM_CREATE))
3822 {
3823 HVD_EX_MSG_ERR("[%s]SHM allocation failed!!!use global structure instead!!!\n",__FUNCTION__);
3824 if(pHVDHalContext == NULL)
3825 {
3826 pHVDHalContext = &gHVDHalContext;
3827 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3828 _HVD_EX_Context_Init_HAL();
3829 HVD_PRINT("[%s]Global structure init Success!!!\n",__FUNCTION__);
3830 }
3831 else
3832 {
3833 HVD_PRINT("[%s]Global structure exists!!!\n",__FUNCTION__);
3834 }
3835 //return FALSE;
3836 }
3837 else
3838 {
3839 memset((MS_U8*)u32Addr,0,sizeof(HVD_Hal_CTX));
3840 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for one process
3841 _HVD_EX_Context_Init_HAL();
3842 }
3843 }
3844 else
3845 {
3846 pHVDHalContext = (HVD_Hal_CTX*)u32Addr; // for another process
3847 }
3848 #else
3849 if(pHVDHalContext == NULL)
3850 {
3851 pHVDHalContext = &gHVDHalContext;
3852 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3853 _HVD_EX_Context_Init_HAL();
3854 }
3855 #endif
3856 _HAL_HVD_MutexCreate();
3857 #else
3858 if(pHVDHalContext == NULL)
3859 {
3860 pHVDHalContext = &gHVDHalContext;
3861 memset(pHVDHalContext,0,sizeof(HVD_Hal_CTX));
3862 _HVD_EX_Context_Init_HAL();
3863 }
3864 #endif
3865
3866 return TRUE;
3867 }
3868
3869
HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)3870 HAL_HVD_StreamId HAL_HVD_EX_GetFreeStream(HAL_HVD_StreamType eStreamType)
3871 {
3872 MS_U32 i = 0;
3873
3874 if (eStreamType == E_HAL_HVD_MVC_STREAM)
3875 {
3876 if ((FALSE == pHVDHalContext->_stHVDStream[0].bUsed) && (FALSE == pHVDHalContext->_stHVDStream[1].bUsed))
3877 return pHVDHalContext->_stHVDStream[0].eStreamId;
3878 }
3879 else if (eStreamType == E_HAL_HVD_MAIN_STREAM)
3880 {
3881 for (i = 0;
3882 i <
3883 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3884 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3885 {
3886 if ((E_HAL_HVD_MAIN_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3887 {
3888 return pHVDHalContext->_stHVDStream[i].eStreamId;
3889 }
3890 }
3891 }
3892 else if (eStreamType == E_HAL_HVD_SUB_STREAM)
3893 {
3894 for (i = 0;
3895 i <
3896 ((E_HAL_HVD_MAIN_STREAM_MAX - E_HAL_HVD_MAIN_STREAM_BASE) +
3897 (E_HAL_HVD_SUB_STREAM_MAX - E_HAL_HVD_SUB_STREAM_BASE)); i++)
3898 {
3899 if ((E_HAL_HVD_SUB_STREAM_BASE & pHVDHalContext->_stHVDStream[i].eStreamId) && (FALSE == pHVDHalContext->_stHVDStream[i].bUsed))
3900 {
3901 return pHVDHalContext->_stHVDStream[i].eStreamId;
3902 }
3903 }
3904 }
3905 #ifdef VDEC3
3906 else if ((eStreamType >= E_HAL_HVD_N_STREAM) && (eStreamType < E_HAL_HVD_N_STREAM + HAL_HVD_EX_MAX_SUPPORT_STREAM))
3907 {
3908 i = eStreamType - E_HAL_HVD_N_STREAM;
3909 if (!pHVDHalContext->_stHVDStream[i].bUsed)
3910 return pHVDHalContext->_stHVDStream[i].eStreamId;
3911 }
3912 #endif
3913
3914 return E_HAL_HVD_STREAM_NONE;
3915 }
3916
HAL_VP8_PowerCtrl(MS_BOOL bEnable)3917 static void HAL_VP8_PowerCtrl(MS_BOOL bEnable)
3918 {
3919 if (bEnable)
3920 {
3921 _HVD_WriteWordMask(REG_TOP_VP8, ~TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3922
3923 switch (pHVDHalContext->u32HVDClockType)
3924 {
3925 case 384:
3926 {
3927 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3928 break;
3929 }
3930 case 345:
3931 {
3932 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3933 break;
3934 }
3935 case 320:
3936 {
3937 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3938 break;
3939 }
3940 case 288:
3941 {
3942 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3943 break;
3944 }
3945 case 240:
3946 {
3947 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_240MHZ, TOP_CKG_VP8_CLK_MASK);
3948 break;
3949 }
3950 case 216:
3951 {
3952 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3953 break;
3954 }
3955 case 172:
3956 {
3957 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_216MHZ, TOP_CKG_VP8_CLK_MASK);
3958 break;
3959 }
3960 default:
3961 {
3962 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_288MHZ, TOP_CKG_VP8_CLK_MASK);
3963 break;
3964 }
3965 }
3966 }
3967 else
3968 {
3969 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_DIS, TOP_CKG_VP8_DIS);
3970 }
3971
3972 }
3973
HAL_AEC_PowerCtrl(MS_BOOL bEnable)3974 static void HAL_AEC_PowerCtrl(MS_BOOL bEnable)
3975 {
3976 if (bEnable)
3977 {
3978 _HVD_WriteWordMask(REG_TOP_HVD_AEC, ~TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
3979
3980 switch (pHVDHalContext->u32HVDClockType)
3981 {
3982 case 384:
3983 {
3984 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3985 break;
3986 }
3987 case 345:
3988 {
3989 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3990 break;
3991 }
3992 case 320:
3993 {
3994 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
3995 break;
3996 }
3997 case 288:
3998 {
3999 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4000 break;
4001 }
4002 case 240:
4003 {
4004 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_240MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4005 break;
4006 }
4007 case 216:
4008 {
4009 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4010 break;
4011 }
4012 case 172:
4013 {
4014 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_216MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4015 break;
4016 }
4017 default:
4018 {
4019 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_288MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4020 break;
4021 }
4022 }
4023 }
4024 else
4025 {
4026 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_DIS, TOP_CKG_HVD_AEC_DIS);
4027 }
4028
4029 }
4030
HAL_HVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)4031 void HAL_HVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
4032 {
4033 if (bEnable)
4034 {
4035 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4036 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, ~TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4037 }
4038 else
4039 {
4040 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_DIS, TOP_CKG_HVD_DIS);
4041 //_HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_DIS, TOP_CKG_HVD_IDB_DIS);
4042 }
4043
4044 // fix to not inverse
4045 _HVD_WriteWordMask(REG_TOP_HVD, ~TOP_CKG_HVD_INV, TOP_CKG_HVD_INV);
4046
4047 switch (pHVDHalContext->u32HVDClockType)
4048 {
4049 #if 0 //for overclocking
4050 case 432:
4051 {
4052 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_432MHZ, TOP_CKG_HVD_CLK_MASK);
4053 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4054 _HVD_WriteWordMask(REG_TOP_HVD_AEC, TOP_CKG_HVD_AEC_320MHZ, TOP_CKG_HVD_AEC_CLK_MASK);
4055 _HVD_WriteWordMask(REG_TOP_VP8, TOP_CKG_VP8_320MHZ, TOP_CKG_VP8_CLK_MASK);
4056 break;
4057 }
4058 #endif
4059 case 384:
4060 {
4061 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4062 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4063 break;
4064 }
4065 case 345:
4066 {
4067 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_345MHZ, TOP_CKG_HVD_CLK_MASK);
4068 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_384MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4069 break;
4070 }
4071 case 320:
4072 {
4073 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_320MHZ, TOP_CKG_HVD_CLK_MASK);
4074 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_345MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4075 break;
4076 }
4077 case 288:
4078 {
4079 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_288MHZ, TOP_CKG_HVD_CLK_MASK);
4080 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_320MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4081 break;
4082 }
4083 case 240:
4084 {
4085 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_240MHZ, TOP_CKG_HVD_CLK_MASK);
4086 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_288MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4087 break;
4088 }
4089 case 216:
4090 {
4091 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_216MHZ, TOP_CKG_HVD_CLK_MASK);
4092 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_240MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4093 break;
4094 }
4095 case 172:
4096 {
4097 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_172MHZ, TOP_CKG_HVD_CLK_MASK);
4098 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_216MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4099 break;
4100 }
4101
4102 default:
4103 {
4104 _HVD_WriteWordMask(REG_TOP_HVD, TOP_CKG_HVD_384MHZ, TOP_CKG_HVD_CLK_MASK);
4105 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_432MHZ, TOP_CKG_HVD_IDB_CLK_MASK);
4106 break;
4107 }
4108 }
4109
4110 return;
4111 }
4112
HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)4113 void HAL_HVD_EX_InitRegBase(MS_VIRT u32RegBase)
4114 {
4115 u32HVDRegOSBase = u32RegBase;
4116 HAL_VPU_EX_InitRegBase(u32RegBase);
4117 }
4118
HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)4119 void HAL_HVD_EX_SetPreCtrlVariables(MS_U32 u32Id,MS_VIRT drvprectrl)
4120 {
4121 HVD_Pre_Ctrl *pHVDPreCtrl_in = (HVD_Pre_Ctrl*)drvprectrl;
4122 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4123 pHVDHalContext->pHVDPreCtrl_Hal[u8Idx] = pHVDPreCtrl_in;
4124 }
4125
HAL_HVD_EX_InitVariables(MS_U32 u32Id)4126 HVD_Return HAL_HVD_EX_InitVariables(MS_U32 u32Id)
4127 {
4128 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4129 HVD_ShareMem *pShm = NULL;
4130 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4131 #if HVD_ENABLE_MVC
4132 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4133 #endif ///HVD_ENABLE_MVC
4134
4135 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = 0;
4136 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = 0;
4137 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = 0;
4138 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
4139 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4140 pHVDHalContext->_stHVDStream[u8Idx].bfirstGetFrmInfoDone = TRUE;
4141 int i;
4142 for(i = 0; i<HAL_HVD_EX_MAX_SUPPORT_STREAM;i++)
4143 pHVDHalContext->_s32VDEC_BBU_TaskId[i] = -1;
4144 #if HVD_ENABLE_MVC
4145 if(bMVC)
4146 {
4147 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSPreWptr = 0;
4148 pHVDHalContext->_stHVDStream[u8Idx+1].u32PTSByteCnt = 0;
4149 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUWptr = 0;
4150 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = 0;
4151 }
4152 #endif ///HVD_ENABLE_MVC
4153
4154 // set a local copy of FW code address; assuming there is only one copy of FW,
4155 // no matter how many task will be created.
4156
4157 pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4158
4159 memset((void *) (pHVDHalContext->g_hvd_nal_fill_pair), 0, 16);
4160
4161 // global variables
4162 pHVDHalContext->u32HVDCmdTimeout = pCtrl->u32CmdTimeout;
4163
4164
4165 // pHVDHalContext->u32VPUClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4166 // pHVDHalContext->u32HVDClockType = (MS_U32) pCtrl->InitParams.u16DecoderClock;
4167 // Create mutex
4168 //_HAL_HVD_MutexCreate();
4169
4170 // fill HVD init variables
4171 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4172 {
4173 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = VP8_BBU_DRAM_TBL_ENTRY;
4174 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = VP8_BBU_DRAM_TBL_ENTRY_TH;
4175 }
4176 else
4177 #if HVD_ENABLE_RV_FEATURE
4178 if (((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4179 {
4180 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = RVD_BBU_DRAM_TBL_ENTRY;
4181 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = RVD_BBU_DRAM_TBL_ENTRY_TH;
4182 #ifdef VDEC3_FB
4183 pHVDHalContext->u32RV_VLCTableAddr = 0;
4184 #else
4185 if (pCtrl->MemMap.u32FrameBufSize > RV_VLC_TABLE_SIZE)
4186 {
4187 pHVDHalContext->u32RV_VLCTableAddr = pCtrl->MemMap.u32FrameBufSize - RV_VLC_TABLE_SIZE;
4188 pCtrl->MemMap.u32FrameBufSize -= RV_VLC_TABLE_SIZE;
4189 }
4190 else
4191 {
4192 HVD_EX_MSG_ERR("HAL_HVD_EX_InitVariables failed: frame buffer size too small. FB:%x min:%x\n",
4193 (MS_U32) pCtrl->MemMap.u32FrameBufSize, (MS_U32) RV_VLC_TABLE_SIZE);
4194 return E_HVD_RETURN_INVALID_PARAMETER;
4195 }
4196 #endif
4197 }
4198 else
4199 #endif
4200 {
4201 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum = HVD_BBU_DRAM_TBL_ENTRY;
4202 pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH = HVD_BBU_DRAM_TBL_ENTRY_TH;
4203 #if HVD_ENABLE_MVC
4204 if(bMVC)
4205 {
4206 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum = MVC_BBU_DRAM_TBL_ENTRY;
4207 pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNumTH = MVC_BBU_DRAM_TBL_ENTRY_TH;
4208 }
4209 #endif /// HVD_ENABLE_MVC
4210 pHVDHalContext->u32RV_VLCTableAddr = 0;
4211 }
4212
4213 if ((HAL_VPU_EX_GetShareInfoAddr(u32Id) != 0xFFFFFFFF)
4214 || ((MS_VIRT) (pCtrl->MemMap.u32CodeBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32CodeBufVAddr + pCtrl->MemMap.u32CodeBufSize)))
4215 || ((MS_VIRT) (pCtrl->MemMap.u32BitstreamBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->MemMap.u32BitstreamBufSize)))
4216 || ((MS_VIRT) (pCtrl->MemMap.u32FrameBufVAddr <= (MS_VIRT) pShm) && ((MS_VIRT) pShm <= (pCtrl->MemMap.u32FrameBufVAddr + pCtrl->MemMap.u32FrameBufSize))))
4217 {
4218 HVD_EX_MSG_DBG("input memory: Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4219 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4220 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4221 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4222 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4223 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4224 #if HVD_ENABLE_MVC
4225 if(bMVC)
4226 {
4227 HVD_EX_Drv_Ctrl *pHVDCtrl_in_sub = _HVD_EX_GetDrvCtrl(u32Id+0x00011000);
4228 if (( (pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr) <= (MS_VIRT)pShm)&& ( (MS_VIRT)pShm <= ((pHVDCtrl_in_sub->MemMap.u32BitstreamBufVAddr )+ pHVDCtrl_in_sub->MemMap.u32BitstreamBufSize)))
4229 {
4230 HVD_EX_MSG_DBG("[MVC] Bitstream2: 0x%lx.\n", (unsigned long) pCtrl->MemMap.u32BitstreamBufAddr);
4231 }
4232 }
4233 #endif /// HVD_ENABLE_MVC
4234
4235 return E_HVD_RETURN_SUCCESS;
4236 }
4237 else
4238 {
4239 HVD_EX_MSG_ERR("failed: Shm addr=0x%lx, Code addr=0x%lx, Bits addr=0x%lx, FB addr=0x%lx, Miu1base=0x%lx, Miu2base=0x%lx\n",
4240 (unsigned long)MS_VA2PA((MS_VIRT)pShm),
4241 (unsigned long)pCtrl->MemMap.u32CodeBufAddr,
4242 (unsigned long)pCtrl->MemMap.u32FrameBufAddr,
4243 (unsigned long)pCtrl->MemMap.u32BitstreamBufAddr,
4244 (unsigned long)pCtrl->MemMap.u32MIU1BaseAddr,
4245 (unsigned long)pCtrl->MemMap.u32MIU2BaseAddr);
4246 return E_HVD_RETURN_INVALID_PARAMETER;
4247 }
4248 }
4249
4250 #ifdef VDEC3
HAL_HVD_EX_InitShareMem(MS_U32 u32Id,MS_BOOL bFWdecideFB,MS_BOOL bCMAUsed)4251 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id, MS_BOOL bFWdecideFB, MS_BOOL bCMAUsed)
4252 #else
4253 HVD_Return HAL_HVD_EX_InitShareMem(MS_U32 u32Id)
4254 #endif
4255 {
4256 MS_U32 u32Addr = 0;
4257 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4258 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4259 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4260
4261 MS_U32 u32TmpStartOffset;
4262 MS_U8 u8TmpMiuSel;
4263
4264
4265 memset(pShm, 0, sizeof(HVD_ShareMem));
4266
4267 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pCtrl->MemMap.u32FrameBufAddr);
4268
4269 pShm->u32FrameRate = pCtrl->InitParams.u32FrameRate;
4270 pShm->u32FrameRateBase = pCtrl->InitParams.u32FrameRateBase;
4271 #ifdef VDEC3
4272 if (bFWdecideFB || bCMAUsed)
4273 {
4274 pShm->u32FrameBufAddr = 0;
4275 pShm->u32FrameBufSize = 0;
4276 }
4277 else
4278 #endif
4279 {
4280 pShm->u32FrameBufAddr = u32Addr;
4281 pShm->u32FrameBufSize = pCtrl->MemMap.u32FrameBufSize;
4282 }
4283
4284 // FIXME: need to use the avaliable task resource instead of using next task resource
4285 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
4286 pShm->u8ExternalHeapIdx = u8Idx + 1;
4287 else
4288 pShm->u8ExternalHeapIdx = 0xFF;
4289 pShm->DispInfo.u16DispWidth = 1;
4290 pShm->DispInfo.u16DispHeight = 1;
4291 pShm->u32CodecType = pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK;
4292 pShm->u32CPUClock = pHVDHalContext->u32VPUClockType;
4293 pShm->u32UserCCIdxWrtPtr = 0xFFFFFFFF;
4294 pShm->DispFrmInfo.u32TimeStamp = 0xFFFFFFFF;
4295 //Chip info
4296 pShm->u16ChipID = E_MSTAR_CHIP_MAXIM;
4297 pShm->u16ChipECONum = pCtrl->InitParams.u16ChipECONum;
4298 // PreSetControl
4299 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bOnePendingBuffer)
4300 {
4301 pShm->u32PreSetControl |= PRESET_ONE_PENDING_BUFFER;
4302 }
4303
4304 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bCalFrameRate)
4305 {
4306 pShm->u32PreSetControl |= PRESET_CAL_FRAMERATE;
4307 }
4308
4309 pShm->bUseTSPInBBUMode = FALSE;
4310
4311
4312 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.bEnable) &&
4313 ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_AVC))
4314 {
4315 pShm->u32PreSetControl |= PRESET_IAP_GN_SHARE_BW_MODE;
4316
4317 _phy_to_miu_offset(u8TmpMiuSel, u32Addr, pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufAddr);
4318
4319 pShm->u32IapGnBufAddr = u32Addr;
4320 pShm->u32IapGnBufSize = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stIapGnShBWMode.u32IapGnBufSize;
4321
4322 }
4323
4324 pShm->u8CodecFeature &= ~E_VDEC_MFCODEC_MASK;
4325 switch(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eMFCodecMode)
4326 {
4327 case E_HVD_DEF_MFCODEC_DEFAULT:
4328 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4329 break;
4330 case E_HVD_DEF_MFCODEC_FORCE_ENABLE:
4331 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_ENABLE;
4332 break;
4333 case E_HVD_DEF_MFCODEC_FORCE_DISABLE:
4334 pShm->u8CodecFeature |= E_VDEC_MFCODEC_FORCE_DISABLE;
4335 break;
4336 default:
4337 pShm->u8CodecFeature |= E_VDEC_MFCODEC_DEFAULT;
4338 }
4339
4340 pShm->u8CodecFeature &= ~E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4341 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bDVSingleLayerMode)
4342 pShm->u8CodecFeature |= E_VDEC_DOLBY_VISION_SINGLE_LAYER_MODE;
4343
4344 pShm->u8CodecFeature &= ~E_VDEC_FORCE_8BITS_MASK;
4345 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bForce8BitMode)
4346 pShm->u8CodecFeature |= E_VDEC_FORCE_8BITS_MODE;
4347 pShm->u8CodecFeature &= ~E_VDEC_FORCE_MAIN_PROFILE_MASK;
4348 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & 1)
4349 pShm->u8CodecFeature |= E_VDEC_FORCE_MAIN_PROFILE;
4350
4351 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.bEnable))
4352 {
4353 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4354
4355 pShm->stDynmcDispPath.u8Connect = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.bConnect;
4356 pShm->stDynmcDispPath.u8DispPath = (MS_U8)(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectDispPath.stDynmcDispPath.eMvopPath);
4357 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4358
4359 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, pShm->stDynmcDispPath.u8DispPath);
4360 }
4361 else
4362 {
4363 pShm->u32PreSetControl |= PRESET_CONNECT_DISPLAY_PATH;
4364
4365 MS_U8 u8Connect = FALSE;
4366 MS_U8 u8Path = E_CTL_DISPLAY_PATH_NONE;
4367 switch (pCtrl->eStream)
4368 {
4369 case E_HVD_ORIGINAL_MAIN_STREAM:
4370 u8Connect = TRUE;
4371 u8Path = E_CTL_DISPLAY_PATH_MVOP_0;
4372 break;
4373 case E_HVD_ORIGINAL_SUB_STREAM:
4374 u8Connect = TRUE;
4375 u8Path = E_CTL_DISPLAY_PATH_MVOP_1;
4376 break;
4377 case E_HVD_ORIGINAL_N_STREAM:
4378 default:
4379 u8Connect = FALSE;
4380 u8Path = E_CTL_DISPLAY_PATH_NONE;
4381 break;
4382 }
4383
4384 pShm->stDynmcDispPath.u8Connect = u8Connect;
4385 pShm->stDynmcDispPath.u8DispPath = u8Path;
4386 pShm->stDynmcDispPath.u8ConnectStatus = E_DISP_PATH_DYNMC_HANDLING;
4387
4388 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset mvop, connect %d, path 0x%x \n", u32Id, u8Idx, pShm->stDynmcDispPath.u8Connect, u8Path);
4389 }
4390
4391 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
4392 {
4393 if ((pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.bEnable))
4394 {
4395 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
4396 pShm->u8InputTSP = pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->stPreConnectInputTsp.u8InputTsp;
4397
4398 HVD_EX_MSG_DBG("[NDec][0x%x][%d] preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
4399 }
4400 else
4401 {
4402 pShm->u32PreSetControl |= PRESET_CONNECT_INPUT_TSP;
4403
4404 MS_U8 u8Input = E_CTL_INPUT_TSP_NONE;
4405 switch (pCtrl->eStream)
4406 {
4407 case E_HVD_ORIGINAL_MAIN_STREAM:
4408 u8Input = E_CTL_INPUT_TSP_0;
4409 break;
4410 case E_HVD_ORIGINAL_SUB_STREAM:
4411 u8Input = E_CTL_INPUT_TSP_1;
4412 break;
4413 case E_HVD_ORIGINAL_N_STREAM:
4414 default:
4415 u8Input = E_CTL_INPUT_TSP_NONE;
4416 break;
4417 }
4418
4419 pShm->u8InputTSP = u8Input;
4420
4421 HVD_EX_MSG_DBG("[NDec][0x%x][%d] no preset tsp, input %d \n", u32Id, u8Idx, pShm->u8InputTSP);
4422 }
4423 }
4424 else
4425 {
4426 HVD_EX_MSG_DBG("[NDec][0x%x][%d] not TSP input, ignore PRESET_CONNECT_INPUT_TSP \n", u32Id, u8Idx);
4427 }
4428
4429 //pShm->bColocateBBUMode = pCtrl->InitParams.bColocateBBUMode;//johnny.ko
4430 //pShm->bColocateBBUMode = _stHVDPreSet[u8Idx].bColocateBBUMode;//johnny.ko
4431 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4432 pShm->u8BBUMode = E_HVD_FW_AUTO_BBU_MODE;
4433 else
4434 pShm->u8BBUMode = E_HVD_DRV_AUTO_BBU_MODE;
4435 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_RAW)
4436 {
4437 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4438 {
4439 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE_DUAL_ES;
4440 }
4441 else
4442 {
4443 pShm->u8SrcMode = E_HVD_SRC_MODE_FILE;
4444 }
4445 }
4446 else if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_MAIN_MASK) == E_HVD_INIT_MAIN_FILE_TS)
4447 {
4448 if((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_DUAL_ES_MASK) == E_HVD_INIT_DUAL_ES_ENABLE)
4449 {
4450 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE_DUAL_ES;
4451 }
4452 else
4453 {
4454 pShm->u8SrcMode = E_HVD_SRC_MODE_TS_FILE;
4455 }
4456 }
4457 else
4458 {
4459 pShm->u8SrcMode = E_HVD_SRC_MODE_DTV;
4460 }
4461
4462 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4463 {
4464 pShm->bHVDIMIEnable = TRUE; //AVC FW enable IMI only for 4k2k
4465 }
4466
4467 #if 0
4468 if (pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->bEnableDynamicCMA)
4469 {
4470 pShm->u8CodecFeature |= E_VDEC_DYNAMIC_CMA_MODE;
4471 }
4472 #endif
4473
4474 if((E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4475 (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4476 (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4477 (E_HVD_INIT_HW_AVS == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4478 (E_HVD_INIT_HW_RM == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4479 (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4480 (E_HVD_INIT_HW_MJPEG== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4481 (E_HVD_INIT_HW_MVC== (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) ||
4482 (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)))
4483 {
4484 pShm->bUseWbMvop = 1;
4485 }
4486
4487 if (E_HVD_INIT_HW_HEVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)
4488 || E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4489 {
4490 if(!(pHVDHalContext->pHVDPreCtrl_Hal[u8Idx]->eVdecFeature & E_HVD_DEF_FEATURE_DISABLE_TEMPORAL_SCALABILITY))
4491 pShm->u8CodecFeature |= E_VDEC_TEMPORAL_SCALABILITY_MODE;
4492 }
4493
4494 #if 1//From T4 and the later chips, QDMA can support the address more than MIU1 base.
4495
4496 #if (VPU_FORCE_MIU_MODE)
4497 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4498
4499 pShm->u32FWBaseAddr = u32TmpStartOffset;
4500
4501 #else
4502 ///TODO:
4503 /*
4504 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, pCtrl->MemMap.u32CodeBufAddr);
4505
4506 if(u8TmpMiuSel == E_CHIP_MIU_0)
4507 {
4508 pShm->u32FWBaseAddr = pCtrl->MemMap.u32CodeBufAddr;
4509 }
4510 else if(u8TmpMiuSel == E_CHIP_MIU_1)
4511 {
4512 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x40000000; ///TODO:
4513 }
4514 else if(u8TmpMiuSel == E_CHIP_MIU_2)
4515 {
4516 pShm->u32FWBaseAddr = u32TmpStartOffset | 0x80000000; ///TODO:
4517 }
4518 */
4519 #endif
4520 //printf("<DBG>QDMA Addr = %lx <<<<<<<<<<<<<<<<<<<<<<<<\n",pShm->u32FWBaseAddr);
4521 #else
4522 u32Addr = pCtrl->MemMap.u32CodeBufAddr;
4523 if (u32Addr >= pCtrl->MemMap.u32MIU1BaseAddr)
4524 {
4525 u32Addr -= pCtrl->MemMap.u32MIU1BaseAddr;
4526 }
4527 pShm->u32FWBaseAddr = u32Addr;
4528 #endif
4529
4530 // RM only
4531 #if HVD_ENABLE_RV_FEATURE
4532 if ((((pCtrl->InitParams.u32ModeFlag) & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_RM)
4533 && (pCtrl->InitParams.pRVFileInfo != NULL))
4534 {
4535 MS_U32 i = 0;
4536
4537 for (i = 0; i < HVD_RM_INIT_PICTURE_SIZE_NUMBER; i++)
4538 {
4539 pShm->pRM_PictureSize[i].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[i];
4540 pShm->pRM_PictureSize[i].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[i];
4541 }
4542
4543 pShm->u8RM_Version = (MS_U8) pCtrl->InitParams.pRVFileInfo->RV_Version;
4544 pShm->u8RM_NumSizes = (MS_U8) pCtrl->InitParams.pRVFileInfo->ulNumSizes;
4545 #ifdef VDEC3_FB
4546 pShm->u32RM_VLCTableAddr = 0;
4547 // HVD_EX_MSG_DBG("===== Set pShm->u32RM_VLCTableAddr = 0 in InitShareMem\n");
4548 #else
4549 u32Addr = pCtrl->MemMap.u32FrameBufAddr + pHVDHalContext->u32RV_VLCTableAddr;
4550
4551 _phy_to_miu_offset(u8TmpMiuSel, u32TmpStartOffset, u32Addr);
4552 u32Addr = u32TmpStartOffset;
4553
4554 pShm->u32RM_VLCTableAddr = u32Addr;
4555 #endif
4556 }
4557 #endif
4558
4559 if ((E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4560 && (pCtrl->InitParams.pRVFileInfo != NULL))
4561 {
4562 pShm->pRM_PictureSize[0].u16Width = pCtrl->InitParams.pRVFileInfo->ulPicSizes_w[0];
4563 pShm->pRM_PictureSize[0].u16Height = pCtrl->InitParams.pRVFileInfo->ulPicSizes_h[0];
4564 }
4565
4566 //if(pCtrl->InitParams.bColocateBBUMode)
4567 if(_stHVDPreSet[u8Idx].bColocateBBUMode)
4568 {
4569 pShm->u32ColocateBBUWritePtr = pShm->u32ColocateBBUReadPtr = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
4570 }
4571
4572 #if SUPPORT_G2VP9
4573 // Enable SW detile support for G2 VP9
4574 if (E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
4575 {
4576 pShm->u8FrmPostProcSupport |= E_HVD_POST_PROC_DETILE;
4577 }
4578 #endif
4579
4580 HAL_HVD_EX_FlushMemory();
4581
4582 return E_HVD_RETURN_SUCCESS;
4583 }
4584 #ifdef VDEC3
HAL_HVD_EX_InitRegCPU(MS_U32 u32Id,MS_BOOL bFWdecideFB)4585 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id, MS_BOOL bFWdecideFB)
4586 #else
4587 HVD_Return HAL_HVD_EX_InitRegCPU(MS_U32 u32Id)
4588 #endif
4589 {
4590 MS_BOOL bInitRet = FALSE;
4591
4592 #if 0
4593 // check MVD power on
4594 if (_HVD_Read2Byte(REG_TOP_MVD) & (TOP_CKG_MHVD_DIS))
4595 {
4596 HVD_EX_MSG_INF("HVD warning: MVD is not power on before HVD init.\n");
4597 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
4598 HVD_Delay_ms(1);
4599 }
4600 // Check VPU power on
4601 if (_HVD_Read2Byte(REG_TOP_VPU) & (TOP_CKG_VPU_DIS))
4602 {
4603 HVD_EX_MSG_INF("HVD warning: VPU is not power on before HVD init.\n");
4604 _HVD_WriteWordMask(REG_TOP_VPU, 0, TOP_CKG_VPU_DIS);
4605 HVD_Delay_ms(1);
4606 }
4607 // check HVD power on
4608 if (_HVD_Read2Byte(REG_TOP_HVD) & (TOP_CKG_HVD_DIS))
4609 {
4610 HVD_EX_MSG_INF("HVD warning: HVD is not power on before HVD init.\n");
4611 HAL_HVD_EX_PowerCtrl(TRUE);
4612 HVD_Delay_ms(1);
4613 }
4614 #endif
4615 #ifdef VDEC3
4616 bInitRet = _HVD_EX_SetRegCPU(u32Id, bFWdecideFB);
4617 #else
4618 bInitRet = _HVD_EX_SetRegCPU(u32Id);
4619 #endif
4620 if (!bInitRet)
4621 {
4622 return E_HVD_RETURN_FAIL;
4623 }
4624
4625 bInitRet = HAL_HVD_EX_RstPTSCtrlVariable(u32Id);
4626
4627 if (!bInitRet)
4628 {
4629 return E_HVD_RETURN_FAIL;
4630 }
4631
4632 return E_HVD_RETURN_SUCCESS;
4633 }
4634
HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id,MS_BOOL bEnable)4635 HVD_Return HAL_HVD_EX_SetHVDColBBUMode(MS_U32 u32Id, MS_BOOL bEnable)
4636 {
4637 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4638
4639 _stHVDPreSet[u8Idx].bColocateBBUMode = bEnable;
4640
4641 return E_HVD_RETURN_SUCCESS;
4642 }
4643
HAL_HVD_EX_SetData(MS_U32 u32Id,HVD_SetData u32type,MS_VIRT u32Data)4644 HVD_Return HAL_HVD_EX_SetData(MS_U32 u32Id, HVD_SetData u32type, MS_VIRT u32Data)
4645 {
4646 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
4647 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4648 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4649 MS_BOOL bMVC = FALSE;
4650 #if HVD_ENABLE_MVC
4651 bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
4652 #endif
4653
4654 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
4655 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
4656
4657 switch (u32type)
4658 {
4659 // share memory
4660 // switch
4661 case E_HVD_SDATA_FRAMEBUF_ADDR:
4662 {
4663 pShm->u32FrameBufAddr = u32Data;
4664 break;
4665 }
4666 case E_HVD_SDATA_FRAMEBUF_SIZE:
4667 {
4668 pShm->u32FrameBufSize = u32Data;
4669 break;
4670 }
4671 case E_HVD_SDATA_FRAMEBUF2_ADDR:
4672 {
4673 pShm->u32FrameBuf2Addr = u32Data;
4674 break;
4675 }
4676 case E_HVD_SDATA_FRAMEBUF2_SIZE:
4677 {
4678 pShm->u32FrameBuf2Size = u32Data;
4679 break;
4680 }
4681 case E_HVD_SDATA_MAX_CMA_SIZE:
4682 {
4683 pShm->u32MaxCMAFrameBufSize = u32Data;
4684 break;
4685 }
4686 case E_HVD_SDATA_MAX_CMA_SIZE2:
4687 {
4688 pShm->u32MaxCMAFrameBuf2Size = u32Data;
4689 break;
4690 }
4691 case E_HVD_SDATA_CMA_USED:
4692 {
4693 pShm->bCMA_Use = u32Data;
4694 break;
4695 }
4696 case E_HVD_SDATA_CMA_ALLOC_DONE:
4697 {
4698 pShm->bCMA_AllocDone = u32Data;
4699 break;
4700 }
4701 case E_HVD_SDATA_CMA_TWO_MIU:
4702 {
4703 pShm->bCMA_TwoMIU = u32Data;
4704 break;
4705 }
4706 case E_HVD_SDATA_RM_PICTURE_SIZES:
4707 {
4708 HVD_memcpy((volatile void *) pShm->pRM_PictureSize, (void *) ((HVD_PictureSize *) u32Data),
4709 HVD_RM_INIT_PICTURE_SIZE_NUMBER * sizeof(HVD_PictureSize));
4710 break;
4711 }
4712 case E_HVD_SDATA_ERROR_CODE:
4713 {
4714 pShm->u16ErrCode = (MS_U16) u32Data;
4715 break;
4716 }
4717 case E_HVD_SDATA_DISP_INFO_TH:
4718 {
4719 HVD_memcpy((volatile void *) &(pShm->DispThreshold), (void *) ((HVD_DISP_THRESHOLD *) u32Data),
4720 sizeof(HVD_DISP_THRESHOLD));
4721 break;
4722 }
4723 case E_HVD_SDATA_FW_FLUSH_STATUS:
4724 {
4725 pShm->u8FlushStatus = (MS_U8)u32Data;
4726 break;
4727 }
4728 case E_HVD_SDATA_DMX_FRAMERATE:
4729 {
4730 pShm->u32DmxFrameRate = u32Data;
4731 break;
4732 }
4733 case E_HVD_SDATA_DMX_FRAMERATEBASE:
4734 {
4735 pShm->u32DmxFrameRateBase = u32Data;
4736 break;
4737 }
4738 case E_HVD_SDATA_MIU_SEL:
4739 {
4740 pShm->u32VDEC_MIU_SEL = u32Data;
4741 break;
4742 }
4743 case E_HVD_SDATA_DV_XC_SHM_SIZE:
4744 {
4745 pShm->u32DolbyVisionXCShmSize = u32Data;
4746 break;
4747 }
4748 // SRAM
4749
4750 // Mailbox
4751 case E_HVD_SDATA_TRIGGER_DISP: // HVD HI mbox 0
4752 {
4753 if (u32Data != 0)
4754 {
4755 pShm->bEnableDispCtrl = TRUE;
4756 pShm->bIsTrigDisp = TRUE;
4757 }
4758 else
4759 {
4760 pShm->bEnableDispCtrl = FALSE;
4761 }
4762
4763 break;
4764 }
4765 case E_HVD_SDATA_GET_DISP_INFO_START:
4766 {
4767 pShm->bSpsChange = FALSE;
4768 break;
4769 }
4770 case E_HVD_SDATA_VIRTUAL_BOX_WIDTH:
4771 {
4772 pShm->u32VirtualBoxWidth = u32Data;
4773 break;
4774 }
4775 case E_HVD_SDATA_DV_INFO:
4776 {
4777 pShm->u8DVLevelFromDriverAPI = (MS_U8)(u32Data & 0xff);
4778 pShm->u8DVProfileFromDriverAPI = (MS_U8)((u32Data >> 8) & 0xff);
4779 pShm->u8DolbyMetaReorder = (MS_U8)((u32Data >> 16) & 0xff);
4780 break;
4781 }
4782 case E_HVD_SDATA_VIRTUAL_BOX_HEIGHT:
4783 {
4784 pShm->u32VirtualBoxHeight = u32Data;
4785 break;
4786 }
4787 case E_HVD_SDATA_DISPQ_STATUS_VIEW:
4788 {
4789 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_INIT)
4790 {
4791 //printf("DispFrame DqPtr: %d\n", u32Data);
4792 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_VIEW;
4793 }
4794 break;
4795 }
4796 case E_HVD_SDATA_DISPQ_STATUS_DISP:
4797 {
4798 if(!(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide))
4799 {
4800 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4801 {
4802 //printf("DispFrame DqPtr: %ld\n", u32Data);
4803 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_DISP;
4804 }
4805 }
4806 break;
4807 }
4808 case E_HVD_SDATA_DISPQ_STATUS_FREE:
4809 {
4810 if(pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
4811 {
4812 if (bMVC || (bDolbyVision && !pShm->bSingleLayer))
4813 {
4814 if (pHVDHalContext->_stHVDStream[u8Idx].u32FreeData == 0xFFFF)
4815 {
4816 //ALOGE("R1: %x", u32Data);
4817 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = u32Data;
4818 }
4819 else
4820 {
4821 //ALOGE("R2: %x", (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4822 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData);
4823 //pShm->FreeQueue[pShm->u16FreeQWtPtr] = (u32Data << 16) | pHVDHalContext->_stHVDStream[u8Idx].u32FreeData;
4824 //pShm->u16FreeQWtPtr = (pShm->u16FreeQWtPtr + 1) % HVD_DISP_QUEUE_MAX_SIZE;
4825 pHVDHalContext->_stHVDStream[u8Idx].u32FreeData = 0xFFFF;
4826 }
4827 }
4828 else
4829 {
4830 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_RELEASE_DISPQ, u32Data);
4831 }
4832 }
4833 else
4834 {
4835 if (pShm->DispQueue[u32Data].u32Status == E_HVD_DISPQ_STATUS_VIEW)
4836 {
4837 pShm->DispQueue[u32Data].u32Status = E_HVD_DISPQ_STATUS_FREE;
4838 }
4839 }
4840 break;
4841 }
4842 case E_HVD_SDATA_HDR_PERFRAME:
4843 {
4844 if (u32Data != 0)
4845 {
4846 pShm->u8IsDoblyHDR10 = TRUE;
4847 }
4848 else
4849 {
4850 pShm->u8IsDoblyHDR10 = FALSE;
4851 }
4852 break;
4853 }
4854 #if (HVD_ENABLE_IQMEM)
4855 case E_HVD_SDATA_FW_IQMEM_CTRL:
4856 {
4857 pShm->u8IQmemCtrl= (MS_U8)u32Data;
4858 break;
4859
4860 }
4861 case E_HVD_SDATA_FW_IQMEM_ENABLE_IF_SUPPORT:
4862 {
4863 if (u32Data != 0)
4864 {
4865 pShm->bIQmemEnableIfSupport= TRUE;
4866 }
4867 else
4868 {
4869 pShm->bIQmemEnableIfSupport= FALSE;
4870 }
4871
4872
4873 break;
4874
4875 }
4876 #endif
4877 case E_HVD_SDATA_DYNMC_DISP_PATH_STATUS:
4878 {
4879 pShm->stDynmcDispPath.u8ConnectStatus = u32Data;
4880 break;
4881 }
4882 case E_HVD_SDATA_VP9HDR10INFO:
4883 {
4884 int i,j;
4885 HVD_Config_VP9HDR10* stVP9HDR10Info = (HVD_Config_VP9HDR10*) u32Data;
4886
4887 pShm->VP9HDR10Info.u32Version = stVP9HDR10Info->u32Version;
4888 pShm->VP9HDR10Info.u8MatrixCoefficients = stVP9HDR10Info->u8MatrixCoefficients;
4889 pShm->VP9HDR10Info.u8BitsPerChannel = stVP9HDR10Info->u8BitsPerChannel;
4890 pShm->VP9HDR10Info.u8ChromaSubsamplingHorz = stVP9HDR10Info->u8ChromaSubsamplingHorz;
4891 pShm->VP9HDR10Info.u8ChromaSubsamplingVert = stVP9HDR10Info->u8ChromaSubsamplingVert;
4892 pShm->VP9HDR10Info.u8CbSubsamplingHorz = stVP9HDR10Info->u8CbSubsamplingHorz;
4893 pShm->VP9HDR10Info.u8CbSubsamplingVert = stVP9HDR10Info->u8CbSubsamplingVert;
4894 pShm->VP9HDR10Info.u8ChromaSitingHorz = stVP9HDR10Info->u8ChromaSitingHorz;
4895 pShm->VP9HDR10Info.u8ChromaSitingVert = stVP9HDR10Info->u8ChromaSitingVert;
4896 pShm->VP9HDR10Info.u8ColorRange = stVP9HDR10Info->u8ColorRange;
4897 pShm->VP9HDR10Info.u8TransferCharacteristics = stVP9HDR10Info->u8TransferCharacteristics;
4898 pShm->VP9HDR10Info.u8ColourPrimaries = stVP9HDR10Info->u8ColourPrimaries;
4899 pShm->VP9HDR10Info.u16MaxCLL = stVP9HDR10Info->u16MaxCLL;
4900 pShm->VP9HDR10Info.u16MaxFALL = stVP9HDR10Info->u16MaxFALL;
4901 pShm->VP9HDR10Info.u32MaxLuminance = stVP9HDR10Info->u32MaxLuminance;
4902 pShm->VP9HDR10Info.u32MinLuminance = stVP9HDR10Info->u32MinLuminance;
4903
4904 for(i=0;i<2;i++)
4905 {
4906 pShm->VP9HDR10Info.u16WhitePoint[i] = stVP9HDR10Info->u16WhitePoint[i];
4907 }
4908
4909 for(i=0;i<3;i++)
4910 {
4911 for(j=0;j<2;j++)
4912 {
4913 pShm->VP9HDR10Info.u16Primaries[i][j] = stVP9HDR10Info->u16Primaries[i][j];
4914 }
4915 }
4916 pShm->u8VP9HDR10InfoVaild = TRUE;
4917 break;
4918 }
4919 default:
4920 break;
4921 }
4922
4923 HAL_HVD_EX_FlushMemory();
4924
4925 return eRet;
4926 }
4927
HAL_HVD_EX_GetData_EX(MS_U32 u32Id,HVD_GetData eType)4928 MS_S64 HAL_HVD_EX_GetData_EX(MS_U32 u32Id, HVD_GetData eType)
4929 {
4930 MS_S64 s64Ret = 0;
4931 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4932
4933 HAL_HVD_EX_ReadMemory();
4934
4935 switch (eType)
4936 {
4937 case E_HVD_GDATA_PTS_STC_DIFF:
4938 s64Ret = pShm->s64PtsStcDiff;
4939 break;
4940 default:
4941 break;
4942 }
4943
4944 return s64Ret;
4945 }
4946
HAL_HVD_EX_GetData(MS_U32 u32Id,HVD_GetData eType)4947 MS_VIRT HAL_HVD_EX_GetData(MS_U32 u32Id, HVD_GetData eType)
4948 {
4949 MS_VIRT u32Ret = 0;
4950 //static MS_U64 u64pts_real = 0;
4951 MS_U64 u64pts_low = 0;
4952 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
4953 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
4954
4955 HAL_HVD_EX_ReadMemory();
4956
4957 if(pShm == NULL)
4958 {
4959 printf("########## VDEC patch for Debug ###########\n");
4960 return 0x0;
4961 }
4962
4963 switch (eType)
4964 {
4965 // share memory
4966 // switch
4967 case E_HVD_GDATA_DISP_INFO_ADDR:
4968 {
4969 u32Ret = (MS_VIRT) (&pShm->DispInfo);
4970 break;
4971 }
4972 case E_HVD_GDATA_MIU_SEL:
4973 u32Ret = pShm->u32VDEC_MIU_SEL;
4974 break;
4975 case E_HVD_GDATA_FRAMEBUF_ADDR:
4976 u32Ret = pShm->u32FrameBufAddr;
4977 break;
4978 case E_HVD_GDATA_FRAMEBUF_SIZE:
4979 u32Ret = pShm->u32FrameBufSize;
4980 break;
4981 case E_HVD_GDATA_FRAMEBUF2_ADDR:
4982 u32Ret = pShm->u32FrameBuf2Addr;
4983 break;
4984 case E_HVD_GDATA_FRAMEBUF2_SIZE:
4985 u32Ret = pShm->u32FrameBuf2Size;
4986 break;
4987 case E_HVD_GDATA_CMA_ALLOC_DONE:
4988 u32Ret = pShm->bCMA_AllocDone;
4989 break;
4990 case E_HVD_GDATA_CMA_USED:
4991 u32Ret = pShm->bCMA_Use;
4992 break;
4993 case E_HVD_GDATA_DYNMC_DISP_PATH_STATUS:
4994 u32Ret = pShm->stDynmcDispPath.u8ConnectStatus;//pShm->u8SetDynmcDispPathStatus;
4995 break;
4996 // report
4997 case E_HVD_GDATA_PTS:
4998 {
4999 u32Ret = pShm->DispFrmInfo.u32TimeStamp;
5000 break;
5001 }
5002 case E_HVD_GDATA_U64PTS:
5003 {
5004 u64pts_low = (MS_U64)(pShm->DispFrmInfo.u32TimeStamp);
5005 pHVDHalContext->u64pts_real = (MS_U64)(pShm->DispFrmInfo.u32ID_H);
5006 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
5007 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
5008 break;
5009 }
5010 case E_HVD_GDATA_U64PTS_PRE_PARSE:
5011 {
5012 u64pts_low = (MS_U64)(pShm->u32WRPTR_PTS_LOW);
5013 pHVDHalContext->u64pts_real = (MS_U64)(pShm->u32WRPTR_PTS_HIGH);
5014 pHVDHalContext->u64pts_real = (pHVDHalContext->u64pts_real<<32)|u64pts_low;
5015 u32Ret = (MS_VIRT)(&(pHVDHalContext->u64pts_real));
5016 break;
5017 }
5018 case E_HVD_GDATA_DECODE_CNT:
5019 {
5020 u32Ret = pShm->u32DecodeCnt;
5021 break;
5022 }
5023 case E_HVD_GDATA_DATA_ERROR_CNT:
5024 {
5025 u32Ret = pShm->u32DataErrCnt;
5026 break;
5027 }
5028 case E_HVD_GDATA_DEC_ERROR_CNT:
5029 {
5030 u32Ret = pShm->u32DecErrCnt;
5031 break;
5032 }
5033 case E_HVD_GDATA_ERROR_CODE:
5034 {
5035 u32Ret = (MS_U32) (pShm->u16ErrCode);
5036 break;
5037 }
5038 case E_HVD_GDATA_VPU_IDLE_CNT:
5039 {
5040 u32Ret = pShm->u32VPUIdleCnt;
5041 break;
5042 }
5043 case E_HVD_GDATA_DISP_FRM_INFO:
5044 {
5045 u32Ret = (MS_VIRT) (&pShm->DispFrmInfo);
5046 break;
5047 }
5048 case E_HVD_GDATA_DEC_FRM_INFO:
5049 {
5050 u32Ret = (MS_VIRT) (&pShm->DecoFrmInfo);
5051 break;
5052 }
5053 case E_HVD_GDATA_ES_LEVEL:
5054 {
5055 u32Ret = (MS_U32) (_HVD_EX_GetESLevel(u32Id));
5056 break;
5057 }
5058 #if HVD_ENABLE_MVC
5059 case E_HVD_GDATA_DISP_FRM_INFO_SUB:
5060 {
5061 u32Ret= (MS_VIRT) (&(pShm->DispFrmInfo_Sub));
5062 break;
5063 }
5064 case E_HVD_GDATA_DEC_FRM_INFO_SUB:
5065 {
5066 u32Ret= (MS_VIRT) (&(pShm->DecoFrmInfo_Sub));
5067 break;
5068 }
5069 #endif
5070
5071 // user data
5072 case E_HVD_GDATA_USERDATA_WPTR:
5073 {
5074 u32Ret = (MS_U32) (pShm->u32UserCCIdxWrtPtr);
5075 break;
5076 }
5077 case E_HVD_GDATA_USERDATA_IDX_TBL_ADDR:
5078 {
5079 u32Ret = (MS_VIRT) (pShm->u8UserCCIdx);
5080 break;
5081 }
5082 case E_HVD_GDATA_USERDATA_PACKET_TBL_ADDR:
5083 {
5084 u32Ret = (MS_VIRT) (pShm->u32UserCCBase);
5085 break;
5086 }
5087 case E_HVD_GDATA_USERDATA_PACKET_SIZE:
5088 {
5089 u32Ret = (MS_U32) (sizeof(DTV_BUF_type));
5090 break;
5091 }
5092 case E_HVD_GDATA_USERDATA_IDX_TBL_SIZE:
5093 {
5094 u32Ret = (MS_U32) (USER_CC_IDX_SIZE);
5095 break;
5096 }
5097 case E_HVD_GDATA_USERDATA_PACKET_TBL_SIZE:
5098 {
5099 u32Ret = (MS_U32) (USER_CC_DATA_SIZE);
5100 break;
5101 }
5102 // report - modes
5103 case E_HVD_GDATA_IS_SHOW_ERR_FRM:
5104 {
5105 u32Ret = pShm->ModeStatus.bIsShowErrFrm;
5106 break;
5107 }
5108 case E_HVD_GDATA_IS_REPEAT_LAST_FIELD:
5109 {
5110 u32Ret = pShm->ModeStatus.bIsRepeatLastField;
5111 break;
5112 }
5113 case E_HVD_GDATA_IS_ERR_CONCEAL:
5114 {
5115 u32Ret = pShm->ModeStatus.bIsErrConceal;
5116 break;
5117 }
5118 case E_HVD_GDATA_IS_SYNC_ON:
5119 {
5120 u32Ret = pShm->ModeStatus.bIsSyncOn;
5121 break;
5122 }
5123 case E_HVD_GDATA_IS_PLAYBACK_FINISH:
5124 {
5125 u32Ret = pShm->ModeStatus.bIsPlaybackFinish;
5126 break;
5127 }
5128 case E_HVD_GDATA_SYNC_MODE:
5129 {
5130 u32Ret = pShm->ModeStatus.u8SyncType;
5131 break;
5132 }
5133 case E_HVD_GDATA_SKIP_MODE:
5134 {
5135 u32Ret = pShm->ModeStatus.u8SkipMode;
5136 break;
5137 }
5138 case E_HVD_GDATA_DROP_MODE:
5139 {
5140 u32Ret = pShm->ModeStatus.u8DropMode;
5141 break;
5142 }
5143 case E_HVD_GDATA_DISPLAY_DURATION:
5144 {
5145 u32Ret = pShm->ModeStatus.s8DisplaySpeed;
5146 break;
5147 }
5148 case E_HVD_GDATA_FRC_MODE:
5149 {
5150 u32Ret = pShm->ModeStatus.u8FrcMode;
5151 break;
5152 }
5153 case E_HVD_GDATA_NEXT_PTS:
5154 {
5155 u32Ret = pShm->u32NextPTS;
5156 break;
5157 }
5158 case E_HVD_GDATA_DISP_Q_SIZE:
5159 {
5160 u32Ret = pShm->u16DispQSize;
5161 break;
5162 }
5163 case E_HVD_GDATA_DISP_Q_PTR:
5164 {
5165 u32Ret = (MS_U32) pHVDHalContext->_u16DispQPtr;
5166 break;
5167 }
5168 case E_HVD_GDATA_NEXT_DISP_FRM_INFO:
5169 {
5170 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrame(u32Id);
5171 break;
5172 }
5173 case E_HVD_GDATA_NEXT_DISP_FRM_INFO_EXT:
5174 {
5175 u32Ret = (MS_VIRT) _HVD_EX_GetNextDispFrameExt(u32Id);
5176 break;
5177 }
5178 case E_HVD_GDATA_REAL_FRAMERATE:
5179 {
5180 // return VPS/VUI timing info framerate, and 0 if timing info not exist
5181 u32Ret = pShm->u32RealFrameRate;
5182 break;
5183 }
5184 case E_HVD_GDATA_IS_ORI_INTERLACE_MODE:
5185 u32Ret=(MS_U32)pShm->DispInfo.u8IsOriginInterlace;
5186 break;
5187 case E_HVD_GDATA_FRM_PACKING_SEI_DATA:
5188 u32Ret=((MS_VIRT)(pShm->u32Frm_packing_arr_data_addr));
5189 break;
5190 case E_HVD_GDATA_DISPLAY_COLOUR_VOLUME_SEI_DATA:
5191 u32Ret=((MS_U32)(pShm->u32DisplayColourVolume_addr));
5192 break;
5193 case E_HVD_GDATA_CONTENT_LIGHT_LEVEL_INFO:
5194 u32Ret=((MS_U32)(pShm->u32ContentLightLevel_addr));
5195 break;
5196 case E_HVD_GDATA_TYPE_FRAME_MBS_ONLY_FLAG:
5197 u32Ret=((MS_U32)(pShm->u8FrameMbsOnlyFlag));
5198 break;
5199 case E_HVD_GDATA_FW_STATUS_FLAG:
5200 u32Ret=((MS_U32)(pShm->u32FWStatusFlag));
5201 break;
5202
5203 // internal control
5204 case E_HVD_GDATA_IS_1ST_FRM_RDY:
5205 {
5206 u32Ret = pShm->bIs1stFrameRdy;
5207 break;
5208 }
5209 case E_HVD_GDATA_IS_I_FRM_FOUND:
5210 {
5211 u32Ret = pShm->bIsIFrmFound;
5212 break;
5213 }
5214 case E_HVD_GDATA_IS_SYNC_START:
5215 {
5216 u32Ret = pShm->bIsSyncStart;
5217 break;
5218 }
5219 case E_HVD_GDATA_IS_SYNC_REACH:
5220 {
5221 u32Ret = pShm->bIsSyncReach;
5222 break;
5223 }
5224 case E_HVD_GDATA_FW_VERSION_ID:
5225 {
5226 u32Ret = pShm->u32FWVersionID;
5227 break;
5228 }
5229 case E_HVD_GDATA_FW_IF_VERSION_ID:
5230 {
5231 u32Ret = pShm->u32FWIfVersionID;
5232 break;
5233 }
5234 case E_HVD_GDATA_BBU_Q_NUMB:
5235 {
5236 u32Ret = _HVD_EX_GetBBUQNumb(u32Id);
5237 break;
5238 }
5239 case E_HVD_GDATA_DEC_Q_NUMB:
5240 {
5241 u32Ret = pShm->u16DecQNumb;
5242 break;
5243 }
5244 case E_HVD_GDATA_DISP_Q_NUMB:
5245 {
5246 u32Ret = pShm->u16DispQNumb;
5247 break;
5248 }
5249 case E_HVD_GDATA_PTS_Q_NUMB:
5250 {
5251 u32Ret = _HVD_EX_GetPTSQNumb(u32Id);
5252 break;
5253 }
5254 case E_HVD_GDATA_FW_INIT_DONE:
5255 {
5256 u32Ret = pShm->bInitDone;
5257 break;
5258 }
5259 // debug
5260 case E_HVD_GDATA_SKIP_CNT:
5261 {
5262 u32Ret = pShm->u32SkipCnt;
5263 break;
5264 }
5265 case E_HVD_GDATA_GOP_CNT:
5266 {
5267 u32Ret = pShm->u32DropCnt;
5268 break;
5269 }
5270 case E_HVD_GDATA_DISP_CNT:
5271 {
5272 u32Ret = pShm->u32DispCnt;
5273 break;
5274 }
5275 case E_HVD_GDATA_DROP_CNT:
5276 {
5277 u32Ret = pShm->u32DropCnt;
5278 break;
5279 }
5280 case E_HVD_GDATA_DISP_STC:
5281 {
5282 u32Ret = pShm->u32DispSTC;
5283 break;
5284 }
5285 case E_HVD_GDATA_VSYNC_CNT:
5286 {
5287 u32Ret = pShm->u32VsyncCnt;
5288 break;
5289 }
5290 case E_HVD_GDATA_MAIN_LOOP_CNT:
5291 {
5292 u32Ret = pShm->u32MainLoopCnt;
5293 break;
5294 }
5295
5296 // AVC
5297 case E_HVD_GDATA_AVC_LEVEL_IDC:
5298 {
5299 u32Ret = pShm->u16AVC_SPS_LevelIDC;
5300 break;
5301 }
5302 case E_HVD_GDATA_AVC_LOW_DELAY:
5303 {
5304 u32Ret = pShm->u8AVC_SPS_LowDelayHrdFlag;
5305 break;
5306 }
5307 case E_HVD_GDATA_AVC_VUI_DISP_INFO:
5308 {
5309 u32Ret = _HVD_EX_GetVUIDispInfo(u32Id);
5310 break;
5311 }
5312 case E_HVD_GDATA_FW_FLUSH_STATUS:
5313 {
5314 u32Ret = (MS_U32) (pShm->u8FlushStatus);
5315 break;
5316 }
5317 case E_HVD_GDATA_FW_CODEC_TYPE:
5318 {
5319 u32Ret = pShm->u32CodecType;
5320 break;
5321 }
5322 case E_HVD_GDATA_FW_ES_BUF_STATUS:
5323 {
5324 u32Ret = (MS_U32)pShm->u8ESBufStatus;
5325 break;
5326 }
5327 case E_HVD_GDATA_VIDEO_FULL_RANGE_FLAG:
5328 {
5329 if(pShm->u32CodecMiscInfo & E_VIDEO_FULL_RANGE)
5330 {
5331 u32Ret = 1;
5332 }
5333 else
5334 {
5335 u32Ret = 0;
5336 }
5337 break;
5338 }
5339
5340 // SRAM
5341
5342 // Mailbox
5343 case E_HVD_GDATA_FW_STATE: // HVD RISC MBOX 0 (esp. FW init done)
5344 {
5345 u32Ret = pShm->u32FwState;
5346 break;
5347 }
5348 case E_HVD_GDATA_IS_DISP_INFO_UNCOPYED:
5349 {
5350 u32Ret = pShm->bSpsChange;
5351 break;
5352 }
5353 case E_HVD_GDATA_IS_DISP_INFO_CHANGE: // HVD RISC MBOX 1 (rdy only)
5354 {
5355 u32Ret = pShm->bSpsChange;
5356
5357 if (pShm->bSpsChange &&
5358 !(pShm->u8FrmPostProcSupport & E_HVD_POST_PROC_DETILE) &&
5359 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)].s32HvdPpTaskId))
5360 {
5361 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[_HVD_EX_GetStreamIdx(u32Id)]);
5362 }
5363
5364 break;
5365 }
5366 case E_HVD_GDATA_HVD_ISR_STATUS: // HVD RISC MBOX 1 (value only)
5367 {
5368 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5369
5370 if ((pCtrl->HVDISRCtrl.u32IntCount != pShm->u32IntCount) && pShm->u32FwInfo) // fetch ISR status
5371 {
5372 u32Ret = pShm->u32FwInfo;
5373 pCtrl->HVDISRCtrl.u32IntCount = pShm->u32IntCount;
5374 }
5375 break;
5376 }
5377 case E_HVD_GDATA_IS_FRAME_SHOWED: // HVD HI mbox 0 ( showed: rdy cleared ; not show: rdy enable )
5378 {
5379 if (pShm->bIsTrigDisp) // not clear yet
5380 {
5381 u32Ret = FALSE;
5382 }
5383 else
5384 {
5385 u32Ret = TRUE;
5386 }
5387 break;
5388 }
5389 case E_HVD_GDATA_ES_READ_PTR:
5390 {
5391 u32Ret = _HVD_EX_GetESReadPtr(u32Id, FALSE);
5392 break;
5393 }
5394 case E_HVD_GDATA_ES_WRITE_PTR:
5395 {
5396 u32Ret = _HVD_EX_GetESWritePtr(u32Id);
5397 break;
5398 }
5399 case E_HVD_GDATA_BBU_READ_PTR:
5400 {
5401 u32Ret = _HVD_EX_GetBBUReadptr(u32Id);
5402 break;
5403 }
5404 case E_HVD_GDATA_BBU_WRITE_PTR:
5405 {
5406 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5407 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5408 {
5409 u32Ret = pHVDHalContext->u32VP8BBUWptr;
5410 }
5411 else
5412 {
5413 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
5414 }
5415 break;
5416 }
5417 case E_HVD_GDATA_BBU_WRITE_PTR_FIRED:
5418 {
5419 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5420
5421 u32Ret = pCtrl->u32BBUWptr_Fired;
5422
5423 break;
5424 }
5425 case E_HVD_GDATA_VPU_PC_CNT:
5426 {
5427 u32Ret = _HVD_EX_GetPC();
5428 break;
5429 }
5430 case E_HVD_GDATA_ES_QUANTITY:
5431 {
5432 u32Ret=_HVD_EX_GetESQuantity(u32Id);
5433 break;
5434 }
5435
5436
5437 // FW def
5438 case E_HVD_GDATA_FW_MAX_DUMMY_FIFO: // AVC: 256Bytes AVS: 2kB RM:???
5439 u32Ret = HVD_MAX3(HVD_FW_AVC_DUMMY_FIFO, HVD_FW_AVS_DUMMY_FIFO, HVD_FW_RM_DUMMY_FIFO);
5440 break;
5441
5442 case E_HVD_GDATA_FW_AVC_MAX_VIDEO_DELAY:
5443 u32Ret = HVD_FW_AVC_MAX_VIDEO_DELAY;
5444 break;
5445 case E_HVD_GDATA_FW_BBU_TOTAL_TBL_ENTRY:
5446 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNumTH;
5447 break;
5448 case E_HVD_GDATA_FW_BBU_TBL_ENTRY_NUMB:
5449 u32Ret = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
5450 break;
5451 case E_HVD_GDATA_FW_PTS_TOTAL_ENTRY_NUMB:
5452 u32Ret = MAX_PTS_TABLE_SIZE;
5453 break;
5454 case E_HVD_GDATA_FW_DUMMY_WRITE_ADDR:
5455 u32Ret = (MS_VIRT) pShm->u32HVD_DUMMY_WRITE_ADDR;
5456 break;
5457 case E_HVD_GDATA_FW_DS_BUF_ADDR:
5458 u32Ret = (MS_VIRT) pShm->u32HVD_DYNAMIC_SCALING_ADDR;
5459 break;
5460 case E_HVD_GDATA_FW_DS_BUF_SIZE:
5461 u32Ret = pShm->u32DSBuffSize; //3k or 6k
5462 break;
5463 case E_HVD_GDATA_FW_DS_VECTOR_DEPTH:
5464 u32Ret = pShm->u8DSBufferDepth; //16 or 24 or 32
5465 break;
5466 case E_HVD_GDATA_FW_DS_INFO_ADDR:
5467 u32Ret = (MS_VIRT) pShm->u32HVD_SCALER_INFO_ADDR;
5468 break;
5469 case E_HVD_GDATA_FW_DS_IS_ENABLED:
5470 {
5471 if (pShm->bDSIsRunning)
5472 {
5473 u32Ret = TRUE;
5474 }
5475 else
5476 {
5477 u32Ret = FALSE;
5478 }
5479 break;
5480 }
5481 #if (HVD_ENABLE_IQMEM)
5482 case E_HVD_GDATA_FW_IQMEM_CTRL:
5483 {
5484
5485 u32Ret = (MS_U32)pShm->u8IQmemCtrl;
5486
5487 break;
5488 }
5489 case E_HVD_GDATA_FW_IS_IQMEM_SUPPORT:
5490 {
5491 if(pShm->bIsIQMEMSupport){
5492 u32Ret = TRUE;
5493 }
5494 else{
5495
5496 u32Ret = FALSE;
5497 }
5498
5499 break;
5500 }
5501 #endif
5502 case E_HVD_GDATA_TYPE_IS_LEAST_DISPQ_SIZE:
5503 u32Ret = ((MS_U32)(pShm->bIsLeastDispQSize));
5504 break;
5505 case E_HVD_GDATA_FIELD_PIC_FLAG:
5506 u32Ret = ((MS_U32)(pShm->u8FieldPicFlag));
5507 break;
5508 case E_HVD_GDATA_TS_SEAMLESS_STATUS:
5509 u32Ret = pShm->u32SeamlessTSStatus;
5510 break;
5511 case E_HVD_GDATA_HVD_HW_MAX_PIXEL:
5512 u32Ret = (MS_U32)(_HAL_EX_GetHwMaxPixel(u32Id)/1000);
5513 break;
5514 #ifdef VDEC3
5515 case E_HVD_GDATA_FW_VBBU_ADDR:
5516 u32Ret = (MS_VIRT) pShm->u32HVD_VBBU_DRAM_ST_ADDR;
5517 break;
5518 #endif
5519 case E_HVD_GDATA_SEQ_CHANGE_INFO:
5520 u32Ret = (MS_U32)pShm->u32SeqChangeInfo;
5521 break;
5522 default:
5523 break;
5524 }
5525 return u32Ret;
5526 }
5527
HAL_HVD_EX_GetDVSupportProfiles(void)5528 MS_U32 HAL_HVD_EX_GetDVSupportProfiles(void)
5529 {
5530 #if 0 // wait avc finish DV dual job
5531 return E_DV_STREAM_PROFILE_ID_DVAV_PER | E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5532 #else
5533 return E_DV_STREAM_PROFILE_ID_DVHE_DER | E_DV_STREAM_PROFILE_ID_DVHE_DTR | E_DV_STREAM_PROFILE_ID_DVHE_STN | E_DV_STREAM_PROFILE_ID_DVHE_DTH;
5534 #endif
5535 }
5536
HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)5537 MS_U32 HAL_HVD_EX_GetDVSupportHighestLevel(MS_U32 u32DV_Stream_Profile)
5538 {
5539 switch (u32DV_Stream_Profile)
5540 {
5541 #if 0 // wait avc finish DV dual job
5542 case E_DV_STREAM_PROFILE_ID_DVAV_PER:
5543 return E_DV_STREAM_LEVEL_ID_UHD24;// level 6
5544 #endif
5545
5546 #if 0 // unsupported profile
5547 case E_DV_STREAM_PROFILE_ID_DVAV_PEN:
5548 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5549 #endif
5550
5551 case E_DV_STREAM_PROFILE_ID_DVHE_DER:
5552 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5553
5554 #if 0 // unsupported profile
5555 case E_DV_STREAM_PROFILE_ID_DVHE_DEN:
5556 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5557 #endif
5558
5559 case E_DV_STREAM_PROFILE_ID_DVHE_DTR:
5560 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5561
5562 case E_DV_STREAM_PROFILE_ID_DVHE_STN:
5563 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5564
5565 case E_DV_STREAM_PROFILE_ID_DVHE_DTH:
5566 return E_DV_STREAM_LEVEL_ID_UHD60;// level 9
5567
5568 case E_DV_STREAM_PROFILE_ID_UNSUPPORTED:
5569 default:
5570 return E_DV_STREAM_LEVEL_ID_UNSUPPORTED;
5571 }
5572 }
5573
HAL_HVD_EX_SetCmd(MS_U32 u32Id,HVD_User_Cmd eUsrCmd,MS_U32 u32CmdArg)5574 HVD_Return HAL_HVD_EX_SetCmd(MS_U32 u32Id, HVD_User_Cmd eUsrCmd, MS_U32 u32CmdArg)
5575 {
5576 HVD_Return eRet = E_HVD_RETURN_SUCCESS;
5577 MS_U32 u32Cmd = (MS_U32) eUsrCmd;
5578 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5579 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5580 {
5581 // skip mutex
5582 }
5583 else
5584 {
5585 _HAL_HVD_Entry();
5586 }
5587 // check if old SVD cmds
5588 if (u32Cmd < E_HVD_CMD_SVD_BASE)
5589 {
5590 HVD_EX_MSG_ERR("Old SVD FW cmd(%x %x) used in HVD.\n", u32Cmd, u32CmdArg);
5591
5592 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5593 {
5594 return E_HVD_RETURN_INVALID_PARAMETER;
5595 }
5596 else
5597 {
5598 _HAL_HVD_Return(E_HVD_RETURN_INVALID_PARAMETER);
5599 }
5600 }
5601
5602 if (u32Cmd == E_HVD_CMD_ENABLE_DISP_OUTSIDE)
5603 {
5604 pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide = (MS_BOOL)u32CmdArg;
5605 }
5606
5607 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
5608 {
5609 if (u32Cmd == E_HVD_CMD_FLUSH)
5610 pHVDHalContext->_stHVDStream[u8Idx].u32DispQIndex = 0;
5611 }
5612
5613 if (u32Cmd == E_HVD_CMD_FLUSH &&
5614 IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId) &&
5615 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState == E_HAL_HVD_STATE_RUNNING)
5616 {
5617 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_PAUSING;
5618 while (pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState != E_HAL_HVD_STATE_PAUSE_DONE)
5619 {
5620 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5621 {
5622 HVD_Delay_ms(1);
5623 }
5624 else
5625 {
5626 _HAL_HVD_Release();
5627 HVD_Delay_ms(1);
5628 _HAL_HVD_Entry();
5629 }
5630 }
5631 }
5632
5633 HVD_EX_MSG_DBG("cmd=0x%x, arg=0x%x\n", u32Cmd, u32CmdArg);
5634
5635 eRet = _HVD_EX_SendCmd(u32Id, u32Cmd, u32CmdArg);
5636 if (pHVDHalContext->_stHVDStream[u8Idx].u32CodecType == E_HAL_HVD_HEVC_DV)
5637 {
5638 return eRet;
5639 }
5640 else
5641 {
5642 _HAL_HVD_Return(eRet);
5643 }
5644 }
5645
HAL_HVD_EX_DeInit(MS_U32 u32Id)5646 HVD_Return HAL_HVD_EX_DeInit(MS_U32 u32Id)
5647 {
5648 HVD_Return eRet = E_HVD_RETURN_FAIL;
5649 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5650 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5651 MS_U32 u32Timeout = HVD_GetSysTime_ms() + 3000;
5652 MS_U8 u8MiuSel;
5653 MS_U32 u32StartOffset;
5654 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
5655
5656 #if HVD_ENABLE_TIME_MEASURE
5657 MS_U32 ExitTimeCnt = 0;
5658 ExitTimeCnt = HVD_GetSysTime_ms();
5659 #endif
5660
5661 pCtrl->MemMap.u32CodeBufVAddr = MS_PA2KSEG1((MS_PHY)pCtrl->MemMap.u32CodeBufAddr);
5662
5663 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_PAUSE, 0);
5664
5665 if (E_HVD_RETURN_SUCCESS != eRet)
5666 {
5667 HVD_EX_MSG_ERR("HVD fail to PAUSE %d\n", eRet);
5668 }
5669
5670 eRet = HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_STOP, 0);
5671
5672 if (E_HVD_RETURN_SUCCESS != eRet)
5673 {
5674 HVD_EX_MSG_ERR("HVD fail to STOP %d\n", eRet);
5675 }
5676
5677 // check FW state to make sure it's STOP DONE
5678 while (E_HVD_FW_STOP_DONE != (HVD_FW_State) HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_FW_STATE))
5679 {
5680 if (HVD_GetSysTime_ms() > u32Timeout)
5681 {
5682 HVD_EX_MSG_ERR("FW stop timeout, pc = 0x%x\n", HAL_VPU_EX_GetProgCnt());
5683
5684 //return E_HVD_RETURN_TIMEOUT;
5685 eRet = E_HVD_RETURN_TIMEOUT;
5686 break;
5687 }
5688 }
5689
5690 if (pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt)
5691 {
5692 HVD_EX_MSG_INF("VDEC PLUS: DropRatio %d, Drop:0.%d (%d), Dec:0.%d (%d), Disp:0.%d\n",
5693 pShm->u8VdecPlusDropRatio,
5694 100*pShm->u32VdecPlusDropCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5695 pShm->u32VdecPlusDropCnt,
5696 100*pShm->u32VdecPlusDecCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt),
5697 pShm->u32VdecPlusDecCnt,
5698 100*pShm->u32VdecPlusDispPicCnt/(pShm->u32VdecPlusDecCnt+pShm->u32VdecPlusDropCnt));
5699 }
5700 else
5701 {
5702 HVD_EX_MSG_INF("VDEC PLUS DISABLE: DropRatio %d, Drop: %d, Dec: %d, Disp: %d\n",
5703 pShm->u8VdecPlusDropRatio,
5704 pShm->u32VdecPlusDropCnt,
5705 pShm->u32VdecPlusDecCnt,
5706 pShm->u32VdecPlusDispPicCnt);
5707 }
5708
5709 VPU_EX_FWCodeCfg fwCfg;
5710 VPU_EX_TaskInfo taskInfo;
5711 VPU_EX_NDecInitPara nDecInitPara;
5712
5713 nDecInitPara.pFWCodeCfg = &fwCfg;
5714 nDecInitPara.pTaskInfo = &taskInfo;
5715
5716 fwCfg.u32DstAddr = pCtrl->MemMap.u32CodeBufVAddr;
5717 fwCfg.u8SrcType = E_HVD_FW_INPUT_SOURCE_NONE;
5718
5719 HAL_HVD_EX_GetTaskInfo(u32Id,&taskInfo);//power control
5720 #if 0
5721 taskInfo.u32Id = u32Id;
5722 taskInfo.eDecType = E_VPU_EX_DECODER_HVD;
5723 taskInfo.eVpuId = (HAL_VPU_StreamId) (0xFF & u32Id);
5724 #endif
5725
5726 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5727 {
5728 taskInfo.eSrcType = E_VPU_EX_INPUT_FILE;
5729 }
5730 else
5731 {
5732 taskInfo.eSrcType = E_VPU_EX_INPUT_TSP;
5733 }
5734
5735 if(HAL_VPU_EX_TaskDelete(u32Id, &nDecInitPara) != TRUE)
5736 {
5737 HVD_EX_MSG_ERR("HAL_VPU_EX_TaskDelete fail\n");
5738 }
5739
5740 /* clear es buffer */
5741 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_TSP)
5742 {
5743 //printf("Clear ES buffer\n");
5744
5745 memset((void *) pCtrl->MemMap.u32BitstreamBufVAddr, 0, MIN(128, pCtrl->MemMap.u32BitstreamBufSize));
5746 }
5747
5748 //_HAL_HVD_MutexDelete();
5749
5750 #if HVD_ENABLE_TIME_MEASURE
5751 HVD_EX_MSG_DBG("HVD Stop Time(Wait FW):%d\n", HVD_GetSysTime_ms() - ExitTimeCnt);
5752 #endif
5753
5754 pHVDHalContext->_stHVDStream[u8Idx].bUsed = FALSE;
5755 #ifndef VDEC3
5756 // reset bbu wptr
5757 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
5758 {
5759 if(TRUE == HAL_VPU_EX_HVDInUsed())
5760 {
5761 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))//apple
5762 {
5763 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5764 pHVDHalContext->u32VP8BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5765 }
5766 else
5767 {
5768 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5769 {
5770 _HVD_EX_SetBBUWriteptr(u32Id, _HVD_EX_GetBBUReadptr(u32Id));
5771 }
5772 pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr = _HVD_EX_GetBBUReadptr(u32Id);
5773 }
5774 }
5775 else
5776 {
5777 pHVDHalContext->_stHVDStream[0].u32BBUWptr = 0; //main
5778 pHVDHalContext->_stHVDStream[1].u32BBUWptr = 0; //sub
5779 pHVDHalContext->u32VP8BBUWptr = 0; //VP8
5780 if (E_HVD_INIT_HW_AVC == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5781 {
5782 if(!_stHVDPreSet[u8Idx].bColocateBBUMode)
5783 {
5784 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5785 }
5786 }
5787 else
5788 {
5789 _HVD_EX_ResetMainSubBBUWptr(u32Id);
5790 }
5791 }
5792 }
5793 #endif
5794 _stHVDPreSet[u8Idx].bColocateBBUMode = FALSE;
5795
5796 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
5797 {
5798 _HVD_EX_PpTask_Delete(&pHVDHalContext->_stHVDStream[u8Idx]);
5799 }
5800
5801 if(pHVDHalContext->pHVDPreCtrl_Hal[_HVD_EX_GetStreamIdx(u32Id)]->stIapGnShBWMode.bEnable)
5802 {
5803
5804 _phy_to_miu_offset(u8MiuSel, u32StartOffset, pCtrl->MemMap.u32FrameBufAddr);
5805
5806 _HAL_HVD_Entry();
5807 HAL_HVD_MIF1_MiuClientSel(u8MiuSel);
5808 _HAL_HVD_Release();
5809
5810 }
5811
5812 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = 0;
5813 HVD_EX_MSG_DBG("success\n");
5814
5815 return eRet;
5816 }
5817
HAL_HVD_EX_PushPacket(MS_U32 u32Id,HVD_BBU_Info * pInfo)5818 HVD_Return HAL_HVD_EX_PushPacket(MS_U32 u32Id, HVD_BBU_Info *pInfo)
5819 {
5820 HVD_Return eRet = E_HVD_RETURN_UNSUPPORTED;
5821 MS_U32 u32Addr = 0;
5822 HVD_EX_Drv_Ctrl *pCtrl = NULL;
5823 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5824
5825 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
5826
5827 //if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8 PTS table is not ready yet
5828 {
5829 eRet = _HVD_EX_UpdatePTSTable(u32Id, pInfo);
5830
5831 if (E_HVD_RETURN_SUCCESS != eRet)
5832 {
5833 return eRet;
5834 }
5835 }
5836
5837 //printf(">>> halHVD pts,idH = %lu, %lu\n", pInfo->u32TimeStamp, pInfo->u32ID_H); //STS input
5838
5839 //T9: for 128 bit memory. BBU need to get 2 entry at a time.
5840 if (E_HVD_INIT_HW_VP8 != (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5841 {
5842 eRet = _HVD_EX_UpdateESWptr(u32Id, 0, 0);
5843
5844 if (E_HVD_RETURN_SUCCESS != eRet)
5845 {
5846 return eRet;
5847 }
5848 }
5849
5850 u32Addr = pInfo->u32Staddr;
5851
5852 if (pInfo->bRVBrokenPacket)
5853 {
5854 u32Addr = pInfo->u32Staddr | BIT(HVD_RV_BROKENBYUS_BIT);
5855 }
5856
5857 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK)) // VP8
5858 {
5859 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, pInfo->u32Length, pInfo->u32Staddr2, pInfo->u32Length2);
5860 }
5861 else
5862 {
5863 eRet = _HVD_EX_UpdateESWptr(u32Id, u32Addr, pInfo->u32Length);
5864 }
5865
5866 if (E_HVD_RETURN_SUCCESS != eRet)
5867 {
5868 return eRet;
5869 }
5870
5871 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
5872 {
5873 //eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, 0, 0, 0, 0);
5874 eRet = _HVD_EX_UpdateESWptr_VP8(u32Id, pInfo->u32Staddr, 0, pInfo->u32Staddr2, 0);
5875
5876 if (E_HVD_RETURN_SUCCESS != eRet)
5877 {
5878 return eRet;
5879 }
5880 }
5881
5882 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt += pInfo->u32Length;
5883
5884 // do not add local pointer
5885 if ((pCtrl->MemMap.u32DrvProcessBufSize != 0) && (pCtrl->MemMap.u32DrvProcessBufAddr != 0))
5886 {
5887 MS_U32 u32PacketStAddr = pInfo->u32Staddr + pCtrl->MemMap.u32BitstreamBufAddr;
5888
5889 if (!((pCtrl->MemMap.u32DrvProcessBufAddr <= u32PacketStAddr) &&
5890 (u32PacketStAddr <
5891 (pCtrl->MemMap.u32DrvProcessBufAddr + pCtrl->MemMap.u32DrvProcessBufSize))))
5892 {
5893 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5894 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5895 }
5896 else
5897 {
5898 //null packet
5899 pCtrl->LastNal.u32NalAddr = pInfo->u32OriPktAddr;
5900 pCtrl->LastNal.u32NalSize = 0;
5901 }
5902 }
5903 else
5904 {
5905 pCtrl->LastNal.u32NalAddr = pInfo->u32Staddr;
5906 pCtrl->LastNal.u32NalSize = pInfo->u32AllocLength;
5907 }
5908
5909 pCtrl->LastNal.bRVBrokenPacket = pInfo->bRVBrokenPacket;
5910 pCtrl->u32BBUPacketCnt++;
5911
5912 return eRet;
5913 }
5914
HAL_HVD_EX_EnableISR(MS_U32 u32Id,MS_BOOL bEnable)5915 void HAL_HVD_EX_EnableISR(MS_U32 u32Id, MS_BOOL bEnable)
5916 {
5917 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5918 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5919 MS_BOOL bCurrentStatus = HAL_HVD_EX_IsEnableISR(u32Id);
5920 if(bCurrentStatus == bEnable)
5921 return;
5922
5923 if (bEnable)
5924 {
5925 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_MSK);
5926 }
5927 else
5928 {
5929 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_MSK, HVD_REG_RISC_ISR_MSK);
5930 }
5931 }
5932
HAL_HVD_EX_SetForceISR(MS_U32 u32Id,MS_BOOL bEnable)5933 void HAL_HVD_EX_SetForceISR(MS_U32 u32Id, MS_BOOL bEnable)
5934 {
5935 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5936 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5937
5938 if (bEnable)
5939 {
5940 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_FORCE, HVD_REG_RISC_ISR_FORCE);
5941 }
5942 else
5943 {
5944 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), 0, HVD_REG_RISC_ISR_FORCE);
5945 }
5946 }
5947
HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)5948 void HAL_HVD_EX_SetClearISR(HWDEC_ISR_TYPE eISRType)
5949 {
5950 MS_U32 u32RB = 0;
5951 switch(eISRType)
5952 {
5953 case E_HWDEC_ISR_HVD:
5954 u32RB = REG_HVD_BASE;
5955 break;
5956 #if SUPPORT_EVD
5957 case E_HWDEC_ISR_EVD:
5958 u32RB = REG_EVD_BASE;
5959 break;
5960 #endif
5961 #if SUPPORT_G2VP9
5962 case E_HWDEC_ISR_G2VP9:
5963 break;
5964 #endif
5965 default:
5966 break;
5967 }
5968 if(u32RB)
5969 {
5970 _HVD_WriteWordMask(HVD_REG_RISC_MBOX_CLR(u32RB), HVD_REG_RISC_ISR_CLR, HVD_REG_RISC_ISR_CLR);
5971 }
5972 }
5973
HAL_HVD_EX_IsISROccured(MS_U32 u32Id)5974 MS_BOOL HAL_HVD_EX_IsISROccured(MS_U32 u32Id)
5975 {
5976 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5977 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5978
5979 return (MS_BOOL) (_HVD_Read2Byte(HVD_REG_RISC_MBOX_RDY(u32RB)) & HVD_REG_RISC_ISR_VALID);
5980 }
5981
HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)5982 MS_BOOL HAL_HVD_EX_IsEnableISR(MS_U32 u32Id)
5983 {
5984 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
5985 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
5986
5987 if (_HVD_Read2Byte(HVD_REG_RISC_MBOX_CLR(u32RB)) & HVD_REG_RISC_ISR_MSK)
5988 {
5989 return FALSE;
5990 }
5991 else
5992 {
5993 return TRUE;
5994 }
5995 }
5996
HAL_HVD_EX_IsAlive(MS_U32 u32Id)5997 MS_BOOL HAL_HVD_EX_IsAlive(MS_U32 u32Id)
5998 {
5999 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6000
6001 if (pCtrl)
6002 {
6003 if ((pCtrl->LivingStatus.u32DecCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_DECODE_CNT)) &&
6004 (pCtrl->LivingStatus.u32SkipCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_SKIP_CNT)) &&
6005 (pCtrl->LivingStatus.u32IdleCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_VPU_IDLE_CNT)) &&
6006 (pCtrl->LivingStatus.u32MainLoopCnt == HAL_HVD_EX_GetData(u32Id, E_HVD_GDATA_MAIN_LOOP_CNT)))
6007 {
6008 return FALSE;
6009 }
6010 else
6011 {
6012 return TRUE;
6013 }
6014 }
6015 else
6016 {
6017 return FALSE;
6018 }
6019 }
6020
HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)6021 MS_BOOL HAL_HVD_EX_RstPTSCtrlVariable(MS_U32 u32Id)
6022 {
6023 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6024 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6025 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6026
6027 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_INPUT_MASK) == E_HVD_INIT_INPUT_DRV)
6028 {
6029 HAL_HVD_EX_ReadMemory();
6030
6031 pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt = pShm->u32PTStableByteCnt;
6032 pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr = _HVD_EX_GetPTSTableWptr(u32Id);
6033
6034 HVD_EX_MSG_DBG("PTS table: WptrAddr:%x RptrAddr:%x ByteCnt:%x PreWptr:%lx\n",
6035 pShm->u32PTStableWptrAddr, pShm->u32PTStableRptrAddr, pHVDHalContext->_stHVDStream[u8Idx].u32PTSByteCnt, (unsigned long)pHVDHalContext->_stHVDStream[u8Idx].u32PTSPreWptr);
6036 }
6037
6038 return TRUE;
6039 }
6040
HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)6041 MS_BOOL HAL_HVD_EX_FlushRstShareMem(MS_U32 u32Id)
6042 {
6043 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6044 HVD_EX_Drv_Ctrl *pCtrl = NULL;
6045 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6046 MS_U32 u32Data;
6047 pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6048
6049 memset(&pShm->DecoFrmInfo, 0, sizeof(HVD_Frm_Information));
6050
6051 HAL_HVD_EX_FlushMemory();
6052 if (pHVDHalContext->_stHVDStream[u8Idx].bDispOutSide)
6053 {
6054 u32Data = _HVD_EX_GetESReadPtr(u32Id, FALSE);
6055 pCtrl->LastNal.u32NalAddr = u32Data;
6056 pCtrl->LastNal.u32NalSize = 0;
6057 }
6058
6059 if (IS_TASK_ALIVE(pHVDHalContext->_stHVDStream[u8Idx].s32HvdPpTaskId))
6060 pHVDHalContext->_stHVDStream[u8Idx].ePpTaskState = E_HAL_HVD_STATE_RUNNING;
6061
6062 return TRUE;
6063 }
6064
HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)6065 void HAL_HVD_EX_UartSwitch2FW(MS_BOOL bEnable)
6066 {
6067 if (bEnable)
6068 {
6069 if (HAL_VPU_EX_IsEVDR2())
6070 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6071 else
6072 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_VD_MHEG5, REG_TOP_UART_SEL_0_MASK);
6073 }
6074 else
6075 {
6076 #if defined (__aeon__)
6077 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_MHEG5, REG_TOP_UART_SEL_0_MASK);
6078 #else // defined (__mips__)
6079 _HVD_WriteWordMask(REG_TOP_UART_SEL0, REG_TOP_UART_SEL_PIU_0, REG_TOP_UART_SEL_0_MASK);
6080 #endif
6081 }
6082 }
6083
HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)6084 MS_U32 HAL_HVD_EX_GetData_Dbg(MS_U32 u32Addr)
6085 {
6086 return 0;
6087 }
6088
HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr,MS_U32 u32Data)6089 void HAL_HVD_EX_SetData_Dbg(MS_U32 u32Addr, MS_U32 u32Data)
6090 {
6091 return;
6092 }
6093
HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)6094 MS_U16 HAL_HVD_EX_GetCorretClock(MS_U16 u16Clock)
6095 {
6096 //if( u16Clock == 0 )
6097 return 216; //140;
6098 //if( )
6099 }
6100
HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)6101 void HAL_HVD_EX_UpdateESWptr_Fire(MS_U32 u32Id)
6102 {
6103 //MS_BOOL bBitMIU1 = FALSE;
6104 //MS_BOOL bCodeMIU1 = FALSE;
6105 MS_U8 u8BitMiuSel = 0;
6106 MS_U8 u8CodeMiuSel = 0;
6107 MS_U32 u32BitStartOffset;
6108 MS_U32 u32CodeStartOffset;
6109 //MS_U8 u8MiuSel;
6110 //MS_U32 u32StartOffset;
6111 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6112 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6113 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6114 MS_VIRT u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR;
6115
6116 #if HVD_ENABLE_MVC
6117 if(HAL_HVD_EX_CheckMVCID(u32Id))
6118 {
6119 // if MVC_BBU_ADDR and HVD_BBU_ADDR are different, we need to add MVC_BBU_DRAM_ST_ADDR and MVC_BBU2_DRAM_ST_ADDR in share memory
6120 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU_DRAM_ST_ADDR; //pShm->u32MVC_BBU_DRAM_ST_ADDR;
6121 if(E_VDEC_EX_SUB_VIEW == HAL_HVD_EX_GetView(u32Id))
6122 {
6123 u32BBU_DRAM_ST_ADDR = (MS_VIRT) pShm->u32HVD_BBU2_DRAM_ST_ADDR; //pShm->u32MVC_BBU2_DRAM_ST_ADDR;
6124 }
6125 }
6126 #endif /// HVD_ENABLE_MVC
6127
6128 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6129 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6130
6131
6132
6133
6134 if (u8BitMiuSel != u8CodeMiuSel)
6135 {
6136 #if HVD_ENABLE_BDMA_2_BITSTREAMBUF
6137 BDMA_Result bdmaRlt;
6138 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6139
6140 u32DstAdd = pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6141 u32SrcAdd = pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR;
6142 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6143
6144 bdmaRlt = HVD_dmacpy(u32DstAdd, u32SrcAdd, u32tabsize);
6145
6146 if (E_BDMA_OK != bdmaRlt)
6147 {
6148 HVD_EX_MSG_ERR("MDrv_BDMA_MemCopy fail ret=%x!\n", bdmaRlt);
6149 }
6150 #else
6151 MS_VIRT u32DstAdd = 0, u32SrcAdd = 0, u32tabsize = 0;
6152
6153 u32DstAdd = pCtrl->MemMap.u32BitstreamBufVAddr + pCtrl->u32BBUTblInBitstreamBufAddr;
6154 u32SrcAdd = MsOS_PA2KSEG1(pCtrl->MemMap.u32CodeBufAddr + u32BBU_DRAM_ST_ADDR);
6155 u32tabsize = pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum << 3;
6156
6157 HVD_memcpy(u32DstAdd, u32SrcAdd, u32tabsize);
6158 #endif
6159 }
6160
6161 //HVD_EX_MSG_DBG("%lu st:%lx size:%lx BBU: %lu\n", pCtrl->u32BBUPacketCnt, pCtrl->LastNal.u32NalAddr, pCtrl->LastNal.u32NalSize, _stHVDStream[u8Idx].u32BBUWptr);
6162
6163 HAL_HVD_EX_FlushMemory();
6164
6165 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6166 {
6167 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->u32VP8BBUWptr));
6168 pCtrl->u32BBUWptr_Fired = pHVDHalContext->u32VP8BBUWptr;
6169 }
6170 else
6171 {
6172 _HVD_EX_SetBBUWriteptr(u32Id, HVD_LWORD(pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr));
6173
6174 pCtrl->u32BBUWptr_Fired = pHVDHalContext->_stHVDStream[u8Idx].u32BBUWptr;
6175 }
6176 }
6177
HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)6178 void HAL_HVD_EX_MVD_PowerCtrl(MS_BOOL bEnable)
6179 {
6180 if (bEnable)
6181 {
6182 _HVD_WriteWordMask(REG_TOP_MVD, 0, TOP_CKG_MHVD_DIS);
6183 _HVD_WriteWordMask(REG_TOP_MVD2, 0, TOP_CKG_MHVD2_DIS);
6184 }
6185 else
6186 {
6187 _HVD_WriteWordMask(REG_TOP_MVD, TOP_CKG_MHVD_DIS, TOP_CKG_MHVD_DIS);
6188 _HVD_WriteWordMask(REG_TOP_MVD2, TOP_CKG_MHVD2_DIS, TOP_CKG_MHVD2_DIS);
6189 }
6190 }
6191
HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)6192 void HAL_HVD_EX_Dump_FW_Status(MS_U32 u32Id)
6193 {
6194 MS_U32 tmp1 = 0;
6195 MS_U32 tmp2 = 0;
6196 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6197
6198 HAL_HVD_EX_ReadMemory();
6199
6200 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_MBOX, &tmp1);
6201 _HVD_EX_MBoxRead(u32Id, HAL_HVD_CMD_ARG_MBOX, &tmp2);
6202
6203 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6204 {
6205 MS_U32 u32Tmp = u32UartCtrl;
6206
6207 HVD_EX_MSG_DBG("\n");
6208 u32UartCtrl = 0; // turn off debug message to prevent other function prints
6209 printf("\tSystime=%u, FWVersionID=0x%x, FwState=0x%x, ErrCode=0x%x, ProgCnt=0x%x\n",
6210 HVD_GetSysTime_ms(), pShm->u32FWVersionID, pShm->u32FwState, (MS_U32) pShm->u16ErrCode, HAL_VPU_EX_GetProgCnt());
6211
6212 printf("\tTime: DispSTC=%u, DispT=%u, DecT=%u, CurrentPts=%u, Last Cmd=0x%x, Arg=0x%x, Rdy1=0x%x, Rdy2=0x%x\n",
6213 pShm->u32DispSTC, pShm->DispFrmInfo.u32TimeStamp,
6214 pShm->DecoFrmInfo.u32TimeStamp, pShm->u32CurrentPts, tmp1, tmp2,
6215 (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_MBOX), (MS_U32) _HVD_EX_MBoxReady(u32Id, HAL_HVD_CMD_ARG_MBOX));
6216
6217 printf("\tFlag: InitDone=%d, SpsChange=%d, IsIFrmFound=%d, 1stFrmRdy=%d, SyncStart=%d, SyncReach=%d\n",
6218 pShm->bInitDone, pShm->bSpsChange, pShm->bIsIFrmFound,
6219 pShm->bIs1stFrameRdy, pShm->bIsSyncStart, pShm->bIsSyncReach);
6220
6221 printf("\tQueue: BBUQNumb=%u, DecQNumb=%d, DispQNumb=%d, ESR=%u, ESRfromFW=%u, ESW=%u, ESLevel=%u\n",
6222 _HVD_EX_GetBBUQNumb(u32Id), pShm->u16DecQNumb, pShm->u16DispQNumb,
6223 _HVD_EX_GetESReadPtr(u32Id, TRUE), pShm->u32ESReadPtr, _HVD_EX_GetESWritePtr(u32Id),
6224 _HVD_EX_GetESLevel(u32Id));
6225
6226 printf("\tCounter: DecodeCnt=%u, DispCnt=%u, DataErrCnt=%u, DecErrCnt=%u, SkipCnt=%u, DropCnt=%u, idle=%u, MainLoopCnt=%u, VsyncCnt=%u\n",
6227 pShm->u32DecodeCnt, pShm->u32DispCnt, pShm->u32DataErrCnt,
6228 pShm->u32DecErrCnt, pShm->u32SkipCnt, pShm->u32DropCnt,
6229 pShm->u32VPUIdleCnt, pShm->u32MainLoopCnt, pShm->u32VsyncCnt);
6230 printf
6231 ("\tMode: ShowErr=%d, RepLastField=%d, SyncOn=%d, FileEnd=%d, Skip=%d, Drop=%d, DispSpeed=%d, FRC=%d, BlueScreen=%d, FreezeImg=%d, 1Field=%d\n",
6232 pShm->ModeStatus.bIsShowErrFrm, pShm->ModeStatus.bIsRepeatLastField,
6233 pShm->ModeStatus.bIsSyncOn, pShm->ModeStatus.bIsPlaybackFinish,
6234 pShm->ModeStatus.u8SkipMode, pShm->ModeStatus.u8DropMode,
6235 pShm->ModeStatus.s8DisplaySpeed, pShm->ModeStatus.u8FrcMode,
6236 pShm->ModeStatus.bIsBlueScreen, pShm->ModeStatus.bIsFreezeImg,
6237 pShm->ModeStatus.bShowOneField);
6238
6239 u32UartCtrl = u32Tmp; // recover debug level
6240 }
6241 }
6242
HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32Idx,MS_U32 * u32NalOffset,MS_U32 * u32NalSize)6243 void HAL_HVD_EX_GetBBUEntry(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32Idx, MS_U32 *u32NalOffset, MS_U32 *u32NalSize)
6244 {
6245 MS_U8 *u32Addr = NULL;
6246 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6247 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6248
6249 if (u32Idx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6250 {
6251 return;
6252 }
6253
6254 u32Addr = (MS_U8 *)(MsOS_PA2KSEG1(pDrvCtrl->MemMap.u32CodeBufAddr + (MS_PHY)pShm->u32HVD_BBU_DRAM_ST_ADDR + (u32Idx << 3)));
6255
6256 *u32NalSize = *(u32Addr + 2) & 0x1f;
6257 *u32NalSize <<= 8;
6258 *u32NalSize |= *(u32Addr + 1) & 0xff;
6259 *u32NalSize <<= 8;
6260 *u32NalSize |= *(u32Addr) & 0xff;
6261
6262 *u32NalOffset = ((MS_U32) (*(u32Addr + 2) & 0xe0)) >> 5;
6263 *u32NalOffset |= ((MS_U32) (*(u32Addr + 3) & 0xff)) << 3;
6264 *u32NalOffset |= ((MS_U32) (*(u32Addr + 4) & 0xff)) << 11;
6265 *u32NalOffset |= ((MS_U32) (*(u32Addr + 5) & 0xff)) << 19;
6266 }
6267
HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id,HVD_EX_Drv_Ctrl * pDrvCtrl,MS_U32 u32StartIdx,MS_U32 u32EndIdx,MS_BOOL bShowEmptyEntry)6268 void HAL_HVD_EX_Dump_BBUs(MS_U32 u32Id, HVD_EX_Drv_Ctrl *pDrvCtrl, MS_U32 u32StartIdx, MS_U32 u32EndIdx, MS_BOOL bShowEmptyEntry)
6269 {
6270 MS_U32 u32CurIdx = 0;
6271 MS_BOOL bFinished = FALSE;
6272 MS_U32 u32NalOffset = 0;
6273 MS_U32 u32NalSize = 0;
6274 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6275
6276 if ((u32StartIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum) || (u32EndIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum))
6277 {
6278 return;
6279 }
6280
6281 u32CurIdx = u32StartIdx;
6282
6283 do
6284 {
6285 if (u32CurIdx == u32EndIdx)
6286 {
6287 bFinished = TRUE;
6288 }
6289
6290 HAL_HVD_EX_GetBBUEntry(u32Id, pDrvCtrl, u32CurIdx, &u32NalOffset, &u32NalSize);
6291
6292 if ((bShowEmptyEntry == FALSE) || (bShowEmptyEntry && (u32NalOffset == 0) && (u32NalSize == 0)))
6293 {
6294 HVD_EX_MSG_DBG("HVD BBU Entry: Idx:%u Offset:%x Size:%x\n", u32CurIdx, u32NalOffset, u32NalSize);
6295 }
6296
6297 u32CurIdx++;
6298
6299 if (u32CurIdx >= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum)
6300 {
6301 u32CurIdx %= pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum;
6302 }
6303 } while (bFinished == TRUE);
6304 }
6305
HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)6306 void HAL_HVD_EX_Dump_HW_Status(MS_U32 u32Num)
6307 {
6308 MS_U32 i = 0;
6309 MS_U32 value = 0;
6310
6311 if (u32UartCtrl & E_HVD_UART_CTRL_DBG)
6312 {
6313 HVD_EX_MSG_DBG("\n");
6314
6315 for (i = 0; i <= u32Num; i++)
6316 {
6317 _HVD_Write2Byte(HVD_REG_DEBUG_SEL, i);
6318 value = _HVD_Read2Byte(HVD_REG_DEBUG_DAT_L);
6319 value |= ((MS_U32) _HVD_Read2Byte(HVD_REG_DEBUG_DAT_H)) << 16;
6320
6321 if (value == 0)
6322 {
6323 break;
6324 }
6325
6326 printf(" %08x", value);
6327
6328 if (((i % 8) + 1) == 8)
6329 {
6330 printf(" |%u\n", i + 1);
6331 }
6332 }
6333
6334 printf("\nHVD Dump HW status End: total number:%u\n", i);
6335 }
6336 }
6337
HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl * pDrvCtrl,HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)6338 void HAL_HVD_EX_SetMiuBurstLevel(HVD_EX_Drv_Ctrl *pDrvCtrl, HVD_MIU_Burst_Cnt_Ctrl eMiuBurstCntCtrl)
6339 {
6340 if (pDrvCtrl)
6341 {
6342 pDrvCtrl->Settings.u32MiuBurstLevel = (MS_U32) eMiuBurstCntCtrl;
6343 }
6344 }
6345
6346 #if HVD_ENABLE_MVC
HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)6347 MS_BOOL HAL_HVD_EX_CheckMVCID(MS_U32 u32Id)
6348 {
6349 return ( E_HAL_VPU_MVC_STREAM_BASE == (0xFF & u32Id) );
6350 }
6351
HAL_HVD_EX_GetView(MS_U32 u32Id)6352 VDEC_EX_View HAL_HVD_EX_GetView(MS_U32 u32Id)
6353 {
6354 if( (0xFF & (u32Id >> 8)) == 0x10)
6355 return E_VDEC_EX_MAIN_VIEW;
6356 else
6357 return E_VDEC_EX_SUB_VIEW;
6358 }
6359 #endif ///HVD_ENABLE_MVC
6360
HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id)6361 void HAL_HVD_EX_SpareBandwidth(MS_U32 u32Id) //// For MVC
6362 {
6363 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_QUART_PIXEL, TRUE);
6364 //HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_DIS_DBF, TRUE);
6365 return;
6366 }
6367
HAL_HVD_EX_PowerSaving(MS_U32 u32Id)6368 void HAL_HVD_EX_PowerSaving(MS_U32 u32Id) //// turn on power saving mode for STB chips, ex. clippers, kano
6369 {
6370 HAL_HVD_EX_SetCmd(u32Id, E_HVD_CMD_POWER_SAVING, TRUE);
6371 return;
6372 }
6373
HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id,MS_U16 u16HSize,MS_U16 u16VSize,MS_U32 u32FrmRate)6374 MS_BOOL HAL_HVD_EX_GetFrmRateIsSupported(MS_U32 u32Id, MS_U16 u16HSize, MS_U16 u16VSize, MS_U32 u32FrmRate)
6375 {
6376 MS_U64 _hw_max_pixel = 0;
6377 _hw_max_pixel = _HAL_EX_GetHwMaxPixel(u32Id);
6378
6379 HVD_EX_MSG_DBG("%s w:%d, h:%d, fr:%d, MAX:%ld\n", __FUNCTION__,
6380 u16HSize, u16VSize, u32FrmRate, (unsigned long)_hw_max_pixel);
6381 return (((MS_U64)u16HSize*(MS_U64)u16VSize*(MS_U64)u32FrmRate) <= _hw_max_pixel);
6382 }
6383
6384
HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)6385 MS_U32 HAL_HVD_EX_GetDispFrmNum(MS_U32 u32Id)
6386 {
6387 #if 1
6388 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6389 MS_U16 u16QNum = pShm->u16DispQNumb;
6390 MS_U16 u16QPtr = pShm->u16DispQPtr;
6391 // MS_U16 u16QSize = pShm->u16DispQSize;
6392 //static volatile HVD_Frm_Information *pHvdFrm = NULL;
6393 MS_U32 u32DispQNum = 0;
6394 #if HVD_ENABLE_MVC
6395 MS_BOOL bMVC = HAL_HVD_EX_CheckMVCID(u32Id);
6396
6397 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6398 MS_BOOL bDolbyVision = (E_HVD_INIT_HW_HEVC_DV == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK));
6399
6400 if(bMVC || bDolbyVision)
6401 {
6402 #if 0
6403 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT*3)
6404 {
6405 u16QNum = HVD_DISPQ_PREFETCH_COUNT*3;
6406 }
6407 #endif
6408
6409 //printf("OQ:%d,DQ:%d.\n",pShm->u16DispQNumb,pShm->u16DecQNumb);
6410 //search the next frame to display
6411 while (u16QNum > 0)
6412 {
6413 //printf("Pr:%d,%d.[%ld,%ld,%ld,%ld].\n",u16QPtr,u16QNum,pShm->DispQueue[u16QPtr].u32Status,pShm->DispQueue[u16QPtr+1].u32Status,
6414 // pShm->DispQueue[u16QPtr+2].u32Status,pShm->DispQueue[u16QPtr+3].u32Status);
6415 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6416
6417 //printf("Q2: %ld\n", pHVDShareMem->DispQueue[u16QPtr].u32Status);
6418 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6419 {
6420 /// For MVC. Output views after the pair of (base and depend) views were decoded.
6421 /// Check the depned view was initial when Output the base view.
6422 if((u16QPtr%2) == 0)
6423 {
6424 volatile HVD_Frm_Information *pHvdFrm_sub = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr+1];
6425 //if(pHvdFrm_sub->u32Status != E_HVD_DISPQ_STATUS_INIT)
6426 if(pHvdFrm_sub->u32Status == E_HVD_DISPQ_STATUS_NONE)
6427 {
6428 ///printf("[MVC] %d is not E_HVD_DISPQ_STATUS_INIT (%ld).\n",u16QPtr+1,pHvdFrm_sub->u32Status);
6429 ///printf("Return NULL.\n");
6430 break;
6431 }
6432 }
6433 u32DispQNum++;
6434 }
6435
6436 u16QNum--;
6437 //go to next frame in the dispQ
6438 u16QPtr++;
6439
6440 if (u16QPtr >= pShm->u16DispQSize)
6441 {
6442 u16QPtr -= pShm->u16DispQSize; //wrap to the begin
6443 }
6444 }
6445 }
6446 else
6447 #endif ///HVD_ENABLE_MVC
6448 {
6449 #if 0
6450 if (u16QNum > HVD_DISPQ_PREFETCH_COUNT)
6451 {
6452 u16QNum = HVD_DISPQ_PREFETCH_COUNT;
6453 }
6454 #endif
6455 // printf("Q: %d %d %d\n", u16QNum, u16QPtr, u16QSize);
6456 //search the next frame to display
6457 while (u16QNum != 0)
6458 {
6459 pHVDHalContext->pHvdFrm = (volatile HVD_Frm_Information *) &pShm->DispQueue[u16QPtr];
6460
6461 // printf("Q2[%d]: %ld\n", u16QPtr, pShm->DispQueue[u16QPtr].u32Status);
6462 if (pHVDHalContext->pHvdFrm->u32Status == E_HVD_DISPQ_STATUS_INIT)
6463 {
6464 u32DispQNum++;
6465 }
6466
6467 u16QNum--;
6468 //go to next frame in the dispQ
6469 u16QPtr++;
6470
6471 if (u16QPtr == pShm->u16DispQSize)
6472 {
6473 u16QPtr = 0; //wrap to the begin
6474 }
6475 }
6476 }
6477
6478 //printf("dispQnum = %ld, pShm->u16DispQNumb = %d\n", u32DispQNum, pShm->u16DispQNumb);
6479 return u32DispQNum;
6480 #else
6481 HVD_ShareMem *pShm = (HVD_ShareMem *) _HVD_EX_GetShmAddr(u32Id);
6482 return pShm->u16DispQNumb;
6483 #endif
6484 }
6485
HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id,MS_U32 u32ModeFlag)6486 void HAL_HVD_EX_SetHwRegBase(MS_U32 u32Id, MS_U32 u32ModeFlag)
6487 {
6488 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6489 if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC ||
6490 (u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_HEVC_DV)
6491 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6492 else if ((u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_VP9)
6493 #if SUPPORT_G2VP9 && defined(VDEC3)
6494 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_G2VP9_BASE;
6495 #else // Not using G2 VP9 implies using Mstar EVD VP9
6496 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_EVD_BASE;
6497 #endif
6498 else
6499 pHVDHalContext->_stHVDStream[u8Idx].u32RegBase = REG_HVD_BASE;
6500 }
6501
6502 #if SUPPORT_EVD
HAL_EVD_EX_PowerCtrl(MS_U32 u32Id,MS_BOOL bEnable)6503 void HAL_EVD_EX_PowerCtrl(MS_U32 u32Id, MS_BOOL bEnable)
6504 {
6505 #ifdef CONFIG_MSTAR_CLKM
6506 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD, bEnable);
6507 HAL_VPU_EX_SetClkManagement(E_VPU_EX_CLKPORT_EVD_PPU, bEnable);
6508 #else
6509 if (bEnable)
6510 {
6511 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, ~TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6512 _HVD_WriteWordMask(REG_TOP_CKG_EVD, ~TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6513 _HVD_WriteWordMask(REG_EVDPLL_PD, ~REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6514 }
6515 else
6516 {
6517 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_DIS, TOP_CKG_EVD_PPU_DIS);
6518 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_DIS, TOP_CKG_EVD_DIS);
6519 _HVD_WriteWordMask(REG_EVDPLL_PD, REG_EVDPLL_PD_DIS, REG_EVDPLL_PD_DIS);
6520 }
6521
6522 switch (pHVDHalContext->u32EVDClockType)
6523 {
6524 case 576:
6525 {
6526 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6527 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6528 break;
6529 }
6530 case 532:
6531 {
6532 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU128PLL, TOP_CKG_EVD_PPU_MASK);
6533 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU128PLL, TOP_CKG_EVD_MASK);
6534 break;
6535 }
6536 case 456:
6537 {
6538 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6539 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6540 _HVD_WriteWordMask(REG_EVDPLL_LOOP_DIV_SECOND, REG_EVDPLL_LOOP_DIV_SECOND_456MHZ, REG_EVDPLL_LOOP_DIV_SECOND_MASK);
6541 break;
6542 }
6543 case 466:
6544 {
6545 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_MIU256PLL, TOP_CKG_EVD_PPU_MASK);
6546 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_MIU256PLL, TOP_CKG_EVD_MASK);
6547 break;
6548 }
6549 case 480:
6550 {
6551 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_480MHZ, TOP_CKG_EVD_PPU_MASK);
6552 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_480MHZ, TOP_CKG_EVD_MASK);
6553 break;
6554 }
6555 case 384:
6556 {
6557 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_384MHZ, TOP_CKG_EVD_PPU_MASK);
6558 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_384MHZ, TOP_CKG_EVD_MASK);
6559 break;
6560 }
6561 case 320:
6562 {
6563 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_320MHZ, TOP_CKG_EVD_PPU_MASK);
6564 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_320MHZ, TOP_CKG_EVD_MASK);
6565 break;
6566 }
6567 case 240:
6568 {
6569 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_240MHZ, TOP_CKG_EVD_PPU_MASK);
6570 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_240MHZ, TOP_CKG_EVD_MASK);
6571 break;
6572 }
6573 case 192:
6574 {
6575 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_192MHZ, TOP_CKG_EVD_PPU_MASK);
6576 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_192MHZ, TOP_CKG_EVD_MASK);
6577 break;
6578 }
6579 default:
6580 {
6581 _HVD_WriteWordMask(REG_TOP_CKG_EVD_PPU, TOP_CKG_EVD_PPU_PLL_BUF, TOP_CKG_EVD_PPU_MASK);
6582 _HVD_WriteWordMask(REG_TOP_CKG_EVD, TOP_CKG_EVD_PLL_BUF, TOP_CKG_EVD_MASK);
6583 break;
6584 }
6585 }
6586 #endif
6587 #ifdef CONFIG_MSTAR_SRAMPD
6588 if (bEnable)
6589 {
6590 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6591 HVD_Delay_ms(1);
6592 }
6593 else
6594 {
6595 _HVD_WriteByteMask(REG_HICODEC_SRAM_SD_EN, ~HICODEC_SRAM_HICODEC0, HICODEC_SRAM_HICODEC0);
6596 HVD_Delay_ms(1);
6597 }
6598 #endif
6599 return;
6600 }
6601
HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)6602 void HAL_EVD_EX_ClearTSPInput(MS_U32 u32Id)
6603 {
6604 #ifndef VDEC3
6605 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6606 #endif
6607 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6608 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6609 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6610
6611 #ifdef VDEC3
6612 if (0 == pCtrl->u32BBUId)
6613 #else
6614 if (0 == u8TaskId)
6615 #endif
6616 {
6617 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_HK_TSP2EVD_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for main-DTV mode
6618 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6619 _HVD_Write2Byte(HVD_REG_MIF_BBU(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)) & (~HVD_REG_BBU_TSP_INPUT));
6620 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU(u32RB)));
6621 }
6622 else
6623 {
6624 _HVD_Write2Byte(EVD_REG_RESET, (_HVD_Read2Byte(EVD_REG_RESET) & ~EVD_REG_RESET_USE_HVD_MIU_EN)); //0: tsp2hvd, coz EVD & HVD use the same MVD parser for sub-DTV mode
6625 // disable TSP mode in EVD since EVD maybe effected by MVD parser's write pointer used by previous decoder
6626 _HVD_Write2Byte(HVD_REG_MIF_BBU_BS2(u32RB), _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)) & (~HVD_REG_BBU_TSP_INPUT_BS2));
6627 HVD_EX_MSG_INF("id %d disable TSP mode, val 0x%x\n", pCtrl->u32BBUId, _HVD_Read2Byte(HVD_REG_MIF_BBU_BS2(u32RB)));
6628 }
6629
6630 return;
6631 }
6632
HAL_EVD_EX_DeinitHW(MS_U32 u32Id)6633 MS_BOOL HAL_EVD_EX_DeinitHW(MS_U32 u32Id)
6634 {
6635 MS_U16 u16Timeout = 1000;
6636 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6637 MS_BOOL isVP8Used = FALSE;
6638 MS_BOOL isAECUsed = FALSE;
6639 MS_BOOL isAVCUsed = FALSE;
6640 HAL_HVD_EX_VP8AECInUsed(u32Id, &isVP8Used, &isAECUsed, &isAVCUsed);
6641
6642 if(TRUE == HAL_VPU_EX_EVDInUsed())
6643 {
6644 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6645 {
6646 HAL_AEC_PowerCtrl(FALSE);
6647 }
6648 return FALSE;
6649 }
6650 else if(!isAVCUsed)//no AVC/EVD use , close EVD power
6651 {
6652 _HVD_EX_SetMIUProtectMask(TRUE);
6653
6654 _HVD_WriteWordMask(EVD_REG_RESET, EVD_REG_RESET_SWRST, EVD_REG_RESET_SWRST);
6655
6656 while (u16Timeout)
6657 {
6658 if ((_HVD_Read2Byte(EVD_REG_RESET) & (EVD_REG_RESET_SWRST_FIN)) == (EVD_REG_RESET_SWRST_FIN))
6659 {
6660 break;
6661 }
6662 u16Timeout--;
6663 }
6664
6665 HAL_EVD_EX_PowerCtrl(u32Id, FALSE);
6666
6667 if(!isAECUsed && E_HVD_INIT_HW_VP9 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6668 {
6669 HAL_AEC_PowerCtrl(FALSE);
6670 }
6671
6672 _HVD_EX_SetMIUProtectMask(FALSE);
6673
6674 return TRUE;
6675 }
6676
6677 return FALSE;
6678 }
6679 #endif
6680
6681 #if SUPPORT_G2VP9 && defined(VDEC3)
HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)6682 static void HAL_VP9_EX_PowerCtrl(MS_BOOL bEnable)
6683 {
6684 if (bEnable)
6685 {
6686 _HVD_WriteWordMask(REG_TOP_VP9, ~TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6687 }
6688 else
6689 {
6690 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_DIS, TOP_CKG_VP9_DIS);
6691 }
6692
6693 switch (pHVDHalContext->u32VP9ClockType)
6694 {
6695 case 432:
6696 {
6697 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6698 break;
6699 }
6700 case 384:
6701 {
6702 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_384MHZ, TOP_CKG_VP9_CLK_MASK);
6703 break;
6704 }
6705 case 345:
6706 {
6707 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_345MHZ, TOP_CKG_VP9_CLK_MASK);
6708 break;
6709 }
6710 case 320:
6711 {
6712 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_320MHZ, TOP_CKG_VP9_CLK_MASK);
6713 break;
6714 }
6715 case 288:
6716 {
6717 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_288MHZ, TOP_CKG_VP9_CLK_MASK);
6718 break;
6719 }
6720 case 240:
6721 {
6722 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_240MHZ, TOP_CKG_VP9_CLK_MASK);
6723 break;
6724 }
6725 case 216:
6726 {
6727 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_216MHZ, TOP_CKG_VP9_CLK_MASK);
6728 break;
6729 }
6730 case 172:
6731 {
6732 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_172MHZ, TOP_CKG_VP9_CLK_MASK);
6733 break;
6734 }
6735 default:
6736 {
6737 _HVD_WriteWordMask(REG_TOP_VP9, TOP_CKG_VP9_432MHZ, TOP_CKG_VP9_CLK_MASK);
6738 break;
6739 }
6740 }
6741
6742 return;
6743 }
6744
HAL_VP9_EX_DeinitHW(void)6745 MS_BOOL HAL_VP9_EX_DeinitHW(void)
6746 {
6747 MS_U16 u16Timeout = 1000;
6748
6749 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST);
6750
6751 while (u16Timeout)
6752 {
6753 if ((_HVD_Read2Byte(VP9_REG_RESET) & (VP9_REG_RESET_SWRST_FIN)) == (VP9_REG_RESET_SWRST_FIN))
6754 {
6755 break;
6756 }
6757 u16Timeout--;
6758 }
6759
6760 HAL_VP9_EX_PowerCtrl(FALSE);
6761
6762 return TRUE;
6763 }
6764 #endif
6765
HAL_HVD_EX_GetSupport2ndMVOPInterface(void)6766 MS_BOOL HAL_HVD_EX_GetSupport2ndMVOPInterface(void)
6767 {
6768 return TRUE;
6769 }
6770
HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)6771 void HAL_HVD_EX_SetNalTblAddr(MS_U32 u32Id)
6772 {
6773 MS_VIRT u32StAddr = 0;
6774 MS_U8 u8BitMiuSel = 0;
6775 MS_U8 u8CodeMiuSel = 0;
6776 MS_U8 u8TmpMiuSel = 0;
6777 MS_U32 u32BitStartOffset;
6778 MS_U32 u32CodeStartOffset;
6779
6780 #ifndef VDEC3
6781 MS_U8 u8TaskId = HAL_VPU_EX_GetTaskId(u32Id);
6782 #endif
6783 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6784 MS_U8 u8Idx = _HVD_EX_GetStreamIdx(u32Id);
6785 MS_U32 u32RB = pHVDHalContext->_stHVDStream[u8Idx].u32RegBase;
6786 HVD_ShareMem *pShm = (HVD_ShareMem *) HAL_HVD_EX_GetShmAddr(u32Id);
6787
6788 _HAL_HVD_Entry();
6789
6790 if (pCtrl == NULL)
6791 {
6792 _HAL_HVD_Return();
6793 }
6794
6795 MS_BOOL bNalTblAlreadySet = FALSE;
6796 VPU_EX_TaskInfo taskInfo;
6797 memset(&taskInfo, 0, sizeof(VPU_EX_TaskInfo));
6798 HAL_HVD_EX_GetTaskInfo(u32Id, &taskInfo);
6799
6800 bNalTblAlreadySet = HAL_VPU_EX_CheckBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
6801
6802
6803
6804 _phy_to_miu_offset(u8BitMiuSel, u32BitStartOffset, pCtrl->MemMap.u32BitstreamBufAddr);
6805 _phy_to_miu_offset(u8CodeMiuSel, u32CodeStartOffset, pCtrl->MemMap.u32CodeBufAddr);
6806
6807 if (u8BitMiuSel != u8CodeMiuSel)
6808 {
6809 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32BitstreamBufAddr + pCtrl->u32BBUTblInBitstreamBufAddr));
6810 }
6811 else
6812 {
6813 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pCtrl->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU_DRAM_ST_ADDR));
6814 }
6815
6816 if (E_HVD_INIT_HW_VP8 == (pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK))
6817 {
6818 #ifdef VDEC3
6819 if (!_HAL_EX_BBU_VP8_InUsed())
6820 #endif
6821 {
6822 _HVD_Write2Byte(HVD_REG_HK_VP8, HVD_REG_HK_PLAYER_FM);
6823
6824 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS3, (MS_U16)(u32StAddr >> 3));
6825 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS3, (MS_U16)(u32StAddr >> 19));
6826 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS3, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6827
6828 u32StAddr += VP8_BBU_TBL_SIZE;
6829
6830 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_L_BS4, (MS_U16)(u32StAddr >> 3));
6831 _HVD_Write2Byte(HVD_REG_NAL_TAB_ST_H_BS4, (MS_U16)(u32StAddr >> 19));
6832 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS4, (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6833 }
6834
6835 _HAL_HVD_Return();
6836 }
6837
6838 HVD_EX_MSG_DBG("NAL start addr=%lx\n", (unsigned long)u32StAddr);
6839
6840 #ifdef VDEC3
6841 if (!bNalTblAlreadySet)
6842 {
6843 if (pCtrl->u32BBUId == 0)
6844 {
6845 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
6846 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
6847 // -1 is for NAL_TAB_LEN counts from zero.
6848 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6849 }
6850 else
6851 {
6852 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
6853 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
6854 // -1 is for NAL_TAB_LEN counts from zero.
6855 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6856 }
6857 }
6858 #else
6859 if (0 == u8TaskId)
6860 {
6861 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L(u32RB), (MS_U16) (u32StAddr >> 3));
6862 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H(u32RB), (MS_U16) (u32StAddr >> 19));
6863 // -1 is for NAL_TAB_LEN counts from zero.
6864 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6865 }
6866 else
6867 {
6868 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16) (u32StAddr >> 3));
6869 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16) (u32StAddr >> 19));
6870 // -1 is for NAL_TAB_LEN counts from zero.
6871 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16) (pHVDHalContext->_stHVDStream[u8Idx].u32BBUEntryNum - 1));
6872 }
6873 #endif
6874
6875
6876 #if (HVD_ENABLE_MVC)
6877 if ((pCtrl->InitParams.u32ModeFlag & E_HVD_INIT_HW_MASK) == E_HVD_INIT_HW_MVC)
6878 {
6879 /// Used sub stream to record sub view data.
6880 HVD_EX_Drv_Ctrl *pDrvCtrl_Sub = _HVD_EX_GetDrvCtrl((u32Id+0x00011000));
6881 //printf("**************** Buffer setting for MVC dual-BBU *************\n");
6882
6883 if (u8BitMiuSel != u8CodeMiuSel)
6884 {
6885 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32BitstreamBufAddr + pDrvCtrl_Sub->u32BBUTblInBitstreamBufAddr));
6886 }
6887 else
6888 {
6889 _phy_to_miu_offset(u8TmpMiuSel, u32StAddr, (pDrvCtrl_Sub->MemMap.u32CodeBufAddr + pShm->u32HVD_BBU2_DRAM_ST_ADDR));
6890 }
6891
6892 HVD_EX_MSG_DBG("[MVC] _HAL_HVD_SetBuffer2Addr: nal StAddr:%lx \n", (unsigned long) u32StAddr);
6893 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_L_BS2(u32RB), (MS_U16)(u32StAddr >> 3));
6894 _HVD_Write2Byte(HVD_REG_NAL_TBL_ST_ADDR_H_BS2(u32RB), (MS_U16)(u32StAddr >> 19));
6895 // -1 is for NAL_TAB_LEN counts from zero.
6896 _HVD_Write2Byte(HVD_REG_NAL_TAB_LEN_BS2(u32RB), (MS_U16)(pHVDHalContext->_stHVDStream[u8Idx+1].u32BBUEntryNum - 1));
6897 }
6898 #endif
6899
6900 if (!bNalTblAlreadySet)
6901 {
6902 HAL_VPU_EX_SetBBUSetting(u32Id, pCtrl->u32BBUId, taskInfo.eDecType, VPU_BBU_NAL_TBL);
6903 }
6904
6905 _HAL_HVD_Return();
6906 }
6907
HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)6908 MS_BOOL HAL_HVD_EX_Is_RM_Supported(MS_U32 u32Id)
6909 {
6910 HVD_EX_Drv_Ctrl *pCtrl = _HVD_EX_GetDrvCtrl(u32Id);
6911
6912 if(pCtrl->InitParams.u16ChipECONum == 0)
6913 return FALSE;
6914 else
6915 return TRUE;
6916 }
6917
HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)6918 void HAL_HVD_EX_BBU_Proc(MS_U32 u32streamIdx)
6919 {
6920
6921 }
6922
HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)6923 void HAL_HVD_EX_BBU_StopProc(MS_U32 u32streamIdx)
6924 {
6925
6926 }
6927 #endif
6928