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Searched refs:sdhci_readl (Results 1 – 25 of 30) sorted by relevance

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/OK3568_Linux_fs/u-boot/drivers/mmc/
H A Dxenon_sdhci.c128 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
142 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_init()
155 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
168 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_init()
204 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL); in xenon_mmc_phy_set()
210 var = sdhci_readl(host, EMMC_PHY_PAD_CONTROL1); in xenon_mmc_phy_set()
226 var = sdhci_readl(host, EMMC_PHY_TIMING_ADJUST); in xenon_mmc_phy_set()
235 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
239 var = sdhci_readl(host, EMMC_PHY_FUNC_CONTROL); in xenon_mmc_phy_set()
249 var = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_mmc_phy_set()
[all …]
H A Dkona_sdhci.c34 mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET; in init_kona_mmc_core()
47 (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) & in init_kona_mmc_core()
55 mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET); in init_kona_mmc_core()
62 mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET); in init_kona_mmc_core()
67 while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) { in init_kona_mmc_core()
H A Dsdhci.c47 cmd->response[i] = sdhci_readl(host, in sdhci_cmd_done()
54 cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE); in sdhci_cmd_done()
65 *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER); in sdhci_transfer_pio()
87 stat = sdhci_readl(host, SDHCI_INT_STATUS); in sdhci_transfer_data()
94 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask)) in sdhci_transfer_data()
170 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
273 stat = sdhci_readl(host, SDHCI_INT_STATUS);
300 stat = sdhci_readl(host, SDHCI_INT_STATUS);
346 while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
489 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
[all …]
H A Datmel_sdhci.c81 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in atmel_sdhci_probe()
83 caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in atmel_sdhci_probe()
H A Drockchip_sdhci.c212 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & in rockchip_emmc_set_clock()
363 if (DLL_LOCK_WO_TMOUT((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0)))) in dwcmshc_sdhci_emmc_set_clock()
368 dll_lock_value = ((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0) & 0xFF) * 2 ) & 0xFF; in dwcmshc_sdhci_emmc_set_clock()
411 extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3); in dwcmshc_sdhci_emmc_set_clock()
443 vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL); in dwcmshc_sdhci_set_enhanced_strobe()
H A Ds5p_sdhci.c42 val = sdhci_readl(host, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
70 ctrl = sdhci_readl(host, SDHCI_CONTROL2); in s5p_sdhci_set_control_reg()
/OK3568_Linux_fs/kernel/drivers/mmc/host/
H A Dsdhci-xenon-phy.c235 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
265 reg = sdhci_readl(host, phy_regs->timing_adj); in xenon_emmc_phy_init()
331 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
336 reg = sdhci_readl(host, phy_regs->dll_ctrl); in xenon_emmc_phy_enable_dll()
392 reg = sdhci_readl(host, XENON_SLOT_DLL_CUR_DLY_VAL); in xenon_emmc_phy_config_tuning()
402 reg = sdhci_readl(host, XENON_SLOT_OP_STATUS_CTRL); in xenon_emmc_phy_config_tuning()
420 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_disable_strobe()
426 reg = sdhci_readl(host, XENON_EMMC_5_0_PHY_PAD_CONTROL); in xenon_emmc_phy_disable_strobe()
430 reg = sdhci_readl(host, XENON_EMMC_PHY_PAD_CONTROL1); in xenon_emmc_phy_disable_strobe()
454 reg = sdhci_readl(host, XENON_SLOT_EMMC_CTRL); in xenon_emmc_phy_strobe_delay_adj()
[all …]
H A Dsdhci-of-esdhc.c538 value = sdhci_readl(host, ESDHC_DMA_SYSCTL); in esdhc_of_enable_dma()
590 val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_clock_enable()
607 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) in esdhc_clock_enable()
623 val = sdhci_readl(host, ESDHC_DMA_SYSCTL); in esdhc_flush_async_fifo()
632 if (!(sdhci_readl(host, ESDHC_DMA_SYSCTL) & in esdhc_flush_async_fifo()
714 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); in esdhc_of_set_clock()
728 if (sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE) in esdhc_of_set_clock()
741 temp = sdhci_readl(host, ESDHC_TBCTL); in esdhc_of_set_clock()
743 temp = sdhci_readl(host, ESDHC_SDCLKCTL); in esdhc_of_set_clock()
747 temp = sdhci_readl(host, ESDHC_DLLCFG0); in esdhc_of_set_clock()
[all …]
H A Dsdhci-xenon.c29 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); in xenon_enable_internal_clk()
57 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_sdclk_off_idle()
73 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_set_acg()
87 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_enable_sdhc()
105 reg = sdhci_readl(host, XENON_SYS_OP_CTRL); in xenon_disable_sdhc()
116 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_enable_sdhc_parallel_tran()
126 reg = sdhci_readl(host, XENON_SYS_EXT_OP_CTRL); in xenon_mask_cmd_conflict_err()
138 reg = sdhci_readl(host, XENON_SLOT_RETUNING_REQ_CTRL); in xenon_retune_setup()
143 reg = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); in xenon_retune_setup()
146 reg = sdhci_readl(host, SDHCI_INT_ENABLE); in xenon_retune_setup()
[all …]
H A Dsdhci_f_sdh30.c35 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_f_sdh30_soft_voltage_switch()
47 ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_soft_voltage_switch()
52 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_f_sdh30_soft_voltage_switch()
73 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_reset()
162 reg = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_f_sdh30_probe()
167 reg = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_f_sdh30_probe()
H A Dsdhci-bcm-kona.c67 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
71 while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) { in sdhci_bcm_kona_sd_reset()
79 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_reset()
99 val = sdhci_readl(host, KONA_SDHOST_COREIMR); in sdhci_bcm_kona_sd_init()
104 val = sdhci_readl(host, KONA_SDHOST_CORECTRL); in sdhci_bcm_kona_sd_init()
138 val = sdhci_readl(host, KONA_SDHOST_CORESTAT); in sdhci_bcm_kona_sd_card_emulate()
H A Dsdhci-pci-gli.c118 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_on()
135 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); in gl9750_wt_off()
159 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); in gli_set_9750()
160 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gli_set_9750()
161 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); in gli_set_9750()
162 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750()
163 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); in gli_set_9750()
164 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); in gli_set_9750()
247 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); in gli_set_9750_rx_inv()
319 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); in gl9750_disable_ssc_pll()
[all …]
H A Dsdhci-pci-dwc-mshc.c39 reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr)); in sdhci_snps_set_clock()
47 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
63 reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr)); in sdhci_snps_set_clock()
H A Dsdhci-brcmstb.c47 reg = sdhci_readl(host, SDHCI_VENDOR); in enable_clock_gating()
134 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
136 sdhci_readl(host, SDHCI_BUFFER); in sdhci_brcmstb_cqe_enable()
137 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_brcmstb_cqe_enable()
323 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_brcmstb_probe()
326 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in sdhci_brcmstb_probe()
H A Dsdhci-milbeaut.c65 ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_soft_voltage_switch()
75 ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING); in sdhci_milbeaut_soft_voltage_switch()
118 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_reset()
149 val = sdhci_readl(host, MLB_CR_SET); in sdhci_milbeaut_bridge_init()
181 ctl = sdhci_readl(host, F_SDH30_IO_CONTROL2); in sdhci_milbeaut_vendor_init()
196 ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL); in sdhci_milbeaut_vendor_init()
H A Dsdhci-tegra.c345 reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_set_tap()
372 misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL); in tegra_sdhci_reset()
373 clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL); in tegra_sdhci_reset()
404 pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_reset()
423 val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL); in tegra_sdhci_configure_cal_pad()
441 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_set_pad_autocal_offset()
486 reg = sdhci_readl(host, in tegra_sdhci_set_padctrl()
550 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
568 reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); in tegra_sdhci_pad_autocalib()
784 val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); in tegra_sdhci_hs400_enhanced_strobe()
[all …]
H A Dsdhci-pci-o2micro.c84 scratch32 = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_o2_wait_card_detect_stable()
106 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
140 scratch32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_enable_internal_clock()
154 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in sdhci_o2_get_cd()
173 return sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_pll_dll_wdt_control()
253 scratch_32 = sdhci_readl(host, O2_PLL_DLL_WDT_CONTROL1); in sdhci_o2_dll_recovery()
572 caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_pci_o2_probe_slot()
587 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING); in sdhci_pci_o2_probe_slot()
623 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2); in sdhci_pci_o2_probe_slot()
H A Dsdhci-sprd.c109 val = sdhci_readl(host, SDHCI_SPRD_REG_DEBOUNCE); in sdhci_sprd_init_config()
183 dll_dly_offset = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_DLY_OFFSET); in sdhci_sprd_set_dll_invert()
228 val = sdhci_readl(host, SDHCI_SPRD_REG_32_BUSY_POSI); in _sdhci_sprd_set_clock()
241 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
247 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
254 tmp = sdhci_readl(host, SDHCI_SPRD_REG_32_DLL_CFG); in sdhci_sprd_enable_phy_dll()
659 host->caps = sdhci_readl(host, SDHCI_CAPABILITIES); in sdhci_sprd_probe()
660 host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1); in sdhci_sprd_probe()
H A Dsdhci.c62 sdhci_readl(host, SDHCI_DMA_ADDRESS), in sdhci_dumpregs()
68 sdhci_readl(host, SDHCI_ARGUMENT), in sdhci_dumpregs()
71 sdhci_readl(host, SDHCI_PRESENT_STATE), in sdhci_dumpregs()
81 sdhci_readl(host, SDHCI_INT_STATUS)); in sdhci_dumpregs()
83 sdhci_readl(host, SDHCI_INT_ENABLE), in sdhci_dumpregs()
84 sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); in sdhci_dumpregs()
89 sdhci_readl(host, SDHCI_CAPABILITIES), in sdhci_dumpregs()
90 sdhci_readl(host, SDHCI_CAPABILITIES_1)); in sdhci_dumpregs()
93 sdhci_readl(host, SDHCI_MAX_CURRENT)); in sdhci_dumpregs()
95 sdhci_readl(host, SDHCI_RESPONSE), in sdhci_dumpregs()
[all …]
H A Dsdhci-of-sparx5.c236 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION)); in sdhci_sparx5_probe()
238 mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE)); in sdhci_sparx5_probe()
H A Dsdhci-of-dwcmshc.c223 vendor = sdhci_readl(host, reg); in dwcmshc_hs400_enhanced_strobe()
273 extra = sdhci_readl(host, reg); in dwcmshc_rk3568_set_clock()
323 dll_lock_value = ((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0) & 0xFF) * 2) & 0xFF; in dwcmshc_rk3568_set_clock()
630 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; in dwcmshc_probe()
H A Dsdhci-of-arasan.c348 vendor = sdhci_readl(host, SDHCI_ARASAN_VENDOR_REGISTER); in sdhci_arasan_hs400_enhanced_strobe()
427 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
429 sdhci_readl(host, SDHCI_BUFFER); in sdhci_arasan_cqe_enable()
430 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); in sdhci_arasan_cqe_enable()
793 regval = sdhci_readl(host, SDHCI_ARASAN_OTAPDLY_REGISTER); in sdhci_versal_sdcardclk_set_phase()
859 regval = sdhci_readl(host, SDHCI_ARASAN_ITAPDLY_REGISTER); in sdhci_versal_sampleclk_set_phase()
H A Dsdhci-acpi.c376 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); in bxt_get_cd()
390 sdhci_readl(host, SDHCI_CAPABILITIES) == 0x446cc8b2 && in intel_probe_slot()
391 sdhci_readl(host, SDHCI_CAPABILITIES_1) == 0x00000807) in intel_probe_slot()
982 dead = (sdhci_readl(c->host, SDHCI_INT_STATUS) == ~0); in sdhci_acpi_remove()
H A Dsdhci-of-at91.c126 u32 calcr = sdhci_readl(host, SDMMC_CALCR); in sdhci_at91_reset()
131 if (read_poll_timeout(sdhci_readl, tmp, !(tmp & SDMMC_CALCR_EN), in sdhci_at91_reset()
/OK3568_Linux_fs/u-boot/include/
H A Dsdhci.h324 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function
364 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl() function

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