345 	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);  in tegra_sdhci_set_tap()
372 	misc_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);  in tegra_sdhci_reset()
373 	clk_ctrl = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);  in tegra_sdhci_reset()
404 		pad_ctrl = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);  in tegra_sdhci_reset()
423 	val = sdhci_readl(host, SDHCI_TEGRA_SDMEM_COMP_PADCTRL);  in tegra_sdhci_configure_cal_pad()
441 	reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);  in tegra_sdhci_set_pad_autocal_offset()
486 			reg = sdhci_readl(host,  in tegra_sdhci_set_padctrl()
550 	reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);  in tegra_sdhci_pad_autocalib()
568 		reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG);  in tegra_sdhci_pad_autocalib()
784 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL);  in tegra_sdhci_hs400_enhanced_strobe()
815 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CAP_OVERRIDES);  in tegra_sdhci_set_dqs_trim()
826 	reg = sdhci_readl(host, SDHCI_TEGRA_VENDOR_DLLCAL_CFG);  in tegra_sdhci_hs400_dll_cal()
863 		val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);  in tegra_sdhci_tap_correction()
867 		tun_status = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS0);  in tegra_sdhci_tap_correction()
934 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_CLOCK_CTRL);  in tegra_sdhci_post_tuning()
957 		val = sdhci_readl(host, SDHCI_TEGRA_VNDR_TUN_STATUS1);  in tegra_sdhci_post_tuning()
1027 	val = sdhci_readl(host, SDHCI_VNDR_TUN_CTRL0_0);  in tegra_sdhci_set_uhs_signaling()
1292 	val = sdhci_readl(host, SDHCI_TEGRA_VENDOR_MISC_CTRL);  in tegra_sdhci_set_timeout()