1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * SDHCI driver for Synopsys DWC_MSHC controller
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018 Synopsys, Inc. (www.synopsys.com)
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Authors:
8*4882a593Smuzhiyun * Prabu Thangamuthu <prabu.t@synopsys.com>
9*4882a593Smuzhiyun * Manjunath M B <manjumb@synopsys.com>
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include "sdhci.h"
13*4882a593Smuzhiyun #include "sdhci-pci.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define SDHCI_VENDOR_PTR_R 0xE8
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun /* Synopsys vendor specific registers */
18*4882a593Smuzhiyun #define SDHC_GPIO_OUT 0x34
19*4882a593Smuzhiyun #define SDHC_AT_CTRL_R 0x40
20*4882a593Smuzhiyun #define SDHC_SW_TUNE_EN 0x00000010
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* MMCM DRP */
23*4882a593Smuzhiyun #define SDHC_MMCM_DIV_REG 0x1020
24*4882a593Smuzhiyun #define DIV_REG_100_MHZ 0x1145
25*4882a593Smuzhiyun #define DIV_REG_200_MHZ 0x1083
26*4882a593Smuzhiyun #define SDHC_MMCM_CLKFBOUT 0x1024
27*4882a593Smuzhiyun #define CLKFBOUT_100_MHZ 0x0000
28*4882a593Smuzhiyun #define CLKFBOUT_200_MHZ 0x0080
29*4882a593Smuzhiyun #define SDHC_CCLK_MMCM_RST 0x00000001
30*4882a593Smuzhiyun
sdhci_snps_set_clock(struct sdhci_host * host,unsigned int clock)31*4882a593Smuzhiyun static void sdhci_snps_set_clock(struct sdhci_host *host, unsigned int clock)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun u16 clk;
34*4882a593Smuzhiyun u32 reg, vendor_ptr;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun vendor_ptr = sdhci_readw(host, SDHCI_VENDOR_PTR_R);
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Disable software managed rx tuning */
39*4882a593Smuzhiyun reg = sdhci_readl(host, (SDHC_AT_CTRL_R + vendor_ptr));
40*4882a593Smuzhiyun reg &= ~SDHC_SW_TUNE_EN;
41*4882a593Smuzhiyun sdhci_writel(host, reg, (SDHC_AT_CTRL_R + vendor_ptr));
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun if (clock <= 52000000) {
44*4882a593Smuzhiyun sdhci_set_clock(host, clock);
45*4882a593Smuzhiyun } else {
46*4882a593Smuzhiyun /* Assert reset to MMCM */
47*4882a593Smuzhiyun reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr));
48*4882a593Smuzhiyun reg |= SDHC_CCLK_MMCM_RST;
49*4882a593Smuzhiyun sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr));
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /* Configure MMCM */
52*4882a593Smuzhiyun if (clock == 100000000) {
53*4882a593Smuzhiyun sdhci_writel(host, DIV_REG_100_MHZ, SDHC_MMCM_DIV_REG);
54*4882a593Smuzhiyun sdhci_writel(host, CLKFBOUT_100_MHZ,
55*4882a593Smuzhiyun SDHC_MMCM_CLKFBOUT);
56*4882a593Smuzhiyun } else {
57*4882a593Smuzhiyun sdhci_writel(host, DIV_REG_200_MHZ, SDHC_MMCM_DIV_REG);
58*4882a593Smuzhiyun sdhci_writel(host, CLKFBOUT_200_MHZ,
59*4882a593Smuzhiyun SDHC_MMCM_CLKFBOUT);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* De-assert reset to MMCM */
63*4882a593Smuzhiyun reg = sdhci_readl(host, (SDHC_GPIO_OUT + vendor_ptr));
64*4882a593Smuzhiyun reg &= ~SDHC_CCLK_MMCM_RST;
65*4882a593Smuzhiyun sdhci_writel(host, reg, (SDHC_GPIO_OUT + vendor_ptr));
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /* Enable clock */
68*4882a593Smuzhiyun clk = SDHCI_PROG_CLOCK_MODE | SDHCI_CLOCK_INT_EN |
69*4882a593Smuzhiyun SDHCI_CLOCK_CARD_EN;
70*4882a593Smuzhiyun sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static const struct sdhci_ops sdhci_snps_ops = {
75*4882a593Smuzhiyun .set_clock = sdhci_snps_set_clock,
76*4882a593Smuzhiyun .enable_dma = sdhci_pci_enable_dma,
77*4882a593Smuzhiyun .set_bus_width = sdhci_set_bus_width,
78*4882a593Smuzhiyun .reset = sdhci_reset,
79*4882a593Smuzhiyun .set_uhs_signaling = sdhci_set_uhs_signaling,
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun const struct sdhci_pci_fixes sdhci_snps = {
83*4882a593Smuzhiyun .ops = &sdhci_snps_ops,
84*4882a593Smuzhiyun };
85