1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2015 Atmel Corporation
3*4882a593Smuzhiyun * Wenyou.Yang <wenyou.yang@atmel.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <clk.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <malloc.h>
12*4882a593Smuzhiyun #include <sdhci.h>
13*4882a593Smuzhiyun #include <asm/arch/clk.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define ATMEL_SDHC_MIN_FREQ 400000
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #ifndef CONFIG_DM_MMC
atmel_sdhci_init(void * regbase,u32 id)18*4882a593Smuzhiyun int atmel_sdhci_init(void *regbase, u32 id)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun struct sdhci_host *host;
21*4882a593Smuzhiyun u32 max_clk, min_clk = ATMEL_SDHC_MIN_FREQ;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun host = (struct sdhci_host *)calloc(1, sizeof(struct sdhci_host));
24*4882a593Smuzhiyun if (!host) {
25*4882a593Smuzhiyun printf("%s: sdhci_host calloc failed\n", __func__);
26*4882a593Smuzhiyun return -ENOMEM;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun host->name = "atmel_sdhci";
30*4882a593Smuzhiyun host->ioaddr = regbase;
31*4882a593Smuzhiyun host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
32*4882a593Smuzhiyun max_clk = at91_get_periph_generated_clk(id);
33*4882a593Smuzhiyun if (!max_clk) {
34*4882a593Smuzhiyun printf("%s: Failed to get the proper clock\n", __func__);
35*4882a593Smuzhiyun free(host);
36*4882a593Smuzhiyun return -ENODEV;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun host->max_clk = max_clk;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun add_sdhci(host, 0, min_clk);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun return 0;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun #else
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct atmel_sdhci_plat {
50*4882a593Smuzhiyun struct mmc_config cfg;
51*4882a593Smuzhiyun struct mmc mmc;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
atmel_sdhci_probe(struct udevice * dev)54*4882a593Smuzhiyun static int atmel_sdhci_probe(struct udevice *dev)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
57*4882a593Smuzhiyun struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
58*4882a593Smuzhiyun struct sdhci_host *host = dev_get_priv(dev);
59*4882a593Smuzhiyun u32 max_clk;
60*4882a593Smuzhiyun u32 caps, caps_1;
61*4882a593Smuzhiyun u32 clk_base, clk_mul;
62*4882a593Smuzhiyun ulong gck_rate;
63*4882a593Smuzhiyun struct clk clk;
64*4882a593Smuzhiyun int ret;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun ret = clk_get_by_index(dev, 0, &clk);
67*4882a593Smuzhiyun if (ret)
68*4882a593Smuzhiyun return ret;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun ret = clk_enable(&clk);
71*4882a593Smuzhiyun if (ret)
72*4882a593Smuzhiyun return ret;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun host->name = dev->name;
75*4882a593Smuzhiyun host->ioaddr = (void *)devfdt_get_addr(dev);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
78*4882a593Smuzhiyun host->bus_width = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
79*4882a593Smuzhiyun "bus-width", 4);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun caps = sdhci_readl(host, SDHCI_CAPABILITIES);
82*4882a593Smuzhiyun clk_base = (caps & SDHCI_CLOCK_V3_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
83*4882a593Smuzhiyun caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
84*4882a593Smuzhiyun clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >> SDHCI_CLOCK_MUL_SHIFT;
85*4882a593Smuzhiyun gck_rate = clk_base * 1000000 * (clk_mul + 1);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun ret = clk_get_by_index(dev, 1, &clk);
88*4882a593Smuzhiyun if (ret)
89*4882a593Smuzhiyun return ret;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun ret = clk_set_rate(&clk, gck_rate);
92*4882a593Smuzhiyun if (ret)
93*4882a593Smuzhiyun return ret;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun max_clk = clk_get_rate(&clk);
96*4882a593Smuzhiyun if (!max_clk)
97*4882a593Smuzhiyun return -EINVAL;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun host->max_clk = max_clk;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun ret = sdhci_setup_cfg(&plat->cfg, host, 0, ATMEL_SDHC_MIN_FREQ);
102*4882a593Smuzhiyun if (ret)
103*4882a593Smuzhiyun return ret;
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun host->mmc = &plat->mmc;
106*4882a593Smuzhiyun host->mmc->dev = dev;
107*4882a593Smuzhiyun host->mmc->priv = host;
108*4882a593Smuzhiyun upriv->mmc = host->mmc;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun clk_free(&clk);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun return sdhci_probe(dev);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
atmel_sdhci_bind(struct udevice * dev)115*4882a593Smuzhiyun static int atmel_sdhci_bind(struct udevice *dev)
116*4882a593Smuzhiyun {
117*4882a593Smuzhiyun struct atmel_sdhci_plat *plat = dev_get_platdata(dev);
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return sdhci_bind(dev, &plat->mmc, &plat->cfg);
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun static const struct udevice_id atmel_sdhci_ids[] = {
123*4882a593Smuzhiyun { .compatible = "atmel,sama5d2-sdhci" },
124*4882a593Smuzhiyun { }
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun U_BOOT_DRIVER(atmel_sdhci_drv) = {
128*4882a593Smuzhiyun .name = "atmel_sdhci",
129*4882a593Smuzhiyun .id = UCLASS_MMC,
130*4882a593Smuzhiyun .of_match = atmel_sdhci_ids,
131*4882a593Smuzhiyun .ops = &sdhci_ops,
132*4882a593Smuzhiyun .bind = atmel_sdhci_bind,
133*4882a593Smuzhiyun .probe = atmel_sdhci_probe,
134*4882a593Smuzhiyun .priv_auto_alloc_size = sizeof(struct sdhci_host),
135*4882a593Smuzhiyun .platdata_auto_alloc_size = sizeof(struct atmel_sdhci_plat),
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun #endif
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