1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013 Broadcom Corporation.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <malloc.h>
9*4882a593Smuzhiyun #include <sdhci.h>
10*4882a593Smuzhiyun #include <linux/errno.h>
11*4882a593Smuzhiyun #include <asm/kona-common/clk.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define SDHCI_CORECTRL_OFFSET 0x00008000
14*4882a593Smuzhiyun #define SDHCI_CORECTRL_EN 0x01
15*4882a593Smuzhiyun #define SDHCI_CORECTRL_RESET 0x02
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define SDHCI_CORESTAT_OFFSET 0x00008004
18*4882a593Smuzhiyun #define SDHCI_CORESTAT_CD_SW 0x01
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define SDHCI_COREIMR_OFFSET 0x00008008
21*4882a593Smuzhiyun #define SDHCI_COREIMR_IP 0x01
22*4882a593Smuzhiyun
init_kona_mmc_core(struct sdhci_host * host)23*4882a593Smuzhiyun static int init_kona_mmc_core(struct sdhci_host *host)
24*4882a593Smuzhiyun {
25*4882a593Smuzhiyun unsigned int mask;
26*4882a593Smuzhiyun unsigned int timeout;
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun if (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & SDHCI_RESET_ALL) {
29*4882a593Smuzhiyun printf("%s: sd host controller reset error\n", __func__);
30*4882a593Smuzhiyun return -EBUSY;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* For kona a hardware reset before anything else. */
34*4882a593Smuzhiyun mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET) | SDHCI_CORECTRL_RESET;
35*4882a593Smuzhiyun sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Wait max 100 ms */
38*4882a593Smuzhiyun timeout = 1000;
39*4882a593Smuzhiyun do {
40*4882a593Smuzhiyun if (timeout == 0) {
41*4882a593Smuzhiyun printf("%s: reset timeout error\n", __func__);
42*4882a593Smuzhiyun return -ETIMEDOUT;
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun timeout--;
45*4882a593Smuzhiyun udelay(100);
46*4882a593Smuzhiyun } while (0 ==
47*4882a593Smuzhiyun (sdhci_readl(host, SDHCI_CORECTRL_OFFSET) &
48*4882a593Smuzhiyun SDHCI_CORECTRL_RESET));
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Clear the reset bit. */
51*4882a593Smuzhiyun mask = mask & ~SDHCI_CORECTRL_RESET;
52*4882a593Smuzhiyun sdhci_writel(host, mask, SDHCI_CORECTRL_OFFSET);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /* Enable AHB clock */
55*4882a593Smuzhiyun mask = sdhci_readl(host, SDHCI_CORECTRL_OFFSET);
56*4882a593Smuzhiyun sdhci_writel(host, mask | SDHCI_CORECTRL_EN, SDHCI_CORECTRL_OFFSET);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Enable interrupts */
59*4882a593Smuzhiyun sdhci_writel(host, SDHCI_COREIMR_IP, SDHCI_COREIMR_OFFSET);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* Make sure Card is detected in controller */
62*4882a593Smuzhiyun mask = sdhci_readl(host, SDHCI_CORESTAT_OFFSET);
63*4882a593Smuzhiyun sdhci_writel(host, mask | SDHCI_CORESTAT_CD_SW, SDHCI_CORESTAT_OFFSET);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* Wait max 100 ms */
66*4882a593Smuzhiyun timeout = 1000;
67*4882a593Smuzhiyun while (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
68*4882a593Smuzhiyun if (timeout == 0) {
69*4882a593Smuzhiyun printf("%s: CARD DETECT timeout error\n", __func__);
70*4882a593Smuzhiyun return -ETIMEDOUT;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun timeout--;
73*4882a593Smuzhiyun udelay(100);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
kona_sdhci_init(int dev_index,u32 min_clk,u32 quirks)78*4882a593Smuzhiyun int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun int ret = 0;
81*4882a593Smuzhiyun u32 max_clk;
82*4882a593Smuzhiyun void *reg_base;
83*4882a593Smuzhiyun struct sdhci_host *host = NULL;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
86*4882a593Smuzhiyun if (!host) {
87*4882a593Smuzhiyun printf("%s: sdhci host malloc fail!\n", __func__);
88*4882a593Smuzhiyun return -ENOMEM;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun switch (dev_index) {
91*4882a593Smuzhiyun case 0:
92*4882a593Smuzhiyun reg_base = (void *)CONFIG_SYS_SDIO_BASE0;
93*4882a593Smuzhiyun ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK,
94*4882a593Smuzhiyun &max_clk);
95*4882a593Smuzhiyun break;
96*4882a593Smuzhiyun case 1:
97*4882a593Smuzhiyun reg_base = (void *)CONFIG_SYS_SDIO_BASE1;
98*4882a593Smuzhiyun ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK,
99*4882a593Smuzhiyun &max_clk);
100*4882a593Smuzhiyun break;
101*4882a593Smuzhiyun case 2:
102*4882a593Smuzhiyun reg_base = (void *)CONFIG_SYS_SDIO_BASE2;
103*4882a593Smuzhiyun ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK,
104*4882a593Smuzhiyun &max_clk);
105*4882a593Smuzhiyun break;
106*4882a593Smuzhiyun case 3:
107*4882a593Smuzhiyun reg_base = (void *)CONFIG_SYS_SDIO_BASE3;
108*4882a593Smuzhiyun ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK,
109*4882a593Smuzhiyun &max_clk);
110*4882a593Smuzhiyun break;
111*4882a593Smuzhiyun default:
112*4882a593Smuzhiyun printf("%s: sdio dev index %d not supported\n",
113*4882a593Smuzhiyun __func__, dev_index);
114*4882a593Smuzhiyun ret = -EINVAL;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun if (ret) {
117*4882a593Smuzhiyun free(host);
118*4882a593Smuzhiyun return ret;
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun host->name = "kona-sdhci";
122*4882a593Smuzhiyun host->ioaddr = reg_base;
123*4882a593Smuzhiyun host->quirks = quirks;
124*4882a593Smuzhiyun host->max_clk = max_clk;
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun if (init_kona_mmc_core(host)) {
127*4882a593Smuzhiyun free(host);
128*4882a593Smuzhiyun return -EINVAL;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun add_sdhci(host, 0, min_clk);
132*4882a593Smuzhiyun return ret;
133*4882a593Smuzhiyun }
134