1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * linux/drivers/mmc/host/sdhci_f_sdh30.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
6*4882a593Smuzhiyun * Vincent Yang <vincent.yang@tw.fujitsu.com>
7*4882a593Smuzhiyun * Copyright (C) 2015 Linaro Ltd Andy Green <andy.green@linaro.org>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/acpi.h>
11*4882a593Smuzhiyun #include <linux/err.h>
12*4882a593Smuzhiyun #include <linux/delay.h>
13*4882a593Smuzhiyun #include <linux/module.h>
14*4882a593Smuzhiyun #include <linux/of.h>
15*4882a593Smuzhiyun #include <linux/property.h>
16*4882a593Smuzhiyun #include <linux/clk.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "sdhci-pltfm.h"
19*4882a593Smuzhiyun #include "sdhci_f_sdh30.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun struct f_sdhost_priv {
22*4882a593Smuzhiyun struct clk *clk_iface;
23*4882a593Smuzhiyun struct clk *clk;
24*4882a593Smuzhiyun u32 vendor_hs200;
25*4882a593Smuzhiyun struct device *dev;
26*4882a593Smuzhiyun bool enable_cmd_dat_delay;
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host * host)29*4882a593Smuzhiyun static void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct f_sdhost_priv *priv = sdhci_priv(host);
32*4882a593Smuzhiyun u32 ctrl = 0;
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun usleep_range(2500, 3000);
35*4882a593Smuzhiyun ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
36*4882a593Smuzhiyun ctrl |= F_SDH30_CRES_O_DN;
37*4882a593Smuzhiyun sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
38*4882a593Smuzhiyun ctrl |= F_SDH30_MSEL_O_1_8;
39*4882a593Smuzhiyun sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun ctrl &= ~F_SDH30_CRES_O_DN;
42*4882a593Smuzhiyun sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
43*4882a593Smuzhiyun usleep_range(2500, 3000);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun if (priv->vendor_hs200) {
46*4882a593Smuzhiyun dev_info(priv->dev, "%s: setting hs200\n", __func__);
47*4882a593Smuzhiyun ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
48*4882a593Smuzhiyun ctrl |= priv->vendor_hs200;
49*4882a593Smuzhiyun sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL);
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
53*4882a593Smuzhiyun ctrl |= F_SDH30_CMD_CHK_DIS;
54*4882a593Smuzhiyun sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
sdhci_f_sdh30_get_min_clock(struct sdhci_host * host)57*4882a593Smuzhiyun static unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun return F_SDH30_MIN_CLOCK;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
sdhci_f_sdh30_reset(struct sdhci_host * host,u8 mask)62*4882a593Smuzhiyun static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun struct f_sdhost_priv *priv = sdhci_priv(host);
65*4882a593Smuzhiyun u32 ctl;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
68*4882a593Smuzhiyun sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun sdhci_reset(host, mask);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun if (priv->enable_cmd_dat_delay) {
73*4882a593Smuzhiyun ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
74*4882a593Smuzhiyun ctl |= F_SDH30_CMD_DAT_DELAY;
75*4882a593Smuzhiyun sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun static const struct sdhci_ops sdhci_f_sdh30_ops = {
80*4882a593Smuzhiyun .voltage_switch = sdhci_f_sdh30_soft_voltage_switch,
81*4882a593Smuzhiyun .get_min_clock = sdhci_f_sdh30_get_min_clock,
82*4882a593Smuzhiyun .reset = sdhci_f_sdh30_reset,
83*4882a593Smuzhiyun .set_clock = sdhci_set_clock,
84*4882a593Smuzhiyun .set_bus_width = sdhci_set_bus_width,
85*4882a593Smuzhiyun .set_uhs_signaling = sdhci_set_uhs_signaling,
86*4882a593Smuzhiyun };
87*4882a593Smuzhiyun
sdhci_f_sdh30_probe(struct platform_device * pdev)88*4882a593Smuzhiyun static int sdhci_f_sdh30_probe(struct platform_device *pdev)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct sdhci_host *host;
91*4882a593Smuzhiyun struct device *dev = &pdev->dev;
92*4882a593Smuzhiyun int irq, ctrl = 0, ret = 0;
93*4882a593Smuzhiyun struct f_sdhost_priv *priv;
94*4882a593Smuzhiyun u32 reg = 0;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun irq = platform_get_irq(pdev, 0);
97*4882a593Smuzhiyun if (irq < 0)
98*4882a593Smuzhiyun return irq;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv));
101*4882a593Smuzhiyun if (IS_ERR(host))
102*4882a593Smuzhiyun return PTR_ERR(host);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun priv = sdhci_priv(host);
105*4882a593Smuzhiyun priv->dev = dev;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
108*4882a593Smuzhiyun SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
109*4882a593Smuzhiyun host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE |
110*4882a593Smuzhiyun SDHCI_QUIRK2_TUNING_WORK_AROUND;
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun priv->enable_cmd_dat_delay = device_property_read_bool(dev,
113*4882a593Smuzhiyun "fujitsu,cmd-dat-delay-select");
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun ret = mmc_of_parse(host->mmc);
116*4882a593Smuzhiyun if (ret)
117*4882a593Smuzhiyun goto err;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun platform_set_drvdata(pdev, host);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun host->hw_name = "f_sdh30";
122*4882a593Smuzhiyun host->ops = &sdhci_f_sdh30_ops;
123*4882a593Smuzhiyun host->irq = irq;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
126*4882a593Smuzhiyun if (IS_ERR(host->ioaddr)) {
127*4882a593Smuzhiyun ret = PTR_ERR(host->ioaddr);
128*4882a593Smuzhiyun goto err;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (dev_of_node(dev)) {
132*4882a593Smuzhiyun sdhci_get_of_property(pdev);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
135*4882a593Smuzhiyun if (IS_ERR(priv->clk_iface)) {
136*4882a593Smuzhiyun ret = PTR_ERR(priv->clk_iface);
137*4882a593Smuzhiyun goto err;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun ret = clk_prepare_enable(priv->clk_iface);
141*4882a593Smuzhiyun if (ret)
142*4882a593Smuzhiyun goto err;
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun priv->clk = devm_clk_get(&pdev->dev, "core");
145*4882a593Smuzhiyun if (IS_ERR(priv->clk)) {
146*4882a593Smuzhiyun ret = PTR_ERR(priv->clk);
147*4882a593Smuzhiyun goto err_clk;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun ret = clk_prepare_enable(priv->clk);
151*4882a593Smuzhiyun if (ret)
152*4882a593Smuzhiyun goto err_clk;
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun /* init vendor specific regs */
156*4882a593Smuzhiyun ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
157*4882a593Smuzhiyun ctrl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
158*4882a593Smuzhiyun F_SDH30_AHB_INCR_4;
159*4882a593Smuzhiyun ctrl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
160*4882a593Smuzhiyun sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun reg = sdhci_readl(host, F_SDH30_ESD_CONTROL);
163*4882a593Smuzhiyun sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
164*4882a593Smuzhiyun msleep(20);
165*4882a593Smuzhiyun sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun reg = sdhci_readl(host, SDHCI_CAPABILITIES);
168*4882a593Smuzhiyun if (reg & SDHCI_CAN_DO_8BIT)
169*4882a593Smuzhiyun priv->vendor_hs200 = F_SDH30_EMMC_HS200;
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun ret = sdhci_add_host(host);
172*4882a593Smuzhiyun if (ret)
173*4882a593Smuzhiyun goto err_add_host;
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun return 0;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun err_add_host:
178*4882a593Smuzhiyun clk_disable_unprepare(priv->clk);
179*4882a593Smuzhiyun err_clk:
180*4882a593Smuzhiyun clk_disable_unprepare(priv->clk_iface);
181*4882a593Smuzhiyun err:
182*4882a593Smuzhiyun sdhci_free_host(host);
183*4882a593Smuzhiyun return ret;
184*4882a593Smuzhiyun }
185*4882a593Smuzhiyun
sdhci_f_sdh30_remove(struct platform_device * pdev)186*4882a593Smuzhiyun static int sdhci_f_sdh30_remove(struct platform_device *pdev)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun struct sdhci_host *host = platform_get_drvdata(pdev);
189*4882a593Smuzhiyun struct f_sdhost_priv *priv = sdhci_priv(host);
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) ==
192*4882a593Smuzhiyun 0xffffffff);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun clk_disable_unprepare(priv->clk_iface);
195*4882a593Smuzhiyun clk_disable_unprepare(priv->clk);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun sdhci_free_host(host);
198*4882a593Smuzhiyun platform_set_drvdata(pdev, NULL);
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return 0;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun #ifdef CONFIG_OF
204*4882a593Smuzhiyun static const struct of_device_id f_sdh30_dt_ids[] = {
205*4882a593Smuzhiyun { .compatible = "fujitsu,mb86s70-sdhci-3.0" },
206*4882a593Smuzhiyun { /* sentinel */ }
207*4882a593Smuzhiyun };
208*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, f_sdh30_dt_ids);
209*4882a593Smuzhiyun #endif
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun #ifdef CONFIG_ACPI
212*4882a593Smuzhiyun static const struct acpi_device_id f_sdh30_acpi_ids[] = {
213*4882a593Smuzhiyun { "SCX0002" },
214*4882a593Smuzhiyun { /* sentinel */ }
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun MODULE_DEVICE_TABLE(acpi, f_sdh30_acpi_ids);
217*4882a593Smuzhiyun #endif
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun static struct platform_driver sdhci_f_sdh30_driver = {
220*4882a593Smuzhiyun .driver = {
221*4882a593Smuzhiyun .name = "f_sdh30",
222*4882a593Smuzhiyun .probe_type = PROBE_PREFER_ASYNCHRONOUS,
223*4882a593Smuzhiyun .of_match_table = of_match_ptr(f_sdh30_dt_ids),
224*4882a593Smuzhiyun .acpi_match_table = ACPI_PTR(f_sdh30_acpi_ids),
225*4882a593Smuzhiyun .pm = &sdhci_pltfm_pmops,
226*4882a593Smuzhiyun },
227*4882a593Smuzhiyun .probe = sdhci_f_sdh30_probe,
228*4882a593Smuzhiyun .remove = sdhci_f_sdh30_remove,
229*4882a593Smuzhiyun };
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun module_platform_driver(sdhci_f_sdh30_driver);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun MODULE_DESCRIPTION("F_SDH30 SD Card Controller driver");
234*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
235*4882a593Smuzhiyun MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD.");
236*4882a593Smuzhiyun MODULE_ALIAS("platform:f_sdh30");
237