1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2013 Broadcom Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
5*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
6*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
10*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11*4882a593Smuzhiyun * GNU General Public License for more details.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/delay.h>
17*4882a593Smuzhiyun #include <linux/highmem.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/mmc/host.h>
20*4882a593Smuzhiyun #include <linux/io.h>
21*4882a593Smuzhiyun #include <linux/clk.h>
22*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
23*4882a593Smuzhiyun #include <linux/of.h>
24*4882a593Smuzhiyun #include <linux/of_device.h>
25*4882a593Smuzhiyun #include <linux/mmc/slot-gpio.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "sdhci-pltfm.h"
28*4882a593Smuzhiyun #include "sdhci.h"
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #define SDHCI_SOFT_RESET 0x01000000
31*4882a593Smuzhiyun #define KONA_SDHOST_CORECTRL 0x8000
32*4882a593Smuzhiyun #define KONA_SDHOST_CD_PINCTRL 0x00000008
33*4882a593Smuzhiyun #define KONA_SDHOST_STOP_HCLK 0x00000004
34*4882a593Smuzhiyun #define KONA_SDHOST_RESET 0x00000002
35*4882a593Smuzhiyun #define KONA_SDHOST_EN 0x00000001
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define KONA_SDHOST_CORESTAT 0x8004
38*4882a593Smuzhiyun #define KONA_SDHOST_WP 0x00000002
39*4882a593Smuzhiyun #define KONA_SDHOST_CD_SW 0x00000001
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define KONA_SDHOST_COREIMR 0x8008
42*4882a593Smuzhiyun #define KONA_SDHOST_IP 0x00000001
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define KONA_SDHOST_COREISR 0x800C
45*4882a593Smuzhiyun #define KONA_SDHOST_COREIMSR 0x8010
46*4882a593Smuzhiyun #define KONA_SDHOST_COREDBG1 0x8014
47*4882a593Smuzhiyun #define KONA_SDHOST_COREGPO_MASK 0x8018
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define SD_DETECT_GPIO_DEBOUNCE_128MS 128
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define KONA_MMC_AUTOSUSPEND_DELAY (50)
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun struct sdhci_bcm_kona_dev {
54*4882a593Smuzhiyun struct mutex write_lock; /* protect back to back writes */
55*4882a593Smuzhiyun };
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun
sdhci_bcm_kona_sd_reset(struct sdhci_host * host)58*4882a593Smuzhiyun static int sdhci_bcm_kona_sd_reset(struct sdhci_host *host)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun unsigned int val;
61*4882a593Smuzhiyun unsigned long timeout;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* This timeout should be sufficent for core to reset */
64*4882a593Smuzhiyun timeout = jiffies + msecs_to_jiffies(100);
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* reset the host using the top level reset */
67*4882a593Smuzhiyun val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
68*4882a593Smuzhiyun val |= KONA_SDHOST_RESET;
69*4882a593Smuzhiyun sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun while (!(sdhci_readl(host, KONA_SDHOST_CORECTRL) & KONA_SDHOST_RESET)) {
72*4882a593Smuzhiyun if (time_is_before_jiffies(timeout)) {
73*4882a593Smuzhiyun pr_err("Error: sd host is stuck in reset!!!\n");
74*4882a593Smuzhiyun return -EFAULT;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /* bring the host out of reset */
79*4882a593Smuzhiyun val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
80*4882a593Smuzhiyun val &= ~KONA_SDHOST_RESET;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
84*4882a593Smuzhiyun * Back-to-Back writes to same register needs delay when SD bus clock
85*4882a593Smuzhiyun * is very low w.r.t AHB clock, mainly during boot-time and during card
86*4882a593Smuzhiyun * insert-removal.
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun usleep_range(1000, 5000);
89*4882a593Smuzhiyun sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun return 0;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
sdhci_bcm_kona_sd_init(struct sdhci_host * host)94*4882a593Smuzhiyun static void sdhci_bcm_kona_sd_init(struct sdhci_host *host)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun unsigned int val;
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /* enable the interrupt from the IP core */
99*4882a593Smuzhiyun val = sdhci_readl(host, KONA_SDHOST_COREIMR);
100*4882a593Smuzhiyun val |= KONA_SDHOST_IP;
101*4882a593Smuzhiyun sdhci_writel(host, val, KONA_SDHOST_COREIMR);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Enable the AHB clock gating module to the host */
104*4882a593Smuzhiyun val = sdhci_readl(host, KONA_SDHOST_CORECTRL);
105*4882a593Smuzhiyun val |= KONA_SDHOST_EN;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun * Back-to-Back register write needs a delay of 1ms at bootup (min 10uS)
109*4882a593Smuzhiyun * Back-to-Back writes to same register needs delay when SD bus clock
110*4882a593Smuzhiyun * is very low w.r.t AHB clock, mainly during boot-time and during card
111*4882a593Smuzhiyun * insert-removal.
112*4882a593Smuzhiyun */
113*4882a593Smuzhiyun usleep_range(1000, 5000);
114*4882a593Smuzhiyun sdhci_writel(host, val, KONA_SDHOST_CORECTRL);
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /*
118*4882a593Smuzhiyun * Software emulation of the SD card insertion/removal. Set insert=1 for insert
119*4882a593Smuzhiyun * and insert=0 for removal. The card detection is done by GPIO. For Broadcom
120*4882a593Smuzhiyun * IP to function properly the bit 0 of CORESTAT register needs to be set/reset
121*4882a593Smuzhiyun * to generate the CD IRQ handled in sdhci.c which schedules card_tasklet.
122*4882a593Smuzhiyun */
sdhci_bcm_kona_sd_card_emulate(struct sdhci_host * host,int insert)123*4882a593Smuzhiyun static int sdhci_bcm_kona_sd_card_emulate(struct sdhci_host *host, int insert)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun struct sdhci_pltfm_host *pltfm_priv = sdhci_priv(host);
126*4882a593Smuzhiyun struct sdhci_bcm_kona_dev *kona_dev = sdhci_pltfm_priv(pltfm_priv);
127*4882a593Smuzhiyun u32 val;
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun * Back-to-Back register write needs a delay of min 10uS.
131*4882a593Smuzhiyun * Back-to-Back writes to same register needs delay when SD bus clock
132*4882a593Smuzhiyun * is very low w.r.t AHB clock, mainly during boot-time and during card
133*4882a593Smuzhiyun * insert-removal.
134*4882a593Smuzhiyun * We keep 20uS
135*4882a593Smuzhiyun */
136*4882a593Smuzhiyun mutex_lock(&kona_dev->write_lock);
137*4882a593Smuzhiyun udelay(20);
138*4882a593Smuzhiyun val = sdhci_readl(host, KONA_SDHOST_CORESTAT);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun if (insert) {
141*4882a593Smuzhiyun int ret;
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun ret = mmc_gpio_get_ro(host->mmc);
144*4882a593Smuzhiyun if (ret >= 0)
145*4882a593Smuzhiyun val = (val & ~KONA_SDHOST_WP) |
146*4882a593Smuzhiyun ((ret) ? KONA_SDHOST_WP : 0);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun val |= KONA_SDHOST_CD_SW;
149*4882a593Smuzhiyun sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
150*4882a593Smuzhiyun } else {
151*4882a593Smuzhiyun val &= ~KONA_SDHOST_CD_SW;
152*4882a593Smuzhiyun sdhci_writel(host, val, KONA_SDHOST_CORESTAT);
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun mutex_unlock(&kona_dev->write_lock);
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun return 0;
157*4882a593Smuzhiyun }
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /*
160*4882a593Smuzhiyun * SD card interrupt event callback
161*4882a593Smuzhiyun */
sdhci_bcm_kona_card_event(struct sdhci_host * host)162*4882a593Smuzhiyun static void sdhci_bcm_kona_card_event(struct sdhci_host *host)
163*4882a593Smuzhiyun {
164*4882a593Smuzhiyun if (mmc_gpio_get_cd(host->mmc) > 0) {
165*4882a593Smuzhiyun dev_dbg(mmc_dev(host->mmc),
166*4882a593Smuzhiyun "card inserted\n");
167*4882a593Smuzhiyun sdhci_bcm_kona_sd_card_emulate(host, 1);
168*4882a593Smuzhiyun } else {
169*4882a593Smuzhiyun dev_dbg(mmc_dev(host->mmc),
170*4882a593Smuzhiyun "card removed\n");
171*4882a593Smuzhiyun sdhci_bcm_kona_sd_card_emulate(host, 0);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
sdhci_bcm_kona_init_74_clocks(struct sdhci_host * host,u8 power_mode)175*4882a593Smuzhiyun static void sdhci_bcm_kona_init_74_clocks(struct sdhci_host *host,
176*4882a593Smuzhiyun u8 power_mode)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun /*
179*4882a593Smuzhiyun * JEDEC and SD spec specify supplying 74 continuous clocks to
180*4882a593Smuzhiyun * device after power up. With minimum bus (100KHz) that
181*4882a593Smuzhiyun * that translates to 740us
182*4882a593Smuzhiyun */
183*4882a593Smuzhiyun if (power_mode != MMC_POWER_OFF)
184*4882a593Smuzhiyun udelay(740);
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun static const struct sdhci_ops sdhci_bcm_kona_ops = {
188*4882a593Smuzhiyun .set_clock = sdhci_set_clock,
189*4882a593Smuzhiyun .get_max_clock = sdhci_pltfm_clk_get_max_clock,
190*4882a593Smuzhiyun .get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
191*4882a593Smuzhiyun .platform_send_init_74_clocks = sdhci_bcm_kona_init_74_clocks,
192*4882a593Smuzhiyun .set_bus_width = sdhci_set_bus_width,
193*4882a593Smuzhiyun .reset = sdhci_reset,
194*4882a593Smuzhiyun .set_uhs_signaling = sdhci_set_uhs_signaling,
195*4882a593Smuzhiyun .card_event = sdhci_bcm_kona_card_event,
196*4882a593Smuzhiyun };
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun static const struct sdhci_pltfm_data sdhci_pltfm_data_kona = {
199*4882a593Smuzhiyun .ops = &sdhci_bcm_kona_ops,
200*4882a593Smuzhiyun .quirks = SDHCI_QUIRK_NO_CARD_NO_RESET |
201*4882a593Smuzhiyun SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_32BIT_DMA_ADDR |
202*4882a593Smuzhiyun SDHCI_QUIRK_32BIT_DMA_SIZE | SDHCI_QUIRK_32BIT_ADMA_SIZE |
203*4882a593Smuzhiyun SDHCI_QUIRK_FORCE_BLK_SZ_2048 |
204*4882a593Smuzhiyun SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
205*4882a593Smuzhiyun };
206*4882a593Smuzhiyun
207*4882a593Smuzhiyun static const struct of_device_id sdhci_bcm_kona_of_match[] = {
208*4882a593Smuzhiyun { .compatible = "brcm,kona-sdhci"},
209*4882a593Smuzhiyun { .compatible = "bcm,kona-sdhci"}, /* deprecated name */
210*4882a593Smuzhiyun {}
211*4882a593Smuzhiyun };
212*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, sdhci_bcm_kona_of_match);
213*4882a593Smuzhiyun
sdhci_bcm_kona_probe(struct platform_device * pdev)214*4882a593Smuzhiyun static int sdhci_bcm_kona_probe(struct platform_device *pdev)
215*4882a593Smuzhiyun {
216*4882a593Smuzhiyun struct sdhci_bcm_kona_dev *kona_dev = NULL;
217*4882a593Smuzhiyun struct sdhci_pltfm_host *pltfm_priv;
218*4882a593Smuzhiyun struct device *dev = &pdev->dev;
219*4882a593Smuzhiyun struct sdhci_host *host;
220*4882a593Smuzhiyun int ret;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun ret = 0;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun host = sdhci_pltfm_init(pdev, &sdhci_pltfm_data_kona,
225*4882a593Smuzhiyun sizeof(*kona_dev));
226*4882a593Smuzhiyun if (IS_ERR(host))
227*4882a593Smuzhiyun return PTR_ERR(host);
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun dev_dbg(dev, "%s: inited. IOADDR=%p\n", __func__, host->ioaddr);
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun pltfm_priv = sdhci_priv(host);
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun kona_dev = sdhci_pltfm_priv(pltfm_priv);
234*4882a593Smuzhiyun mutex_init(&kona_dev->write_lock);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun ret = mmc_of_parse(host->mmc);
237*4882a593Smuzhiyun if (ret)
238*4882a593Smuzhiyun goto err_pltfm_free;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun if (!host->mmc->f_max) {
241*4882a593Smuzhiyun dev_err(&pdev->dev, "Missing max-freq for SDHCI cfg\n");
242*4882a593Smuzhiyun ret = -ENXIO;
243*4882a593Smuzhiyun goto err_pltfm_free;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun /* Get and enable the core clock */
247*4882a593Smuzhiyun pltfm_priv->clk = devm_clk_get(dev, NULL);
248*4882a593Smuzhiyun if (IS_ERR(pltfm_priv->clk)) {
249*4882a593Smuzhiyun dev_err(dev, "Failed to get core clock\n");
250*4882a593Smuzhiyun ret = PTR_ERR(pltfm_priv->clk);
251*4882a593Smuzhiyun goto err_pltfm_free;
252*4882a593Smuzhiyun }
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun ret = clk_set_rate(pltfm_priv->clk, host->mmc->f_max);
255*4882a593Smuzhiyun if (ret) {
256*4882a593Smuzhiyun dev_err(dev, "Failed to set rate core clock\n");
257*4882a593Smuzhiyun goto err_pltfm_free;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun ret = clk_prepare_enable(pltfm_priv->clk);
261*4882a593Smuzhiyun if (ret) {
262*4882a593Smuzhiyun dev_err(dev, "Failed to enable core clock\n");
263*4882a593Smuzhiyun goto err_pltfm_free;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun dev_dbg(dev, "non-removable=%c\n",
267*4882a593Smuzhiyun mmc_card_is_removable(host->mmc) ? 'N' : 'Y');
268*4882a593Smuzhiyun dev_dbg(dev, "cd_gpio %c, wp_gpio %c\n",
269*4882a593Smuzhiyun (mmc_gpio_get_cd(host->mmc) != -ENOSYS) ? 'Y' : 'N',
270*4882a593Smuzhiyun (mmc_gpio_get_ro(host->mmc) != -ENOSYS) ? 'Y' : 'N');
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun if (!mmc_card_is_removable(host->mmc))
273*4882a593Smuzhiyun host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun dev_dbg(dev, "is_8bit=%c\n",
276*4882a593Smuzhiyun (host->mmc->caps & MMC_CAP_8_BIT_DATA) ? 'Y' : 'N');
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun ret = sdhci_bcm_kona_sd_reset(host);
279*4882a593Smuzhiyun if (ret)
280*4882a593Smuzhiyun goto err_clk_disable;
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun sdhci_bcm_kona_sd_init(host);
283*4882a593Smuzhiyun
284*4882a593Smuzhiyun ret = sdhci_add_host(host);
285*4882a593Smuzhiyun if (ret)
286*4882a593Smuzhiyun goto err_reset;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /* if device is eMMC, emulate card insert right here */
289*4882a593Smuzhiyun if (!mmc_card_is_removable(host->mmc)) {
290*4882a593Smuzhiyun ret = sdhci_bcm_kona_sd_card_emulate(host, 1);
291*4882a593Smuzhiyun if (ret) {
292*4882a593Smuzhiyun dev_err(dev,
293*4882a593Smuzhiyun "unable to emulate card insertion\n");
294*4882a593Smuzhiyun goto err_remove_host;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun }
297*4882a593Smuzhiyun /*
298*4882a593Smuzhiyun * Since the card detection GPIO interrupt is configured to be
299*4882a593Smuzhiyun * edge sensitive, check the initial GPIO value here, emulate
300*4882a593Smuzhiyun * only if the card is present
301*4882a593Smuzhiyun */
302*4882a593Smuzhiyun if (mmc_gpio_get_cd(host->mmc) > 0)
303*4882a593Smuzhiyun sdhci_bcm_kona_sd_card_emulate(host, 1);
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun dev_dbg(dev, "initialized properly\n");
306*4882a593Smuzhiyun return 0;
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun err_remove_host:
309*4882a593Smuzhiyun sdhci_remove_host(host, 0);
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun err_reset:
312*4882a593Smuzhiyun sdhci_bcm_kona_sd_reset(host);
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun err_clk_disable:
315*4882a593Smuzhiyun clk_disable_unprepare(pltfm_priv->clk);
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun err_pltfm_free:
318*4882a593Smuzhiyun sdhci_pltfm_free(pdev);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun dev_err(dev, "Probing of sdhci-pltfm failed: %d\n", ret);
321*4882a593Smuzhiyun return ret;
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun static struct platform_driver sdhci_bcm_kona_driver = {
325*4882a593Smuzhiyun .driver = {
326*4882a593Smuzhiyun .name = "sdhci-kona",
327*4882a593Smuzhiyun .probe_type = PROBE_PREFER_ASYNCHRONOUS,
328*4882a593Smuzhiyun .pm = &sdhci_pltfm_pmops,
329*4882a593Smuzhiyun .of_match_table = sdhci_bcm_kona_of_match,
330*4882a593Smuzhiyun },
331*4882a593Smuzhiyun .probe = sdhci_bcm_kona_probe,
332*4882a593Smuzhiyun .remove = sdhci_pltfm_unregister,
333*4882a593Smuzhiyun };
334*4882a593Smuzhiyun module_platform_driver(sdhci_bcm_kona_driver);
335*4882a593Smuzhiyun
336*4882a593Smuzhiyun MODULE_DESCRIPTION("SDHCI driver for Broadcom Kona platform");
337*4882a593Smuzhiyun MODULE_AUTHOR("Broadcom");
338*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
339