| /utopia/UTPA2-700.0.x/modules/dmx/hal/maldives/tsp/ |
| H A D | halTSP.c | 130 static MS_U32 _u32RegBase = 0; variable
201 #define TSP_INT_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x3200 + ((addr)<<2))))
203 #define TSP_CLKGEN0_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x1600 + ((addr)<<2))))
243 #define TSP_CLKGEN1_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x6600 + ((addr)<<2))))
254 #define TSP_TOP_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x3c00 + ((addr)<<2))))
281 #define TSP_TSO0_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x27400UL + ((addr)<<2UL))…
292 #define TSP_TS_SAMPLE_REG(addr) (*((volatile MS_U16*)(_u32RegBase + 0x21600 + ((addr)<<2)…
371 #define ADDR_INDR_CTRL (_u32RegBase+ 0x2b20)
372 #define ADDR_INDR_ADDR0 (_u32RegBase+ 0x2b24)
373 #define ADDR_INDR_ADDR1 (_u32RegBase+ 0x2b28)
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6lite/otv/ |
| H A D | halOTV.c | 112 static MS_VIRT _u32RegBase = 0; variable
170 _u32RegBase = u32BankAddr; in HAL_OTV_SetBank()
172 _OTVReg[0] = (REG_OTV*)(_u32RegBase + OTV0_REG_CTRL_BASE); in HAL_OTV_SetBank()
173 _u32OTV_PidfltBase[0] = _u32RegBase + OTV0_PIDFLT_BASE; in HAL_OTV_SetBank()
174 _u32OTV_EventMaskBase[0] = _u32RegBase + OTV0_EVENT_MASK_BASE; in HAL_OTV_SetBank()
177 _OTVReg[1] = (REG_OTV*)(_u32RegBase + OTV1_REG_CTRL_BASE); in HAL_OTV_SetBank()
178 _u32OTV_PidfltBase[1] = _u32RegBase + OTV1_PIDFLT_BASE; in HAL_OTV_SetBank()
179 _u32OTV_EventMaskBase[1] = _u32RegBase + OTV1_EVENT_MASK_BASE; in HAL_OTV_SetBank()
182 _OTVReg[2] = (REG_OTV*)(_u32RegBase + OTV2_REG_CTRL_BASE); in HAL_OTV_SetBank()
183 _u32OTV_PidfltBase[2] = _u32RegBase + OTV2_PIDFLT_BASE; in HAL_OTV_SetBank()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/k6/otv/ |
| H A D | halOTV.c | 112 static MS_VIRT _u32RegBase = 0; variable
170 _u32RegBase = u32BankAddr; in HAL_OTV_SetBank()
172 _OTVReg[0] = (REG_OTV*)(_u32RegBase + OTV0_REG_CTRL_BASE); in HAL_OTV_SetBank()
173 _u32OTV_PidfltBase[0] = _u32RegBase + OTV0_PIDFLT_BASE; in HAL_OTV_SetBank()
174 _u32OTV_EventMaskBase[0] = _u32RegBase + OTV0_EVENT_MASK_BASE; in HAL_OTV_SetBank()
177 _OTVReg[1] = (REG_OTV*)(_u32RegBase + OTV1_REG_CTRL_BASE); in HAL_OTV_SetBank()
178 _u32OTV_PidfltBase[1] = _u32RegBase + OTV1_PIDFLT_BASE; in HAL_OTV_SetBank()
179 _u32OTV_EventMaskBase[1] = _u32RegBase + OTV1_EVENT_MASK_BASE; in HAL_OTV_SetBank()
182 _OTVReg[2] = (REG_OTV*)(_u32RegBase + OTV2_REG_CTRL_BASE); in HAL_OTV_SetBank()
183 _u32OTV_PidfltBase[2] = _u32RegBase + OTV2_PIDFLT_BASE; in HAL_OTV_SetBank()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/kano/otv/ |
| H A D | halOTV.c | 112 static MS_VIRT _u32RegBase = 0; variable
170 _u32RegBase = u32BankAddr; in HAL_OTV_SetBank()
172 _OTVReg[0] = (REG_OTV*)(_u32RegBase + OTV0_REG_CTRL_BASE); in HAL_OTV_SetBank()
173 _u32OTV_PidfltBase[0] = _u32RegBase + OTV0_PIDFLT_BASE; in HAL_OTV_SetBank()
174 _u32OTV_EventMaskBase[0] = _u32RegBase + OTV0_EVENT_MASK_BASE; in HAL_OTV_SetBank()
177 _OTVReg[1] = (REG_OTV*)(_u32RegBase + OTV1_REG_CTRL_BASE); in HAL_OTV_SetBank()
178 _u32OTV_PidfltBase[1] = _u32RegBase + OTV1_PIDFLT_BASE; in HAL_OTV_SetBank()
179 _u32OTV_EventMaskBase[1] = _u32RegBase + OTV1_EVENT_MASK_BASE; in HAL_OTV_SetBank()
182 _OTVReg[2] = (REG_OTV*)(_u32RegBase + OTV2_REG_CTRL_BASE); in HAL_OTV_SetBank()
183 _u32OTV_PidfltBase[2] = _u32RegBase + OTV2_PIDFLT_BASE; in HAL_OTV_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/maxim/aesdma/ |
| H A D | halAESDMA.c | 114 static MS_VIRT _u32RegBase = NULL; variable
158 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
160 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
161 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
162 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
164 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
165 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
166 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
167 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
168 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/manhattan/aesdma/ |
| H A D | halAESDMA.c | 114 static MS_VIRT _u32RegBase = NULL; variable
158 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
160 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
161 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
162 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
164 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
165 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
166 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
167 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
168 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/M7621/aesdma/ |
| H A D | halAESDMA.c | 114 static MS_VIRT _u32RegBase = NULL; variable
158 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
160 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
161 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
162 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
164 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
165 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
166 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
167 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
168 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/macan/aesdma/ |
| H A D | halAESDMA.c | 117 static MS_VIRT _u32RegBase = NULL; variable
159 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
161 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
162 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
163 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
165 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
166 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
167 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
168 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
169 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/maserati/aesdma/ |
| H A D | halAESDMA.c | 130 static MS_VIRT _u32RegBase = NULL; variable
174 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
176 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
177 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
178 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
180 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
181 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
182 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
183 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
184 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/M7821/aesdma/ |
| H A D | halAESDMA.c | 130 static MS_VIRT _u32RegBase = NULL; variable
174 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
176 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
177 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
178 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
180 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
181 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
182 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
183 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
184 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/mainz/aesdma/ |
| H A D | halAESDMA.c | 118 static MS_VIRT _u32RegBase = NULL; variable
158 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
160 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
161 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
162 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
164 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
165 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
166 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
167 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
168 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/messi/aesdma/ |
| H A D | halAESDMA.c | 118 static MS_VIRT _u32RegBase = NULL; variable
158 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
160 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
161 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
162 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
164 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
165 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
166 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
167 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
168 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/curry/nsk2/ |
| H A D | halNDSRASP.c | 115 static MS_U32 _u32RegBase = 0; variable
320 _u32RegBase = u32BankAddr; in HAL_NDSRASP_SetBank()
321 _RASPReg[0] = (REG_RASP*)(_u32RegBase + RASP0_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
322 _u32RASP_PidfltBase[0] = _u32RegBase + RASP0_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
323 _u32RASP_EventMaskBase[0] = _u32RegBase + RASP0_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
324 _u32RASP_PayloadMaskBase[0] = _u32RegBase + RASP0_BANK1_PAYLOAD_MASK_BASE; in HAL_NDSRASP_SetBank()
325 _u32RASP_EcmPidfltBase[0] = _u32RegBase + RASP0_BANK1_ECM_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
327 _RASPReg[1] = (REG_RASP*)(_u32RegBase + RASP1_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
328 _u32RASP_PidfltBase[1] = _u32RegBase + RASP1_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
329 _u32RASP_EventMaskBase[1] = _u32RegBase + RASP1_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6/nsk2/ |
| H A D | halNDSRASP.c | 115 static MS_U32 _u32RegBase = 0; variable
320 _u32RegBase = u32BankAddr; in HAL_NDSRASP_SetBank()
321 _RASPReg[0] = (REG_RASP*)(_u32RegBase + RASP0_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
322 _u32RASP_PidfltBase[0] = _u32RegBase + RASP0_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
323 _u32RASP_EventMaskBase[0] = _u32RegBase + RASP0_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
324 _u32RASP_PayloadMaskBase[0] = _u32RegBase + RASP0_BANK1_PAYLOAD_MASK_BASE; in HAL_NDSRASP_SetBank()
325 _u32RASP_EcmPidfltBase[0] = _u32RegBase + RASP0_BANK1_ECM_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
327 _RASPReg[1] = (REG_RASP*)(_u32RegBase + RASP1_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
328 _u32RASP_PidfltBase[1] = _u32RegBase + RASP1_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
329 _u32RASP_EventMaskBase[1] = _u32RegBase + RASP1_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/kano/nsk2/ |
| H A D | halNDSRASP.c | 115 static MS_U32 _u32RegBase = 0; variable
320 _u32RegBase = u32BankAddr; in HAL_NDSRASP_SetBank()
321 _RASPReg[0] = (REG_RASP*)(_u32RegBase + RASP0_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
322 _u32RASP_PidfltBase[0] = _u32RegBase + RASP0_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
323 _u32RASP_EventMaskBase[0] = _u32RegBase + RASP0_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
324 _u32RASP_PayloadMaskBase[0] = _u32RegBase + RASP0_BANK1_PAYLOAD_MASK_BASE; in HAL_NDSRASP_SetBank()
325 _u32RASP_EcmPidfltBase[0] = _u32RegBase + RASP0_BANK1_ECM_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
327 _RASPReg[1] = (REG_RASP*)(_u32RegBase + RASP1_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
328 _u32RASP_PidfltBase[1] = _u32RegBase + RASP1_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
329 _u32RASP_EventMaskBase[1] = _u32RegBase + RASP1_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k7u/nsk2/ |
| H A D | halNDSRASP.c | 115 static MS_U32 _u32RegBase = 0; variable
320 _u32RegBase = u32BankAddr; in HAL_NDSRASP_SetBank()
321 _RASPReg[0] = (REG_RASP*)(_u32RegBase + RASP0_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
322 _u32RASP_PidfltBase[0] = _u32RegBase + RASP0_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
323 _u32RASP_EventMaskBase[0] = _u32RegBase + RASP0_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
324 _u32RASP_PayloadMaskBase[0] = _u32RegBase + RASP0_BANK1_PAYLOAD_MASK_BASE; in HAL_NDSRASP_SetBank()
325 _u32RASP_EcmPidfltBase[0] = _u32RegBase + RASP0_BANK1_ECM_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
327 _RASPReg[1] = (REG_RASP*)(_u32RegBase + RASP1_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
328 _u32RASP_PidfltBase[1] = _u32RegBase + RASP1_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
329 _u32RASP_EventMaskBase[1] = _u32RegBase + RASP1_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
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| /utopia/UTPA2-700.0.x/modules/dscmb/hal/k6lite/nsk2/ |
| H A D | halNDSRASP.c | 115 static MS_U32 _u32RegBase = 0; variable
320 _u32RegBase = u32BankAddr; in HAL_NDSRASP_SetBank()
321 _RASPReg[0] = (REG_RASP*)(_u32RegBase + RASP0_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
322 _u32RASP_PidfltBase[0] = _u32RegBase + RASP0_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
323 _u32RASP_EventMaskBase[0] = _u32RegBase + RASP0_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
324 _u32RASP_PayloadMaskBase[0] = _u32RegBase + RASP0_BANK1_PAYLOAD_MASK_BASE; in HAL_NDSRASP_SetBank()
325 _u32RASP_EcmPidfltBase[0] = _u32RegBase + RASP0_BANK1_ECM_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
327 _RASPReg[1] = (REG_RASP*)(_u32RegBase + RASP1_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
328 _u32RASP_PidfltBase[1] = _u32RegBase + RASP1_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
329 _u32RASP_EventMaskBase[1] = _u32RegBase + RASP1_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/mooney/aesdma/ |
| H A D | halAESDMA.c | 115 static MS_VIRT _u32RegBase = NULL; variable
154 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
156 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
157 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
158 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
160 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
161 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
162 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
163 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
164 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/curry/cipher/ |
| H A D | halCIPHER.c | 63 static MS_VIRT _u32RegBase = 0; variable
598 _u32RegBase = u32BankAddr; in HAL_CIPHER_SetBank()
599 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_CIPHER_SetBank()
1178 MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_DMA_Start()
1179 REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf); //enable MIU crossbar in HAL_CIPHER_DMA_Start()
1342 MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_OTPHash_Start()
1343 REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf); //enable MIU crossbar in HAL_CIPHER_OTPHash_Start()
1578 MS_U16 u16MaskTmp = REG16_R(_u32RegBase + REG_HST0_FIQ_MASK_63_48); in HAL_CIPHER_IntEnable()
1580 REG16_W(_u32RegBase + REG_HST0_FIQ_MASK_63_48, u16MaskTmp); in HAL_CIPHER_IntEnable()
1585 …REG16_W(_u32RegBase + REG_HST0_FIQ_STATUS_63_48, REG_HTS0_FIQ_CRYPTODMA); //set 1 to clear interru… in HAL_CIPHER_IntClear()
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| /utopia/UTPA2-700.0.x/modules/security/hal/mustang/aesdma/ |
| H A D | halAESDMA.c | 115 static MS_U32 _u32RegBase = NULL; variable
153 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
155 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
156 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
157 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
159 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
160 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
161 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
162 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
163 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/maldives/aesdma/ |
| H A D | halAESDMA.c | 115 static MS_U32 _u32RegBase = NULL; variable
153 _u32RegBase = u32NonPmBankAddr; in HAL_AESDMA_SetBank()
155 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE); in HAL_AESDMA_SetBank()
156 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE); in HAL_AESDMA_SetBank()
157 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE); in HAL_AESDMA_SetBank()
159 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE); in HAL_AESDMA_SetBank()
160 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_AESDMA_SetBank()
161 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE); in HAL_AESDMA_SetBank()
162 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE); in HAL_AESDMA_SetBank()
163 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE); in HAL_AESDMA_SetBank()
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| /utopia/UTPA2-700.0.x/modules/security/hal/k6/cipher/ |
| H A D | halCIPHER.c | 63 static MS_VIRT _u32RegBase = 0; variable
543 _u32RegBase = u32BankAddr; in HAL_CIPHER_SetBank()
544 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_CIPHER_SetBank()
1137 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_DMA_Start()
1138 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_DMA_Start()
1301 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_OTPHash_Start()
1302 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_OTPHash_Start()
1537 MS_U16 u16MaskTmp = REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48); in HAL_CIPHER_IntEnable()
1539 REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48) = u16MaskTmp; in HAL_CIPHER_IntEnable()
1544 …REG16(_u32RegBase + REG_HST0_FIQ_STATUS_63_48) = REG_HTS0_FIQ_CRYPTODMA; //set 1 to clear interrupt in HAL_CIPHER_IntClear()
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| /utopia/UTPA2-700.0.x/modules/security/hal/kano/cipher/ |
| H A D | halCIPHER.c | 63 static MS_VIRT _u32RegBase = 0; variable
540 _u32RegBase = u32BankAddr; in HAL_CIPHER_SetBank()
541 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_CIPHER_SetBank()
1134 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_DMA_Start()
1135 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_DMA_Start()
1298 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_OTPHash_Start()
1299 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_OTPHash_Start()
1534 MS_U16 u16MaskTmp = REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48); in HAL_CIPHER_IntEnable()
1536 REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48) = u16MaskTmp; in HAL_CIPHER_IntEnable()
1541 …REG16(_u32RegBase + REG_HST0_FIQ_STATUS_63_48) = REG_HTS0_FIQ_CRYPTODMA; //set 1 to clear interrupt in HAL_CIPHER_IntClear()
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| /utopia/UTPA2-700.0.x/modules/security/hal/k6lite/cipher/ |
| H A D | halCIPHER.c | 63 static MS_VIRT _u32RegBase = 0; variable
543 _u32RegBase = u32BankAddr; in HAL_CIPHER_SetBank()
544 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE); in HAL_CIPHER_SetBank()
1137 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_DMA_Start()
1138 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_DMA_Start()
1301 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613 in HAL_CIPHER_OTPHash_Start()
1302 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar in HAL_CIPHER_OTPHash_Start()
1537 MS_U16 u16MaskTmp = REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48); in HAL_CIPHER_IntEnable()
1539 REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48) = u16MaskTmp; in HAL_CIPHER_IntEnable()
1544 …REG16(_u32RegBase + REG_HST0_FIQ_STATUS_63_48) = REG_HTS0_FIQ_CRYPTODMA; //set 1 to clear interrupt in HAL_CIPHER_IntClear()
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| /utopia/UTPA2-700.0.x/modules/dmx/hal/curry/otv/ |
| H A D | halOTV.c | 112 static MS_VIRT _u32RegBase = 0; variable
170 _u32RegBase = u32BankAddr; in HAL_OTV_SetBank()
172 _OTVReg[0] = (REG_OTV*)(_u32RegBase + OTV0_REG_CTRL_BASE); in HAL_OTV_SetBank()
173 _u32OTV_PidfltBase[0] = _u32RegBase + OTV0_PIDFLT_BASE; in HAL_OTV_SetBank()
174 _u32OTV_EventMaskBase[0] = _u32RegBase + OTV0_EVENT_MASK_BASE; in HAL_OTV_SetBank()
177 _OTVReg[1] = (REG_OTV*)(_u32RegBase + OTV1_REG_CTRL_BASE); in HAL_OTV_SetBank()
178 _u32OTV_PidfltBase[1] = _u32RegBase + OTV1_PIDFLT_BASE; in HAL_OTV_SetBank()
179 _u32OTV_EventMaskBase[1] = _u32RegBase + OTV1_EVENT_MASK_BASE; in HAL_OTV_SetBank()
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