Lines Matching refs:_u32RegBase
115 static MS_U32 _u32RegBase = 0; variable
320 _u32RegBase = u32BankAddr; in HAL_NDSRASP_SetBank()
321 _RASPReg[0] = (REG_RASP*)(_u32RegBase + RASP0_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
322 _u32RASP_PidfltBase[0] = _u32RegBase + RASP0_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
323 _u32RASP_EventMaskBase[0] = _u32RegBase + RASP0_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
324 _u32RASP_PayloadMaskBase[0] = _u32RegBase + RASP0_BANK1_PAYLOAD_MASK_BASE; in HAL_NDSRASP_SetBank()
325 _u32RASP_EcmPidfltBase[0] = _u32RegBase + RASP0_BANK1_ECM_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
327 _RASPReg[1] = (REG_RASP*)(_u32RegBase + RASP1_BANK0_REG_CTRL_BASE); in HAL_NDSRASP_SetBank()
328 _u32RASP_PidfltBase[1] = _u32RegBase + RASP1_BANK0_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
329 _u32RASP_EventMaskBase[1] = _u32RegBase + RASP1_BANK1_EVENT_MASK_BASE; in HAL_NDSRASP_SetBank()
330 _u32RASP_PayloadMaskBase[1] = _u32RegBase + RASP1_BANK1_PAYLOAD_MASK_BASE; in HAL_NDSRASP_SetBank()
331 _u32RASP_EcmPidfltBase[1] = _u32RegBase + RASP1_BANK1_ECM_PIDFLT_BASE; in HAL_NDSRASP_SetBank()
333 _REG_RASP1_MIU = (REG16*)(_u32RegBase + _REG_RASP1_MIU_BASE); in HAL_NDSRASP_SetBank()
335 _gRaspFileIn_Addr[0] = _u32RegBase + REG_RASP0_FILE_BASE; in HAL_NDSRASP_SetBank()
336 _gRaspFileIn_Addr[1] = _u32RegBase + REG_RASP1_FILE_BASE; in HAL_NDSRASP_SetBank()
338 _gRaspEng_Addr[0] = _u32RegBase + REG_RASP0_BASE; in HAL_NDSRASP_SetBank()
339 _gRaspEng_Addr[1] = _u32RegBase + REG_RASP1_BASE; in HAL_NDSRASP_SetBank()
341 _gChipTp_Addr = _u32RegBase + REG_CHIPTOP_RP_BASE; in HAL_NDSRASP_SetBank()
342 _gClkGen_Addr = _u32RegBase + REG_CLKGEN_RP_BASE; in HAL_NDSRASP_SetBank()
343 _gClkGen2_Addr = _u32RegBase + REG_CLKGEN2_BASE; in HAL_NDSRASP_SetBank()
380 addr = _u32RegBase + (0x161300*2 + 0x00*4); //$ enable MIUCrossbar in HAL_NDSRASP_Init()
383 addr = _u32RegBase + (0x161300*2 + 0x1b*4); //$ enable gate clock in HAL_NDSRASP_Init()