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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halAESDMA.c
97 // @brief AESDMA HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100
101 #include "MsCommon.h"
102 #include "regAESDMA.h"
103 #include "halAESDMA.h"
104 #include "halCHIP.h"
105
106
107 //--------------------------------------------------------------------------------------------------
108 // Driver Compiler Option
109 //--------------------------------------------------------------------------------------------------
110
111
112 //--------------------------------------------------------------------------------------------------
113 // TSP Hardware Abstraction Layer
114 //--------------------------------------------------------------------------------------------------
115 static MS_U32 _u32RegBase = NULL;
116 static MS_U32 _u32PmRegBase = NULL;
117 static MS_U32 SECUREBASECtrl_Buffer;
118 static REG_AESDMACtrl *_AESDMACtrl = (REG_AESDMACtrl*)REG_AESDMACTRL_BASE;
119 static REG_SHARNGCtrl *_SHARNGCtrl = (REG_SHARNGCtrl*)REG_SHARNGCTRL_BASE;
120 static REG_AESDMAClk *_AESDMAClk = (REG_AESDMAClk*)REG_AESDMACLK_BASE;
121 static REG_AESDMAMbx *_AESDMAMbx = (REG_AESDMAMbx*)REG_AESDMAMBX_BASE;
122 static REG_PARSERCtrl *_PARSERCtrl = (REG_PARSERCtrl*)REG_PARSERCTRL_BASE;
123 static REG_CIPHERCtrl *_CIPHERCtrl = (REG_CIPHERCtrl*)REG_CIPHERCTRL_BASE;
124 static REG_DMASECURECtrl *_DMASECURECtrl = (REG_DMASECURECtrl*)REG_DMASECURE_BASE;
125 static REG_SECUREBASECtrl *_SECUREBASECtrl = (REG_SECUREBASECtrl*)REG_DMASECURE_CTRL_BASE;
126 static REG_AESDMACtrlEx *_AESDMACtrlEx = (REG_AESDMACtrlEx*)REG_AESDMAEXT_BASE;
127 static REG_HDCP22Data *_HDCP22Data = (REG_HDCP22Data*)REG_HDCP22_BASE;
128 static REG_HDCP22SEKCtrl *_HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)REG_HDCP22_SEK;
129 #define REG32_W(reg, value) do { \
130 (reg)->H = ((value) >> 16); \
131 (reg)->L = ((value) & 0x0000FFFF); \
132 } while(0)
133
134 //--------------------------------------------------------------------------------------------------
135 // Macro of bit operations
136 //--------------------------------------------------------------------------------------------------
137
_AESDMA_REG32_R(REG32 * reg)138 MS_U32 _AESDMA_REG32_R(REG32 *reg)
139 {
140 MS_U32 value;
141
142 value = (reg)->H << 16;
143 value |= (reg)->L;
144
145 return value;
146 }
147
148 //--------------------------------------------------------------------------------------------------
149 // Inline Function
150 //--------------------------------------------------------------------------------------------------
HAL_AESDMA_SetBank(MS_U32 u32NonPmBankAddr,MS_U32 u32PmBankAddr)151 void HAL_AESDMA_SetBank(MS_U32 u32NonPmBankAddr, MS_U32 u32PmBankAddr)
152 {
153 _u32RegBase = u32NonPmBankAddr;
154 _u32PmRegBase = u32PmBankAddr;
155 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE);
156 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE);
157 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE);
158 _AESDMAMbx = (REG_AESDMAMbx*)(_u32PmRegBase + REG_AESDMAMBX_BASE);
159 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE);
160 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);
161 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE);
162 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE);
163 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE);
164 _HDCP22Data = (REG_HDCP22Data*)(_u32RegBase + REG_HDCP22_BASE);
165 _HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)(_u32RegBase + REG_HDCP22_SEK);
166 }
167
AESDMA_GetMIU1Base(void)168 MS_U32 AESDMA_GetMIU1Base(void)
169 {
170 return HAL_MIU1_BASE;
171 }
172
AESDMA_GetMIU2Base(void)173 MS_U32 AESDMA_GetMIU2Base(void)
174 {
175 //not support
176 return FALSE;
177 }
178
AESDMA_Reset(void)179 void AESDMA_Reset(void)
180 {
181 MS_U32 Reg_AESDMA;
182 int i = 0;
183 Reg_AESDMA = (MS_U32)(&_AESDMACtrl[0].Dma_Ctrl);
184
185 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
186 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST)); // sw rst
187 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RST));
188
189 // reset all AESdma register
190 for (i = 0 ; i < 19 ; i++)
191 {
192 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
193 }
194 // reset secure_dma3_ctrl register
195 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
196
197 // reset hw_parser_ctrl register
198 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x01000000);
199 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
200 }
201
AESDMA_Set_CipherKey(MS_U32 * cipherkey)202 void AESDMA_Set_CipherKey(MS_U32 *cipherkey)
203 {
204 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
205 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
206 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
207 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
208 }
209
AESDMA_Set_InitVector(MS_U32 * pInitVector)210 void AESDMA_Set_InitVector(MS_U32 *pInitVector)
211 {
212 REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_L), pInitVector[0]);
213 REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_H), pInitVector[1]);
214 REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_L), pInitVector[2]);
215 REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_H), pInitVector[3]);
216 }
217
AESDMA_Sel_Key(MS_BOOL keysel)218 void AESDMA_Sel_Key(MS_BOOL keysel)
219 {
220 }
221
AESDMA_Sel_SecureKey(void)222 void AESDMA_Sel_SecureKey(void)
223 {
224 MS_U32 u32Ctrl = _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2);
225 u32Ctrl |= AESDMA_USE_SECRET_KEY;
226 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), u32Ctrl);
227 }
228
AESDMA_Set_FileinDesc(MS_U32 FileinAddr,MS_U32 FileinNum)229 void AESDMA_Set_FileinDesc(MS_U32 FileinAddr , MS_U32 FileinNum)
230 {
231 REG32_W((&_AESDMACtrl[0].Dma_Filein_Addr), FileinAddr);
232 REG32_W((&_AESDMACtrl[0].Dma_Filein_Num), FileinNum);
233 }
234
AESDMA_Set_FileoutDesc(MS_U32 FileoutSAddr,MS_U32 FileoutEAddr)235 void AESDMA_Set_FileoutDesc(MS_U32 FileoutSAddr , MS_U32 FileoutEAddr)
236 {
237 REG32_W((&_AESDMACtrl[0].Dma_Fileout_SAddr), FileoutSAddr);
238 REG32_W((&_AESDMACtrl[0].Dma_Fileout_EAddr), FileoutEAddr);
239 }
240
AESDMA_Start(MS_BOOL AESDMAStart)241 void AESDMA_Start(MS_BOOL AESDMAStart)
242 {
243 if (AESDMAStart)
244 {
245 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) &~ AESDMA_CTRL_FILEOUT_START &~ AESDMA_CTRL_FILEIN_START));
246 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) | AESDMA_CTRL_FILEOUT_START | AESDMA_CTRL_FILEIN_START));
247 }
248 else
249 {
250 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_FILEOUT_START|AESDMA_CTRL_FILEIN_START));
251 }
252 }
253
AESDMA_Set_PS_PTN(MS_U32 MatchPTN)254 void AESDMA_Set_PS_PTN(MS_U32 MatchPTN)
255 {
256 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern) , MatchPTN);
257 }
258
AESDMA_Set_PS_Mask(MS_U32 MatchMask)259 void AESDMA_Set_PS_Mask(MS_U32 MatchMask)
260 {
261 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern_Mask) , MatchMask);
262 }
263
AESDMA_Set_PS_ENG(MS_BOOL PSin_en,MS_BOOL PSout_en)264 void AESDMA_Set_PS_ENG(MS_BOOL PSin_en, MS_BOOL PSout_en)
265 {
266 MS_U32 u32PSin, u32PSout;
267
268 u32PSin = AESDMA_ENG_PS_IN_EN & (PSin_en<<20);
269 u32PSout = AESDMA_ENG_PS_OUT_EN & (PSout_en<<21);
270
271 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(u32PSin|u32PSout));
272 }
273
AESDMA_Get_PS_MatchedBytecnt(void)274 MS_U32 AESDMA_Get_PS_MatchedBytecnt(void)
275 {
276 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Btyecnt);
277 }
278
AESDMA_Get_PS_MatchedPTN(void)279 MS_U32 AESDMA_Get_PS_MatchedPTN(void)
280 {
281 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Pat);
282 }
283
AESDMA_Set_PS_Release(void)284 void AESDMA_Set_PS_Release(void)
285 {
286 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ENG_PS_RELEASE);
287 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & ~AESDMA_ENG_PS_RELEASE);
288 }
289
AESDMA_Get_AESDMA_Status(void)290 MS_U32 AESDMA_Get_AESDMA_Status(void)
291 {
292 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status);
293 }
294
AESDMA_Get_AESDMA_IsFinished(void)295 MS_U32 AESDMA_Get_AESDMA_IsFinished(void)
296 {
297 return (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status) & AESDMA_IS_FINISHED);
298 }
299
AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode,MS_BOOL Descrypt)300 void AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode, MS_BOOL Descrypt)
301 {
302 MS_U32 u32Cmd = 0;
303
304 switch (eMode)
305 {
306 case E_AESDMA_CIPHER_ECB:
307 u32Cmd |= AESDMA_ENG_AES_EN;
308 break;
309
310 case E_AESDMA_CIPHER_CTR:
311 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTR_MODE);
312 break;
313
314 case E_AESDMA_CIPHER_CBC:
315 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CBC_MODE);
316 break;
317
318 case E_AESDMA_CIPHER_DES_ECB:
319 u32Cmd |= AESDMA_ENG_DES_EN;
320 break;
321
322 case E_AESDMA_CIPHER_DES_CTR:
323 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTR_MODE);
324 break;
325
326 case E_AESDMA_CIPHER_DES_CBC:
327 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CBC_MODE);
328 break;
329
330 case E_AESDMA_CIPHER_TDES_ECB:
331 u32Cmd |= AESDMA_ENG_TDES_EN;
332 break;
333
334 case E_AESDMA_CIPHER_TDES_CTR:
335 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTR_MODE);
336 break;
337
338 case E_AESDMA_CIPHER_TDES_CBC:
339 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CBC_MODE);
340 break;
341
342 case E_AESDMA_CIPHER_CTS_CBC:
343 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_CBC_MODE);
344 break;
345
346 case E_AESDMA_CIPHER_CTS_ECB:
347 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_ECB_MODE);
348 break;
349
350 case E_AESDMA_CIPHER_DES_CTS_CBC:
351 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_CBC_MODE);
352 break;
353
354 case E_AESDMA_CIPHER_DES_CTS_ECB:
355 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_ECB_MODE);
356 break;
357
358 case E_AESDMA_CIPHER_TDES_CTS_CBC:
359 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_CBC_MODE);
360 break;
361
362 case E_AESDMA_CIPHER_TDES_CTS_ECB:
363 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_ECB_MODE);
364 break;
365 default:
366 return;
367 }
368
369 if( eMode >= E_AESDMA_CIPHER_DES_ECB )
370 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) | AESDMA_DMA_USE_TDES_EN);
371
372 u32Cmd |= AESDMA_ENG_DESCRYPT & (Descrypt<<25);
373 REG32_W((&_AESDMACtrl[0].Dma_Ctrl),(( _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & (~DmaCtrlSet)) | u32Cmd ) );
374 }
375
AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)376 MS_U32 AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)
377 {
378 MS_U32 u32Result = 1;
379
380 switch (eMode)
381 {
382 case E_AESDMA_CIPHER_ECB:
383 case E_AESDMA_CIPHER_CTR:
384 case E_AESDMA_CIPHER_CBC:
385 case E_AESDMA_CIPHER_DES_ECB:
386 case E_AESDMA_CIPHER_DES_CTR:
387 case E_AESDMA_CIPHER_DES_CBC:
388 case E_AESDMA_CIPHER_TDES_ECB:
389 case E_AESDMA_CIPHER_TDES_CTR:
390 case E_AESDMA_CIPHER_TDES_CBC:
391 case E_AESDMA_CIPHER_CTS_CBC:
392 case E_AESDMA_CIPHER_CTS_ECB:
393 case E_AESDMA_CIPHER_DES_CTS_CBC:
394 case E_AESDMA_CIPHER_DES_CTS_ECB:
395 case E_AESDMA_CIPHER_TDES_CTS_CBC:
396 case E_AESDMA_CIPHER_TDES_CTS_ECB:
397 u32Result = 0;
398 break;
399 default:
400 break;
401 }
402 return u32Result;
403
404 }
405
AESDMA_Set_MIU_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)406 void AESDMA_Set_MIU_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
407 {
408 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_R));
409 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_W));
410
411 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_R & ((MS_U32)MIU_R << 4))));
412 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_W & ((MS_U32)MIU_W << 5))));
413 }
414
AESDMA_Set_MIU2_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)415 void AESDMA_Set_MIU2_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
416 {
417 // Not support
418 }
419
AESDMA_Enable_Int(void)420 void AESDMA_Enable_Int(void)
421 {
422 // in Mustang biforst bring-up, we fond interrupt handler is keeping calling so that R2 hang
423 // so we temporary disable interrupt for Mustang
424 // REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)|AESDMA_INT_EN);
425 }
426
AESDMA_Disable_Int(void)427 void AESDMA_Disable_Int(void)
428 {
429 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)&~AESDMA_INT_EN);
430 }
431
AESDMA_Clear_Int(void)432 void AESDMA_Clear_Int(void)
433 {
434 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)|AESDMA_WADR_ERR_CLR);
435 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)&~AESDMA_WADR_ERR_CLR);
436 }
437
AESDMA_HW_Patch(void)438 void AESDMA_HW_Patch(void)
439 {
440 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ECO_FIX_LAST_BYTE);
441 }
442
AESDMA_Enable_Clk(void)443 void AESDMA_Enable_Clk(void)
444 {
445 MS_U32 u32Val;
446
447 //1. clk_aesdma
448 u32Val = _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA);
449 u32Val &= ~0xF0000; //Set Clk to 172M, Enable Clk
450 REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , u32Val);
451
452 //
453 // Due to the security concern
454 // Set this CLK at SBOOT
455 //
456
457 //2. clk_rc
458 //Enable 0x1239_0x03[3:0] = 4b'1111
459
460 //3. Enable Rng
461 u32Val = _AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0001);
462 u32Val |= REG_RNG_EN;
463 REG32_W((&_SECUREBASECtrl[0].Reg0001) , u32Val);
464
465 }
466
AESDMA_Disable_Clk(void)467 void AESDMA_Disable_Clk(void)
468 {
469 REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) | AESDMA_CLK_DISABLE);
470 }
471
AESDMA_Rand(void)472 MS_U8 AESDMA_Rand(void)
473 {
474 MS_U8 u8RN = 0x00;
475 u8RN = (MS_U8)_AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0203)&0xFF;
476
477 return u8RN;
478 }
479
SHA_Reset(void)480 void SHA_Reset(void)
481 {
482 MS_U32 Reg_SHARNG;
483 int i = 0;
484 Reg_SHARNG = (MS_U32)(&_SHARNGCtrl[0].Sha_Ctrl);
485 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , SHARNG_CTRL_SHA_RST); // 0->1
486 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&(~SHARNG_CTRL_SHA_RST))); // 1->0
487
488 // reset all SHA & RNG register
489 for (i = 0 ; i < 7 ; i++)
490 {
491 REG32_W((REG32 *)(Reg_SHARNG+(i*8)), 0x00000000);
492 }
493 }
494
SHA_Get_Status(void)495 MS_U32 SHA_Get_Status(void)
496 {
497 return _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Status);
498 }
499
SHA_SelMode(AESDMA_SHAMode eMode)500 void SHA_SelMode(AESDMA_SHAMode eMode)
501 {
502 MS_U32 u32Cmd = 0;
503
504 switch (eMode)
505 {
506 case E_AESDMA_SHA1:
507 u32Cmd |= (SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
508 break;
509
510 case E_AESDMA_SHA256:
511 u32Cmd |= (SHARNG_CTRL_SHA_SEL_SHA256 | SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
512 break;
513
514 default:
515 return;
516 }
517
518 //Turn off speedup mode
519 //// comment for mustung SHA Fail: avoid toggle speed mode n
520 //// u32Cmd |= SHARNG_CTRL_SPEED_MODE_N;
521
522 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl), _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl) | u32Cmd);
523 }
524
SHA_SetAddress(MS_U32 u32Addr)525 void SHA_SetAddress(MS_U32 u32Addr)
526 {
527 REG32_W((&_SHARNGCtrl[0].Sha_Start), u32Addr);
528 }
529
SHA_SetLength(MS_U32 u32Size)530 void SHA_SetLength(MS_U32 u32Size)
531 {
532 REG32_W((&_SHARNGCtrl[0].Sha_Length), u32Size);
533 }
534
SHA_Start(MS_BOOL SHAStart)535 void SHA_Start(MS_BOOL SHAStart)
536 {
537 if(SHAStart)
538 {
539 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
540 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_FIRE_ONCE));
541 }
542 else
543 {
544 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
545 }
546 }
547
SHA_Out(MS_U32 u32Buf)548 void SHA_Out(MS_U32 u32Buf)
549 {
550 MS_U32 Index, u32Size, u32offset;
551 MS_U32 eMode = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&SHARNG_CTRL_SHA_SEL_SHA256;
552
553 if(eMode == SHARNG_CTRL_SHA_SEL_SHA256)
554 {
555 u32Size = DIGEST_SIZE_SHA256;
556 u32offset = 0;
557 }
558 else
559 {
560 u32Size = DIGEST_SIZE_SHA1;
561 u32offset = 3;
562 }
563
564 for( Index = 0; Index < u32Size; Index++ )
565 {
566 *((MS_U32 *)u32Buf + Index) = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Out[Index + u32offset]);
567 }
568 //Set "1" to idle state after reg_read_sha_ready = 1
569 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_CLR));
570 }
571
SHA_SetByPassTable(MS_BOOL bEnable)572 void SHA_SetByPassTable(MS_BOOL bEnable)
573 {
574 if (bEnable == TRUE)
575 {
576 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|SHARNG_CTRL_SHA_BYPASS_TABLE_EN);
577 }
578 else
579 {
580 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_BYPASS_TABLE_EN));
581 }
582 }
583
SHA_SetInitialHashEn(MS_BOOL bEnable)584 void SHA_SetInitialHashEn(MS_BOOL bEnable)
585 {
586 if (bEnable == TRUE)
587 {
588 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|SHARNG_CTRL_SHA_INITIAL_HASH_EN);
589 }
590 else
591 {
592 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_INITIAL_HASH_EN));
593 }
594 }
595
SHA_SetShaManualMode(MS_BOOL bEnable)596 void SHA_SetShaManualMode(MS_BOOL bEnable)
597 {
598 if (bEnable == TRUE)
599 {
600 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|SHARNG_CTRL_SHA_WORKMODE_MANUAL_EN);
601 }
602 else
603 {
604 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_WORKMODE_MANUAL_EN));
605 }
606 }
607
SHA_SetInitialSha(MS_U32 u32Buf)608 void SHA_SetInitialSha(MS_U32 u32Buf)
609 {
610 MS_U32 Index, u32Size, u32offset;
611 MS_U32 eMode = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&SHARNG_CTRL_SHA_SEL_SHA256;
612
613 if(eMode == SHARNG_CTRL_SHA_SEL_SHA256)
614 {
615 u32Size = DIGEST_SIZE_SHA256;
616 u32offset = 0;
617 }
618 else
619 {
620 u32Size = DIGEST_SIZE_SHA1;
621 u32offset = 3;
622 }
623
624 for( Index = 0; Index < u32Size; Index++ )
625 {
626 REG32_W((&_SHARNGCtrl[0].Sha_Out[Index + u32offset]), *((MS_U32 *)u32Buf + Index));
627 }
628 }
629
630 //-------------------------------------------------------------------------------------------------
631 /// Enable mobf one way function
632 /// @param NULL
633
634 /// @note : disable read mobf key, and could not enable read mobf key anymore
635 //-------------------------------------------------------------------------------------------------
MOBF_OneWay(void)636 void MOBF_OneWay(void)
637 {
638 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_ONEWAY_EN));
639 }
640
641 //-------------------------------------------------------------------------------------------------
642 /// Set MOBF encrypt key
643 /// @param u32WriteKey \b IN: Encrypt Key
644
645 /// @note
646 //-------------------------------------------------------------------------------------------------
MOBF_WriteKey(MS_U32 u32WriteKey)647 void MOBF_WriteKey(MS_U32 u32WriteKey)
648 {
649 REG32_W((&_SHARNGCtrl[0].MOBF_KeyW) , u32WriteKey);
650 }
651
652 //-------------------------------------------------------------------------------------------------
653 /// Set MOBF decrypt key
654 /// @param u32ReadKey \b IN: Decrypt Key
655
656 /// @note
657 //-------------------------------------------------------------------------------------------------
MOBF_ReadKey(MS_U32 u32ReadKey)658 void MOBF_ReadKey(MS_U32 u32ReadKey)
659 {
660 REG32_W((&_SHARNGCtrl[0].MOBF_KeyR) , u32ReadKey);
661 }
662
663 //-------------------------------------------------------------------------------------------------
664 /// Enable MOBF in MIU write port
665 /// @param bEnable \b IN: Enable/Disable
666
667 /// @note : MOBF Encrypt
668 //-------------------------------------------------------------------------------------------------
MOBF_WriteEnable(MS_BOOL bEnable)669 void MOBF_WriteEnable(MS_BOOL bEnable)
670 {
671 if(bEnable)
672 {
673 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
674 }
675 else
676 {
677 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
678 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_WRITE_EN));
679 }
680 }
681
682 //-------------------------------------------------------------------------------------------------
683 /// Enable MOBF in MIU read port
684 /// @param bEnable \b IN: Enable/Disable
685
686 /// @note : MOBF Decrypt
687 //-------------------------------------------------------------------------------------------------
MOBF_ReadEnable(MS_BOOL bEnable)688 void MOBF_ReadEnable(MS_BOOL bEnable)
689 {
690 if(bEnable)
691 {
692 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
693 }
694 else
695 {
696 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
697 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_READ_EN));
698 }
699 }
700
701 //-------------------------------------------------------------------------------------------------
702 /// Disable TDES
703 ///
704
705 /// @note : MOBF Decrypt
706 //-------------------------------------------------------------------------------------------------
MOBF_DisableTDES(void)707 void MOBF_DisableTDES(void)
708 {
709 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) & (~AESDMA_DMA_USE_TDES_EN));
710 }
711
AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)712 void AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)
713 {
714 MS_U32 u32Cmd = 0;
715
716 switch (eMode)
717 {
718 case E_AESDMA_PARSER_TS_PKT192:
719 u32Cmd |= (TS_MODE | PKT192_MODE);
720 break;
721
722 case E_AESDMA_PARSER_TS_PKT192_CLEAR:
723 u32Cmd |= (TS_MODE | PKT192_MODE | CLEAR_MODE);
724 break;
725
726 case E_AESDMA_PARSER_TS_PKT188:
727 u32Cmd |= (TS_MODE);
728 u32Cmd &= (~PKT192_MODE);
729 break;
730
731 case E_AESDMA_PARSER_TS_PKT188_CLEAR:
732 u32Cmd |= (TS_MODE | CLEAR_MODE);
733 u32Cmd &= (~PKT192_MODE);
734 break;
735
736 case E_AESDMA_PARSER_HDCP20_PKT192:
737 u32Cmd |= (HDCP20_MODE | PKT192_MODE);
738 break;
739
740 case E_AESDMA_PARSER_HDCP20_PKT192_CLEAR:
741 u32Cmd |= (HDCP20_MODE | PKT192_MODE | CLEAR_MODE);
742 break;
743
744 case E_AESDMA_PARSER_HDCP20_PKT188:
745 u32Cmd |= (HDCP20_MODE);
746 u32Cmd &= (~PKT192_MODE);
747 break;
748
749 case E_AESDMA_PARSER_HDCP20_PKT188_CLEAR:
750 u32Cmd |= (HDCP20_MODE | CLEAR_MODE);
751 u32Cmd &= (~PKT192_MODE);
752 break;
753
754 default:
755 return;
756 }
757
758 u32Cmd |= (AUTO_MODE | INIT_TRUST);
759 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~ParserCtrlSet)) | u32Cmd ) );
760 }
761
762
AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)763 void AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)
764 {
765 if(bEnable)
766 {
767 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
768 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (INSERT_SCRMB)) );
769 }
770 else
771 {
772 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
773 }
774 }
775
AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)776 void AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)
777 {
778 if(bEnable)
779 {
780 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
781 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (REMOVE_SCRMB)) );
782 }
783 else
784 {
785 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
786 }
787 }
788
AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)789 void AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)
790 {
791 if(bEnable)
792 {
793 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
794 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (TS_SCRMB_MASK)) );
795 }
796 else
797 {
798 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
799 }
800 }
801
AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)802 void AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)
803 {
804 if(bEnable)
805 {
806 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
807 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (BYPASS_PID)) );
808 }
809 else
810 {
811 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
812 }
813 }
814
AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)815 void AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)
816 {
817 MS_U32 u32Cmd = 0;
818
819 switch (ePattern)
820 {
821 case E_AESDMA_PARSER_SCRMB_10:
822 u32Cmd |= (SCRMB_PATTERN10);
823 break;
824
825 case E_AESDMA_PARSER_SCRMB_11:
826 u32Cmd |= (SCRMB_PATTERN11);
827 break;
828
829 default:
830 u32Cmd &= ~(SCRMB_PATTERN11);
831 break;
832 }
833
834 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~SCRMB_INITVALUE)) | u32Cmd ) );
835
836 }
837
AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)838 void AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)
839 {
840 MS_U32 u32Cmd = 0;
841
842 switch (ePattern)
843 {
844 case E_AESDMA_PARSER_SCRMB_10:
845 u32Cmd |= (SCRMB_PATTERN10_ADD);
846 break;
847
848 case E_AESDMA_PARSER_SCRMB_11:
849 u32Cmd |= (SCRMB_PATTERN11_ADD);
850 break;
851
852 default:
853 return;
854 }
855
856 REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_INITVALUE_ADD)) | u32Cmd ) );
857
858 }
859
AESDMA_Parser_Set_Pid(MS_U8 u8Index,MS_U16 u16Pid)860 void AESDMA_Parser_Set_Pid(MS_U8 u8Index, MS_U16 u16Pid)
861 {
862 if(u8Index==0)
863 {
864 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~PARSER_PID0_MASK)) | (u16Pid<<16) ) );
865 }
866 else if(u8Index==1)
867 {
868 REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~PARSER_PID1_MASK)) | u16Pid ) );
869 }
870 else
871 {
872 printf("Edison do not support other PID\n");
873 }
874 }
875
AESDMA_Parser_Query_PidCount(void)876 MS_U8 AESDMA_Parser_Query_PidCount(void)
877 {
878 return PARSER_PID_COUNT;
879 }
880
AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)881 void AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)
882 {
883 if(bEnable)
884 {
885 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE)) );
886 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (HW_PARSER_MODE)) );
887 }
888 else
889 {
890 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE)) );
891 }
892
893 //make sure CC_CTRL_BY_ACPU is set 0
894 REG32_W((&_CIPHERCtrl[0].Cipher_Ctrl),( _AESDMA_REG32_R(&_CIPHERCtrl[0].Cipher_Ctrl) & (~CC_CTRL_BY_ACPU)) );
895 }
896
RSA_ClearInt(void)897 void RSA_ClearInt(void)
898 {
899 //RSA interrupt clear
900 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_INT_CLR));
901 }
902
RSA_Reset(void)903 void RSA_Reset(void)
904 {
905 //RSA Rst
906 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_RSA_RST));
907 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_RSA_RST));
908
909 //add polling RSA status before load data to SRAM
910 while (( RSA_GetStatus() & RSA_STATUS_RSA_BUSY ) != 0);
911 }
912
RSA_Ind32Ctrl(MS_U8 u8dirction)913 void RSA_Ind32Ctrl(MS_U8 u8dirction)
914 {
915 //[1] reg_ind32_direction 0: Read. 1: Write
916 if(u8dirction==1)
917 {
918 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_DIRECTION_WRITE));
919 }
920 else
921 {
922 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)&(~RSA_IND32_CTRL_DIRECTION_WRITE));
923 }
924
925 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_ADDR_AUTO_INC|RSA_IND32_CTRL_ACCESS_AUTO_START));
926
927 }
928
RSA_LoadSram(MS_U32 * u32Buf,RSA_IND32Address eMode)929 void RSA_LoadSram(MS_U32 *u32Buf, RSA_IND32Address eMode)
930 {
931 MS_U32 u32Cmd = 0;
932 MS_U32 i = 0;
933 MS_U32 WData_H = 0;
934 MS_U32 WData_L = 0;
935
936 switch (eMode)
937 {
938 case E_RSA_ADDRESS_E:
939 u32Cmd |= (RSA_E_BASE_ADDR);
940 break;
941
942 case E_RSA_ADDRESS_N:
943 u32Cmd |= (RSA_N_BASE_ADDR);
944 break;
945
946 case E_RSA_ADDRESS_A:
947 u32Cmd |= (RSA_A_BASE_ADDR);
948 break;
949
950 default:
951 return;
952 }
953
954 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Cmd));
955 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
956
957 for( i = 0; i < 64; i++ )
958 {
959 if( eMode == E_RSA_ADDRESS_E )
960 {
961 WData_L = (((*(u32Buf+i))>>8)&0xFF00)|(((*(u32Buf+i))>>24)&0xFF);
962 WData_H = (((*(u32Buf+i))>>8)&0xFF)|(((*(u32Buf+i))<<8)&0xFF00);
963 }
964 else
965 {
966 WData_L = (((*(u32Buf-i))>>8)&0xFF00)|(((*(u32Buf-i))>>24)&0xFF);
967 WData_H = (((*(u32Buf-i))>>8)&0xFF)|(((*(u32Buf-i))<<8)&0xFF00);
968 }
969
970 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_WDATA_MASK_L))|(WData_L<<16)));
971 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_WData) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&(~RSA_WDATA_MASK_H))|WData_H));
972 }
973
974 }
975
RSA_SetKeyLength(MS_U32 u32keylen)976 void RSA_SetKeyLength(MS_U32 u32keylen)
977 {
978 //[13:8] n_len_e: key length
979 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_KEY_LENGTH_MASK))|(u32keylen<<8));
980 }
981
RSA_SetKeyType(MS_U8 u8hwkey,MS_U8 u8pubkey)982 void RSA_SetKeyType(MS_U8 u8hwkey, MS_U8 u8pubkey)
983 {
984 //[1] hw_key_e : 0 : software key, 1: hardware key
985 //[2] e_pub_e : 0: pvivate key, 1: public key
986 if(u8hwkey==1)
987 {
988 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_HW_KEY));
989 }
990 else
991 {
992 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_HW_KEY));
993 }
994
995 if(u8pubkey==1)
996 {
997 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_PUBLIC_KEY));
998 }
999 else
1000 {
1001 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_PUBLIC_KEY));
1002 }
1003
1004 }
1005
RSA_ExponetialStart(void)1006 void RSA_ExponetialStart(void)
1007 {
1008 //RSA exp start
1009 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_EXP_START));
1010 }
1011
RSA_GetStatus(void)1012 MS_U32 RSA_GetStatus(void)
1013 {
1014 return _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl) & RSA_STATUS_MASK;
1015 }
1016
RSA_FileOutStart(void)1017 void RSA_FileOutStart(void)
1018 {
1019 //RSA ind32_start
1020 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
1021 }
1022
RSA_SetFileOutAddr(MS_U32 u32offset)1023 void RSA_SetFileOutAddr(MS_U32 u32offset)
1024 {
1025 MS_U32 u32Addr = 0;
1026 u32Addr = RSA_Z_BASE_ADDR + u32offset;
1027
1028 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Addr));
1029 }
1030
RSA_FileOut(void)1031 MS_U32 RSA_FileOut(void)
1032 {
1033 MS_U32 u32out_L = 0;
1034 MS_U32 u32out_H = 0;
1035
1036 u32out_L = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&RSA_RDATA_MASK_L)>>16;
1037 u32out_H = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)&RSA_RDATA_MASK_H)<<16;
1038
1039 return (u32out_H|u32out_L);
1040 }
1041
RSA_Get_RSA_IsFinished(void)1042 MS_U32 RSA_Get_RSA_IsFinished(void)
1043 {
1044 return (RSA_GetStatus()&RSA_STATUS_RSA_BUSY);
1045 }
1046
1047 //-------------------------------------------------------------------------------------------------
1048 /// Get status of Secret Key in Normal bank
1049 /// @param N/A
1050 /// @note : Get Status
1051 //-------------------------------------------------------------------------------------------------
AESDMA_IsSecretKeyInNormalBank(void)1052 MS_U32 AESDMA_IsSecretKeyInNormalBank(void)
1053 {
1054 return (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl) & (SECRET_KEY_IN_NORMAL_BANK));
1055 }
1056
1057 //-------------------------------------------------------------------------------------------------
1058 /// Enable Two keys (Odd/Even) in using HW auto select key.
1059 /// @param bEnable \b IN: Enable/Disable
1060
1061 /// @note : Hardware Parser Decrypt
1062 //-------------------------------------------------------------------------------------------------
AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)1063 void AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)
1064 {
1065 if(bEnable)
1066 {
1067 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (SCRMB_ENABLE_TWO_KEY) );
1068 }
1069 else
1070 {
1071 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_ENABLE_TWO_KEY) );
1072 }
1073 }
1074
1075 //-------------------------------------------------------------------------------------------------
1076 /// Set Odd keys in using HW auto select key.
1077 /// @param cipherkey
1078 /// @note : Hardware Parser Decrypt
1079 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherOddKey(MS_U32 * cipherkey)1080 void AESDMA_Set_CipherOddKey(MS_U32 *cipherkey)
1081 {
1082 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
1083 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
1084 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
1085 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
1086 }
1087
1088 //-------------------------------------------------------------------------------------------------
1089 /// Set Odd IVs in using HW auto select key.
1090 /// @param cipherkey
1091 /// @note : Hardware Parser Decrypt
1092 //-------------------------------------------------------------------------------------------------
AESDMA_Set_OddInitVector(MS_U32 * pInitVector)1093 void AESDMA_Set_OddInitVector(MS_U32 *pInitVector)
1094 {
1095 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_L), pInitVector[0]);
1096 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_H), pInitVector[1]);
1097 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_L), pInitVector[2]);
1098 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_H), pInitVector[3]);
1099 }
1100
1101 //-------------------------------------------------------------------------------------------------
1102 /// Set Even keys in using HW auto select key.
1103 /// @param cipherkey
1104 /// @note : Hardware Parser Decrypt
1105 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherEvenKey(MS_U32 * cipherkey)1106 void AESDMA_Set_CipherEvenKey(MS_U32 *cipherkey)
1107 {
1108 AESDMA_Set_CipherKey(cipherkey);
1109 }
1110
1111 //-------------------------------------------------------------------------------------------------
1112 /// Set Even IVs in using HW auto select key.
1113 /// @param cipherkey
1114 /// @note : Hardware Parser Decrypt
1115 //-------------------------------------------------------------------------------------------------
AESDMA_Set_EvenInitVector(MS_U32 * pInitVector)1116 void AESDMA_Set_EvenInitVector(MS_U32 *pInitVector)
1117 {
1118 AESDMA_Set_InitVector(pInitVector);
1119 }
1120
1121 //-------------------------------------------------------------------------------------------------
1122 /// Set HDCP Data
1123 /// @param u8Idx \b IN: Index
1124 /// @param pu8Data \b IN: Data array
1125 /// @param pu8privData \b IN: Private data array
1126 /// @note : Set HDCP2.2
1127 //-------------------------------------------------------------------------------------------------
HDCP_ProcessCipher(MS_U8 u8Idx,MS_U8 * pu8Data,MS_U8 * pu8privData)1128 void HDCP_ProcessCipher (MS_U8 u8Idx, MS_U8 *pu8Data, MS_U8* pu8privData)
1129 {
1130 //
1131 //Ks^LC128:
1132 //P0: Bank 0x162A_h��00~07
1133 //P1: Bank 0x162B_h��00~07
1134 //P2: Bank 0x162C_h��00~07
1135 //P3: Bank 0x162D_h��00~07
1136 //Riv:
1137 //P0: Bank 0x162A_h��08~0B
1138 //P1: Bank 0x162B_h��08~0B
1139 //P2: Bank 0x162C_h��08~0B
1140 //P3: Bank 0x162D_h��08~0B
1141 //
1142
1143 REG_HDCP22Data *pData = NULL;
1144 REG_HDCP22SEKCtrl *pCtrl = NULL;
1145 MS_U32 offset = 0;
1146 MS_U32 BKOffset = 0;
1147
1148 if (u8Idx >= MAX_HDMI_PORT_MUN)
1149 {
1150 printf ("[Error] %s (%d), Wrong HDMI Port\n", __FUNCTION__, __LINE__);
1151 return;
1152 }
1153
1154 MS_U32 *cipherkey = (MS_U32 *)((void *)pu8Data);
1155 MS_U32 *riv = (MS_U32 *)((void *)pu8privData);
1156
1157 offset = u8Idx * 0x200;
1158 BKOffset = u8Idx * 0x200;
1159
1160 pData = (REG_HDCP22Data*)((MS_U32)_HDCP22Data + offset);
1161 pCtrl = (REG_HDCP22SEKCtrl*)((MS_U32)_HDCP22SekCtrl + BKOffset);
1162
1163 //Content Keys
1164 REG32_W((&pData[0].Hdcp22_ContentKey[0]) , cipherkey[0]);
1165 REG32_W((&pData[0].Hdcp22_ContentKey[1]) , cipherkey[1]);
1166 REG32_W((&pData[0].Hdcp22_ContentKey[2]) , cipherkey[2]);
1167 REG32_W((&pData[0].Hdcp22_ContentKey[3]) , cipherkey[3]);
1168
1169 //RIV
1170 REG32_W((&pData[0].Hdcp22_Riv[0]) , riv[0]);
1171 REG32_W((&pData[0].Hdcp22_Riv[1]) , riv[1]);
1172
1173 //Set SKE successful
1174 REG32_W((&pCtrl[0].SEK), (_AESDMA_REG32_R(&pCtrl[0].SEK) | HDCP_SEK_BIT0));
1175 }
1176
1177 //-------------------------------------------------------------------------------------------------
1178 /// Get the status of HW supports HDCP2.2
1179 /// @param N/A
1180 /// @note : Support HDCP2.2
1181 //-------------------------------------------------------------------------------------------------
HDCP_GetHdcpCipherState(MS_U8 u8Idx,MS_U8 * pu8State)1182 void HDCP_GetHdcpCipherState(MS_U8 u8Idx, MS_U8 *pu8State)
1183 {
1184 //
1185 // Set SKE successful:
1186 // P0: Bank 0x162A_h��0E[0]
1187 // P1: Bank 0x162B_h��0E[0]
1188 // P2: Bank 0x162C_h��0E[0]
1189 // P3: Bank 0x162D_h��0E[0]
1190 //
1191
1192 #define HDCP_SUPPORT_EN 0x00000001
1193 REG_HDCP22SEKCtrl *pCtrl = NULL;
1194 MS_U16 BKOffset = 0;
1195
1196 if (u8Idx >= MAX_HDMI_PORT_MUN)
1197 {
1198 printf ("[Error] %s (%d), Wrong HDMI Port\n", __FUNCTION__, __LINE__);
1199 return;
1200 }
1201
1202 BKOffset = u8Idx * 0x200;
1203 pCtrl = (REG_HDCP22SEKCtrl*)((MS_U32)_HDCP22SekCtrl + BKOffset);
1204 *pu8State = (MS_U8)(_AESDMA_REG32_R(&pCtrl[0].SEK) & HDCP_SUPPORT_EN);
1205 }
1206
1207 //-------------------------------------------------------------------------------------------------
1208 /// Reset AESDMA
1209 /// @param N/A
1210 /// @note : Clear Registers, not to do sw reset
1211 //-------------------------------------------------------------------------------------------------
AESDMA_NormalReset(void)1212 void AESDMA_NormalReset(void)
1213 {
1214 MS_U32 Reg_AESDMA;
1215 int i = 0;
1216 Reg_AESDMA = (MS_U32)(&_AESDMACtrl[0].Dma_Ctrl);
1217
1218 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
1219
1220 // reset all AESdma register
1221 for (i = 0 ; i < 19 ; i++)
1222 {
1223 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
1224 }
1225 // reset secure_dma3_ctrl register
1226 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
1227
1228 // reset hw_parser_ctrl register
1229 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000);
1230 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
1231 }
1232
AESDMA_POWER_SUSPEND(void)1233 MS_BOOL AESDMA_POWER_SUSPEND(void)
1234 {
1235 SECUREBASECtrl_Buffer = _AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0001);
1236 return TRUE;
1237 }
1238
AESDMA_POWER_RESUME(void)1239 MS_BOOL AESDMA_POWER_RESUME(void)
1240 {
1241 REG32_W((&_SECUREBASECtrl[0].Reg0001), SECUREBASECtrl_Buffer);
1242 return TRUE;
1243 }
1244
1245