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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halAESDMA.c
97 // @brief AESDMA HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100
101 #include "MsCommon.h"
102 #include "regAESDMA.h"
103 #include "halAESDMA.h"
104 #include "halCHIP.h"
105 #include "ULog.h"
106
107
108 #define TAG_AESDMA "AESDMA"
109
110 //--------------------------------------------------------------------------------------------------
111 // Driver Compiler Option
112 //--------------------------------------------------------------------------------------------------
113
114
115 //--------------------------------------------------------------------------------------------------
116 // TSP Hardware Abstraction Layer
117 //--------------------------------------------------------------------------------------------------
118 static MS_VIRT _u32RegBase = NULL;
119 static MS_VIRT _u32PmRegBase = NULL;
120 static REG_AESDMACtrl *_AESDMACtrl = (REG_AESDMACtrl*)REG_AESDMACTRL_BASE;
121 static REG_SHARNGCtrl *_SHARNGCtrl = (REG_SHARNGCtrl*)REG_SHARNGCTRL_BASE;
122 static REG_AESDMAClk *_AESDMAClk = (REG_AESDMAClk*)REG_AESDMACLK_BASE;
123 static REG_AESDMAMbx *_AESDMAMbx = (REG_AESDMAMbx*)REG_AESDMAMBX_BASE;
124 static REG_PARSERCtrl *_PARSERCtrl = (REG_PARSERCtrl*)REG_PARSERCTRL_BASE;
125 static REG_CIPHERCtrl *_CIPHERCtrl = (REG_CIPHERCtrl*)REG_CIPHERCTRL_BASE;
126 static REG_DMASECURECtrl *_DMASECURECtrl = (REG_DMASECURECtrl*)REG_DMASECURE_BASE;
127 static REG_SECUREBASECtrl *_SECUREBASECtrl = (REG_SECUREBASECtrl*)REG_DMASECURE_CTRL_BASE;
128 static REG_AESDMACtrlEx *_AESDMACtrlEx = (REG_AESDMACtrlEx*)REG_AESDMAEXT_BASE;
129 static REG_TZPCCtrl *_TZPCCtrl = (REG_TZPCCtrl*)REG_TZPC_NONPM_BASE;
130 static REG_HDCP22Data *_HDCP22Data = (REG_HDCP22Data*)REG_HDCP22_BASE;
131 static REG_HDCP22SEKCtrl *_HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)REG_HDCP22_SEK;
132 static REG_MIPSOCCCLKCtrl *_MispOccCtrl = (REG_MIPSOCCCLKCtrl*)REG_MIPS_OCC_CLK_BASE;
133
134 #define REG32_W(reg, value) do { \
135 (reg)->H = ((value) >> 16); \
136 (reg)->L = ((value) & 0x0000FFFF); \
137 } while(0)
138
139 //--------------------------------------------------------------------------------------------------
140 // Macro of bit operations
141 //--------------------------------------------------------------------------------------------------
142
_AESDMA_REG32_R(REG32 * reg)143 MS_U32 _AESDMA_REG32_R(REG32 *reg)
144 {
145 MS_U32 value;
146
147 value = (reg)->H << 16;
148 value |= (reg)->L;
149
150 return value;
151 }
152
153 //--------------------------------------------------------------------------------------------------
154 // Inline Function
155 //--------------------------------------------------------------------------------------------------
HAL_AESDMA_SetBank(MS_VIRT u32NonPmBankAddr,MS_VIRT u32PmBankAddr)156 void HAL_AESDMA_SetBank(MS_VIRT u32NonPmBankAddr, MS_VIRT u32PmBankAddr)
157 {
158 _u32RegBase = u32NonPmBankAddr;
159 _u32PmRegBase = u32PmBankAddr;
160 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE);
161 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE);
162 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE);
163 _AESDMAMbx = (REG_AESDMAMbx*)(_u32PmRegBase + REG_AESDMAMBX_BASE);
164 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE);
165 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);
166 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE);
167 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE);
168 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE);
169 _TZPCCtrl = (REG_TZPCCtrl*)(_u32RegBase + REG_TZPC_NONPM_BASE);
170 _HDCP22Data = (REG_HDCP22Data*)(_u32RegBase + REG_HDCP22_BASE);
171 _HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)(_u32RegBase + REG_HDCP22_SEK);
172 _MispOccCtrl = (REG_MIPSOCCCLKCtrl*)(_u32RegBase + REG_MIPS_OCC_CLK_BASE);
173 }
174
AESDMA_GetMIU1Base(void)175 MS_PHY AESDMA_GetMIU1Base(void)
176 {
177 return HAL_MIU1_BASE;
178 }
179
AESDMA_GetMIU2Base(void)180 MS_PHY AESDMA_GetMIU2Base(void)
181 {
182 //not support
183 return FALSE;
184 }
185
AESDMA_Reset(void)186 void AESDMA_Reset(void)
187 {
188 MS_VIRT Reg_AESDMA;
189 MS_U32 i = 0;
190 Reg_AESDMA = (MS_VIRT)(&_AESDMACtrl[0].Dma_Ctrl);
191
192 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
193 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST)); // sw rst
194 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RST));
195
196 // reset all AESdma register
197 for (i = 0 ; i < 19 ; i++)
198 {
199 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
200 }
201 // reset secure_dma3_ctrl register
202 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
203
204 // reset hw_parser_ctrl register
205 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x01000000);
206 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
207 }
208
AESDMA_Set_CipherKey(MS_U32 * cipherkey)209 void AESDMA_Set_CipherKey(MS_U32 *cipherkey)
210 {
211 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
212 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
213 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
214 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
215 }
216
AESDMA_Set_InitVector(MS_U32 * pInitVector)217 void AESDMA_Set_InitVector(MS_U32 *pInitVector)
218 {
219 REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_L), pInitVector[0]);
220 REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_H), pInitVector[1]);
221 REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_L), pInitVector[2]);
222 REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_H), pInitVector[3]);
223 }
224
AESDMA_Sel_Key(MS_BOOL keysel)225 void AESDMA_Sel_Key(MS_BOOL keysel)
226 {
227 }
228
AESDMA_Sel_SecureKey(void)229 void AESDMA_Sel_SecureKey(void)
230 {
231 MS_U32 u32Ctrl = _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2);
232 u32Ctrl |= AESDMA_USE_SECRET_KEY;
233 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), u32Ctrl);
234 }
235
AESDMA_Set_FileinDesc(MS_PHY FileinAddr,MS_PHY FileinNum)236 void AESDMA_Set_FileinDesc(MS_PHY FileinAddr , MS_PHY FileinNum)
237 {
238 REG32_W((&_AESDMACtrl[0].Dma_Filein_Addr), FileinAddr);
239 REG32_W((&_AESDMACtrl[0].Dma_Filein_Num), FileinNum);
240 }
241
AESDMA_Set_FileoutDesc(MS_PHY FileoutSAddr,MS_PHY FileoutEAddr)242 void AESDMA_Set_FileoutDesc(MS_PHY FileoutSAddr , MS_PHY FileoutEAddr)
243 {
244 REG32_W((&_AESDMACtrl[0].Dma_Fileout_SAddr), FileoutSAddr);
245 REG32_W((&_AESDMACtrl[0].Dma_Fileout_EAddr), FileoutEAddr);
246 }
247
AESDMA_Start(MS_BOOL AESDMAStart)248 void AESDMA_Start(MS_BOOL AESDMAStart)
249 {
250 if (AESDMAStart)
251 {
252 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) &~ AESDMA_CTRL_FILEOUT_START &~ AESDMA_CTRL_FILEIN_START));
253 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) | AESDMA_CTRL_FILEOUT_START | AESDMA_CTRL_FILEIN_START));
254 }
255 else
256 {
257 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_FILEOUT_START|AESDMA_CTRL_FILEIN_START));
258 }
259 }
260
AESDMA_Set_PS_PTN(MS_U32 MatchPTN)261 void AESDMA_Set_PS_PTN(MS_U32 MatchPTN)
262 {
263 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern) , MatchPTN);
264 }
265
AESDMA_Set_PS_Mask(MS_U32 MatchMask)266 void AESDMA_Set_PS_Mask(MS_U32 MatchMask)
267 {
268 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern_Mask) , MatchMask);
269 }
270
AESDMA_Set_PS_ENG(MS_BOOL PSin_en,MS_BOOL PSout_en)271 void AESDMA_Set_PS_ENG(MS_BOOL PSin_en, MS_BOOL PSout_en)
272 {
273 MS_U32 u32PSin, u32PSout;
274
275 u32PSin = AESDMA_ENG_PS_IN_EN & (PSin_en<<20);
276 u32PSout = AESDMA_ENG_PS_OUT_EN & (PSout_en<<21);
277
278 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(u32PSin|u32PSout));
279 }
280
AESDMA_Get_PS_MatchedBytecnt(void)281 MS_U32 AESDMA_Get_PS_MatchedBytecnt(void)
282 {
283 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Btyecnt);
284 }
285
AESDMA_Get_PS_MatchedPTN(void)286 MS_U32 AESDMA_Get_PS_MatchedPTN(void)
287 {
288 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Pat);
289 }
290
AESDMA_Set_PS_Release(void)291 void AESDMA_Set_PS_Release(void)
292 {
293 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ENG_PS_RELEASE);
294 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & ~AESDMA_ENG_PS_RELEASE);
295 }
296
AESDMA_Get_AESDMA_Status(void)297 MS_U32 AESDMA_Get_AESDMA_Status(void)
298 {
299 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status);
300 }
301
AESDMA_Get_AESDMA_IsFinished(void)302 MS_U32 AESDMA_Get_AESDMA_IsFinished(void)
303 {
304 return (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status) & AESDMA_IS_FINISHED);
305 }
306
AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode,MS_BOOL Descrypt)307 void AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode, MS_BOOL Descrypt)
308 {
309 MS_U32 u32Cmd = 0;
310
311 switch (eMode)
312 {
313 case E_AESDMA_CIPHER_ECB:
314 u32Cmd |= AESDMA_ENG_AES_EN;
315 break;
316
317 case E_AESDMA_CIPHER_CTR:
318 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTR_MODE);
319 break;
320
321 case E_AESDMA_CIPHER_CBC:
322 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CBC_MODE);
323 break;
324
325 case E_AESDMA_CIPHER_DES_ECB:
326 u32Cmd |= AESDMA_ENG_DES_EN;
327 break;
328
329 case E_AESDMA_CIPHER_DES_CTR:
330 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTR_MODE);
331 break;
332
333 case E_AESDMA_CIPHER_DES_CBC:
334 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CBC_MODE);
335 break;
336
337 case E_AESDMA_CIPHER_TDES_ECB:
338 u32Cmd |= AESDMA_ENG_TDES_EN;
339 break;
340
341 case E_AESDMA_CIPHER_TDES_CTR:
342 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTR_MODE);
343 break;
344
345 case E_AESDMA_CIPHER_TDES_CBC:
346 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CBC_MODE);
347 break;
348
349 case E_AESDMA_CIPHER_CTS_CBC:
350 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_CBC_MODE);
351 break;
352
353 case E_AESDMA_CIPHER_CTS_ECB:
354 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_ECB_MODE);
355 break;
356
357 case E_AESDMA_CIPHER_DES_CTS_CBC:
358 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_CBC_MODE);
359 break;
360
361 case E_AESDMA_CIPHER_DES_CTS_ECB:
362 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_ECB_MODE);
363 break;
364
365 case E_AESDMA_CIPHER_TDES_CTS_CBC:
366 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_CBC_MODE);
367 break;
368
369 case E_AESDMA_CIPHER_TDES_CTS_ECB:
370 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_ECB_MODE);
371 break;
372 default:
373 return;
374 }
375
376 if( eMode >= E_AESDMA_CIPHER_DES_ECB )
377 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) | AESDMA_DMA_USE_TDES_EN);
378
379 u32Cmd |= AESDMA_ENG_DESCRYPT & (Descrypt<<25);
380 REG32_W((&_AESDMACtrl[0].Dma_Ctrl),(( _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & (~DmaCtrlSet)) | u32Cmd ) );
381 }
382
AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)383 MS_U32 AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)
384 {
385 MS_U32 u32Result = 1;
386
387 switch (eMode)
388 {
389 case E_AESDMA_CIPHER_ECB:
390 case E_AESDMA_CIPHER_CTR:
391 case E_AESDMA_CIPHER_CBC:
392 case E_AESDMA_CIPHER_DES_ECB:
393 case E_AESDMA_CIPHER_DES_CTR:
394 case E_AESDMA_CIPHER_DES_CBC:
395 case E_AESDMA_CIPHER_TDES_ECB:
396 case E_AESDMA_CIPHER_TDES_CTR:
397 case E_AESDMA_CIPHER_TDES_CBC:
398 case E_AESDMA_CIPHER_CTS_CBC:
399 case E_AESDMA_CIPHER_CTS_ECB:
400 case E_AESDMA_CIPHER_DES_CTS_CBC:
401 case E_AESDMA_CIPHER_DES_CTS_ECB:
402 case E_AESDMA_CIPHER_TDES_CTS_CBC:
403 case E_AESDMA_CIPHER_TDES_CTS_ECB:
404 u32Result = 0;
405 break;
406 default:
407 break;
408 }
409 return u32Result;
410
411 }
412
AESDMA_Set_MIU_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)413 void AESDMA_Set_MIU_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
414 {
415 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_R));
416 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_W));
417
418 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_R & ((MS_U32)MIU_R << 4))));
419 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_W & ((MS_U32)MIU_W << 5))));
420 }
421
AESDMA_Set_MIU2_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)422 void AESDMA_Set_MIU2_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
423 {
424 // Not support
425 }
426
AESDMA_Enable_Int(void)427 void AESDMA_Enable_Int(void)
428 {
429 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)|AESDMA_INT_EN);
430 }
431
AESDMA_Disable_Int(void)432 void AESDMA_Disable_Int(void)
433 {
434 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)&~AESDMA_INT_EN);
435 }
436
AESDMA_Clear_Int(void)437 void AESDMA_Clear_Int(void)
438 {
439 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)|AESDMA_WADR_ERR_CLR);
440 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)&~AESDMA_WADR_ERR_CLR);
441 }
442
AESDMA_HW_Patch(void)443 void AESDMA_HW_Patch(void)
444 {
445 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ECO_FIX_LAST_BYTE);
446 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_CTRL_BURST_LENGTH);
447 REG32_W((&_AESDMACtrl[0].Dma_Eng3_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Eng3_Ctrl)|AESDMA_ENG_SPEEDUP);
448 }
449
AESDMA_Enable_Clk(void)450 void AESDMA_Enable_Clk(void)
451 {
452 MS_U32 u32Val;
453
454 //
455 // clk_aesdma 0x100A_0x19 = 0x0000
456 //
457 u32Val = _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA);
458 u32Val &= 0x0000FFFF;
459 REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , u32Val);
460
461 //
462 // clk_rc_p 0x1239_0x03 = 0x004F
463 // Due to the security concern
464 // Set this CLK at SBOOT
465 //
466
467 //
468 // clk_mips_occ12 0x110c_0x11[10] = 1
469 //
470 u32Val = _AESDMA_REG32_R(&_MispOccCtrl[0].Reg0001);
471 u32Val |= 0x04000000;
472 REG32_W((&_MispOccCtrl[0].Reg0001) , u32Val);
473
474
475 //3. Enable Rng
476 u32Val = _AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0001);
477 u32Val |= REG_RNG_EN;
478 REG32_W((&_SECUREBASECtrl[0].Reg0001) , u32Val);
479
480 }
481
AESDMA_Disable_Clk(void)482 void AESDMA_Disable_Clk(void)
483 {
484 REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) | AESDMA_CLK_OFF_EN);
485 }
486
AESDMA_Rand(void)487 MS_U8 AESDMA_Rand(void)
488 {
489 MS_U8 u8RN = 0x00;
490 u8RN = (MS_U8)_AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0203)&0xFF;
491
492 return u8RN;
493 }
494
SHA_Reset(void)495 void SHA_Reset(void)
496 {
497 MS_VIRT Reg_SHARNG;
498 MS_U32 i = 0;
499 Reg_SHARNG = (MS_VIRT)(&_SHARNGCtrl[0].Sha_Ctrl);
500 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , SHARNG_CTRL_SHA_RST); // 0->1
501 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&(~SHARNG_CTRL_SHA_RST))); // 1->0
502
503 // reset all SHA & RNG register
504 for (i = 0 ; i < 7 ; i++)
505 {
506 REG32_W((REG32 *)(Reg_SHARNG+(i*8)), 0x00000000);
507 }
508 }
509
SHA_Get_Status(void)510 MS_U32 SHA_Get_Status(void)
511 {
512 return _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Status);
513 }
514
SHA_SelMode(AESDMA_SHAMode eMode)515 void SHA_SelMode(AESDMA_SHAMode eMode)
516 {
517 MS_U32 u32Cmd = 0;
518
519 switch (eMode)
520 {
521 case E_AESDMA_SHA1:
522 u32Cmd |= (SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
523 break;
524
525 case E_AESDMA_SHA256:
526 u32Cmd |= (SHARNG_CTRL_SHA_SEL_SHA256 | SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
527 break;
528
529 default:
530 return;
531 }
532
533 //Turn off speedup mode
534 //u32Cmd |= SHARNG_CTRL_SPEED_MODE_N;
535
536 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl), _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl) | u32Cmd);
537 }
538
SHA_SetAddress(MS_PHY u32Addr)539 void SHA_SetAddress(MS_PHY u32Addr)
540 {
541 REG32_W((&_SHARNGCtrl[0].Sha_Start), u32Addr);
542 }
543
SHA_SetLength(MS_U32 u32Size)544 void SHA_SetLength(MS_U32 u32Size)
545 {
546 REG32_W((&_SHARNGCtrl[0].Sha_Length), u32Size);
547 }
548
SHA_Start(MS_BOOL SHAStart)549 void SHA_Start(MS_BOOL SHAStart)
550 {
551 if(SHAStart)
552 {
553 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
554 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_FIRE_ONCE));
555 }
556 else
557 {
558 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
559 }
560 }
561
SHA_Out(MS_VIRT u32Buf)562 void SHA_Out(MS_VIRT u32Buf)
563 {
564 MS_U32 Index, u32Size, u32offset;
565 MS_U32 eMode = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&SHARNG_CTRL_SHA_SEL_SHA256;
566
567 if(eMode == SHARNG_CTRL_SHA_SEL_SHA256)
568 {
569 u32Size = DIGEST_SIZE_SHA256;
570 u32offset = 0;
571 }
572 else
573 {
574 u32Size = DIGEST_SIZE_SHA1;
575 u32offset = 3;
576 }
577
578 for( Index = 0; Index < u32Size; Index++ )
579 {
580 *((MS_U32 *)u32Buf + Index) = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Out[Index + u32offset]);
581 }
582 //Set "1" to idle state after reg_read_sha_ready = 1
583 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_CLR));
584 }
585
586
587 //-------------------------------------------------------------------------------------------------
588 /// Enable mobf one way function
589 /// @param NULL
590
591 /// @note : disable read mobf key, and could not enable read mobf key anymore
592 //-------------------------------------------------------------------------------------------------
MOBF_OneWay(void)593 void MOBF_OneWay(void)
594 {
595 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_ONEWAY_EN));
596 }
597
598 //-------------------------------------------------------------------------------------------------
599 /// Set MOBF encrypt key
600 /// @param u32WriteKey \b IN: Encrypt Key
601
602 /// @note
603 //-------------------------------------------------------------------------------------------------
MOBF_WriteKey(MS_U32 u32WriteKey)604 void MOBF_WriteKey(MS_U32 u32WriteKey)
605 {
606 REG32_W((&_SHARNGCtrl[0].MOBF_KeyW) , u32WriteKey);
607 }
608
609 //-------------------------------------------------------------------------------------------------
610 /// Set MOBF decrypt key
611 /// @param u32ReadKey \b IN: Decrypt Key
612
613 /// @note
614 //-------------------------------------------------------------------------------------------------
MOBF_ReadKey(MS_U32 u32ReadKey)615 void MOBF_ReadKey(MS_U32 u32ReadKey)
616 {
617 REG32_W((&_SHARNGCtrl[0].MOBF_KeyR) , u32ReadKey);
618 }
619
620 //-------------------------------------------------------------------------------------------------
621 /// Enable MOBF in MIU write port
622 /// @param bEnable \b IN: Enable/Disable
623
624 /// @note : MOBF Encrypt
625 //-------------------------------------------------------------------------------------------------
MOBF_WriteEnable(MS_BOOL bEnable)626 void MOBF_WriteEnable(MS_BOOL bEnable)
627 {
628 if(bEnable)
629 {
630 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
631 }
632 else
633 {
634 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
635 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_WRITE_EN));
636 }
637 }
638
639 //-------------------------------------------------------------------------------------------------
640 /// Enable MOBF in MIU read port
641 /// @param bEnable \b IN: Enable/Disable
642
643 /// @note : MOBF Decrypt
644 //-------------------------------------------------------------------------------------------------
MOBF_ReadEnable(MS_BOOL bEnable)645 void MOBF_ReadEnable(MS_BOOL bEnable)
646 {
647 if(bEnable)
648 {
649 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
650 }
651 else
652 {
653 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
654 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_READ_EN));
655 }
656 }
657
658 //-------------------------------------------------------------------------------------------------
659 /// Disable TDES
660 ///
661
662 /// @note : MOBF Decrypt
663 //-------------------------------------------------------------------------------------------------
MOBF_DisableTDES(void)664 void MOBF_DisableTDES(void)
665 {
666 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) & (~AESDMA_DMA_USE_TDES_EN));
667 }
668
AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)669 void AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)
670 {
671 MS_U32 u32Cmd = 0;
672
673 switch (eMode)
674 {
675 case E_AESDMA_PARSER_TS_PKT192:
676 u32Cmd |= (TS_MODE | PKT192_MODE);
677 break;
678
679 case E_AESDMA_PARSER_TS_PKT192_CLEAR:
680 u32Cmd |= (TS_MODE | PKT192_MODE | CLEAR_MODE);
681 break;
682
683 case E_AESDMA_PARSER_TS_PKT188:
684 u32Cmd |= (TS_MODE);
685 u32Cmd &= (~PKT192_MODE);
686 break;
687
688 case E_AESDMA_PARSER_TS_PKT188_CLEAR:
689 u32Cmd |= (TS_MODE | CLEAR_MODE);
690 u32Cmd &= (~PKT192_MODE);
691 break;
692
693 case E_AESDMA_PARSER_HDCP20_PKT192:
694 u32Cmd |= (HDCP20_MODE | PKT192_MODE);
695 break;
696
697 case E_AESDMA_PARSER_HDCP20_PKT192_CLEAR:
698 u32Cmd |= (HDCP20_MODE | PKT192_MODE | CLEAR_MODE);
699 break;
700
701 case E_AESDMA_PARSER_HDCP20_PKT188:
702 u32Cmd |= (HDCP20_MODE);
703 u32Cmd &= (~PKT192_MODE);
704 break;
705
706 case E_AESDMA_PARSER_HDCP20_PKT188_CLEAR:
707 u32Cmd |= (HDCP20_MODE | CLEAR_MODE);
708 u32Cmd &= (~PKT192_MODE);
709 break;
710
711 default:
712 return;
713 }
714
715 u32Cmd |= (AUTO_MODE | INIT_TRUST);
716 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~ParserCtrlSet)) | u32Cmd ) );
717 }
718
719
AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)720 void AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)
721 {
722 if(bEnable)
723 {
724 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
725 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (INSERT_SCRMB)) );
726 }
727 else
728 {
729 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
730 }
731 }
732
AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)733 void AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)
734 {
735 if(bEnable)
736 {
737 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
738 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (REMOVE_SCRMB)) );
739 }
740 else
741 {
742 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
743 }
744 }
745
AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)746 void AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)
747 {
748 if(bEnable)
749 {
750 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
751 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (TS_SCRMB_MASK)) );
752 }
753 else
754 {
755 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
756 }
757 }
758
AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)759 void AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)
760 {
761 if(bEnable)
762 {
763 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
764 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (BYPASS_PID)) );
765 }
766 else
767 {
768 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
769 }
770 }
771
AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)772 void AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)
773 {
774 MS_U32 u32Cmd = 0;
775
776 switch (ePattern)
777 {
778 case E_AESDMA_PARSER_SCRMB_10:
779 u32Cmd |= (SCRMB_PATTERN10);
780 break;
781
782 case E_AESDMA_PARSER_SCRMB_11:
783 u32Cmd |= (SCRMB_PATTERN11);
784 break;
785
786 default:
787 u32Cmd &= ~(SCRMB_PATTERN11);
788 break;
789 }
790
791 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~SCRMB_INITVALUE)) | u32Cmd ) );
792
793 }
794
AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)795 void AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)
796 {
797 MS_U32 u32Cmd = 0;
798
799 switch (ePattern)
800 {
801 case E_AESDMA_PARSER_SCRMB_10:
802 u32Cmd |= (SCRMB_PATTERN10_ADD);
803 break;
804
805 case E_AESDMA_PARSER_SCRMB_11:
806 u32Cmd |= (SCRMB_PATTERN11_ADD);
807 break;
808
809 default:
810 return;
811 }
812
813 REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_INITVALUE_ADD)) | u32Cmd ) );
814
815 }
816
AESDMA_Parser_Set_Pid(MS_U8 u8Index,MS_U16 u16Pid)817 void AESDMA_Parser_Set_Pid(MS_U8 u8Index, MS_U16 u16Pid)
818 {
819 if(u8Index==0)
820 {
821 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~PARSER_PID0_MASK)) | (u16Pid<<16) ) );
822 }
823 else if(u8Index==1)
824 {
825 REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~PARSER_PID1_MASK)) | u16Pid ) );
826 }
827 else
828 {
829 ULOGE(TAG_AESDMA, "Edison do not support other PID\n");
830 }
831 }
832
AESDMA_Parser_Query_PidCount(void)833 MS_U8 AESDMA_Parser_Query_PidCount(void)
834 {
835 return PARSER_PID_COUNT;
836 }
837
AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)838 void AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)
839 {
840 if(bEnable)
841 {
842 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE)) );
843 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (HW_PARSER_MODE)) );
844 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (ENABLE_LG_PATCH)) );
845 }
846 else
847 {
848 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE)) );
849 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~ENABLE_LG_PATCH)) );
850 }
851
852 //make sure CC_CTRL_BY_ACPU is set 0
853 REG32_W((&_CIPHERCtrl[0].Cipher_Ctrl),( _AESDMA_REG32_R(&_CIPHERCtrl[0].Cipher_Ctrl) & (~CC_CTRL_BY_ACPU)) );
854 }
855
RSA_ClearInt(void)856 void RSA_ClearInt(void)
857 {
858 //RSA interrupt clear
859 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_INT_CLR));
860 }
861
RSA_Reset(void)862 void RSA_Reset(void)
863 {
864 //RSA Rst
865 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_RSA_RST));
866 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_RSA_RST));
867
868 //add polling RSA status before load data to SRAM
869 while (( RSA_GetStatus() & RSA_STATUS_RSA_BUSY ) != 0);
870 }
871
RSA_Ind32Ctrl(MS_U8 u8dirction)872 void RSA_Ind32Ctrl(MS_U8 u8dirction)
873 {
874 //[1] reg_ind32_direction 0: Read. 1: Write
875 if(u8dirction==1)
876 {
877 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_DIRECTION_WRITE));
878 }
879 else
880 {
881 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)&(~RSA_IND32_CTRL_DIRECTION_WRITE));
882 }
883
884 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_ADDR_AUTO_INC|RSA_IND32_CTRL_ACCESS_AUTO_START));
885
886 }
887
RSA_LoadSram(MS_U32 * u32Buf,RSA_IND32Address eMode)888 void RSA_LoadSram(MS_U32 *u32Buf, RSA_IND32Address eMode)
889 {
890 MS_U32 u32Cmd = 0;
891 MS_U32 i = 0;
892 MS_U32 WData_H = 0;
893 MS_U32 WData_L = 0;
894
895 switch (eMode)
896 {
897 case E_RSA_ADDRESS_E:
898 u32Cmd |= (RSA_E_BASE_ADDR);
899 break;
900
901 case E_RSA_ADDRESS_N:
902 u32Cmd |= (RSA_N_BASE_ADDR);
903 break;
904
905 case E_RSA_ADDRESS_A:
906 u32Cmd |= (RSA_A_BASE_ADDR);
907 break;
908
909 default:
910 return;
911 }
912
913 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Cmd));
914 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
915
916 for( i = 0; i < 64; i++ )
917 {
918 if( eMode == E_RSA_ADDRESS_E )
919 {
920 WData_L = (((*(u32Buf+i))>>8)&0xFF00)|(((*(u32Buf+i))>>24)&0xFF);
921 WData_H = (((*(u32Buf+i))>>8)&0xFF)|(((*(u32Buf+i))<<8)&0xFF00);
922 }
923 else
924 {
925 WData_L = (((*(u32Buf-i))>>8)&0xFF00)|(((*(u32Buf-i))>>24)&0xFF);
926 WData_H = (((*(u32Buf-i))>>8)&0xFF)|(((*(u32Buf-i))<<8)&0xFF00);
927 }
928
929 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_WDATA_MASK_L))|(WData_L<<16)));
930 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_WData) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&(~RSA_WDATA_MASK_H))|WData_H));
931 }
932
933 }
934
RSA_SetKeyLength(MS_U32 u32keylen)935 void RSA_SetKeyLength(MS_U32 u32keylen)
936 {
937 //[13:8] n_len_e: key length
938 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_KEY_LENGTH_MASK))|(u32keylen<<8));
939 }
940
RSA_SetKeyType(MS_U8 u8hwkey,MS_U8 u8pubkey)941 void RSA_SetKeyType(MS_U8 u8hwkey, MS_U8 u8pubkey)
942 {
943 //[1] hw_key_e : 0 : software key, 1: hardware key
944 //[2] e_pub_e : 0: pvivate key, 1: public key
945 if(u8hwkey==1)
946 {
947 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_HW_KEY));
948 }
949 else
950 {
951 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_HW_KEY));
952 }
953
954 if(u8pubkey==1)
955 {
956 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_PUBLIC_KEY));
957 }
958 else
959 {
960 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_PUBLIC_KEY));
961 }
962
963 }
964
RSA_ExponetialStart(void)965 void RSA_ExponetialStart(void)
966 {
967 //RSA exp start
968 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_EXP_START));
969 }
970
RSA_GetStatus(void)971 MS_U32 RSA_GetStatus(void)
972 {
973 return _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl) & RSA_STATUS_MASK;
974 }
975
RSA_FileOutStart(void)976 void RSA_FileOutStart(void)
977 {
978 //RSA ind32_start
979 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
980 }
981
RSA_SetFileOutAddr(MS_U32 u32offset)982 void RSA_SetFileOutAddr(MS_U32 u32offset)
983 {
984 MS_PHY u32Addr = 0;
985 u32Addr = RSA_Z_BASE_ADDR + u32offset;
986
987 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Addr));
988 }
989
RSA_FileOut(void)990 MS_U32 RSA_FileOut(void)
991 {
992 MS_U32 u32out_L = 0;
993 MS_U32 u32out_H = 0;
994
995 u32out_L = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&RSA_RDATA_MASK_L)>>16;
996 u32out_H = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)&RSA_RDATA_MASK_H)<<16;
997
998 return (u32out_H|u32out_L);
999 }
1000
RSA_Get_RSA_IsFinished(void)1001 MS_U32 RSA_Get_RSA_IsFinished(void)
1002 {
1003 return (RSA_GetStatus()&RSA_STATUS_RSA_BUSY);
1004 }
1005
1006 //reserved for secure protect function
1007 /*
1008 void AESDMA_Secure_SetCipherKey(MS_U32 *cipherkey)
1009 {
1010 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_L.Key_L) , cipherkey[0]);
1011 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_L.Key_H) , cipherkey[1]);
1012 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_H.Key_L) , cipherkey[2]);
1013 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_H.Key_H) , cipherkey[3]);
1014 }
1015
1016 void AESDMA_Secure_SetInitVector(MS_U32 *pInitVector)
1017 {
1018 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_L.IV_L), pInitVector[0]);
1019 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_L.IV_H), pInitVector[1]);
1020 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_H.IV_L), pInitVector[2]);
1021 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_H.IV_H), pInitVector[3]);
1022 }
1023
1024 void AESDMA_SecureProtect(MS_BOOL bEnable)
1025 {
1026 if(bEnable)
1027 {
1028 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl)|(AESDMA_SECURE_PROTECT_S));
1029 }
1030 else
1031 {
1032 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl)&(~AESDMA_SECURE_PROTECT_S));
1033 }
1034 }
1035
1036 void AESDMA_Set_FileOutEnable(MS_BOOL bEnable)
1037 {
1038 if (bEnable)
1039 {
1040 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) |AESDMA_CTRL_FILEIN_START));
1041 }
1042 else
1043 {
1044 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) &~AESDMA_CTRL_FILEIN_START));
1045 }
1046 }
1047
1048 void AESDMA_Secure_Start(MS_BOOL AESDMAStart)
1049 {
1050 if (AESDMAStart)
1051 {
1052 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) &~AESDMA_SECURE_FILEIN_START));
1053 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) | AESDMA_SECURE_FILEIN_START));
1054 }
1055 else
1056 {
1057 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) &~AESDMA_SECURE_FILEIN_START));
1058 }
1059 }
1060
1061 MS_U32 AESDMA_Get_AESDMA_SecureIsFinished(void)
1062 {
1063 return (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_status) & AESDMA_DONE_S);
1064 }
1065
1066 */
1067
1068 //-------------------------------------------------------------------------------------------------
1069 /// Get status of Secret Key in Normal bank
1070 /// @param N/A
1071 /// @note : Get Status
1072 //-------------------------------------------------------------------------------------------------
AESDMA_IsSecretKeyInNormalBank(void)1073 MS_U32 AESDMA_IsSecretKeyInNormalBank(void)
1074 {
1075 return (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl) & (SECRET_KEY_IN_NORMAL_BANK));
1076 }
1077
1078 //-------------------------------------------------------------------------------------------------
1079 /// Enable Two keys (Odd/Even) in using HW auto select key.
1080 /// @param bEnable \b IN: Enable/Disable
1081
1082 /// @note : Hardware Parser Decrypt
1083 //-------------------------------------------------------------------------------------------------
AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)1084 void AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)
1085 {
1086 if(bEnable)
1087 {
1088 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (SCRMB_ENABLE_TWO_KEY) );
1089 }
1090 else
1091 {
1092 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_ENABLE_TWO_KEY) );
1093 }
1094 }
1095
1096 //-------------------------------------------------------------------------------------------------
1097 /// Set Odd keys in using HW auto select key.
1098 /// @param cipherkey
1099 /// @note : Hardware Parser Decrypt
1100 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherOddKey(MS_U32 * cipherkey)1101 void AESDMA_Set_CipherOddKey(MS_U32 *cipherkey)
1102 {
1103 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
1104 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
1105 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
1106 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
1107 }
1108
1109 //-------------------------------------------------------------------------------------------------
1110 /// Set Odd IVs in using HW auto select key.
1111 /// @param cipherkey
1112 /// @note : Hardware Parser Decrypt
1113 //-------------------------------------------------------------------------------------------------
AESDMA_Set_OddInitVector(MS_U32 * pInitVector)1114 void AESDMA_Set_OddInitVector(MS_U32 *pInitVector)
1115 {
1116 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_L), pInitVector[0]);
1117 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_H), pInitVector[1]);
1118 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_L), pInitVector[2]);
1119 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_H), pInitVector[3]);
1120 }
1121
1122 //-------------------------------------------------------------------------------------------------
1123 /// Set Even keys in using HW auto select key.
1124 /// @param cipherkey
1125 /// @note : Hardware Parser Decrypt
1126 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherEvenKey(MS_U32 * cipherkey)1127 void AESDMA_Set_CipherEvenKey(MS_U32 *cipherkey)
1128 {
1129 AESDMA_Set_CipherKey(cipherkey);
1130 }
1131
1132 //-------------------------------------------------------------------------------------------------
1133 /// Set Even IVs in using HW auto select key.
1134 /// @param cipherkey
1135 /// @note : Hardware Parser Decrypt
1136 //-------------------------------------------------------------------------------------------------
AESDMA_Set_EvenInitVector(MS_U32 * pInitVector)1137 void AESDMA_Set_EvenInitVector(MS_U32 *pInitVector)
1138 {
1139 AESDMA_Set_InitVector(pInitVector);
1140 }
1141
1142 //-------------------------------------------------------------------------------------------------
1143 /// Set HDCP Data
1144 /// @param u8Idx \b IN: Index
1145 /// @param pu8Data \b IN: Content Keys
1146 /// @param pu8privData \b IN: RIV
1147 /// @note : Set HDCP2.2
1148 //-------------------------------------------------------------------------------------------------
HDCP_ProcessCipher(MS_U8 u8Idx,MS_U8 * pu8Data,MS_U8 * pu8privData)1149 void HDCP_ProcessCipher (MS_U8 u8Idx, MS_U8 *pu8Data, MS_U8* pu8privData)
1150 {
1151 REG_HDCP22Data *pData = NULL;
1152 REG_HDCP22SEKCtrl *pCtrl = NULL;
1153 MS_U16 offset = 0;
1154 MS_U16 BKOffset = 0;
1155
1156 MS_U32 cipherkey[4];
1157 MS_U32 riv[2];
1158 int i;
1159
1160 for (i=0; i<4; ++i)
1161 {
1162 int off = i*4;
1163 cipherkey[i] = ((MS_U32)(pu8Data[off]) & 0xff) | (((MS_U32)(pu8Data[off+1]) & 0xff)<<8) | (((MS_U32)(pu8Data[off+2]) & 0xff)<<16) | (((MS_U32)(pu8Data[off+3]) & 0xff)<<24);
1164 }
1165 for (i=0; i<2; ++i)
1166 {
1167 int off = i*4;
1168 riv[i] = ((MS_U32)(pu8privData[off]) & 0xff) | (((MS_U32)(pu8privData[off+1]) & 0xff)<<8) | (((MS_U32)(pu8privData[off+2]) & 0xff)<<16) | (((MS_U32)(pu8privData[off+3]) & 0xff)<<24);
1169 }
1170
1171 offset = u8Idx * (sizeof(REG_HDCP22Data) >> 1);
1172 BKOffset = u8Idx * 0x300;
1173
1174 pData = (REG_HDCP22Data*)((MS_U16*)_HDCP22Data + offset);
1175 pCtrl = (REG_HDCP22SEKCtrl*)((MS_U16*)_HDCP22SekCtrl + BKOffset);
1176
1177 //Content Keys
1178 REG32_W((&pData[0].Hdcp22_ContentKey[0]) , cipherkey[0]);
1179 REG32_W((&pData[0].Hdcp22_ContentKey[1]) , cipherkey[1]);
1180 REG32_W((&pData[0].Hdcp22_ContentKey[2]) , cipherkey[2]);
1181 REG32_W((&pData[0].Hdcp22_ContentKey[3]) , cipherkey[3]);
1182
1183 //RIV
1184 REG32_W((&pData[0].Hdcp22_Riv[0]) , riv[0]);
1185 REG32_W((&pData[0].Hdcp22_Riv[1]) , riv[1]);
1186
1187 //Set SKE successful
1188 REG32_W((&pCtrl[0].SEK), (_AESDMA_REG32_R(&pCtrl[0].SEK) | HDCP_SEK_BIT0));
1189 }
1190
1191 //-------------------------------------------------------------------------------------------------
1192 /// Get the status of HW supports HDCP2.2
1193 /// @param N/A
1194 /// @note : Support HDCP2.2
1195 //-------------------------------------------------------------------------------------------------
HDCP_GetHdcpCipherState(MS_U8 u8Idx,MS_U8 * pu8State)1196 void HDCP_GetHdcpCipherState(MS_U8 u8Idx, MS_U8 *pu8State)
1197 {
1198 #define HDCP_SUPPORT_EN 0x00000001
1199 REG_HDCP22SEKCtrl *pCtrl = NULL;
1200 MS_U16 offset = 0;
1201 MS_U16 BKOffset = 0;
1202
1203 offset = u8Idx * (sizeof(REG_HDCP22Data) >> 1);
1204 BKOffset = u8Idx * 0x300;
1205
1206 pCtrl = (REG_HDCP22SEKCtrl*)((MS_U16*)_HDCP22SekCtrl + BKOffset);
1207
1208 *pu8State = (MS_U8)(_AESDMA_REG32_R(&pCtrl[0].SEK) & HDCP_SUPPORT_EN);
1209 }
1210
1211 //-------------------------------------------------------------------------------------------------
1212 /// Reset AESDMA
1213 /// @param N/A
1214 /// @note : Clear Registers, not to do sw reset
1215 //-------------------------------------------------------------------------------------------------
AESDMA_NormalReset(void)1216 void AESDMA_NormalReset(void)
1217 {
1218 MS_VIRT Reg_AESDMA;
1219 MS_U32 i = 0;
1220 Reg_AESDMA = (MS_VIRT)(&_AESDMACtrl[0].Dma_Ctrl);
1221
1222 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
1223
1224 // reset all AESdma register
1225 for (i = 0 ; i < 19 ; i++)
1226 {
1227 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
1228 }
1229 // reset secure_dma3_ctrl register
1230 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
1231
1232 // reset hw_parser_ctrl register
1233 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x01000000);
1234 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
1235 }
1236