1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2006-2013 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halCIPHER.c
20 // @brief CIPHER HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #ifdef MSOS_TYPE_LINUX_KERNEL
24 #include <linux/string.h>
25 #include <linux/uaccess.h>
26 #include <linux/compat.h>
27 #else
28 #include <stdio.h>
29 #include <string.h>
30 #endif
31
32
33 #include "MsCommon.h"
34 #include "regCIPHER.h"
35 #include "halCIPHER.h"
36 #include "drvCIPHER.h"
37 #include "halCHIP.h"
38
39 #ifndef MSOS_TYPE_LINUX_KERNEL
40 extern void * memset ( void * ptr, int value, size_t num );
41 extern void * memcpy ( void * destination, const void * source, size_t num );
42 extern int printf ( const char * format, ... );
43 #endif
44 //--------------------------------------------------------------------------------------------------
45 // Driver Compiler Option
46 //--------------------------------------------------------------------------------------------------
47
48 //--------------------------------------------------------------------------------------------------
49 // Macro of bit operations
50 //--------------------------------------------------------------------------------------------------
51 #define DELAY_WAITING 1UL
52 #define DELAY_RESCHEDULE 10UL
53 #define COMQ_AVALIABLE 0x10UL
54 #define CIPHER_KEY_SIZE 16UL
55 #define CRYPTODMA_DEBUG_SIZE 32UL
56 #define HASH_MANUAL_BLOCK_SIZE 64UL
57 #define PID_SIZE 2UL
58 #define MIU_SELECT_BIT 0x80000000UL
59
60 //--------------------------------------------------------------------------------------------------
61 // TSP Hardware Abstraction Layer
62 //--------------------------------------------------------------------------------------------------
63 static MS_VIRT _u32RegBase = 0;
64 static REG_AESDMACtrl *_AESDMACtrl = 0 ;
65 static CIPHER_DBGMSG_LEVEL _HAL_CIPHERDBGLevel = CIPHER_DBG_ERR;
66
67 // Algorithm Table for AES/TDES/DES
68 static MS_BOOL _CryptodMA_AlgoTable[4][E_DMA_MODE_NUM][E_DMA_RESIDUE_NUM][E_DMA_SB_NUM];
69
70 #define REG_READ 0
71 #define REG_WRITE 1
72 #define REG32_R(Addr) _REG32_R((MS_VIRT)Addr)
73 #define REG32_W(Addr, Value) _REG32_W((MS_VIRT)Addr, Value)
74 #define REG16_R(Addr) _REG16_R((MS_VIRT)Addr)
75 #define REG16_W(Addr, Value) _REG16_W((MS_VIRT)Addr, Value)
76
77 #ifdef CIPHER_NO_PRINTF
78 #define HAL_DEBUG_CIPHER(debug_level, x)
79 #else
80 #define HAL_DEBUG_CIPHER(debug_level, x) do { if (_HAL_CIPHERDBGLevel >= (debug_level)) (x); } while(0)
81 #endif
82 //--------------------------------------------------------------------------------------------------
83 // Local Variable
84 //--------------------------------------------------------------------------------------------------
85
86 MS_PHY _u32DmaInAddr;
87 MS_U32 _u32DmaInNum;
88 MS_PHY _u32DmaOut_StartAddr;
89 MS_PHY _u32DmaOut_EndAddr;
90 MS_PHY _u32ReportAddr;
91 MS_U32 _u32OTPHashLengthPadding;
92
93 MS_U8 _pu8CipherKey[CIPHER_KEY_SIZE];
94 MS_U8 _pu8CipherKey2[CIPHER_KEY_SIZE];
95 MS_U8 _pu8IV[CIPHER_KEY_SIZE];
96 MS_U8 _pu8IV2[CIPHER_KEY_SIZE];
97 MS_U8 _pu8Data[CIPHER_KEY_SIZE];
98 MS_U8 _pu8PID0[PID_SIZE];
99 MS_U8 _pu8PID1[PID_SIZE];
100
101 MS_U32 _u32CmdLen = 0 ;
102
103 // [NOTE] Solve Strict-Aliasing //
104 union {
105 CMD_DmaFormat0 DmaCtrl0;
106 MS_U32 u32DmaCtrl0;
107 }_uDmaCtrl0;
108
109 union{
110 CMD_DmaFormat1 DmaCtrl1;
111 MS_U32 u32DmaCtrl1;
112 }_uDmaCtrl1;
113
114 union{
115 CMD_DmaFormat2 DmaCtrl2;
116 MS_U32 u32DmaCtrl2;
117 }_uDmaCtrl2;
118
119 union{
120 CMD_DmaFormat3 DmaCtrl3;
121 MS_U32 u32DmaCtrl3;
122 }_uDmaCtrl3;
123
124 union{
125 Hash_DmaFormat0 HashCtrl0;
126 MS_U32 u32HashCtrl0;
127 }_uHashCtrl0;
128
129 union{
130 Hash_DmaFormat1 HashCtrl1;
131 MS_U32 u32HashCtrl1;
132 }_uHashCtrl1;
133
134 union{
135 CMD_HashFormat2 HashCtrl2;
136 MS_U32 u32HashCtrl2;
137 }_uHashCtrl2;
138
139 MS_PHY _u32HashSrcAddr;
140 MS_PHY _u32HashDestAddr;
141 MS_U32 _u32InitWordCnt;
142 MS_U32 _u32HashMsgLen;
143
144 MS_U8 _pu8HashIV[HASH_CMD_IV_SIZE];
145 MS_U8 _pu8HashMsg[HASH_CMD_MSG_SIZE];
146 MS_U8 _pu8HashHMACHostKey[HASH_CMD_HMAC_HOSTKEY_SIZE];
147
148 static MS_U32 _CIPHER_CAVid = 0x0F;
149
150 //--------------------------------------------------------------------------------------------------
151 // Inline Function
152 //--------------------------------------------------------------------------------------------------
153 #ifdef CIPHER_SMC_MODE
REG_REE2ATF(MS_U64 u64Addr,MS_U64 u64Value,MS_U64 u64Status)154 static MS_U64 REG_REE2ATF(MS_U64 u64Addr, MS_U64 u64Value, MS_U64 u64Status)
155 {
156 MS_U64 u64Tmp = 0;
157
158 asm volatile(
159 "ldr x0, =0x8400ee01\n\t"
160 "ldr x1, %1\n\t"
161 "ldr x2, %2\n\t"
162 "ldr x3, %3\n\t"
163 "smc #0\n\t"
164 "mov %0, x0\n\t"
165 : "=r" (u64Tmp)
166 : "m" (u64Addr), "m" (u64Value), "m" (u64Status):"x0", "x1", "x2", "x3"
167 );
168
169 return u64Tmp;
170 }
171 #endif
172
_REG32_R(MS_VIRT u32Reg)173 static MS_U32 _REG32_R(MS_VIRT u32Reg)
174 {
175 #ifdef CIPHER_SMC_MODE
176 return REG_REE2ATF(u32Reg, 0, REG_READ) ;
177 #else
178 return *((volatile MS_U32*)u32Reg);
179 #endif
180 }
181
_REG32_W(MS_VIRT u32Reg,MS_U32 u32Value)182 static void _REG32_W(MS_VIRT u32Reg, MS_U32 u32Value)
183 {
184 #ifdef CIPHER_SMC_MODE
185 REG_REE2ATF(u32Reg, u32Value, REG_WRITE);
186 #else
187 *((volatile MS_U32*)u32Reg) = u32Value;
188 #endif
189 }
190
_REG16_R(MS_VIRT u32Reg)191 static MS_U16 _REG16_R(MS_VIRT u32Reg)
192 {
193 return REG32_R(u32Reg) & 0x0000FFFFUL;
194 }
195
_REG16_W(MS_VIRT u32Reg,MS_U16 u16Value)196 static void _REG16_W(MS_VIRT u32Reg, MS_U16 u16Value)
197 {
198 MS_U32 u32Value = (REG32_R(u32Reg) & 0xFFFF0000UL) | (u16Value & 0x0000FFFFUL);
199 REG32_W(u32Reg, u32Value);
200 }
201
WRITE_CMDQ(MS_U32 u32Value)202 void WRITE_CMDQ(MS_U32 u32Value)
203 {
204 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s] = 0x%08X \n",__func__, (unsigned int)(u32Value)));
205 REG32_W(&_AESDMACtrl->Cmd_Queue, u32Value) ;
206 }
207
_HAL_CIPHER_TransMIUAddr(MS_PHY * phyAddr)208 MS_BOOL _HAL_CIPHER_TransMIUAddr(MS_PHY* phyAddr)
209 {
210 CHIP_MIU_ID eMIUSel;
211 MS_PHY phyOffset;
212
213 if(NULL == phyAddr)
214 {
215 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]NULL Address!\n",__func__, __LINE__));
216 return FALSE;
217 }
218
219 _phy_to_miu_offset(eMIUSel,phyOffset,*phyAddr);
220
221 if(E_CHIP_MIU_0 == eMIUSel)
222 {
223 *phyAddr = phyOffset;
224 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Physical address trans to MIU0\n",__func__, __LINE__));
225 }
226 else
227 {
228 *phyAddr = (phyOffset | MIU_SELECT_BIT);
229 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Physical address trans to MIU1\n",__func__, __LINE__));
230 }
231
232 return TRUE;
233 }
234
_HAL_CIPHER_GetCmdLen(HAL_CIPHER_CMDTYPE CmdType)235 MS_U32 _HAL_CIPHER_GetCmdLen(HAL_CIPHER_CMDTYPE CmdType)
236 {
237
238 MS_U32 u32CmdLen = 0 ;
239
240
241 if ( E_CIPHER_TYPE_DMA == CmdType )
242 {
243 u32CmdLen = 7;
244
245 if ( _uDmaCtrl1.DmaCtrl1.RR == TRUE )
246 {
247 u32CmdLen += 1 ;
248 }
249 if ( _uDmaCtrl0.DmaCtrl0.DIV == TRUE )
250 {
251 u32CmdLen += 4 ;
252 }
253 if ( _uDmaCtrl1.DmaCtrl1.SD == E_DMA_SRC_DIRECT )
254 {
255 u32CmdLen += 4 ;
256 }
257 if ( _uDmaCtrl0.DmaCtrl0.DK == TRUE )
258 {
259 u32CmdLen += 4 ;
260 }
261 if ( _uDmaCtrl2.DmaCtrl2.HP == TRUE )
262 {
263 u32CmdLen += 1 ;
264 }
265 if ( _uDmaCtrl3.DmaCtrl3.DK2 == TRUE )
266 {
267 u32CmdLen += 4 ;
268 }
269 if ( _uDmaCtrl3.DmaCtrl3.DIV2 == TRUE )
270 {
271 u32CmdLen += 4 ;
272 }
273
274 return u32CmdLen ;
275 }
276
277
278 if ( E_CIPHER_TYPE_SHA == CmdType )
279 {
280
281 u32CmdLen = 3 ;
282
283 if (_uHashCtrl0.HashCtrl0.CMD == CMD_HASH_START_RR )
284 {
285 u32CmdLen += 1 ;
286 }
287
288 if (_uHashCtrl0.HashCtrl0.Src != CMD_HASH_SRC_REG )
289 {
290 u32CmdLen += 1 ;
291 }
292
293 if(_uHashCtrl2.HashCtrl2.RR == TRUE)
294 {
295 u32CmdLen += 1 ;
296 }
297
298 if (_uHashCtrl0.HashCtrl0.IWC_Sel == CMD_HASH_IWC_CMDQ )
299 {
300 u32CmdLen += 1 ;
301 }
302
303 if ((_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_DRAM ) || (_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_R2 ))
304 {
305 u32CmdLen += 1 ;
306 }
307
308 if (_uHashCtrl0.HashCtrl0.InitHashSel == CMD_HASH_IV_CMD )
309 {
310 u32CmdLen += 8 ;
311 }
312
313 if (_uHashCtrl0.HashCtrl0.Src == CMD_HASH_SRC_REG )
314 {
315 u32CmdLen += 16 ;
316 }
317
318 if((_uHashCtrl0.HashCtrl0.HMAC_KeySel == CMD_HMAC_KSEL_HK) && (_uHashCtrl0.HashCtrl0.DK == CMD_HMAC_KSEL_DIR_HK))
319 {
320 u32CmdLen += 4 ;
321 }
322
323 return u32CmdLen ;
324
325 }
326
327 if ( E_CIPHER_TYPE_OTPHASH == CmdType )
328 {
329 u32CmdLen = 7 ;
330
331 if ( _uDmaCtrl1.DmaCtrl1.NL == TRUE )
332 {
333 u32CmdLen += 1 ;
334 }
335 if ( _uDmaCtrl1.DmaCtrl1.RR == TRUE )
336 {
337 u32CmdLen += 1 ;
338 }
339 if ( _uDmaCtrl3.DmaCtrl3.AP == TRUE && _uDmaCtrl3.DmaCtrl3.IK == FALSE)
340 {
341 u32CmdLen += 1 ;
342 }
343
344 return u32CmdLen ;
345 }
346
347
348 return 0 ;
349
350 }
351
_HAL_CIPHER_TransKey(CIPHER_KEY_SRC src,MS_U32 idx)352 HAL_CIPHER_KEYSRC _HAL_CIPHER_TransKey(CIPHER_KEY_SRC src, MS_U32 idx)
353 {
354 HAL_CIPHER_KEYSRC KeySrc = E_DMA_KSEL_REGKEY;
355
356 switch(src){
357 case E_CIPHER_KSRC_KL:
358 KeySrc = E_DMA_KSEL_SK0 + idx;
359 break;
360
361 case E_CIPHER_KSRC_OTP:
362 KeySrc = E_DMA_KSEL_MK0 + idx;
363 break;
364
365 case E_CIPHER_KSRC_CPU:
366 KeySrc = E_DMA_KSEL_REGKEY;
367 break;
368
369 case E_CIPHER_KSRC_CAIP:
370 KeySrc = E_DMA_KSEL_CAIP;
371 break;
372
373 //case E_CIPHER_KSRC_STR:
374 // KeySrc = E_DMA_KSEL_STRN;
375 // break;
376
377 default:
378 break;
379 }
380
381 return KeySrc;
382 }
383
_HAL_CIPHER_TransMainAlgo(CIPHER_MAIN_ALGO algo)384 HAL_CIPHER_ALGO _HAL_CIPHER_TransMainAlgo(CIPHER_MAIN_ALGO algo)
385 {
386 HAL_CIPHER_ALGO hal_algo;
387 switch(algo)
388 {
389 case E_CIPHER_MAIN_AES:
390 hal_algo = E_DMA_ALGO_AES;
391 break;
392 case E_CIPHER_MAIN_DES:
393 hal_algo = E_DMA_ALGO_DES;
394 break;
395 case E_CIPHER_MAIN_TDES:
396 hal_algo = E_DMA_ALGO_TDES;
397 break;
398 case E_CIPHER_MAIN_M6_S56_CCBC:
399 hal_algo = E_DMA_ALGO_M6_S56_CCBC;
400 break;
401 case E_CIPHER_MAIN_M6_S56:
402 hal_algo = E_DMA_ALGO_M6_S56;
403 break;
404 case E_CIPHER_MAIN_M6_KE56:
405 hal_algo = E_DMA_ALGO_M6_KE56;
406 break;
407 case E_CIPHER_MAIN_RC4:
408 hal_algo = E_DMA_ALGO_RC4;
409 break;
410 case E_CIPHER_MAIN_RC4_128:
411 hal_algo = E_DMA_ALGO_RC4_128;
412 break;
413 default:
414 hal_algo = E_DMA_ALGO_NONE;
415 }
416
417 return hal_algo;
418 }
419
_HAL_CIPHER_TransSubAlgo(CIPHER_SUB_ALGO algo)420 HAL_CIPHER_MODE _HAL_CIPHER_TransSubAlgo(CIPHER_SUB_ALGO algo)
421 {
422 HAL_CIPHER_MODE hal_algo;
423 switch(algo)
424 {
425 case E_CIPHER_SUB_ECB:
426 hal_algo = E_DMA_MODE_ECB;
427 break;
428 case E_CIPHER_SUB_CBC:
429 hal_algo = E_DMA_MODE_CBC;
430 break;
431 case E_CIPHER_SUB_CTR:
432 hal_algo = E_DMA_MODE_CTR;
433 break;
434 case E_CIPHER_SUB_CBC_MAC:
435 hal_algo = E_DMA_MODE_CBC_MAC;
436 break;
437 case E_CIPHER_SUB_CTR_64:
438 hal_algo = E_DMA_MODE_CTR_64;
439 break;
440 case E_CIPHER_SUB_CMAC_Key:
441 hal_algo = E_DMA_MODE_CMAC_Key;
442 break;
443 case E_CIPHER_SUB_CMAC_Algo:
444 hal_algo = E_DMA_MODE_CMAC_Algo;
445 break;
446 case E_CIPHER_SUB_PCBC_ADD:
447 hal_algo = E_DMA_MODE_PCBC_ADD;
448 break;
449 case E_CIPHER_SUB_PCBC_XOR:
450 hal_algo = E_DMA_MODE_PCBC_XOR;
451 break;
452 case E_CIPHER_SUB_OTPHASH:
453 hal_algo = E_DMA_MODE_OTPHASH;
454 break;
455 default:
456 hal_algo = E_DMA_MODE_NONE;
457 }
458
459 return hal_algo;
460
461 }
462
_HAL_CIPHER_TransResAlgo(CIPHER_RES_ALGO algo)463 HAL_CIPHER_RESIDUE _HAL_CIPHER_TransResAlgo(CIPHER_RES_ALGO algo)
464 {
465 HAL_CIPHER_RESIDUE hal_algo;
466 switch(algo)
467 {
468 case E_CIPHER_RES_CLR:
469 hal_algo = E_DMA_RESIDUE_CLR;
470 break;
471 case E_CIPHER_RES_CTS:
472 hal_algo = E_DMA_RESIDUE_CTS;
473 break;
474 case E_CIPHER_RES_SCTE52:
475 hal_algo = E_DMA_RESIDUE_SCTE52;
476 break;
477 default:
478 hal_algo = E_DMA_RESIDUE_NONE;
479 }
480
481 return hal_algo;
482 }
483
_HAL_CIPHER_TransSBAlgo(CIPHER_SB_ALGO algo)484 HAL_CIPHER_SHORTBLOCK _HAL_CIPHER_TransSBAlgo(CIPHER_SB_ALGO algo)
485 {
486 HAL_CIPHER_SHORTBLOCK hal_algo;
487 switch(algo)
488 {
489 case E_CIPHER_SB_CLR:
490 hal_algo = E_DMA_SB_CLR;
491 break;
492 case E_CIPHER_SB_IV1:
493 hal_algo = E_DMA_SB_IV1;
494 break;
495 case E_CIPHER_SB_IV2:
496 hal_algo = E_DMA_SB_IV2;
497 break;
498 default:
499 hal_algo = E_DMA_SB_NONE;
500 }
501
502 return hal_algo;
503
504 }
505
_HAL_CIPHER_TransHASHAlgo(CIPHER_HASH_ALGO algo)506 HAL_CIPHER_HASHMODE _HAL_CIPHER_TransHASHAlgo(CIPHER_HASH_ALGO algo)
507 {
508 HAL_CIPHER_HASHMODE hal_algo;
509 switch(algo)
510 {
511 case E_CIPHER_HASH_ALGO_SHA1:
512 hal_algo = E_HASH_SHA1;
513 break;
514 case E_CIPHER_HASH_ALGO_SHA256:
515 hal_algo = E_HASH_SHA256;
516 break;
517 case E_CIPHER_HASH_ALGO_MD5:
518 hal_algo = E_HASH_MD5;
519 break;
520 default:
521 hal_algo = E_HASH_SHA256;
522 }
523
524 return hal_algo;
525 }
526
HAL_CIPHER_DMA_AlgoTable_Init(void)527 void HAL_CIPHER_DMA_AlgoTable_Init(void)
528 {
529
530 memset(_CryptodMA_AlgoTable , 0x0 , sizeof(_CryptodMA_AlgoTable));
531
532 // AES algorithms //
533 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
534 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
535 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
536 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
537 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
538 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
539 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
540 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC_MAC][E_DMA_RESIDUE_CLR][E_DMA_RESIDUE_CLR] = TRUE ;
541 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CTR][E_DMA_RESIDUE_NONE][E_DMA_SB_NONE] = TRUE ; // residue & sb don't care
542
543 // DES Algorithms //
544 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
545 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
546 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
547 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
548 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
549 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
550 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV2] = TRUE ;
551 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
552 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CTR][E_DMA_RESIDUE_NONE][E_DMA_SB_NONE] = TRUE ; // residue & sb don't care
553
554 // TDES Algorithm //
555 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
556 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
557 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CTR][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
558 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
559 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
560 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
561 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
562 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV2] = TRUE ;
563 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
564
565 }
566
567
HAL_CIPHER_DMA_CheckAlgo(HAL_CIPHER_ALGO eAlgo,HAL_CIPHER_MODE eMode,HAL_CIPHER_RESIDUE eRes,HAL_CIPHER_SHORTBLOCK eSB)568 MS_BOOL HAL_CIPHER_DMA_CheckAlgo(HAL_CIPHER_ALGO eAlgo, HAL_CIPHER_MODE eMode, HAL_CIPHER_RESIDUE eRes, HAL_CIPHER_SHORTBLOCK eSB)
569 {
570 // Special Cases //
571 if (eAlgo > E_DMA_ALGO_TDES )
572 {
573 if ((E_DMA_ALGO_RC4==eAlgo)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR == eSB)&&(E_DMA_MODE_NONE==eMode))
574 { //RC4/none/none/none
575 return TRUE ;
576 }
577 if ((E_DMA_ALGO_M6_KE56==eAlgo)&&(E_DMA_MODE_ECB==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
578 { //M6_KE56/ecb/none/clr
579 return TRUE;
580 }
581 if ((E_DMA_ALGO_M6_S56==eAlgo)&&(E_DMA_MODE_ECB==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
582 { //M6_S56/ecb/none/clr
583 return TRUE;
584 }
585 if ((E_DMA_ALGO_M6_S56_CCBC==eAlgo)&&(E_DMA_MODE_NONE==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
586 { //M6_S56_CCBC/none/none/clr
587 return TRUE;
588 }
589 return FALSE ;
590 }
591
592 // Reference table for Algorithm AES/TDES/DES //
593 return _CryptodMA_AlgoTable[eAlgo][eMode][eRes][eSB] ;
594 }
595
HAL_CIPHER_SetBank(MS_VIRT u32BankAddr)596 void HAL_CIPHER_SetBank(MS_VIRT u32BankAddr)
597 {
598 _u32RegBase = u32BankAddr;
599 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);
600 }
601
HAL_CIPHER_SetDbgLevel(CIPHER_DBGMSG_LEVEL eDBGMsgLevel)602 void HAL_CIPHER_SetDbgLevel(CIPHER_DBGMSG_LEVEL eDBGMsgLevel)
603 {
604 _HAL_CIPHERDBGLevel = eDBGMsgLevel;
605 }
606
HAL_CIPHER_ResetStatus(MS_BOOL RstDma,MS_BOOL RstHash)607 void HAL_CIPHER_ResetStatus(MS_BOOL RstDma , MS_BOOL RstHash)
608 {
609 if (RstDma)
610 {
611 _uDmaCtrl0.u32DmaCtrl0 = 0 ;
612 _uDmaCtrl1.u32DmaCtrl1 = 0 ;
613 _uDmaCtrl2.u32DmaCtrl2 = 0 ;
614 _uDmaCtrl3.u32DmaCtrl3 = 0 ;
615
616 _u32DmaInAddr = 0;
617 _u32DmaInNum = 0 ;
618 _u32OTPHashLengthPadding = 0;
619 _u32DmaOut_StartAddr = 0;
620 _u32DmaOut_EndAddr = 0;
621 _u32ReportAddr = 0 ;
622 memset(&_pu8CipherKey , 0x0, CIPHER_KEY_SIZE );
623 memset(&_pu8IV , 0x0, CIPHER_KEY_SIZE );
624 memset(&_pu8CipherKey2 , 0x0, CIPHER_KEY_SIZE );
625 memset(&_pu8IV2 , 0x0, CIPHER_KEY_SIZE );
626 memset(&_pu8Data , 0x0, CIPHER_KEY_SIZE );
627 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Reset DMA value\n", __FUNCTION__, __LINE__));
628
629 }
630
631 if (RstHash)
632 {
633 (_uHashCtrl0.u32HashCtrl0) = 0 ;
634 (_uHashCtrl1.u32HashCtrl1) = 0 ;
635 (_uHashCtrl2.u32HashCtrl2) = 0 ;
636
637 _u32HashSrcAddr = 0 ;
638 _u32InitWordCnt = 0 ;
639 _u32HashDestAddr = 0 ;
640 _u32HashMsgLen = 0 ;
641
642 memset(_pu8HashIV, 0x0 ,HASH_CMD_IV_SIZE);
643 memset(_pu8HashMsg, 0x0 , HASH_CMD_MSG_SIZE);
644 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Reset HASH value\n", __FUNCTION__, __LINE__));
645 }
646
647 }
648
HAL_CIPHER_ResetException(void)649 void HAL_CIPHER_ResetException(void)
650 {
651 MS_U32 u32DMACtrl = REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);
652 REG32_W(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL], u32DMACtrl | REG_EXCEPT_FLAG_CLEAR); //clear all except flag
653 REG32_W(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL], u32DMACtrl & ~REG_EXCEPT_FLAG_CLEAR); //enable acpu except flag
654 }
655
HAL_CIPHER_ResetKey(MS_U32 u32KeyIdx)656 MS_BOOL HAL_CIPHER_ResetKey(MS_U32 u32KeyIdx)
657 {
658 HAL_CIPHER_KEYSRC KeySrc;
659
660 //Check Key Index
661 if(u32KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)
662 {
663 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid Key Index[%u]\n",
664 __func__, __LINE__, u32KeyIdx));
665 return FALSE;
666 }
667
668 KeySrc = _HAL_CIPHER_TransKey(E_CIPHER_KSRC_KL, u32KeyIdx);
669
670 _uDmaCtrl0.DmaCtrl0.DK = FALSE;
671 _uDmaCtrl0.DmaCtrl0.KeySel = KeySrc|CMD_DMA_KSEL_CLR_SK;
672
673 return TRUE;
674
675 }
HAL_CIPHER_SWReset(void)676 void HAL_CIPHER_SWReset(void)
677 {
678 MS_U32 DMA_CTRL = REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);
679 REG32_W(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL], DMA_CTRL | REG_DMA_SW_RESET); //reset CryptoDMA
680 REG32_W(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL], DMA_CTRL & ~REG_DMA_SW_RESET); //enable CryptoDMA
681
682 }
683
HAL_CIPHER_Set_OBFIdx(MS_BOOL bDMA,MS_U8 u8ReadIdx,MS_U8 u8WriteIdx)684 MS_BOOL HAL_CIPHER_Set_OBFIdx(MS_BOOL bDMA, MS_U8 u8ReadIdx, MS_U8 u8WriteIdx)
685 {
686 if(bDMA)
687 {
688 _uDmaCtrl2.DmaCtrl2.OBF_IDX_READ = u8ReadIdx;
689 _uDmaCtrl2.DmaCtrl2.OBF_IDX_WRITE = u8WriteIdx;
690 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Set DMA Obf Index Read:[%u], Write:[%u]\n",
691 __func__, __LINE__, u8ReadIdx, u8WriteIdx));
692 }
693 else
694 {
695 _uHashCtrl1.HashCtrl1.OBF_IDX_READ = u8ReadIdx;
696 _uHashCtrl1.HashCtrl1.OBF_IDX_WRITE = u8WriteIdx;
697 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Set HASH Obf Index Read:[%u], Write:[%u]\n",
698 __func__, __LINE__, u8ReadIdx, u8WriteIdx));
699 }
700
701 return TRUE;
702 }
703
HAL_CIPHER_DMA_Set_InputSrcFrom(CIPHER_MEM_TYPE InputSrcFrom,MS_U8 * pu8Data,MS_U32 u32Size)704 void HAL_CIPHER_DMA_Set_InputSrcFrom(CIPHER_MEM_TYPE InputSrcFrom, MS_U8* pu8Data, MS_U32 u32Size)
705 {
706 HAL_CIPHER_DATASRC src = E_DMA_SRC_DRAM;
707
708 switch(InputSrcFrom)
709 {
710 case E_CIPHER_DRAM:
711 _u32DmaInAddr = 0;
712 src = E_DMA_SRC_DRAM;
713 break;
714
715 case E_CIPHER_DQMEM://only for R2
716 _u32DmaInAddr = HAL_CIPHER_BASE_DQMEM;
717 src = E_DMA_SRC_DQMEM;
718 break;
719
720 case E_CIPHER_IQMEM://only for R2
721 _u32DmaInAddr = HAL_CIPHER_BASE_IQMEM;
722 src = E_DMA_SRC_IQMEM;
723 break;
724
725 // TODO: future work, DIRECT data from pu8Data
726 #if 0
727 case E_CIPHER_DIRECT:
728 HAL_CIPHER_DMA_Set_Data(pu8Data, u32Size);
729 src = E_DMA_SRC_DIRECT;
730 break;
731 #endif
732
733 case E_CIPHER_OTP: //only for OTPHASH
734 _u32DmaInAddr = 0;
735 src = E_DMA_SRC_HW_INPUT;
736 break;
737
738 default:
739 _u32DmaInAddr = 0;
740 src = E_DMA_SRC_DRAM;
741 break;
742 }
743
744 _uDmaCtrl1.DmaCtrl1.SD = (MS_U32)src;
745
746 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set input source from [%d]\n", __func__, __LINE__, src));
747 }
748
HAL_CIPHER_DMA_Set_OutputDstTo(CIPHER_MEM_TYPE OutputDstTo,MS_U8 * pu8Data,MS_U32 u32Size)749 MS_BOOL HAL_CIPHER_DMA_Set_OutputDstTo(CIPHER_MEM_TYPE OutputDstTo, MS_U8* pu8Data, MS_U32 u32Size)
750 {
751 HAL_CIPHER_DATADST dst = E_DMA_DST_DRAM;
752
753 switch(OutputDstTo)
754 {
755 case E_CIPHER_DRAM:
756 _u32DmaOut_StartAddr = 0;
757 _u32DmaOut_EndAddr = 0;
758 dst = E_DMA_DST_DRAM;
759 break;
760
761 case E_CIPHER_DQMEM: //only for R2
762 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_DQMEM;
763 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_DQMEM;
764 dst = E_DMA_DST_DQMEM;
765 break;
766
767 case E_CIPHER_IQMEM: //only for R2
768 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_IQMEM;
769 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_IQMEM;
770 dst = E_DMA_DST_IQMEM;
771 break;
772
773 case E_CIPHER_DIRECT: //for ACPU, OTPHASH
774 dst = E_DMA_DST_REGFILE;
775 break;
776
777 case E_CIPHER_KL_LUT: //for KL transform algorithm
778 case E_CIPHER_KL_M:
779 case E_CIPHER_KL_BC:
780 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Not support output destination to Keyladder\n", __func__, __LINE__));
781 return FALSE;
782
783 default:
784 _u32DmaOut_StartAddr = 0;
785 _u32DmaOut_EndAddr = 0;
786 dst = E_DMA_DST_DRAM;
787 break;
788 }
789
790 _uDmaCtrl1.DmaCtrl1.Dest= (MS_U32)dst;
791
792 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set output destination to [%d]\n", __func__, __LINE__, dst));
793
794 return TRUE;
795 }
796
HAL_CIPHER_DMA_Set_OutputDstKL(MS_BOOL bDstKL)797 void HAL_CIPHER_DMA_Set_OutputDstKL(MS_BOOL bDstKL)
798 {
799 if(bDstKL)
800 {
801 _uDmaCtrl1.DmaCtrl1.DestKL = CMD_DMA_OUTPUT_SRAM_KL;
802 _uDmaCtrl0.DmaCtrl0.DK = TRUE;
803 }
804 else
805 {
806 _uDmaCtrl1.DmaCtrl1.DestKL = CMD_DMA_OUTPUT_DEST;
807 }
808 }
809
HAL_CIPHER_DMA_Set_FileinDesc(MS_PHY u32FileinAddr,MS_U32 u32FileinNum)810 void HAL_CIPHER_DMA_Set_FileinDesc(MS_PHY u32FileinAddr, MS_U32 u32FileinNum)
811 {
812
813 _u32DmaInAddr += u32FileinAddr;
814 _u32DmaInNum = u32FileinNum ;
815 }
816
HAL_CIPHER_DMA_Set_FileoutDesc(MS_PHY u32FileoutSAddr,MS_PHY u32phyFileoutEAddr)817 void HAL_CIPHER_DMA_Set_FileoutDesc(MS_PHY u32FileoutSAddr, MS_PHY u32phyFileoutEAddr)
818 {
819 _u32DmaOut_StartAddr += u32FileoutSAddr;
820 _u32DmaOut_EndAddr += u32phyFileoutEAddr;
821
822 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d] _u32DmaOut_StartAddr = %x _u32DmaOut_EndAddr = %x\n", __func__, __LINE__, (unsigned int)_u32DmaOut_StartAddr, (unsigned int)_u32DmaOut_EndAddr));
823 }
824
HAL_CIPHER_OTPHash_Set_FileinDesc(MS_PHY u32FileinAddr,MS_U32 u32FileinNum,MS_U32 u32CurrentRound,CIPHER_MEM_TYPE eInputSrcFrom)825 void HAL_CIPHER_OTPHash_Set_FileinDesc(MS_PHY u32FileinAddr, MS_U32 u32FileinNum, MS_U32 u32CurrentRound, CIPHER_MEM_TYPE eInputSrcFrom)
826 {
827 if(E_CIPHER_OTP == eInputSrcFrom)
828 {
829 _u32DmaInAddr = u32CurrentRound;
830 }
831 else
832 {
833 _u32DmaInAddr = u32FileinAddr + u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT;
834 }
835
836 _u32OTPHashLengthPadding = u32FileinNum;
837 if((u32FileinNum - u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT) >= HAL_CRYPTODMA_OTPHASH_UNIT)
838 {
839 _u32DmaInNum = HAL_CRYPTODMA_OTPHASH_UNIT;
840 }
841 else
842 {
843 _u32DmaInNum = u32FileinNum - u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT;
844 }
845
846 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d] _u32DmaInAddr = %x _u32DmaInNum = %x _u32OTPHashLengthPadding = %x\n", __func__, __LINE__, (unsigned int)_u32DmaInAddr, (unsigned int)_u32DmaInNum, (unsigned int)_u32OTPHashLengthPadding));
847 }
848
HAL_CIPHER_DMA_Set_Key(DRV_CIPHER_KEY stKey)849 MS_BOOL HAL_CIPHER_DMA_Set_Key(DRV_CIPHER_KEY stKey)
850 {
851 HAL_CIPHER_KEYSRC KeySrc = 0;
852 HAL_CIPHER_ALGO algo = 0;
853 MS_BOOL bDK = FALSE;
854
855 algo = _uDmaCtrl0.DmaCtrl0.Algo;
856
857 if(E_DMA_ALGO_NONE == algo)
858 {
859 //No key
860 bDK = TRUE;
861 memset(_pu8CipherKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
862 goto SET_KEY_DONE;
863 }
864 //Check Key Source, Index
865 if(((E_CIPHER_KSRC_KL == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
866 ((E_CIPHER_KSRC_OTP == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
867 {
868 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
869 __func__, __LINE__, stKey.eKeySrc, stKey.u8KeyIdx));
870 return FALSE;
871 }
872
873 //DRV to HAL Type transfer
874 KeySrc = _HAL_CIPHER_TransKey(stKey.eKeySrc, stKey.u8KeyIdx);
875
876 // key from CPU
877 if(E_DMA_KSEL_REGKEY == KeySrc)
878 {
879 if ((NULL != stKey.pu8KeyData) && (stKey.u8KeyLen != 0) && (stKey.u8KeyLen <= HAL_CRYPTODMA_KEYLEN_MAX) )
880 {
881 memset(_pu8CipherKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
882 memcpy(_pu8CipherKey, (MS_U8 *)stKey.pu8KeyData , stKey.u8KeyLen);
883 bDK = TRUE ;
884 KeySrc = 0;
885 }
886 else
887 {
888 return FALSE ;
889 }
890
891 }
892 else if(E_DMA_KSEL_CAIP == KeySrc)
893 {
894 bDK = FALSE ;
895 KeySrc = 0 ;
896 }
897 else// key from KL or OTP or STR
898 {
899 bDK = FALSE;
900 }
901
902 SET_KEY_DONE:
903
904 _uDmaCtrl0.DmaCtrl0.DK = bDK;
905 _uDmaCtrl0.DmaCtrl0.KeySel = KeySrc;
906
907 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DK[%d], KeySel[%d]\n",
908 __func__, __LINE__, bDK, KeySrc));
909
910 return TRUE ;
911 }
912
HAL_CIPHER_DMA_Set_IV(MS_U8 * pu8IV,MS_U32 u32Size)913 void HAL_CIPHER_DMA_Set_IV(MS_U8* pu8IV, MS_U32 u32Size)
914 {
915 MS_BOOL bDIV = FALSE;
916
917 if ((NULL != pu8IV) && (u32Size != 0) && (u32Size <= HAL_CRYPTODMA_KEYLEN_MAX) )
918 {
919 memset(_pu8IV, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
920 memcpy(_pu8IV, (MS_U8 *)pu8IV, u32Size);
921 bDIV = TRUE;
922 }
923 else // Data from Dram
924 {
925 memset(_pu8IV, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
926 bDIV = FALSE;
927 }
928
929 _uDmaCtrl0.DmaCtrl0.DIV = bDIV ;
930
931 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DIV[%d]\n",
932 __func__, __LINE__, bDIV));
933 }
934
935
936 // Set Direct Data to Register Input, if Dram input, set pu8Data = NULL ;
HAL_CIPHER_DMA_Set_Data(MS_U8 * pu8Data,MS_U32 u32Size)937 MS_BOOL HAL_CIPHER_DMA_Set_Data(MS_U8* pu8Data, MS_U32 u32Size)
938 {
939 HAL_CIPHER_DATASRC eDataSrc = E_DMA_SRC_DRAM;
940
941 // Data size can't be zero //
942 if (( 0 == u32Size ) && (NULL != pu8Data ))
943 {
944 return FALSE ;
945 }
946
947 if (NULL != pu8Data ) // Data from CMDQ
948 {
949 _u32DmaInNum = u32Size ;
950 memset(_pu8Data, 0x0, HAL_CRYPTODMA_DIRDATA_MAX);
951 memcpy(_pu8Data, (MS_U8 *)pu8Data, u32Size);
952 eDataSrc = E_DMA_SRC_DIRECT ;
953 }
954 else // Data from Dram
955 {
956 memset(_pu8Data, 0x0 , HAL_CRYPTODMA_DIRDATA_MAX );
957 eDataSrc = E_DMA_SRC_DRAM ;
958 }
959
960 _uDmaCtrl1.DmaCtrl1.SD = (MS_U32)eDataSrc ;
961
962 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set SD[%d]\n",
963 __func__, __LINE__, eDataSrc));
964
965 return TRUE ;
966 }
967
HAL_CIPHER_DMA_Set_CaVid(MS_U32 u32CAVid)968 MS_BOOL HAL_CIPHER_DMA_Set_CaVid(MS_U32 u32CAVid)
969 {
970 MS_U32 u32Tmp = u32CAVid;
971
972 if(u32Tmp > HAL_CRYPTODMA_CAVID_MAX)
973 {
974 return FALSE;
975 }
976
977 if(u32Tmp == 0)
978 {
979 u32Tmp = _CIPHER_CAVid ;
980 }
981 else
982 {
983 u32Tmp = u32CAVid ;
984 }
985
986 _uDmaCtrl1.DmaCtrl1.CaVid = u32Tmp ;
987
988 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set CAVid [0x%x]\n",
989 __func__, __LINE__, (unsigned int)u32Tmp));
990
991 return TRUE;
992 }
993
HAL_CIPHER_DMA_Set_Config(MS_BOOL OutputReg)994 void HAL_CIPHER_DMA_Set_Config(MS_BOOL OutputReg)
995 {
996 _uDmaCtrl1.DmaCtrl1.Dest= OutputReg ;
997 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set dest[%d]\n",
998 __func__, __LINE__, OutputReg));
999 }
1000
1001
HAL_CIPHER_DMA_Set_ReportMode(MS_BOOL RptInDram,MS_PHY u32DramAddr)1002 void HAL_CIPHER_DMA_Set_ReportMode(MS_BOOL RptInDram, MS_PHY u32DramAddr)
1003 {
1004 MS_BOOL bRR = FALSE;
1005
1006 if (RptInDram)
1007 {
1008 bRR = TRUE ;
1009 _u32ReportAddr = u32DramAddr;
1010
1011 }
1012 else
1013 {
1014 bRR = FALSE ;
1015 _u32ReportAddr = 0;
1016
1017 }
1018
1019 _uDmaCtrl1.DmaCtrl1.RR = bRR;
1020
1021 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set report mode[%d], report address[0x%08x]\n",
1022 __func__, __LINE__, bRR, (unsigned int)_u32ReportAddr));
1023 }
1024
1025 // [NOTE] HW Bug, the DMA can't support DRAM Data Swap, Data Error for input and output
HAL_CIPHER_DMA_Set_DataSwap(MS_BOOL InDataSwap,MS_BOOL OutDataSwap,MS_BOOL DInByteSwap,MS_BOOL DOutByteSwap)1026 void HAL_CIPHER_DMA_Set_DataSwap(MS_BOOL InDataSwap , MS_BOOL OutDataSwap,
1027 MS_BOOL DInByteSwap, MS_BOOL DOutByteSwap )
1028 {
1029 _uDmaCtrl1.DmaCtrl1.CIS = InDataSwap ;
1030 _uDmaCtrl1.DmaCtrl1.COS = OutDataSwap ;
1031 //_uDmaCtrl1.DmaCtrl1.DODS = DOutBitSwap ;
1032 _uDmaCtrl1.DmaCtrl1.DOBS = DOutByteSwap ;
1033 _uDmaCtrl1.DmaCtrl1.DIBS = DInByteSwap;
1034
1035 }
1036
1037
1038 //void HAL_CIPHER_DMA_Set_Algo(CipherAlgo algo , CipherMode subalgo , Cipher_Residue eRes , Cipher_ShortBlock eSB )
HAL_CIPHER_DMA_Set_Algo(DRV_CIPHER_ALGO stAlgo)1039 void HAL_CIPHER_DMA_Set_Algo(DRV_CIPHER_ALGO stAlgo)
1040 {
1041 HAL_CIPHER_ALGO algo;
1042 HAL_CIPHER_MODE subalgo;
1043 HAL_CIPHER_RESIDUE eRes;
1044 HAL_CIPHER_SHORTBLOCK eSB;
1045
1046 if(_uDmaCtrl1.DmaCtrl1.CaVid == E_CIPHER_CAVID1)
1047 {
1048 algo = (HAL_CIPHER_ALGO)stAlgo.eMainAlgo;
1049 subalgo = (HAL_CIPHER_MODE)stAlgo.eSubAlgo;
1050
1051 // For OTPHASH in E_CIPHER_CAVID1
1052 if(stAlgo.eSubAlgo == E_CIPHER_SUB_OTPHASH)
1053 subalgo = E_DMA_MODE_OTPHASH;
1054 }
1055 else
1056 {
1057 algo = _HAL_CIPHER_TransMainAlgo(stAlgo.eMainAlgo);
1058 subalgo = _HAL_CIPHER_TransSubAlgo(stAlgo.eSubAlgo);
1059 }
1060
1061 eRes = _HAL_CIPHER_TransResAlgo(stAlgo.eResAlgo);
1062 eSB = _HAL_CIPHER_TransSBAlgo(stAlgo.eSBAlgo);
1063
1064 _uDmaCtrl0.DmaCtrl0.Algo= algo ;
1065 _uDmaCtrl0.DmaCtrl0.SubAlgo= subalgo ;
1066 _uDmaCtrl0.DmaCtrl0.Residue = eRes ;
1067 _uDmaCtrl0.DmaCtrl0.SB = eSB ;
1068
1069 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set algorithm, MAIN[%d], SUB[%d], RES[%d], SB[%d]\n",
1070 __func__, __LINE__, algo, subalgo, eRes, eSB));
1071 }
1072
HAL_CIPHER_DMA_Set_OTPHash(MS_U32 u32CurrentRound,MS_U32 u32OTPHashRound)1073 void HAL_CIPHER_DMA_Set_OTPHash(MS_U32 u32CurrentRound, MS_U32 u32OTPHashRound)
1074 {
1075 _uDmaCtrl3.DmaCtrl3.AP = 0;
1076 _uDmaCtrl3.DmaCtrl3.IK = 0;
1077 // First OTPHASH enable IK, other disable IK
1078 if(u32CurrentRound == 0)
1079 {
1080 _uDmaCtrl3.DmaCtrl3.IK = 1;
1081 }
1082 // Final OTPHASH enable AP, other disable AP
1083 if(u32CurrentRound == u32OTPHashRound)
1084 {
1085 _uDmaCtrl3.DmaCtrl3.AP = 1;
1086 }
1087
1088 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set OTPHASH, AP[%d], IK[%d]\n",
1089 __func__, __LINE__, _uDmaCtrl3.DmaCtrl3.AP, _uDmaCtrl3.DmaCtrl3.IK));
1090 }
1091
HAL_CIPHER_DMA_WriteCMDQ(MS_U32 u32Cmd)1092 void HAL_CIPHER_DMA_WriteCMDQ(MS_U32 u32Cmd)
1093 {
1094 WRITE_CMDQ(u32Cmd) ;
1095 }
1096
HAL_CIPHER_DMA_GetData(MS_U8 * u8Data)1097 void HAL_CIPHER_DMA_GetData(MS_U8 *u8Data)
1098 {
1099
1100 MS_U32 tmp ;
1101
1102 // [Note] for u8Data is not always 4 bytes alignment.
1103 tmp = REG32_R(&_AESDMACtrl->Dma_Out[0]);
1104 u8Data[0] = (tmp >> 0) & 0xFF ;
1105 u8Data[1] = (tmp >> 8) & 0xFF ;
1106 u8Data[2] = (tmp >> 16) & 0xFF ;
1107 u8Data[3] = (tmp >> 24) & 0xFF ;
1108
1109 tmp = REG32_R(&_AESDMACtrl->Dma_Out[1]);
1110 u8Data[4] = (tmp >> 0) & 0xFF ;
1111 u8Data[5] = (tmp >> 8) & 0xFF ;
1112 u8Data[6] = (tmp >> 16) & 0xFF ;
1113 u8Data[7] = (tmp >> 24) & 0xFF ;
1114
1115 tmp = REG32_R(&_AESDMACtrl->Dma_Out[2]);
1116 u8Data[8] = (tmp >> 0) & 0xFF ;
1117 u8Data[9] = (tmp >> 8) & 0xFF ;
1118 u8Data[10] = (tmp >> 16) & 0xFF ;
1119 u8Data[11] = (tmp >> 24) & 0xFF ;
1120
1121 tmp = REG32_R(&_AESDMACtrl->Dma_Out[3]);
1122 u8Data[12] = (tmp >> 0) & 0xFF ;
1123 u8Data[13] = (tmp >> 8) & 0xFF ;
1124 u8Data[14] = (tmp >> 16) & 0xFF ;
1125 u8Data[15] = (tmp >> 24) & 0xFF ;
1126
1127 }
1128
HAL_CIPHER_DMA_GetRpt(MS_U32 * DmaRpt)1129 void HAL_CIPHER_DMA_GetRpt(MS_U32 *DmaRpt)
1130 {
1131 MS_U32 i ;
1132
1133 for (i = 0 ; i < DMA_RPT_REG_SIZE ; i++)
1134 {
1135 DmaRpt[i] = REG32_R(&_AESDMACtrl->Dma_Reportp[i]);
1136 }
1137 }
1138
HAL_CIPHER_DMA_Start(MS_BOOL Decrypt,HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_U16 u16CmdID)1139 MS_BOOL HAL_CIPHER_DMA_Start(MS_BOOL Decrypt, HAL_CIPHER_INTMODE IntMode, MS_BOOL bWaitCmdQ, MS_U16 u16CmdID)
1140 {
1141 MS_U32 u32SpareCnt = 0 , CmdLen = 0 ;
1142
1143 _uDmaCtrl0.DmaCtrl0.OVT = FALSE ;
1144
1145 //Set Thread Id
1146 _uDmaCtrl1.DmaCtrl1.TID = u16CmdID ;
1147
1148 _uDmaCtrl1.DmaCtrl1.IntM = IntMode ;
1149
1150 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_DMA);
1151
1152 _uDmaCtrl0.DmaCtrl0.CL = CmdLen & CMD_LEN_MASK ;
1153 _uDmaCtrl0.DmaCtrl0.CMD = ((Decrypt?0x3:0x2) & 0xF);
1154
1155 _uDmaCtrl2.DmaCtrl2.NS = 0;
1156 _uDmaCtrl1.DmaCtrl1.NL = CMD_NEW_LINE;
1157
1158 //Parser patch
1159 if(TRUE == _uDmaCtrl2.DmaCtrl2.HP)
1160 {
1161 MS_U32 u32Tmp = 0;
1162 u32Tmp = _AESDMACtrl->Dma_Ctrl[1];
1163 u32Tmp |= REG_PARSER_LG_PATH_EN;
1164 _AESDMACtrl->Dma_Ctrl[1] = u32Tmp;
1165 }
1166
1167 //Check STR key valid
1168 if(CMD_DMA_KSEL_TRNG == _uDmaCtrl0.DmaCtrl0.KeySel)
1169 {
1170 MS_U32 u32DMACtrl = REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);
1171 if(0 == (REG_DMA_STR_KEY_VALID & u32DMACtrl))
1172 {
1173 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]STR Key invalid!\n",__func__, __LINE__));
1174 return FALSE;
1175 }
1176 }
1177
1178 MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1179 REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf); //enable MIU crossbar
1180
1181
1182 if(_uDmaCtrl1.DmaCtrl1.SD == CMD_DMA_DATA_DRAM)
1183 {
1184 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaInAddr) == FALSE)
1185 {
1186 return FALSE;
1187 }
1188 }
1189
1190 if(_uDmaCtrl1.DmaCtrl1.Dest == CMD_DMA_OUTPUT_DRAM)
1191 {
1192 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaOut_StartAddr) == FALSE)
1193 {
1194 return FALSE;
1195 }
1196 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaOut_EndAddr) == FALSE)
1197 {
1198 return FALSE;
1199 }
1200 }
1201
1202 DMA_RETRY:
1203 // [HW] Hardware will check Current spare count first, and others read spare count will be zero!
1204 u32SpareCnt = REG32_R(&_AESDMACtrl->SpareCnt) ;
1205
1206 if (u32SpareCnt > CmdLen)
1207 {
1208 u32SpareCnt -= CmdLen ;
1209
1210 WRITE_CMDQ( (_uDmaCtrl0.u32DmaCtrl0)) ;
1211 WRITE_CMDQ( (_uDmaCtrl1.u32DmaCtrl1)) ;
1212 WRITE_CMDQ( (_uDmaCtrl2.u32DmaCtrl2)) ;
1213 WRITE_CMDQ( (_uDmaCtrl3.u32DmaCtrl3)) ;
1214
1215 WRITE_CMDQ((MS_U32)_u32DmaInAddr) ;
1216 WRITE_CMDQ(_u32DmaInNum) ;
1217 WRITE_CMDQ((MS_U32)_u32DmaOut_StartAddr);
1218 WRITE_CMDQ((MS_U32)_u32DmaOut_EndAddr);
1219
1220 if (_uDmaCtrl1.DmaCtrl1.RR == TRUE )
1221 {
1222 WRITE_CMDQ((MS_U32)_u32ReportAddr);
1223 }
1224
1225 // DMA Initial Vector from CmdQ
1226 if (_uDmaCtrl0.DmaCtrl0.DIV == TRUE )
1227 {
1228 #if 0
1229 WRITE_CMDQ(_pu8IV[15]<<24 |_pu8IV[14]<<16 | _pu8IV[13]<<8 | _pu8IV[12]);
1230 WRITE_CMDQ(_pu8IV[11]<<24 |_pu8IV[10]<<16 | _pu8IV[ 9]<<8 | _pu8IV[ 8]);
1231 WRITE_CMDQ(_pu8IV[ 3]<<24 |_pu8IV[ 2]<<16 | _pu8IV[ 1]<<8 | _pu8IV[ 0]);
1232 WRITE_CMDQ(_pu8IV[ 7]<<24 |_pu8IV[ 6]<<16 | _pu8IV[ 5]<<8 | _pu8IV[ 4]);
1233 #else
1234 WRITE_CMDQ(_pu8IV[ 0]<<24 |_pu8IV[ 1]<<16 | _pu8IV[ 2]<<8 | _pu8IV[ 3]);
1235 WRITE_CMDQ(_pu8IV[ 4]<<24 |_pu8IV[ 5]<<16 | _pu8IV[ 6]<<8 | _pu8IV[ 7]);
1236 WRITE_CMDQ(_pu8IV[ 8]<<24 |_pu8IV[ 9]<<16 | _pu8IV[10]<<8 | _pu8IV[11]);
1237 WRITE_CMDQ(_pu8IV[12]<<24 |_pu8IV[13]<<16 | _pu8IV[14]<<8 | _pu8IV[15]);
1238 #endif
1239 }
1240
1241 // DMA Data from CmdQ
1242 if (_uDmaCtrl1.DmaCtrl1.SD == CMD_DMA_DATA_REG )
1243 {
1244 #if 0
1245 WRITE_CMDQ(_pu8Data[15]<<24 |_pu8Data[14]<<16 | _pu8Data[13]<<8 | _pu8Data[12]);
1246 WRITE_CMDQ(_pu8Data[11]<<24 |_pu8Data[10]<<16 | _pu8Data[ 9]<<8 | _pu8Data[ 8]);
1247 WRITE_CMDQ(_pu8Data[ 7]<<24 |_pu8Data[ 6]<<16 | _pu8Data[ 5]<<8 | _pu8Data[ 4]);
1248 WRITE_CMDQ(_pu8Data[ 3]<<24 |_pu8Data[ 2]<<16 | _pu8Data[ 1]<<8 | _pu8Data[ 0]);
1249 #else
1250 WRITE_CMDQ(_pu8Data[ 0]<<24 |_pu8Data[ 1]<<16 | _pu8Data[ 2]<<8 | _pu8Data[ 3]);
1251 WRITE_CMDQ(_pu8Data[ 4]<<24 |_pu8Data[ 5]<<16 | _pu8Data[ 6]<<8 | _pu8Data[ 7]);
1252 WRITE_CMDQ(_pu8Data[ 8]<<24 |_pu8Data[ 9]<<16 | _pu8Data[10]<<8 | _pu8Data[11]);
1253 WRITE_CMDQ(_pu8Data[12]<<24 |_pu8Data[13]<<16 | _pu8Data[14]<<8 | _pu8Data[15]);
1254 #endif
1255 }
1256
1257 // DMA Key from CmdQ
1258 if (_uDmaCtrl0.DmaCtrl0.DK == TRUE )
1259 {
1260 #if 0
1261 WRITE_CMDQ(_pu8CipherKey[15]<<24 |_pu8CipherKey[14]<<16 | _pu8CipherKey[13]<<8 | _pu8CipherKey[12]);
1262 WRITE_CMDQ(_pu8CipherKey[11]<<24 |_pu8CipherKey[10]<<16 | _pu8CipherKey[ 9]<<8 | _pu8CipherKey[ 8]);
1263 WRITE_CMDQ(_pu8CipherKey[ 7]<<24 |_pu8CipherKey[ 6]<<16 | _pu8CipherKey[ 5]<<8 | _pu8CipherKey[ 4]);
1264 WRITE_CMDQ(_pu8CipherKey[ 3]<<24 |_pu8CipherKey[ 2]<<16 | _pu8CipherKey[ 1]<<8 | _pu8CipherKey[ 0]);
1265 #else
1266 WRITE_CMDQ(_pu8CipherKey[ 0]<<24 |_pu8CipherKey[ 1]<<16 | _pu8CipherKey[ 2]<<8 | _pu8CipherKey[ 3]);
1267 WRITE_CMDQ(_pu8CipherKey[ 4]<<24 |_pu8CipherKey[ 5]<<16 | _pu8CipherKey[ 6]<<8 | _pu8CipherKey[ 7]);
1268 WRITE_CMDQ(_pu8CipherKey[ 8]<<24 |_pu8CipherKey[ 9]<<16 | _pu8CipherKey[10]<<8 | _pu8CipherKey[11]);
1269 WRITE_CMDQ(_pu8CipherKey[12]<<24 |_pu8CipherKey[13]<<16 | _pu8CipherKey[14]<<8 | _pu8CipherKey[15]);
1270 #endif
1271 }
1272
1273 // PID for HW parser
1274 if (_uDmaCtrl2.DmaCtrl2.HP == TRUE )
1275 {
1276 WRITE_CMDQ(_pu8PID0[ 0]<<27 |_pu8PID0[ 1]<<19 | _pu8PID1[ 0]<<14 | _pu8PID1[ 1]<<6);
1277
1278 }
1279
1280 if (_uDmaCtrl3.DmaCtrl3.DIV2 == TRUE )
1281 {
1282 WRITE_CMDQ(_pu8IV2[ 0]<<24 |_pu8IV2[ 1]<<16 | _pu8IV2[ 2]<<8 | _pu8IV2[ 3]);
1283 WRITE_CMDQ(_pu8IV2[ 4]<<24 |_pu8IV2[ 5]<<16 | _pu8IV2[ 6]<<8 | _pu8IV2[ 7]);
1284 WRITE_CMDQ(_pu8IV2[ 8]<<24 |_pu8IV2[ 9]<<16 | _pu8IV2[10]<<8 | _pu8IV2[11]);
1285 WRITE_CMDQ(_pu8IV2[12]<<24 |_pu8IV2[13]<<16 | _pu8IV2[14]<<8 | _pu8IV2[15]);
1286 }
1287
1288 if (_uDmaCtrl3.DmaCtrl3.DK2 == TRUE )
1289 {
1290 WRITE_CMDQ(_pu8CipherKey2[ 0]<<24 |_pu8CipherKey2[ 1]<<16 | _pu8CipherKey2[ 2]<<8 | _pu8CipherKey2[ 3]);
1291 WRITE_CMDQ(_pu8CipherKey2[ 4]<<24 |_pu8CipherKey2[ 5]<<16 | _pu8CipherKey2[ 6]<<8 | _pu8CipherKey2[ 7]);
1292 WRITE_CMDQ(_pu8CipherKey2[ 8]<<24 |_pu8CipherKey2[ 9]<<16 | _pu8CipherKey2[10]<<8 | _pu8CipherKey2[11]);
1293 WRITE_CMDQ(_pu8CipherKey2[12]<<24 |_pu8CipherKey2[13]<<16 | _pu8CipherKey2[14]<<8 | _pu8CipherKey2[15]);
1294 }
1295
1296 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
1297 REG32_W(&_AESDMACtrl->SpareCnt, u32SpareCnt) ;
1298 return TRUE ;
1299
1300 }
1301 else
1302 {
1303 // [HW] Check Current spare count == Write back Spare count to start wait cmd
1304 REG32_W(&_AESDMACtrl->SpareCnt, u32SpareCnt) ;
1305 if (bWaitCmdQ)
1306 {
1307 // Retry until CMDQ avaliable
1308 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA retry!\n",__func__, __LINE__));
1309 goto DMA_RETRY;
1310 }
1311 else
1312 {
1313 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Fail!\n",__func__, __LINE__));
1314 // Return Fail, Command abort
1315 return FALSE ;
1316 }
1317 }
1318 //DMA_FAIL:
1319
1320 }
1321
HAL_CIPHER_OTPHash_Start(HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_U16 u16CmdID)1322 MS_BOOL HAL_CIPHER_OTPHash_Start(HAL_CIPHER_INTMODE IntMode, MS_BOOL bWaitCmdQ, MS_U16 u16CmdID)
1323 {
1324 MS_U32 u32SpareCnt = 0 , CmdLen = 0 ;
1325
1326 _uDmaCtrl0.DmaCtrl0.OVT = FALSE ;
1327
1328 //Set Thread Id
1329 _uDmaCtrl1.DmaCtrl1.TID = u16CmdID ;
1330
1331 _uDmaCtrl1.DmaCtrl1.IntM = IntMode ;
1332
1333 _uDmaCtrl1.DmaCtrl1.NL = CMD_NEW_LINE;
1334
1335 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_OTPHASH);
1336
1337 _uDmaCtrl0.DmaCtrl0.CL = CmdLen & CMD_LEN_MASK ;
1338 _uDmaCtrl0.DmaCtrl0.CMD = CMD_DMA_ENCRYPT;
1339
1340 _uDmaCtrl2.DmaCtrl2.NS = 0;
1341
1342 MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1343 REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf); //enable MIU crossbar
1344
1345 DMA_RETRY:
1346 // [HW] Hardware will check Current spare count first, and others read spare count will be zero!
1347 u32SpareCnt = REG32_R(&_AESDMACtrl->SpareCnt) ;
1348
1349 if (u32SpareCnt > CmdLen)
1350 {
1351 u32SpareCnt -= CmdLen ;
1352
1353 WRITE_CMDQ( (_uDmaCtrl0.u32DmaCtrl0)) ;
1354 WRITE_CMDQ( (_uDmaCtrl1.u32DmaCtrl1)) ;
1355 WRITE_CMDQ( (_uDmaCtrl2.u32DmaCtrl2)) ;
1356 WRITE_CMDQ( (_uDmaCtrl3.u32DmaCtrl3)) ;
1357
1358 WRITE_CMDQ((MS_U32)_u32DmaInAddr) ;
1359 WRITE_CMDQ(_u32DmaInNum) ;
1360 WRITE_CMDQ((MS_U32)_u32DmaOut_StartAddr);
1361 WRITE_CMDQ((MS_U32)_u32DmaOut_EndAddr);
1362
1363 if(_uDmaCtrl3.DmaCtrl3.AP == TRUE && _uDmaCtrl3.DmaCtrl3.IK == FALSE)
1364 {
1365 WRITE_CMDQ(_u32OTPHashLengthPadding);
1366 }
1367
1368 if (_uDmaCtrl1.DmaCtrl1.RR == TRUE )
1369 {
1370 WRITE_CMDQ((MS_U32)_u32ReportAddr);
1371 }
1372
1373 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
1374 REG32_W(&_AESDMACtrl->SpareCnt,u32SpareCnt);
1375 return TRUE ;
1376 }
1377 else
1378 {
1379 // [HW] Check Current spare count == Write back Spare count to start wait cmd
1380 REG32_W(&_AESDMACtrl->SpareCnt, u32SpareCnt) ;
1381 if (bWaitCmdQ)
1382 {
1383 // Retry until CMDQ avaliable
1384 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA retry!\n",__func__, __LINE__));
1385 goto DMA_RETRY;
1386 }
1387 else
1388 {
1389 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Fail!\n",__func__, __LINE__));
1390 // Return Fail, Command abort
1391 return FALSE ;
1392 }
1393 }
1394
1395 }
1396
HAL_CIPHER_DMA_CmdDone(MS_U32 u32CmdID,MS_U32 * u32Ret)1397 MS_BOOL HAL_CIPHER_DMA_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret)
1398 {
1399 MS_U32 u32ExcTmp = 0;
1400 MS_U32 u32Rpt = REG32_R(&_AESDMACtrl->Dma_Reportp[0]) ;
1401 MS_U32 u32RptId = u32Rpt & REG_CIPHER_RPT_THREAD_MSK;
1402
1403 if(u32RptId == u32CmdID)
1404 {
1405 u32ExcTmp = (MS_U32) REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
1406 *u32Ret = u32ExcTmp;
1407 }
1408 else
1409 {
1410 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Cmd[%u] Not done!ReportId[%u]\n",
1411 __func__, __LINE__, u32CmdID, u32RptId));
1412 return FALSE;
1413 }
1414
1415 return TRUE;
1416
1417 }
1418
HAL_CIPHER_GetException(MS_U32 * pu32ExcFlag)1419 void HAL_CIPHER_GetException(MS_U32 *pu32ExcFlag)
1420 {
1421 MS_U32 u32ExcTmp = (MS_U32) REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
1422 *pu32ExcFlag = u32ExcTmp;
1423 }
1424
HAL_CIPHER_ReadException(MS_U32 u32ExcTmp)1425 MS_U32 HAL_CIPHER_ReadException(MS_U32 u32ExcTmp)
1426 {
1427 MS_U32 i = 0;
1428 MS_U32 u32ExcOut = 0;
1429
1430 for(i = 0;i<CRYPTODMA_DEBUG_SIZE;i++) //check each error flag
1431 {
1432 if((u32ExcTmp & (1 << i)) >> i)
1433 {
1434 switch(i)
1435 {
1436 case E_CIPHER_NDS_Region_fail:
1437 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_NDS_Region_fail\n", __func__, __LINE__));
1438 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1439 break;
1440 case E_CIPHER_NDS_keyoff:
1441 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_NDS_keyoff\n", __func__, __LINE__));
1442 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1443 break;
1444 case E_CIPHER_sha_write_scr:
1445 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_write_scr\n", __func__, __LINE__));
1446 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1447 break;
1448 case E_CIPHER_sha_read_scr:
1449 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_read_scr\n", __func__, __LINE__));
1450 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1451 break;
1452 case E_CIPHER_sha_error_flag:
1453 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_error_flag\n", __func__, __LINE__));
1454 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1455 break;
1456 case E_CIPHER_except_read_scr:
1457 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_read_scr\n", __func__, __LINE__));
1458 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1459 break;
1460 case E_CIPHER_except_key:
1461 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key\n", __func__, __LINE__));
1462 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1463 break;
1464 case E_CIPHER_except_CAVid:
1465 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_CAVid\n", __func__, __LINE__));
1466 u32ExcOut |= HAL_CIPHER_EXCEPT_CAVID;
1467 break;
1468 case E_CIPHER_except_des:
1469 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_des\n", __func__, __LINE__));
1470 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1471 break;
1472 case E_CIPHER_except_NDS:
1473 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_NDS\n", __func__, __LINE__));
1474 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1475 break;
1476 case E_CIPHER_except_chain:
1477 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_chain\n", __func__, __LINE__));
1478 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1479 break;
1480 case E_CIPHER_except_algo:
1481 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_algo\n", __func__, __LINE__));
1482 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1483 break;
1484 case E_CIPHER_except_key_HID:
1485 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key_HID\n", __func__, __LINE__));
1486 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1487 break;
1488 case E_CIPHER_except_key_cbc_mac:
1489 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key_cbc_mac\n", __func__, __LINE__));
1490 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1491 break;
1492 case E_CIPHER_except_file_dqmem:
1493 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_file_dqmem\n", __func__, __LINE__));
1494 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1495 break;
1496 case E_CIPHER_except_hash_dqmem:
1497 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_hash_dqmem\n", __func__, __LINE__));
1498 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1499 break;
1500 case E_CIPHER_disable_masterkey0:
1501 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_masterkey0\n", __func__, __LINE__));
1502 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1503 break;
1504 case E_CIPHER_disable_masterkey1:
1505 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_masterkey1\n", __func__, __LINE__));
1506 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1507 break;
1508 case E_CIPHER_disable_cck:
1509 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_cck\n", __func__, __LINE__));
1510 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1511 break;
1512 case E_CIPHER_disable_reg_key_0:
1513 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_0\n", __func__, __LINE__));
1514 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1515 break;
1516 case E_CIPHER_disable_reg_key_1:
1517 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_1\n", __func__, __LINE__));
1518 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1519 break;
1520 case E_CIPHER_disable_reg_key_2:
1521 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_2\n", __func__, __LINE__));
1522 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1523 break;
1524 case E_CIPHER_disable_reg_key_3:
1525 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_3\n", __func__, __LINE__));
1526 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1527 break;
1528 case E_CIPHER_dma_forbid_qmem2dram:
1529 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_dma_forbid_qmem2dram\n", __func__, __LINE__));
1530 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1531 break;
1532 case E_CIPHER_dma_forbid_cryptodma_keyslot_qmem:
1533 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_dma_forbid_cryptodma_keyslot_qmem\n", __func__, __LINE__));
1534 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1535 break;
1536 case E_CIPHER_sha_forbid_qmem2dram:
1537 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_forbid_qmem2dram\n", __func__, __LINE__));
1538 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1539 break;
1540 case E_CIPHER_sha_forbid_cryptodma_keyslot_qmem:
1541 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_forbid_cryptodma_keyslot_qmem\n", __func__, __LINE__));
1542 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1543 break;
1544 case E_CIPHER_tdes_key_error:
1545 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_tdes_key_error\n", __func__, __LINE__));
1546 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1547 break;
1548 case E_CIPHER_write_address_error:
1549 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_write_address_error\n", __func__, __LINE__));
1550 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1551 break;
1552 case E_CIPHER_except_str:
1553 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_str\n", __func__, __LINE__));
1554 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1555 break;
1556 case E_CIPHER_except_sha_str:
1557 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_sha_str\n", __func__, __LINE__));
1558 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1559 break;
1560 default:
1561 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] Unknown error \n", __func__, __LINE__));
1562 break;
1563
1564 }
1565
1566 }
1567
1568 }
1569
1570 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Exception out [0x%08x]\n", __func__, __LINE__, (unsigned int)u32ExcOut));
1571
1572 return u32ExcOut;
1573
1574 }
1575
HAL_CIPHER_IntEnable(void)1576 void HAL_CIPHER_IntEnable(void)
1577 {
1578 MS_U16 u16MaskTmp = REG16_R(_u32RegBase + REG_HST0_FIQ_MASK_63_48);
1579 u16MaskTmp &= REG_HTS0_FIQ_MASK_CRYPTODMA; //FIQ 56 in reg_hst0_fiq_mask_63_48_
1580 REG16_W(_u32RegBase + REG_HST0_FIQ_MASK_63_48, u16MaskTmp);
1581 }
1582
HAL_CIPHER_IntClear(void)1583 void HAL_CIPHER_IntClear(void)
1584 {
1585 REG16_W(_u32RegBase + REG_HST0_FIQ_STATUS_63_48, REG_HTS0_FIQ_CRYPTODMA); //set 1 to clear interrupt
1586 }
1587
1588 //======================================================================
1589
HAL_CIPHER_Hash_GetRpt(MS_U32 * HashRpt,MS_U32 u32Size)1590 void HAL_CIPHER_Hash_GetRpt(MS_U32 *HashRpt, MS_U32 u32Size)
1591 {
1592 MS_U32 i , tmp;
1593
1594 if (u32Size < HASH_RPT_REG_SIZE )
1595 {
1596 tmp = u32Size ;
1597 }
1598 else
1599 {
1600 tmp = HASH_RPT_REG_SIZE ;
1601 }
1602
1603 for (i = 0 ; i < tmp ; i++)
1604 {
1605 HashRpt[i] = REG32_R(&_AESDMACtrl->Hash_Reportp[i]);
1606 }
1607 }
1608
HAL_CIPHER_Hash_Set_Config(CIPHER_HASH_ALGO algo,MS_BOOL bAutoPad,MS_BOOL bInv16)1609 void HAL_CIPHER_Hash_Set_Config(CIPHER_HASH_ALGO algo , MS_BOOL bAutoPad , MS_BOOL bInv16)
1610 {
1611 HAL_CIPHER_HASHMODE hash_mode = E_HASH_SHA1;
1612 hash_mode = _HAL_CIPHER_TransHASHAlgo(algo);
1613
1614 _uHashCtrl0.HashCtrl0.HashSel = hash_mode ;
1615 _uHashCtrl0.HashCtrl0.AutoPad = bAutoPad ;
1616 _uHashCtrl0.HashCtrl0.Inv16 = bInv16; //Inverse the byte order per 16 bytes
1617
1618 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH Mode[%d], AutoPad[%d], Inverse16[%d]!\n",
1619 __func__, __LINE__, hash_mode, bAutoPad, bInv16));
1620 }
1621
HAL_CIPHER_Hash_Set_ReportMode(MS_BOOL RptInDram,MS_U32 u32DramAddr)1622 void HAL_CIPHER_Hash_Set_ReportMode(MS_BOOL RptInDram, MS_U32 u32DramAddr)
1623 {
1624 if (RptInDram)
1625 {
1626 _u32ReportAddr = u32DramAddr;
1627
1628 }
1629 else
1630 {
1631 _u32ReportAddr = 0;
1632 }
1633
1634 _uHashCtrl2.HashCtrl2.RR = RptInDram ;
1635
1636 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set report mode[%d], report address[0x%08x]\n",
1637 __func__, __LINE__, RptInDram, (unsigned int)_u32ReportAddr));
1638 }
1639
HAL_CIPHER_Hash_SetHMACKey(DRV_CIPHER_HMAC_KEY stHMACKey,CIPHER_HMAC_KPAD eKpad,MS_BOOL bClear)1640 MS_BOOL HAL_CIPHER_Hash_SetHMACKey(DRV_CIPHER_HMAC_KEY stHMACKey, CIPHER_HMAC_KPAD eKpad, MS_BOOL bClear)
1641 {
1642 MS_BOOL bHMAC = TRUE;
1643 MS_U32 u32HMACKeySel = 0;
1644 MS_U32 u32Kpad = CMD_HASH_IKP;
1645 HAL_CIPHER_KEYSRC KeySrc;
1646
1647 //Check Key Source, Index
1648 if(((E_CIPHER_KSRC_KL == stHMACKey.eKeySrc) && (stHMACKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
1649 ((E_CIPHER_KSRC_OTP == stHMACKey.eKeySrc) && (stHMACKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
1650 {
1651 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
1652 __func__, __LINE__, stHMACKey.eKeySrc, stHMACKey.u8KeyIdx));
1653 return FALSE;
1654 }
1655
1656 //DRV to HAL Type transfer
1657 KeySrc = _HAL_CIPHER_TransKey(stHMACKey.eKeySrc, stHMACKey.u8KeyIdx);
1658
1659 switch(KeySrc)
1660 {
1661 case E_DMA_KSEL_REGKEY:
1662 u32HMACKeySel = CMD_HMAC_KSEL_HK;
1663 break;
1664 case E_DMA_KSEL_STRN:
1665 u32HMACKeySel = CMD_HMAC_KSEL_STRN;
1666 break;
1667 case E_DMA_KSEL_MK0:
1668 u32HMACKeySel = CMD_HMAC_KSEL_MK0;
1669 break;
1670 case E_DMA_KSEL_MK1:
1671 u32HMACKeySel = CMD_HMAC_KSEL_MK1;
1672 break;
1673 case E_DMA_KSEL_CCCK:
1674 u32HMACKeySel = CMD_HMAC_KSEL_CCCK;
1675 break;
1676 case E_DMA_KSEL_SK0:
1677 u32HMACKeySel = CMD_HMAC_KSEL_SK0;
1678 break;
1679 case E_DMA_KSEL_SK1:
1680 u32HMACKeySel = CMD_HMAC_KSEL_SK1;
1681 break;
1682 case E_DMA_KSEL_SK2:
1683 u32HMACKeySel = CMD_HMAC_KSEL_SK2;
1684 break;
1685 case E_DMA_KSEL_SK3:
1686 u32HMACKeySel = CMD_HMAC_KSEL_SK3;
1687 break;
1688 default:
1689 u32HMACKeySel = 0;
1690 break;
1691 }
1692
1693 if(eKpad == E_CIPHER_HMAC_OKPAD)
1694 {
1695 u32Kpad = CMD_HASH_OKP;
1696 }
1697
1698 if(bClear)
1699 {
1700 u32HMACKeySel += (MS_U32)CMD_HMAC_KSEL_CLR_SK;
1701 }
1702
1703 if(KeySrc == E_DMA_KSEL_REGKEY)
1704 {
1705 //command mode
1706 if (0 != stHMACKey.pu8KeyData)
1707 {
1708 memset(_pu8HashHMACHostKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
1709 memcpy(_pu8HashHMACHostKey, (MS_U8 *)stHMACKey.pu8KeyData , stHMACKey.u8KeyLen);
1710 _uHashCtrl0.HashCtrl0.DK = CMD_HMAC_KSEL_DIR_HK;
1711 }
1712 else
1713 {
1714 memset(_pu8HashHMACHostKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
1715 bHMAC = FALSE;
1716 }
1717 }
1718
1719 _uHashCtrl0.HashCtrl0.HMAC = bHMAC;
1720 _uHashCtrl0.HashCtrl0.KPAD = u32Kpad;
1721 _uHashCtrl0.HashCtrl0.HMAC_KeySel = u32HMACKeySel;
1722
1723 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HMAC[%d], HMAC KPAD[%u] HMAC KeySel[%u]!\n",
1724 __func__, __LINE__, bHMAC, u32Kpad, u32HMACKeySel));
1725
1726 return TRUE;
1727 }
1728
HAL_CIPHER_Hash_Set_CaVid(MS_U32 u32CAVid)1729 MS_BOOL HAL_CIPHER_Hash_Set_CaVid(MS_U32 u32CAVid)
1730 {
1731 MS_U32 u32Tmp = u32CAVid;
1732
1733 if(u32Tmp > HAL_CRYPTODMA_CAVID_MAX)
1734 {
1735 return FALSE;
1736 }
1737
1738 if(u32Tmp == 0)
1739 {
1740 u32Tmp = _CIPHER_CAVid ;
1741 }
1742 else
1743 {
1744 u32Tmp = u32CAVid;
1745 }
1746
1747 _uHashCtrl1.HashCtrl1.CaVid = u32Tmp;
1748
1749 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set CAVid [0x%x]\n",
1750 __func__, __LINE__, (unsigned int)u32Tmp));
1751
1752 return TRUE;
1753 }
1754
HAL_CIPHER_Hash_Set_IV(MS_U8 * pu8IV,MS_U32 u32IVSize,MS_U32 u32IVSel)1755 MS_BOOL HAL_CIPHER_Hash_Set_IV(MS_U8* pu8IV, MS_U32 u32IVSize ,MS_U32 u32IVSel)
1756 {
1757 // 256 bits for sha256 , 160 bits for sha1
1758 _uHashCtrl0.HashCtrl0.InitHashSel = u32IVSel ;
1759
1760 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH IVSel [%u]\n",
1761 __func__, __LINE__, u32IVSel));
1762
1763 if(u32IVSel == CMD_HASH_IV_CMD)
1764 {
1765 if((pu8IV != NULL) && (u32IVSize > 0))
1766 {
1767 memset(_pu8HashIV, 0x0, HASH_CMD_IV_SIZE);
1768 memcpy(_pu8HashIV, (MS_U8 *)pu8IV , u32IVSize);
1769
1770 return TRUE;
1771 }
1772 else
1773 {
1774 return FALSE;
1775 }
1776 }
1777
1778 return TRUE;
1779 }
1780
1781
HAL_CIPHER_Hash_Set_InitWordCnt(HAL_CIPHER_IWCTYPE eIWCType,MS_U32 u32StartBytes)1782 MS_BOOL HAL_CIPHER_Hash_Set_InitWordCnt(HAL_CIPHER_IWCTYPE eIWCType, MS_U32 u32StartBytes)
1783 {
1784 MS_U32 u32IWCType = 0;
1785 MS_U32 u32IWC = 0;
1786 MS_U32 Rpt[2] = {0};
1787
1788 if(eIWCType == E_CIPHER_HASH_IWC_PRV) //Init Word Count from report
1789 {
1790 u32IWCType = CMD_HASH_IWC_RPT;
1791 HAL_CIPHER_Hash_GetRpt(Rpt, 2); //For debug
1792 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IWC from report is [%u]\n",
1793 __func__, __LINE__, Rpt[1]>>2));
1794 }
1795 else
1796 {
1797 u32IWCType = CMD_HASH_IWC_CMDQ;
1798 if((u32StartBytes % HASH_MANUAL_BLOCK_SIZE) != 0)
1799 {
1800 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Init word count is 64 bytes alignment!\n",
1801 __func__, __LINE__));
1802 return FALSE;
1803 }
1804
1805 if(u32StartBytes != 0)
1806 {
1807 u32IWC = u32StartBytes/4; //Init Word Count
1808 }
1809 else
1810 {
1811 u32IWC = 0;
1812 }
1813 }
1814
1815 _u32InitWordCnt = u32IWC;
1816 _uHashCtrl0.HashCtrl0.IWC_Sel = u32IWCType;
1817
1818 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IWC type[%u], IWC[%u]\n",
1819 __func__, __LINE__, u32IWCType, _u32InitWordCnt));
1820
1821 return TRUE;
1822 }
1823
HAL_CIPHER_Hash_Set_MsgSrcFrom(CIPHER_MEM_TYPE eMemType,MS_U32 * u32HashSrc)1824 MS_BOOL HAL_CIPHER_Hash_Set_MsgSrcFrom(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashSrc)
1825 {
1826 MS_U32 u32SrcTmp = 0;
1827 switch(eMemType)
1828 {
1829 case E_CIPHER_DRAM:
1830 u32SrcTmp = CMD_HASH_SRC_DRAM;
1831 _u32HashSrcAddr = 0;
1832 break;
1833 case E_CIPHER_DQMEM:
1834 u32SrcTmp = CMD_HASH_SRC_R2;
1835 _u32HashSrcAddr = HAL_CIPHER_BASE_DQMEM;
1836 break;
1837 case E_CIPHER_IQMEM:
1838 u32SrcTmp = CMD_HASH_SRC_R2;
1839 _u32HashSrcAddr = HAL_CIPHER_BASE_IQMEM;
1840 break;
1841 case E_CIPHER_DIRECT:
1842 u32SrcTmp = CMD_HASH_SRC_REG;
1843 _u32HashSrcAddr = 0;
1844 break;
1845 default:
1846 u32SrcTmp = CMD_HASH_SRC_DRAM;
1847 _u32HashSrcAddr = 0;
1848 break;
1849 }
1850
1851 *u32HashSrc = u32SrcTmp;
1852
1853 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH source from [%u]\n",
1854 __func__, __LINE__, u32SrcTmp));
1855
1856 return TRUE;
1857 }
1858
HAL_CIPHER_Hash_Set_OutputDstTo(CIPHER_MEM_TYPE eMemType,MS_U32 * u32HashDst)1859 MS_BOOL HAL_CIPHER_Hash_Set_OutputDstTo(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashDst)
1860 {
1861 MS_U32 u32DstTmp = 0;
1862 switch(eMemType)
1863 {
1864 case E_CIPHER_DRAM:
1865 u32DstTmp = CMD_HASH_OUTPUT_DRAM;
1866 _u32HashDestAddr = 0;
1867 break;
1868 case E_CIPHER_DQMEM:
1869 u32DstTmp = CMD_HASH_OUTPUT_R2;
1870 _u32HashDestAddr = HAL_CIPHER_BASE_DQMEM;
1871 break;
1872 case E_CIPHER_IQMEM:
1873 u32DstTmp = CMD_HASH_OUTPUT_R2;
1874 _u32HashDestAddr = HAL_CIPHER_BASE_IQMEM;
1875 break;
1876 case E_CIPHER_DIRECT:
1877 u32DstTmp = CMD_HASH_OUTPUT_RPT;
1878 _u32HashDestAddr = 0;
1879 break;
1880 default:
1881 u32DstTmp = CMD_HASH_OUTPUT_RPT;
1882 _u32HashDestAddr = 0;
1883 break;
1884 }
1885
1886 *u32HashDst = u32DstTmp;
1887 _uHashCtrl0.HashCtrl0.Dest = u32DstTmp;
1888 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH destination[%u]\n",
1889 __func__, __LINE__, u32DstTmp));
1890
1891 return TRUE;
1892 }
1893
HAL_CIPHER_Hash_Set_OuputAddr(MS_PHY u32OutputPAddr,MS_U32 u32DstSel)1894 MS_BOOL HAL_CIPHER_Hash_Set_OuputAddr(MS_PHY u32OutputPAddr, MS_U32 u32DstSel)
1895 {
1896 if ((CMD_HASH_OUTPUT_DRAM == u32DstSel) || (CMD_HASH_OUTPUT_R2 == u32DstSel))
1897 {
1898 if (0 != u32OutputPAddr)
1899 {
1900 _u32HashDestAddr += u32OutputPAddr;
1901 }
1902 else
1903 {
1904 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Hash output address is NULL\n",__func__, __LINE__));
1905 return FALSE;
1906 }
1907 }
1908 return TRUE;
1909 }
1910
HAL_CIPHER_Hash_SetMsgLength(MS_U32 u32Size)1911 void HAL_CIPHER_Hash_SetMsgLength( MS_U32 u32Size )
1912 {
1913 _u32HashMsgLen = u32Size;
1914
1915 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH message length[%u]\n",
1916 __func__, __LINE__, u32Size));
1917
1918 return ;
1919 }
1920
HAL_CIPHER_Hash_SetHOS(MS_BOOL bHos)1921 void HAL_CIPHER_Hash_SetHOS(MS_BOOL bHos)
1922 {
1923 _uHashCtrl0.HashCtrl0.HOS = bHos;
1924
1925 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HOS[%d]\n",
1926 __func__, __LINE__, bHos));
1927
1928 return ;
1929 }
1930
1931
HAL_CIPHER_Hash_SetMsg(MS_PHY u32MsgPAddr,MS_U32 u32Size,MS_U32 u32SrcSel)1932 MS_BOOL HAL_CIPHER_Hash_SetMsg(MS_PHY u32MsgPAddr, MS_U32 u32Size ,MS_U32 u32SrcSel )
1933 {
1934 _uHashCtrl0.HashCtrl0.Src = u32SrcSel;
1935 _u32HashMsgLen = u32Size;
1936
1937 if ((CMD_HASH_SRC_DRAM == u32SrcSel) || (CMD_HASH_SRC_R2 == u32SrcSel))
1938 {
1939 if (0 != u32MsgPAddr)
1940 {
1941 _u32HashSrcAddr += u32MsgPAddr;
1942 }
1943 else
1944 {
1945 return FALSE;
1946 }
1947 }
1948 else if (CMD_HASH_SRC_REG == u32SrcSel)
1949 {
1950 if((u32MsgPAddr == 0) || (u32Size > HASH_CMD_MSG_SIZE))
1951 {
1952 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Set HASH direct message size[%u] over 64 bytes\n",
1953 __func__, __LINE__, u32Size));
1954 return FALSE;
1955 }
1956 _u32HashSrcAddr = 0;
1957 memset(_pu8HashMsg , 0x0 , HASH_CMD_MSG_SIZE);
1958 memcpy(_pu8HashMsg , (MS_U8 *)(MsOS_PA2KSEG1(u32MsgPAddr)) , u32Size);
1959 }
1960
1961 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH message source[%u], size[%u]\n",
1962 __func__, __LINE__, u32SrcSel, _u32HashMsgLen));
1963
1964 return TRUE;
1965
1966 }
1967
1968
HAL_CIPHER_Hash_Start(HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_BOOL bRst,MS_U16 u16CmdID)1969 MS_BOOL HAL_CIPHER_Hash_Start(HAL_CIPHER_INTMODE IntMode , MS_BOOL bWaitCmdQ , MS_BOOL bRst, MS_U16 u16CmdID)
1970 {
1971 MS_U32 u32SpareCnt = 0 , CmdLen = 0 , i = 0 ;
1972 MS_U32 u32Tmp;
1973
1974 _uHashCtrl1.HashCtrl1.TID = u16CmdID;
1975 _uHashCtrl0.HashCtrl0.CMD = CMD_HASH_START_RR ;
1976
1977 _uHashCtrl0.HashCtrl0.OVT = FALSE ;
1978 _uHashCtrl0.HashCtrl0.IntM = IntMode ;
1979
1980 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_SHA);
1981
1982 _uHashCtrl0.HashCtrl0.CL = CmdLen & CMD_LEN_MASK ;
1983
1984 _uHashCtrl1.HashCtrl1.NS = 0;
1985
1986 MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1987 REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf); //enable MIU crossbar
1988
1989
1990 SHA_RETRY:
1991 u32SpareCnt = REG32_R(&_AESDMACtrl->SpareCnt) ;
1992
1993 if (u32SpareCnt > CmdLen)
1994 {
1995 u32SpareCnt -= CmdLen ;
1996
1997 WRITE_CMDQ( (_uHashCtrl0.u32HashCtrl0)) ;
1998
1999 WRITE_CMDQ( (_uHashCtrl1.u32HashCtrl1)) ;
2000
2001 WRITE_CMDQ( (_uHashCtrl2.u32HashCtrl2)) ;
2002
2003 WRITE_CMDQ(_u32HashMsgLen) ;
2004
2005 //SRC
2006 if (_uHashCtrl0.HashCtrl0.Src != CMD_HASH_SRC_REG)
2007 {
2008 WRITE_CMDQ(_u32HashSrcAddr) ;
2009 }
2010
2011 //RR address
2012 if (_uHashCtrl2.HashCtrl2.RR == TRUE)
2013 {
2014 WRITE_CMDQ(_u32ReportAddr) ;
2015 }
2016
2017 // IWC
2018 if (CMD_HASH_IWC_CMDQ == _uHashCtrl0.HashCtrl0.IWC_Sel)
2019 {
2020 WRITE_CMDQ(_u32InitWordCnt);
2021 }
2022 else
2023 {
2024 REG32_W(&_AESDMACtrl->Hash_Reportp[1], _u32InitWordCnt);
2025 }
2026
2027 // DST
2028 if ((CMD_HASH_OUTPUT_DRAM == _uHashCtrl0.HashCtrl0.Dest) || (_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_R2 ))
2029 {
2030 WRITE_CMDQ(_u32HashDestAddr);
2031 }
2032
2033 // HASH Initial Vector from CmdQ
2034 if (CMD_HASH_IV_CMD == _uHashCtrl0.HashCtrl0.InitHashSel )
2035 {
2036 for ( i = 0 ; i < (HASH_CMD_IV_SIZE/4) ; i ++ )
2037 {
2038 u32Tmp = ((_pu8HashIV[4*i+0]<<24)|(_pu8HashIV[4*i+1]<<16)|(_pu8HashIV[4*i+2]<<8)|(_pu8HashIV[4*i+3]) );
2039
2040 WRITE_CMDQ(u32Tmp);
2041 }
2042 }
2043
2044 // HASH Data from CmdQ
2045 if ( CMD_HASH_SRC_REG == _uHashCtrl0.HashCtrl0.Src )
2046 {
2047 for ( i = 0 ; i < (HASH_CMD_MSG_SIZE/4) ; i ++ )
2048 {
2049 u32Tmp = ( (_pu8HashMsg[i*4+0]<<24)
2050 |(_pu8HashMsg[i*4+1]<<16)
2051 |(_pu8HashMsg[i*4+2]<<8)
2052 |(_pu8HashMsg[i*4+3]<<0)
2053 );
2054
2055 WRITE_CMDQ(u32Tmp);
2056 }
2057 }
2058
2059 if((CMD_HMAC_KSEL_HK == _uHashCtrl0.HashCtrl0.HMAC_KeySel) && (CMD_HMAC_KSEL_DIR_HK == _uHashCtrl0.HashCtrl0.DK))
2060 {
2061 for ( i = 0 ; i < (HASH_CMD_HMAC_HOSTKEY_SIZE/4) ; i ++ )
2062 {
2063 u32Tmp = ((_pu8HashHMACHostKey[4*i+0]<<24)|(_pu8HashHMACHostKey[4*i+1]<<16)|(_pu8HashHMACHostKey[4*i+2]<<8)|(_pu8HashHMACHostKey[4*i+3]) );
2064
2065 WRITE_CMDQ(u32Tmp);
2066 }
2067 }
2068 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
2069 REG32_W(&_AESDMACtrl->SpareCnt, u32SpareCnt) ;
2070 return TRUE ;
2071
2072 }
2073 else
2074 {
2075 // [HW] Check Current spare count == Write back Spare count to start wait cmd
2076 REG32_W(&_AESDMACtrl->SpareCnt, u32SpareCnt) ;
2077
2078 if (bWaitCmdQ)
2079 {
2080 // Retry until CMDQ avaliable
2081 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]HASH cmd retry!\n",
2082 __func__, __LINE__));
2083 goto SHA_RETRY;
2084 }
2085 else
2086 {
2087 // Return Fail, Command abort
2088 return FALSE ;
2089 }
2090 }
2091 }
2092
HAL_CIPHER_Hash_CmdDone(MS_U32 u32CmdID,MS_U32 * u32Ret)2093 MS_BOOL HAL_CIPHER_Hash_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret)
2094 {
2095 MS_U32 u32ExcTmp = 0;
2096
2097 MS_U32 u32Tmp = REG32_R(&_AESDMACtrl->Hash_Reportp[0]) ;
2098 MS_U32 u32RptId = u32Tmp & REG_CIPHER_RPT_THREAD_MSK;
2099
2100 if(u32RptId == u32CmdID)
2101 {
2102 u32ExcTmp = (MS_U32)REG32_R(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
2103 *u32Ret = u32ExcTmp;
2104 }
2105 else
2106 {
2107 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]HASH Cmd[%u] Not done!ReportId[%u]\n",
2108 __func__, __LINE__, u32CmdID, u32RptId));
2109 return FALSE;
2110 }
2111
2112 return TRUE;
2113 }
2114
HAL_CIPHER_Hash_ExceptFilter(MS_U32 * pu32Exception,CIPHER_KEY_SRC eKeySrc,MS_U8 u8KeyIdx)2115 void HAL_CIPHER_Hash_ExceptFilter(MS_U32 *pu32Exception, CIPHER_KEY_SRC eKeySrc, MS_U8 u8KeyIdx)
2116 {
2117 //Because CryptoDMA will check every key slot usage for HMAC
2118 //We need to filter out the correct key exception
2119 MS_U32 u32ExcTmp = 0;
2120 HAL_CIPHER_KEYSRC KeySrc = 0;
2121 MS_U32 i = 0;
2122
2123 u32ExcTmp = *pu32Exception;
2124
2125 //DRV to HAL Type transfer
2126 KeySrc = _HAL_CIPHER_TransKey(eKeySrc, u8KeyIdx);
2127
2128 //Only check HMAC key exception
2129 for(i = E_CIPHER_disable_masterkey0;i<=E_CIPHER_disable_reg_key_3;i++) //check each error flag
2130 {
2131 if((u32ExcTmp & (1 << i)) >> i)
2132 {
2133 switch(i)
2134 {
2135 case E_CIPHER_disable_masterkey0:
2136 if(E_DMA_KSEL_MK0 != KeySrc)
2137 u32ExcTmp &= (~(1 << E_CIPHER_disable_masterkey0));
2138 break;
2139
2140 case E_CIPHER_disable_masterkey1:
2141 if(E_DMA_KSEL_MK1 != KeySrc)
2142 u32ExcTmp &= (~(1 << E_CIPHER_disable_masterkey1));
2143 break;
2144
2145 case E_CIPHER_disable_cck:
2146 if(E_DMA_KSEL_CCCK != KeySrc)
2147 u32ExcTmp &= (~(1 << E_CIPHER_disable_cck));
2148 break;
2149
2150 case E_CIPHER_disable_reg_key_0:
2151 if(E_DMA_KSEL_SK0 != KeySrc)
2152 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_0));
2153 break;
2154
2155 case E_CIPHER_disable_reg_key_1:
2156 if(E_DMA_KSEL_SK1 != KeySrc)
2157 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_1));
2158 break;
2159
2160 case E_CIPHER_disable_reg_key_2:
2161 if(E_DMA_KSEL_SK2 != KeySrc)
2162 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_2));
2163 break;
2164
2165 case E_CIPHER_disable_reg_key_3:
2166 if(E_DMA_KSEL_SK3 != KeySrc)
2167 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_3));
2168 break;
2169
2170 default:
2171 break;
2172 }
2173 }
2174 }
2175
2176 *pu32Exception = u32ExcTmp;
2177
2178 return;
2179
2180 }
2181 // =====================================
2182 // Parser function implementation
2183 // =====================================
HAL_CIPHER_PARSER_Set_Mode(CIPHER_PARSER_MODE eMode)2184 void HAL_CIPHER_PARSER_Set_Mode(CIPHER_PARSER_MODE eMode)
2185
2186 {
2187 HAL_CIPHER_PARSER_HDCPMODE eHDCPMode = 0;
2188 HAL_CIPHER_PARSER_TSMODE eTSMode = 0;
2189 HAL_CIPHER_PARSER_PKTMODE ePKTMode = 0;
2190 HAL_CIPHER_PARSER_AUTOMODE eAutoMode = 0;
2191 HAL_CIPHER_PARSER_ITMODE eITMode = 0;
2192 HAL_CIPHER_PARSER_CLEARMODE eClearMode = 0;
2193
2194 switch(eMode)
2195 {
2196 case E_CIPHER_PARSER_TS_PKT192:
2197 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2198 eTSMode = E_PARSER_TSMODE_TS;
2199 ePKTMode = E_PARSER_PKTMODE_192;
2200 eAutoMode = E_PARSER_AUTOMODE_EN;
2201 eITMode = E_PARSER_ITMODE_EN;
2202 eClearMode = E_PARSER_CLEARMODE_NONE;
2203 break;
2204 case E_CIPHER_PARSER_TS_PKT192_CLEAR:
2205 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2206 eTSMode = E_PARSER_TSMODE_TS;
2207 ePKTMode = E_PARSER_PKTMODE_192;
2208 eAutoMode = E_PARSER_AUTOMODE_EN;
2209 eITMode = E_PARSER_ITMODE_EN;
2210 eClearMode = E_PARSER_CLEARMODE_EN;
2211 break;
2212 case E_CIPHER_PARSER_TS_PKT188:
2213 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2214 eTSMode = E_PARSER_TSMODE_TS;
2215 ePKTMode = E_PARSER_PKTMODE_188;
2216 eAutoMode = E_PARSER_AUTOMODE_EN;
2217 eITMode = E_PARSER_ITMODE_EN;
2218 eClearMode = E_PARSER_CLEARMODE_NONE;
2219 break;
2220 case E_CIPHER_PARSER_TS_PKT188_CLEAR:
2221 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2222 eTSMode = E_PARSER_TSMODE_TS;
2223 ePKTMode = E_PARSER_PKTMODE_188;
2224 eAutoMode = E_PARSER_AUTOMODE_EN;
2225 eITMode = E_PARSER_ITMODE_EN;
2226 eClearMode = E_PARSER_CLEARMODE_EN;
2227 break;
2228 case E_CIPHER_PARSER_HDCP20_PKT192:
2229 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2230 eTSMode = E_PARSER_TSMODE_PES;
2231 ePKTMode = E_PARSER_PKTMODE_192;
2232 eAutoMode = E_PARSER_AUTOMODE_EN;
2233 eITMode = E_PARSER_ITMODE_EN;
2234 eClearMode = E_PARSER_CLEARMODE_NONE;
2235 break;
2236 case E_CIPHER_PARSER_HDCP20_PKT192_CLEAR:
2237 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2238 eTSMode = E_PARSER_TSMODE_PES;
2239 ePKTMode = E_PARSER_PKTMODE_192;
2240 eAutoMode = E_PARSER_AUTOMODE_EN;
2241 eITMode = E_PARSER_ITMODE_NONE;
2242 eClearMode = E_PARSER_CLEARMODE_EN;
2243 break;
2244 case E_CIPHER_PARSER_HDCP20_PKT188:
2245 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2246 eTSMode = E_PARSER_TSMODE_PES;
2247 ePKTMode = E_PARSER_PKTMODE_188;
2248 eAutoMode = E_PARSER_AUTOMODE_EN;
2249 eITMode = E_PARSER_ITMODE_EN;
2250 eClearMode = E_PARSER_CLEARMODE_NONE;
2251 break;
2252 case E_CIPHER_PARSER_HDCP20_PKT188_CLEAR:
2253 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2254 eTSMode = E_PARSER_TSMODE_PES;
2255 ePKTMode = E_PARSER_PKTMODE_188;
2256 eAutoMode = E_PARSER_AUTOMODE_EN;
2257 eITMode = E_PARSER_ITMODE_NONE;
2258 eClearMode = E_PARSER_CLEARMODE_EN;
2259 break;
2260 default:
2261 printf("Error: Not suport parser mode!\n");
2262 break;
2263 }
2264
2265 _uDmaCtrl2.DmaCtrl2.HP = TRUE;
2266 _uDmaCtrl2.DmaCtrl2.HDCP = eHDCPMode;
2267 _uDmaCtrl2.DmaCtrl2.TS = eTSMode;
2268 _uDmaCtrl2.DmaCtrl2.P192 = ePKTMode;
2269 _uDmaCtrl2.DmaCtrl2.AT = eAutoMode;
2270 _uDmaCtrl2.DmaCtrl2.IT = eITMode;
2271 _uDmaCtrl2.DmaCtrl2.CR = eClearMode;
2272
2273 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Parser config:HDCP[%d], TS[%d], P192[%d], AT[%d], IT[%d], ClearMode[%d]\n",
2274 __func__, __LINE__, eHDCPMode, eTSMode, ePKTMode, eAutoMode, eITMode, eClearMode));
2275
2276
2277 }
2278
HAL_CIPHER_PARSER_Set_MaskSCB(MS_BOOL bEnable)2279 void HAL_CIPHER_PARSER_Set_MaskSCB(MS_BOOL bEnable)
2280 {
2281 _uDmaCtrl2.DmaCtrl2.TsSbMk = bEnable;
2282 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Enable MaskSCB[%d]!\n",
2283 __func__, __LINE__, bEnable));
2284 }
2285
HAL_CIPHER_PARSER_Set_SCB(CIPHER_PARSER_SCB eSCB)2286 void HAL_CIPHER_PARSER_Set_SCB(CIPHER_PARSER_SCB eSCB)
2287 {
2288 MS_U8 u8SCB = 0;
2289
2290 if(eSCB == E_CIPHER_PARSER_SCB_10)
2291 {
2292 u8SCB = CMD_PARSER_SCB10;
2293 }
2294 else if(eSCB == E_CIPHER_PARSER_SCB_11)
2295 {
2296 u8SCB = CMD_PARSER_SCB11;
2297 }
2298 else
2299 {
2300 u8SCB = 0;
2301 }
2302 _uDmaCtrl2.DmaCtrl2.TsSbPn = u8SCB;
2303 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set SCB[%u]!\n",
2304 __func__, __LINE__, u8SCB));
2305 }
2306
HAL_CIPHER_PARSER_Set_ForceSCB(MS_BOOL bInsert,CIPHER_PARSER_SCB eSCB)2307 void HAL_CIPHER_PARSER_Set_ForceSCB(MS_BOOL bInsert, CIPHER_PARSER_SCB eSCB)
2308 {
2309 MS_U8 u8SCB = 0;
2310
2311 if(bInsert)
2312 {
2313 if(eSCB == E_CIPHER_PARSER_SCB_10)
2314 {
2315 u8SCB = CMD_PARSER_SCB10;
2316 }
2317 else if(eSCB == E_CIPHER_PARSER_SCB_11)
2318 {
2319 u8SCB = CMD_PARSER_SCB11;
2320 }
2321 else
2322 {
2323 u8SCB = 0;
2324 }
2325 }
2326
2327 _uDmaCtrl2.DmaCtrl2.InSb = bInsert;
2328 _uDmaCtrl2.DmaCtrl2.TsInSb = u8SCB;
2329
2330 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set Insert Enable[%d], SCB[%u]!\n",
2331 __func__, __LINE__, bInsert, u8SCB));
2332
2333 }
2334
HAL_CIPHER_PARSER_Rmv_SCB(MS_BOOL bRemove)2335 void HAL_CIPHER_PARSER_Rmv_SCB(MS_BOOL bRemove)
2336 {
2337 _uDmaCtrl2.DmaCtrl2.RmSb = bRemove;
2338 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Remove SCB[%d]!\n",
2339 __func__, __LINE__, bRemove));
2340 }
2341
HAL_CIPHER_PARSER_BypassPid(MS_BOOL bEnable)2342 void HAL_CIPHER_PARSER_BypassPid(MS_BOOL bEnable)
2343 {
2344 _uDmaCtrl2.DmaCtrl2.BPS = bEnable;
2345 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Bypass PID[%d]!\n",
2346 __func__, __LINE__, bEnable));
2347 }
2348
HAL_CIPHER_PARSER_Set_PID(CIPHER_PARSER_PID stPID)2349 void HAL_CIPHER_PARSER_Set_PID(CIPHER_PARSER_PID stPID)
2350 {
2351 if(stPID.pu8PID0 != NULL)
2352 {
2353 memset(_pu8PID0, 0x0 , PID_SIZE );
2354 memcpy(_pu8PID0, stPID.pu8PID0, PID_SIZE);
2355 }
2356 else
2357 {
2358 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set PID0 NULL!\n",
2359 __func__, __LINE__));
2360 }
2361
2362 if(stPID.pu8PID1 != NULL)
2363 {
2364 memset(_pu8PID1, 0x0 , PID_SIZE );
2365 memcpy(_pu8PID1, stPID.pu8PID1 , PID_SIZE);
2366 }
2367 else
2368 {
2369 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set PID1 NULL!\n",
2370 __func__, __LINE__));
2371 }
2372 }
2373
HAL_CIPHER_PARSER_Set_Key2(DRV_CIPHER_KEY stKey)2374 MS_BOOL HAL_CIPHER_PARSER_Set_Key2(DRV_CIPHER_KEY stKey)
2375 {
2376 HAL_CIPHER_KEYSRC KeySrc = 0;
2377 HAL_CIPHER_ALGO algo = 0;
2378 MS_BOOL bDK2 = FALSE;
2379 MS_BOOL bTwoKey = FALSE;
2380
2381 algo = _uDmaCtrl0.DmaCtrl0.Algo;
2382
2383 if(E_DMA_ALGO_NONE == algo)
2384 {
2385 //No key
2386 bDK2 = FALSE;
2387 bTwoKey = FALSE;
2388 memset(_pu8CipherKey2, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
2389 goto SET_KEY_DONE;
2390 }
2391
2392 //Check Key Source, Index
2393 if(((E_CIPHER_KSRC_KL == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
2394 ((E_CIPHER_KSRC_OTP == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
2395 {
2396 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
2397 __func__, __LINE__, stKey.eKeySrc, stKey.u8KeyIdx));
2398 return FALSE;
2399 }
2400
2401 //DRV to HAL Type transfer
2402 KeySrc = _HAL_CIPHER_TransKey(stKey.eKeySrc, stKey.u8KeyIdx);
2403
2404 // key from CPU
2405 if(E_DMA_KSEL_REGKEY == KeySrc)
2406 {
2407 if ((0 != stKey.pu8KeyData) && (stKey.u8KeyLen != 0) && (stKey.u8KeyLen <= HAL_CRYPTODMA_KEYLEN_MAX) )
2408 {
2409 memset(_pu8CipherKey2, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
2410 memcpy(_pu8CipherKey2, (MS_U8 *)stKey.pu8KeyData , stKey.u8KeyLen);
2411 bDK2 = TRUE;
2412 KeySrc = 0;
2413 }
2414 else
2415 {
2416 return FALSE ;
2417 }
2418 }
2419 else if(E_DMA_KSEL_CAIP == KeySrc)
2420 {
2421 bDK2 = FALSE ;
2422 KeySrc = 0 ;
2423 }
2424 else// key from KL or OTP
2425 {
2426 bDK2 = FALSE;
2427 }
2428
2429 bTwoKey = TRUE;
2430
2431 SET_KEY_DONE:
2432
2433 _uDmaCtrl3.DmaCtrl3.DK2 = bDK2;
2434 _uDmaCtrl3.DmaCtrl3.KeySel2 = KeySrc;
2435 _uDmaCtrl2.DmaCtrl2.TK = bTwoKey;
2436
2437 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DK2[%d], KeySel2[%d]\n",
2438 __func__, __LINE__, bDK2, KeySrc));
2439
2440 return TRUE ;
2441
2442 }
2443
HAL_CIPHER_PARSER_Set_IV2(MS_U8 * pu8IV2,MS_U8 u8IVLen)2444 MS_BOOL HAL_CIPHER_PARSER_Set_IV2(MS_U8 *pu8IV2, MS_U8 u8IVLen)
2445 {
2446 if((pu8IV2 != NULL) && (u8IVLen != 0))
2447 {
2448 memset(_pu8IV2, 0, CIPHER_KEY_SIZE);
2449 memcpy(_pu8IV2, pu8IV2, u8IVLen);
2450 _uDmaCtrl3.DmaCtrl3.DIV2 = TRUE;
2451
2452 return TRUE;
2453 }
2454 else
2455 {
2456 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IV2 NULL!\n",
2457 __func__, __LINE__));
2458 return FALSE;
2459 }
2460
2461 }
2462
HAL_CIPHER_PARSER_Set_ClearStartMode(MS_BOOL bEnable)2463 void HAL_CIPHER_PARSER_Set_ClearStartMode(MS_BOOL bEnable)
2464 {
2465 _uDmaCtrl3.DmaCtrl3.CRS = bEnable;
2466 }
2467
2468 // =====================================
2469 // MISC function implementation
2470 // =====================================
HAL_CIPHER_Misc_Random(MS_U8 * pu8Buf,MS_U32 u32Size)2471 MS_BOOL HAL_CIPHER_Misc_Random(MS_U8 *pu8Buf, MS_U32 u32Size)
2472 {
2473 MS_U16 u16TRN = 0;
2474 MS_U16 u16PreTRN = 0;
2475 MS_U32 u32Count = 0;
2476
2477 if(NULL == pu8Buf || 0 == u32Size)
2478 return FALSE;
2479
2480 #if defined (MCU_AEON)
2481
2482 while(u32Count < u32Size)
2483 {
2484 do{
2485 do{
2486 //Toggle random number bit
2487 MS_U32 u32Tmp=REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU);
2488 u32Tmp^= REG_RNG_TRNG_ACK_SCPU;
2489 REG32_W(_u32RegBase+REG_RNG_TRNG_SCPU, u32Tmp);
2490 }//Read random number valid
2491 while( !(REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) );
2492 }
2493 while( (u16TRN = (REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN );
2494 u16PreTRN = u16TRN;
2495
2496 if(0 == ((u32Size - u32Count)%2UL))
2497 {
2498 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2499 *(pu8Buf+u32Count+1) = (u16TRN & 0xFF00UL) >> 8;
2500 u32Count += 2;
2501 }
2502 else
2503 {
2504 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2505 u32Count += 1;
2506 }
2507 }
2508
2509 #else
2510
2511 while(u32Count < u32Size)
2512 {
2513 do{
2514 do{
2515 //Toggle random number bit
2516 MS_U32 u32Tmp=REG32_R(_u32RegBase+REG_RNG_TRNG_ACPU);
2517 u32Tmp^= REG_RNG_TRNG_ACK_ACPU;
2518 REG32_W(_u32RegBase+REG_RNG_TRNG_ACPU, u32Tmp);
2519 }//Read random number valid
2520 while( !(REG32_R(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_VALID_ACPU_MASK) );
2521 }
2522 while( (u16TRN = (REG32_R(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_OUT_ACPU_MASK))==u16PreTRN );
2523 u16PreTRN = u16TRN;
2524
2525 if(0 == ((u32Size - u32Count)%2UL))
2526 {
2527 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2528 *(pu8Buf+u32Count+1) = (u16TRN & 0xFF00UL) >> 8;
2529 u32Count += 2;
2530 }
2531 else
2532 {
2533 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2534 u32Count += 1;
2535 }
2536 }
2537 #endif
2538
2539 return TRUE;
2540 }
2541
2542
2543