63 static MS_VIRT               _u32RegBase = 0;  variable
543     _u32RegBase = u32BankAddr;  in HAL_CIPHER_SetBank()
544     _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);  in HAL_CIPHER_SetBank()
1137     MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR);  //MIU CrossBar Bank 0x1613  in HAL_CIPHER_DMA_Start()
1138     REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf;  //enable MIU crossbar  in HAL_CIPHER_DMA_Start()
1301     MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR);  //MIU CrossBar Bank 0x1613  in HAL_CIPHER_OTPHash_Start()
1302     REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf;  //enable MIU crossbar  in HAL_CIPHER_OTPHash_Start()
1537     MS_U16 u16MaskTmp = REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48);  in HAL_CIPHER_IntEnable()
1539     REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48) = u16MaskTmp;  in HAL_CIPHER_IntEnable()
1544 …REG16(_u32RegBase + REG_HST0_FIQ_STATUS_63_48) = REG_HTS0_FIQ_CRYPTODMA; //set 1 to clear interrupt  in HAL_CIPHER_IntClear()
1945         MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR);  //MIU CrossBar Bank 0x1613  in HAL_CIPHER_Hash_Start()
1946         REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf;  //enable MIU crossbar  in HAL_CIPHER_Hash_Start()
2446                 REG32(_u32RegBase+REG_RNG_TRNG_SCPU) ^= REG_RNG_TRNG_ACK_SCPU;  in HAL_CIPHER_Misc_Random()
2448             while( !(REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) );  in HAL_CIPHER_Misc_Random()
2450 …while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN );  in HAL_CIPHER_Misc_Random()
2473                 REG32(_u32RegBase+REG_RNG_TRNG_ACPU) ^= REG_RNG_TRNG_ACK_ACPU;  in HAL_CIPHER_Misc_Random()
2475             while( !(REG32(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_VALID_ACPU_MASK) );  in HAL_CIPHER_Misc_Random()
2477 …while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_OUT_ACPU_MASK))==u16PreTRN );  in HAL_CIPHER_Misc_Random()