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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halRASP.c
97 // @brief RASP HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/module.h>
102 #endif
103 #include "MsCommon.h"
104 #include "regNDSRASP.h"
105 #include "halNDSRASP.h"
106
107 //--------------------------------------------------------------------------------------------------
108 // Driver Compiler Option
109 //--------------------------------------------------------------------------------------------------
110
111
112 //--------------------------------------------------------------------------------------------------
113 // TSP Hardware Abstraction Layer
114 //--------------------------------------------------------------------------------------------------
115 static MS_U32 _u32RegBase = 0;
116
117 static REG_RASP* _RASPReg[RASP_NUM] = {NULL , NULL};
118 static MS_U32 _u32RASP_PidfltBase[RASP_NUM] = {NULL , NULL};
119 static MS_U32 _u32RASP_EcmPidfltBase[RASP_NUM] = {NULL , NULL};
120 static MS_U32 _u32RASP_EventMaskBase[RASP_NUM] = {NULL , NULL};
121 static MS_U32 _u32RASP_PayloadMaskBase[RASP_NUM] = {NULL , NULL};
122 static MS_U32 _g32RASPHalDbgLv = RASP_DBGLV_DEBUG;
123
124 // Some register has write order, for example, writing PCR_L will disable PCR counter
125 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
126 #define _HAL_REG32_W(reg, value) { \
127 do { (reg)->L = ((value) & 0x0000FFFF); \
128 (reg)->H = ((value) >> 16); } while(0); }
129
130 #define _HAL_REG16_W(reg, value) { \
131 (reg)->data = ((value) & 0x0000FFFF); }
132
133
134 #define RASP_NUM_CHECK(idx) if( (MS_U32)idx >= (MS_U32)RASP_NUM ) \
135 { printf("[RASP][ERR] Rasp Engine [%d] not exist ! \n",idx); \
136 return ; }
137
138 #define RASP_NUM_CHECK_RET(idx) if( (MS_U32)idx >= (MS_U32)RASP_NUM ) \
139 { printf("[RASP][ERR] Rasp Engine [%d] not exist ! \n",idx); \
140 return 0; }
141
142 #define HALRASP_DBG(lv, x, args...) if (lv <= _g32RASPHalDbgLv ) \
143 { printf("%s, ",__FUNCTION__); \
144 printf(x, ##args); }
145 ////////////////////////////////////////////////////////////////////////////////
146 // Local variable
147 ////////////////////////////////////////////////////////////////////////////////
148
149
150 //K2 RASP1 MIU setting
151 static REG16* _REG_RASP1_MIU;
152 #define _REG_RASP1_MIU_BASE (0x2460)
153 #define _RASP1_MIU_EN (0x4000)
154
155 static MS_U32 _gRaspFileIn_Addr[RASP_NUM];
156 static MS_U32 _gRaspEng_Addr[RASP_NUM];
157
158 static MS_U32 _gChipTp_Addr;
159 static MS_U32 _gClkGen_Addr;
160 static MS_U32 _gClkGen2_Addr;
161
162 //--------------------------------------------------------------------------------------------------
163 // Forward declaration
164 //--------------------------------------------------------------------------------------------------
165
166 ////////////////////////////////////////////////////////////////////////////////
167 // Local Function
168 ////////////////////////////////////////////////////////////////////////////////
169
HAL_RFILEIN_WriteReg_Word(MS_U32 rasp_eng,MS_U32 u32RegAddr,MS_U16 u16Data)170 void HAL_RFILEIN_WriteReg_Word(MS_U32 rasp_eng, MS_U32 u32RegAddr, MS_U16 u16Data)
171 {
172 MS_U32 u32reg;
173 u32reg = (u32RegAddr*4) + _gRaspFileIn_Addr[rasp_eng];
174 (*(volatile MS_U16*)(u32reg)) = u16Data;
175
176 }
177
HAL_RFILEIN_ReadReg_Word(MS_U32 rasp_eng,MS_U32 u32RegAddr)178 MS_U16 HAL_RFILEIN_ReadReg_Word(MS_U32 rasp_eng, MS_U32 u32RegAddr)
179 {
180 MS_U32 u32reg;
181 MS_U16 u16Data;
182 u32reg = (u32RegAddr*4) + _gRaspFileIn_Addr[rasp_eng];
183 u16Data = (*(volatile MS_U16*)(u32reg));
184
185 return u16Data;
186 }
187
HAL_RFILEIN_WriteReg_DWord(MS_U32 rasp_eng,MS_U32 u32RegAddr,MS_U32 u32Data)188 void HAL_RFILEIN_WriteReg_DWord(MS_U32 rasp_eng, MS_U32 u32RegAddr, MS_U32 u32Data)
189 {
190 MS_U32 u32reg;
191
192 u32reg = (u32RegAddr*4) + _gRaspFileIn_Addr[rasp_eng];
193 (*(volatile MS_U16*)(u32reg)) = (MS_U16)(u32Data&0xffff);
194 //printf("(reg,value) = (%x,%x)\n", u32RegAddr, *(volatile MS_U16*)(u32reg) );
195
196 u32reg += 4;
197 (*(volatile MS_U16*)(u32reg)) = (MS_U16)((u32Data>>16)&0xffff);
198 //printf("(reg,value) = (%x,%x)\n", u32RegAddr+1, *(volatile MS_U16*)(u32reg) );
199 }
200
HAL_RFILEIN_ReadReg_DWord(MS_U32 rasp_eng,MS_U32 u32RegAddr)201 MS_U32 HAL_RFILEIN_ReadReg_DWord(MS_U32 rasp_eng, MS_U32 u32RegAddr)
202 {
203 MS_U32 u32reg,u32Data;
204 MS_U16 u16Data1,u16Data2;
205
206 u32reg = (u32RegAddr*4) + _gRaspFileIn_Addr[rasp_eng];
207 u16Data1 = (*(volatile MS_U16*)(u32reg));
208
209 u32reg += 4;
210 u16Data2 = (*(volatile MS_U16*)(u32reg));
211 u32Data = (MS_U32)(u16Data1) + ( ((MS_U32)u16Data2)<<16 );
212
213 return u32Data;
214 }
215
HAL_RASP_WriteReg_Word(MS_U32 rasp_eng,MS_U32 u32RegAddr,MS_U16 u16Data)216 void HAL_RASP_WriteReg_Word(MS_U32 rasp_eng, MS_U32 u32RegAddr, MS_U16 u16Data)
217 {
218 MS_U32 u32reg;
219 u32reg = (u32RegAddr*4) + _gRaspEng_Addr[rasp_eng];
220 (*(volatile MS_U16*)(u32reg)) = u16Data;
221
222 //printf("(reg,value) = (%x,%x)\n",u32reg,u16Data);
223 }
224
HAL_RASP_ReadReg_Word(MS_U32 rasp_eng,MS_U32 u32RegAddr)225 MS_U16 HAL_RASP_ReadReg_Word(MS_U32 rasp_eng, MS_U32 u32RegAddr)
226 {
227 MS_U32 u32reg;
228 MS_U16 u16Data;
229 u32reg = (u32RegAddr*4) + _gRaspEng_Addr[rasp_eng];
230 u16Data = (*(volatile MS_U16*)(u32reg));
231
232 return u16Data;
233 }
234
235 #if 0
236 void HAL_NDSRASP_WriteOtherBank_Word(MS_U32 bank, MS_U32 u32RegAddr, MS_U16 u16Data)
237 {
238 MS_U32 u32reg;
239 MS_U16 temp;
240
241 u32reg = (u32RegAddr*4) + bank;
242 temp = (*(volatile MS_U16*)(u32reg));
243 temp |= u16Data;
244
245 (*(volatile MS_U16*)(u32reg)) = temp;
246
247 }
248
249 void HAL_NDSRASP_MaskOtherBank_Word(MS_U32 bank, MS_U32 u32RegAddr, MS_U16 u16MaskData)
250 {
251 MS_U32 u32reg;
252 MS_U16 temp;
253
254 u32reg = (u32RegAddr*4) + bank;
255 temp = (*(volatile MS_U16*)(u32reg));
256 temp &= u16MaskData;
257
258 (*(volatile MS_U16*)(u32reg)) = temp;
259
260 }
261 #endif
262
HAL_RASP_WriteReg_DWord(MS_U32 rasp_eng,MS_U32 u32RegAddr,MS_U32 u32Data)263 void HAL_RASP_WriteReg_DWord(MS_U32 rasp_eng, MS_U32 u32RegAddr, MS_U32 u32Data)
264 {
265 MS_U32 u32reg;
266
267 u32reg = (u32RegAddr*4) + _gRaspEng_Addr[rasp_eng];
268 (*(volatile MS_U16*)(u32reg)) = (MS_U16)(u32Data&0xffff);
269
270 u32reg += 4;
271 (*(volatile MS_U16*)(u32reg)) = (MS_U16)((u32Data>>16)&0xffff);
272 }
273
HAL_RASP_ReadReg_DWord(MS_U32 rasp_eng,MS_U32 u32RegAddr)274 MS_U32 HAL_RASP_ReadReg_DWord(MS_U32 rasp_eng, MS_U32 u32RegAddr)
275 {
276 MS_U32 u32reg,u32Data;
277 MS_U16 u16Data1,u16Data2;
278
279 u32reg = (u32RegAddr*4) + _gRaspEng_Addr[rasp_eng];
280 u16Data1 = (*(volatile MS_U16*)(u32reg));
281
282 u32reg += 4;
283 u16Data2 = (*(volatile MS_U16*)(u32reg));
284 u32Data = (u16Data1) + ((MS_U32)u16Data2<<16);
285
286 return u32Data;
287 }
288
289 #if 0
290 static void _delay(void)
291 {
292 volatile MS_U32 i;
293 for (i = 0; i< 0xFFFF; i++);
294 }
295 #endif
296
297 #ifdef REG32__
_HAL_REG32_R(REG32 * reg)298 static MS_U32 _HAL_REG32_R(REG32 *reg)
299 {
300 MS_U32 value = 0;
301 value = (reg)->H << 16;
302 value |= (reg)->L;
303 return value;
304 }
305 #endif
306
_HAL_REG16_R(REG16 * reg)307 static MS_U16 _HAL_REG16_R(REG16 *reg)
308 {
309 MS_U16 value;
310 value = (reg)->data;
311 return value;
312 }
313
314 //--------------------------------------------------------------------------------------------------
315 // For MISC part
316 //--------------------------------------------------------------------------------------------------
HAL_NDSRASP_SetBank(MS_U32 u32BankAddr)317 void HAL_NDSRASP_SetBank(MS_U32 u32BankAddr)
318 {
319 HALRASP_DBG(RASP_DBGLV_ALERT,"u32BankAddr = %x\n",u32BankAddr);
320 _u32RegBase = u32BankAddr;
321 _RASPReg[0] = (REG_RASP*)(_u32RegBase + RASP0_BANK0_REG_CTRL_BASE);
322 _u32RASP_PidfltBase[0] = _u32RegBase + RASP0_BANK0_PIDFLT_BASE;
323 _u32RASP_EventMaskBase[0] = _u32RegBase + RASP0_BANK1_EVENT_MASK_BASE;
324 _u32RASP_PayloadMaskBase[0] = _u32RegBase + RASP0_BANK1_PAYLOAD_MASK_BASE;
325 _u32RASP_EcmPidfltBase[0] = _u32RegBase + RASP0_BANK1_ECM_PIDFLT_BASE;
326
327 _RASPReg[1] = (REG_RASP*)(_u32RegBase + RASP1_BANK0_REG_CTRL_BASE);
328 _u32RASP_PidfltBase[1] = _u32RegBase + RASP1_BANK0_PIDFLT_BASE;
329 _u32RASP_EventMaskBase[1] = _u32RegBase + RASP1_BANK1_EVENT_MASK_BASE;
330 _u32RASP_PayloadMaskBase[1] = _u32RegBase + RASP1_BANK1_PAYLOAD_MASK_BASE;
331 _u32RASP_EcmPidfltBase[1] = _u32RegBase + RASP1_BANK1_ECM_PIDFLT_BASE;
332 //K2 RASP1 MIU setting
333 _REG_RASP1_MIU = (REG16*)(_u32RegBase + _REG_RASP1_MIU_BASE);
334
335 _gRaspFileIn_Addr[0] = _u32RegBase + REG_RASP0_FILE_BASE;
336 _gRaspFileIn_Addr[1] = _u32RegBase + REG_RASP1_FILE_BASE;
337
338 _gRaspEng_Addr[0] = _u32RegBase + REG_RASP0_BASE;
339 _gRaspEng_Addr[1] = _u32RegBase + REG_RASP1_BASE;
340
341 _gChipTp_Addr = _u32RegBase + REG_CHIPTOP_RP_BASE;
342 _gClkGen_Addr = _u32RegBase + REG_CLKGEN_RP_BASE;
343 _gClkGen2_Addr = _u32RegBase + REG_CLKGEN2_BASE;
344 }
345
HAL_NDSRASP_Str2MIU_Reset(MS_U32 u32RASPEng)346 static void HAL_NDSRASP_Str2MIU_Reset(MS_U32 u32RASPEng)
347 {
348 MS_U16 HWCtrl1;
349 HWCtrl1 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL1);
350 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (HWCtrl1 | RASP_STR2MIU_RST_WADDR));
351 MsOS_DelayTaskUs(10);
352 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (HWCtrl1 & ~(RASP_STR2MIU_RST_WADDR)) );
353 }
354
HAL_NDSRASP_ECM2MIU_Reset(MS_U32 u32RASPEng)355 static void HAL_NDSRASP_ECM2MIU_Reset(MS_U32 u32RASPEng)
356 {
357 MS_U16 HWCtrl3;
358 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3);
359 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_RST_WADDR));
360 MsOS_DelayTaskUs(10);
361 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_ECM2MIU_RST_WADDR)) );
362 }
363
HAL_NDSRASP_PAYLD2MIU_Reset(MS_U32 u32RASPEng)364 static void HAL_NDSRASP_PAYLD2MIU_Reset(MS_U32 u32RASPEng)
365 {
366 MS_U16 HWCtrl3;
367 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3);
368 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_PAYLD2MIU_RST_WADDR));
369 MsOS_DelayTaskUs(10);
370 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & ~(RASP_PAYLD2MIU_RST_WADDR)) );
371 }
372
HAL_NDSRASP_Init(MS_U32 u32RASPEng)373 void HAL_NDSRASP_Init(MS_U32 u32RASPEng)
374 {
375 HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x\n", u32RASPEng);
376
377 RASP_NUM_CHECK(u32RASPEng);
378 #if 1
379 MS_U32 addr;
380 addr = _u32RegBase + (0x161300*2 + 0x00*4); //$ enable MIUCrossbar
381 (*((volatile MS_U16*)(addr))) = 0x000f;
382
383 addr = _u32RegBase + (0x161300*2 + 0x1b*4); //$ enable gate clock
384 (*((volatile MS_U16*)(addr))) = 0x0003;
385 #endif
386
387
388 MS_U16 HWCtrl0;
389 //Clear all ctrl
390 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, 0x0);
391 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, 0x0);
392 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, 0x0);
393 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, 0x0);
394 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL4, 0x0);
395
396 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_CORPT_PKTSIZE, (RASP_PKT_SIZE_188<<RASP_PKT_SHIFT) );
397
398 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, RASP_SW_RESET);
399
400 HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL0);
401
402 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 | RASP_RISING_SYNC_DETECT|RASP_FALLING_VALID_DETECT) );
403
404 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, RASP_SERIAL_EXT_SYNC_1T);
405
406 #if 0
407 //need to change....
408 if(u32RASPEng == 1)
409 {
410 //K2 RASP1 MIU setting
411 _HAL_REG16_W((REG16*)_REG_RASP1_MIU, SET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_EN));
412 }
413 #endif
414
415 MS_U16 i;
416 for(i=0;i<=RASP_PIDFLT_NUM;i++)
417 HAL_NDSRASP_SetPidflt(u32RASPEng, i, 0x1fff);
418
419
420 HAL_NDSRASP_Str2MIU_Reset(u32RASPEng);
421
422 MS_U16 HWCtrl1;
423
424 HWCtrl1 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL1);
425 HWCtrl1 |= (RASP_ALT_TS_SIZE_EN | RASP_STR2MIU_EN | RASP_PINGPONG_EN);
426 //HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, HWCtrl1);
427
428 HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL0);
429 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 | RASP_TSIF2_ENABLE) );
430
431 HAL_NDSRASP_SetECM_Init_1(u32RASPEng);
432
433 }
434
HAL_NDSRASP_Exit(MS_U32 u32RASPEng)435 void HAL_NDSRASP_Exit(MS_U32 u32RASPEng)
436 {
437 HALRASP_DBG(RASP_DBGLV_INFO, "uRASPEng = %x\n", u32RASPEng);
438 RASP_NUM_CHECK(u32RASPEng);
439
440 MS_U16 HWCtrl0;
441 HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL0);
442 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 & ~RASP_SW_RESET));
443
444 //need to change....
445 if(u32RASPEng == 1)
446 {
447 //K2 RASP1 MIU setting
448 _HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_EN));
449 }
450 }
451
HAL_NDSRASP_Pvr_Enable(MS_U32 u32RASPEng)452 void HAL_NDSRASP_Pvr_Enable(MS_U32 u32RASPEng)
453 {
454 HALRASP_DBG(RASP_DBGLV_INFO, "uRASPEng = %x\n", u32RASPEng);
455 RASP_NUM_CHECK(u32RASPEng);
456
457 HAL_NDSRASP_Str2MIU_Reset(u32RASPEng);
458
459 MS_U16 HWCtrl1;
460
461 HWCtrl1 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL1);
462 HWCtrl1 |= (RASP_ALT_TS_SIZE_EN | RASP_STR2MIU_EN | RASP_PINGPONG_EN);
463 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, HWCtrl1);
464
465 HAL_NDSRASP_Str2MIU_Reset(u32RASPEng);
466
467 //MS_U16 HWCtrl0;
468 //HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL0);
469 //HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 | RASP_TSIF2_ENABLE) );
470 }
471
472
HAL_NDSRASP_ECM_Enable(MS_U32 u32RASPEng,MS_BOOL enable)473 void HAL_NDSRASP_ECM_Enable(MS_U32 u32RASPEng , MS_BOOL enable )
474 {
475 HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x, enable = %d\n", u32RASPEng,enable);
476 RASP_NUM_CHECK(u32RASPEng);
477
478 MS_U16 HWCtrl2,HWCtrl3;
479 HWCtrl2 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL2);
480 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3);
481
482 if (enable)
483 {
484 HAL_NDSRASP_ECM2MIU_Reset(u32RASPEng);
485
486 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, (HWCtrl2 | RASP_ECM_BURST_LEN) );
487
488 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_EN) );
489 }
490 else
491 {
492 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & (~RASP_ECM2MIU_EN)) );
493 }
494 }
495
HAL_NDSRASP_Payload_Enable(MS_U32 u32RASPEng,MS_BOOL enable)496 void HAL_NDSRASP_Payload_Enable(MS_U32 u32RASPEng ,MS_BOOL enable )
497 {
498 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x, enable = %d\n", u32RASPEng,enable);
499 RASP_NUM_CHECK(u32RASPEng);
500
501 MS_U16 HWCtrl2,HWCtrl3;
502 HWCtrl2 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL2);
503 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL3);
504
505 #if 1
506 if (enable)
507 {
508 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_PAYLD2MIU_RST_WADDR) );
509 MsOS_DelayTaskUs(10);
510 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & (~RASP_PAYLD2MIU_RST_WADDR)) );
511
512 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, (HWCtrl2 | RASP_PAYLOAD_BURST_LEN) );
513
514 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_PAYLD2MIU_EN | RASP_PAYLD2MIU_PINGPONE) );
515 }
516 else
517 {
518 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & (~RASP_PAYLD2MIU_EN)) );
519 }
520 #else
521 if (enable)
522 {
523 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3,
524 SET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_RST_WADDR));
525 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3,
526 RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_RST_WADDR));
527
528 //timo
529 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL2,
530 SET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL2), RASP_PAYLOAD_BURST_LEN));
531
532 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3,
533 SET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_EN));
534 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3,
535 SET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_PINGPONE));
536 }
537 else
538 {
539 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3,
540 RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3), RASP_PAYLD2MIU_EN));
541
542 }
543 #endif
544 }
545
546
547
548
HAL_NDSRASP_Stop(MS_U32 u32RASPEng)549 void HAL_NDSRASP_Stop(MS_U32 u32RASPEng)
550 {
551 HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x\n", u32RASPEng);
552 RASP_NUM_CHECK(u32RASPEng);
553 MS_U16 HWCtrl1;
554 HWCtrl1 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL1);
555
556 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (HWCtrl1 & (~RASP_STR2MIU_EN)) );
557 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (HWCtrl1 & (~RASP_TSIF2_ENABLE)) );
558 }
559
HAL_NDSRASP_Pause(MS_U32 u32RASPEng,MS_BOOL bPause)560 void HAL_NDSRASP_Pause(MS_U32 u32RASPEng , MS_BOOL bPause)
561 {
562 HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x, bPause = %d\n", u32RASPEng,bPause);
563 RASP_NUM_CHECK(u32RASPEng);
564 MS_U16 HWCtrl1;
565 HWCtrl1 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL1);
566
567 if (bPause)
568 {
569 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (HWCtrl1 & (~RASP_STR2MIU_EN)) );
570 }
571 else
572 {
573 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (HWCtrl1 | RASP_STR2MIU_RST_WADDR) );
574 MsOS_DelayTaskUs(10);
575 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (HWCtrl1 & (~RASP_STR2MIU_RST_WADDR)) );
576 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (HWCtrl1 | RASP_STR2MIU_EN) );
577 }
578 }
579
HAL_NDSRASP_Rec_PID(MS_U32 u32RASPEng,MS_BOOL bSet)580 void HAL_NDSRASP_Rec_PID(MS_U32 u32RASPEng , MS_BOOL bSet)
581 {
582 HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x, bSet = %d\n", u32RASPEng,bSet);
583 RASP_NUM_CHECK(u32RASPEng);
584 MS_U16 HWCtrl1;
585 HWCtrl1 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL1);
586 if (bSet)
587 {
588 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (HWCtrl1 | RASP_REC_PID) );
589 }
590 else
591 {
592 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (HWCtrl1 & (~RASP_REC_PID)) );
593 }
594 }
595
HAL_NDSRASP_SWReset(MS_U32 u32RASPEng)596 void HAL_NDSRASP_SWReset(MS_U32 u32RASPEng)
597 {
598 HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x\n", u32RASPEng);
599 RASP_NUM_CHECK(u32RASPEng);
600
601 MS_U16 HWCtrl0;
602
603 HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL0);
604 HAL_RASP_WriteReg_Word(u32RASPEng,REG_RASP_HW_CTRL0, (HWCtrl0|RASP_SW_RESET) );
605 MsOS_DelayTaskUs(10);
606 HAL_RASP_WriteReg_Word(u32RASPEng,REG_RASP_HW_CTRL0, HWCtrl0 );
607 }
608
HAL_NDSRASP_SetCorptData(MS_U32 u32RASPEng,MS_U16 u16From,MS_U16 u16To,MS_U8 u8Data)609 void HAL_NDSRASP_SetCorptData(MS_U32 u32RASPEng , MS_U16 u16From ,MS_U16 u16To , MS_U8 u8Data)
610 {
611 RASP_NUM_CHECK(u32RASPEng);
612 #if 1
613 MS_U16 CorptData = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_CORPT_PKTSIZE);
614 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_CORRUPTION, (u16From&RASP_FROMTO_MASK) | ((u16To&RASP_FROMTO_MASK)<< RASP_TO_SHIFT) );
615 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_CORPT_PKTSIZE, ((CorptData & 0xff00) | u8Data) );
616 #else
617 // set corrupt data //
618 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_CorptFromTo, ((u16To << RASP_TO_SHIFT )&RASP_FROMTO_MASK)|(u16From&RASP_FROMTO_MASK) );
619 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_CorptData_PktSize2,
620 _HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_CorptData_PktSize2)|u8Data);
621 #endif
622 }
623
624
HAL_NDSRASP_SetCorptFlt(MS_U32 u32RASPEng,MS_U16 u16Fltid,MS_BOOL Enable)625 void HAL_NDSRASP_SetCorptFlt(MS_U32 u32RASPEng , MS_U16 u16Fltid, MS_BOOL Enable)
626 {
627 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x, u16Fltid = %d(0x%x), Enable = %d\n", u32RASPEng,u16Fltid,u16Fltid,Enable);
628 RASP_NUM_CHECK(u32RASPEng);
629
630 #if 1
631 MS_U16 PidFlt = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_PIDFLT_N(u16Fltid));
632 if(Enable)
633 {
634 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_PIDFLT_N(u16Fltid), (PidFlt | RASP_PID_PKT_CORPT_EN));
635 }
636 else
637 {
638 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_PIDFLT_N(u16Fltid), (PidFlt & (~RASP_PID_PKT_CORPT_EN)) );
639 }
640 #else
641 MS_U32 _u32PidfltReg = _u32RASP_PidfltBase[u32RASPEng] + (u16Fltid*0x04);
642
643 if(Enable)
644 {
645 _HAL_REG16_W((REG16 *)_u32PidfltReg, SET_FLAG1(_HAL_REG16_R((REG16 *)_u32PidfltReg), RASP_PID_PKT_CORPT_EN));
646 }
647 else
648 {
649 _HAL_REG16_W((REG16 *)_u32PidfltReg, RESET_FLAG1(_HAL_REG16_R((REG16 *)_u32PidfltReg), RASP_PID_PKT_CORPT_EN));
650 }
651 #endif
652
653 }
654
HAL_NDSRASP_SetPidflt(MS_U32 u32RASPEng,MS_U16 u16Fltid,MS_U16 u16Pid)655 void HAL_NDSRASP_SetPidflt(MS_U32 u32RASPEng , MS_U16 u16Fltid , MS_U16 u16Pid)
656 {
657 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x, u16Fltid = %d(0x%x), u16Pid = %x\n", u32RASPEng,u16Fltid,u16Fltid,u16Pid);
658 RASP_NUM_CHECK(u32RASPEng);
659 HAL_RASP_WriteReg_Word(u32RASPEng,REG_RASP_PIDFLT_N(u16Fltid),u16Pid);
660 }
661
HAL_NDSRASP_GetPidflt(MS_U32 u32RASPEng,MS_U16 u16Fltid,MS_U16 * u16Pid)662 void HAL_NDSRASP_GetPidflt(MS_U32 u32RASPEng , MS_U16 u16Fltid , MS_U16 *u16Pid)
663 {
664 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x, u16Fltid = %d(0x%x)\n", u32RASPEng,u16Fltid,u16Fltid);
665 RASP_NUM_CHECK(u32RASPEng);
666 *u16Pid = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_PIDFLT_N(u16Fltid));
667 HALRASP_DBG(RASP_DBGLV_INFO, "u16Pid = 0x%x\n", *u16Pid);
668 }
669
HAL_NDSRASP_SetEcmPidflt(MS_U32 u32RASPEng,MS_U16 u16Fltid,MS_U16 u16Pid)670 void HAL_NDSRASP_SetEcmPidflt(MS_U32 u32RASPEng , MS_U16 u16Fltid , MS_U16 u16Pid)
671 {
672
673 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x, u16Fltid = %d(0x%x) u16Pid = %x\n", u32RASPEng,u16Fltid,u16Fltid,u16Pid);
674 RASP_NUM_CHECK(u32RASPEng);
675
676 MS_U16 LockCtrlReg;
677 u16Pid = u16Pid | 0xE000; //
678
679 if(u16Fltid <= 3)
680 {
681 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_PID_N(u16Fltid), u16Pid);
682 LockCtrlReg = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_ECM_LOCK_CTRL);
683 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_LOCK_CTRL, (LockCtrlReg | (0x1<<(4*u16Fltid)) ) );
684 }
685 else if(u16Fltid == 4)
686 {
687 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_PID_4, u16Pid);
688 LockCtrlReg = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_ECM45_LOCK_CTRL);
689 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM45_LOCK_CTRL, (LockCtrlReg | (0x1) ) );
690 }
691 else if(u16Fltid == 5)
692 {
693 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_PID_5, u16Pid);
694 LockCtrlReg = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_ECM45_LOCK_CTRL);
695 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM45_LOCK_CTRL, (LockCtrlReg | (0x1<<4) ) );
696 }
697
698 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_TID, 0x8180); //odd,even
699 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_LOCK_CTRL, 0x7777);
700 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM45_LOCK_CTRL, 0x77);
701
702 }
703
HAL_NDSRASP_ReadEcmPidflt(MS_U32 u32RASPEng,MS_U16 u16Fltid,MS_U16 * pu16Pid)704 void HAL_NDSRASP_ReadEcmPidflt(MS_U32 u32RASPEng , MS_U16 u16Fltid , MS_U16 *pu16Pid)
705 {
706
707 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x, u16Fltid = %d(0x%x)\n", u32RASPEng,u16Fltid,u16Fltid);
708 RASP_NUM_CHECK(u32RASPEng);
709
710 if(u16Fltid <= 3)
711 *pu16Pid = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_ECM_PID_N(u16Fltid));
712 else if(u16Fltid == 4)
713 *pu16Pid = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_ECM_PID_4);
714 else if(u16Fltid == 5)
715 *pu16Pid = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_ECM_PID_5);
716
717 }
718
719
HAL_NDSRASP_SetECM_Init_1(MS_U32 u32RASPEng)720 void HAL_NDSRASP_SetECM_Init_1(MS_U32 u32RASPEng)
721 {
722 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x\n", u32RASPEng);
723 RASP_NUM_CHECK(u32RASPEng);
724 #if 1
725 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_CA_INT, 0x0007);
726 //MsOS_DelayTaskUs(10);
727 //HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_INT_STATE, 0xff);
728 #else
729 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_Ecm_reg_18,0X0007);
730 #endif
731 }
732
HAL_NDSRASP_SetECM_Init_2(MS_U32 u32RASPEng)733 void HAL_NDSRASP_SetECM_Init_2(MS_U32 u32RASPEng)
734 {
735 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x\n", u32RASPEng);
736 RASP_NUM_CHECK(u32RASPEng);
737 #if 1
738 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_TID, 0x8180); //odd,even
739 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_LOCK_CTRL, 0x7777);
740 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM45_LOCK_CTRL, 0x77);
741 #else
742 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_Ecm_reg_16 ,0X8180);
743 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_Ecm_reg_17 ,0X7777);
744 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_Ecm_reg_32 ,0X0077);
745 #endif
746 }
747
HAL_NDSRASP_SetECM_GetHW(MS_U32 u32RASPEng)748 MS_U16 HAL_NDSRASP_SetECM_GetHW(MS_U32 u32RASPEng)
749 {
750 HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x\n", u32RASPEng);
751 RASP_NUM_CHECK_RET(u32RASPEng);
752
753 return HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_ECM_INT_STATE);
754 }
755
HAL_NDSRASP_SetECM_ResetHW(MS_U32 u32RASPEng,MS_U16 IntStatus)756 void HAL_NDSRASP_SetECM_ResetHW(MS_U32 u32RASPEng, MS_U16 IntStatus)
757 {
758 RASP_NUM_CHECK(u32RASPEng);
759
760 //HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_INT_STATE, 0xFFFF);
761 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_INT_STATE, IntStatus);
762 //MsOS_DelayTaskUs(10);
763 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_ECM_INT_STATE, 0x0000);
764 }
765
HAL_NDSRASP_SetEventMask(MS_U32 u32RASPEng,MS_U16 u16Fltid,MS_U32 u32Mask)766 void HAL_NDSRASP_SetEventMask(MS_U32 u32RASPEng , MS_U16 u16Fltid, MS_U32 u32Mask)
767 {
768 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x, u16Fltid = %d(0x%x) u32Mask = %x\n",u32RASPEng,u16Fltid,u16Fltid,u32Mask);
769 RASP_NUM_CHECK(u32RASPEng);
770 #if 1
771 HAL_RASP_WriteReg_DWord(u32RASPEng,REG_RASP_EVENT_MASK_N(u16Fltid),u32Mask);
772 #else
773 MS_U32 _u32EventMaskReg = _u32RASP_EventMaskBase[u32RASPEng] + (u16Fltid*0x08);
774 _HAL_REG32_W((REG32 *)_u32EventMaskReg, u32Mask);
775 #endif
776 }
777
HAL_NDSRASP_SetPayloadMask(MS_U32 u32RASPEng,MS_U16 u16Fltid,MS_U32 u32Mask)778 void HAL_NDSRASP_SetPayloadMask(MS_U32 u32RASPEng , MS_U16 u16Fltid, MS_U32 u32Mask)
779 {
780 HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x, u16Fltid = %d(0x%x) u32Mask = %x\n", u32RASPEng,u16Fltid,u16Fltid,u32Mask);
781 RASP_NUM_CHECK(u32RASPEng);
782 #if 1
783 HAL_RASP_WriteReg_DWord(u32RASPEng,REG_RASP_PAYLOAD_MASK_N(u16Fltid),u32Mask);
784 #else
785 MS_U32 _u32PayloadMaskReg = _u32RASP_PayloadMaskBase[u32RASPEng] + (u16Fltid*0x08);
786 _HAL_REG32_W((REG32 *)_u32PayloadMaskReg, u32Mask);
787 #endif
788 }
789
790
HAL_NDSRASP_SetPayloadPacketMode(MS_U32 u32RASPEng,MS_BOOL bDisable192)791 void HAL_NDSRASP_SetPayloadPacketMode(MS_U32 u32RASPEng, MS_BOOL bDisable192)
792 {
793 HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x\n", u32RASPEng);
794 RASP_NUM_CHECK(u32RASPEng);
795
796 MS_U16 HW_CTRL3;
797 HW_CTRL3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3);
798
799 if (bDisable192)
800 {
801 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HW_CTRL3 | RASP_PAYLD2_PKT_192_DIS /*| RASP_ECMPKT_192_DIS */) );
802 }
803
804 else
805 {
806 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HW_CTRL3 & ~(RASP_PAYLD2_PKT_192_DIS /* |RASP_ECMPKT_192_DIS */)) );
807 }
808
809 }
810
HAL_NDSRASP_SetECMPacketMode(MS_U32 u32RASPEng,MS_BOOL bDisable192)811 void HAL_NDSRASP_SetECMPacketMode(MS_U32 u32RASPEng, MS_BOOL bDisable192)
812 {
813 HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x\n", u32RASPEng);
814 RASP_NUM_CHECK(u32RASPEng);
815
816 MS_U16 HW_CTRL3;
817 HW_CTRL3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3);
818
819 if (bDisable192)
820 {
821 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HW_CTRL3 | RASP_ECMPKT_192_DIS /*| RASP_ECMPKT_192_DIS */) );
822 }
823
824 else
825 {
826 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HW_CTRL3 & ~(RASP_ECMPKT_192_DIS /* |RASP_ECMPKT_192_DIS */)) );
827 }
828
829 }
830
831
832 #if 0
833
834 void HAL_NDSRASP_SetStr2Miu_StartAddr(MS_U32 u32RASPEng , MS_U32 u32StartAddr0, MS_U32 u32StartAddr1)
835 {
836 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x \n",u32RASPEng);
837 RASP_NUM_CHECK(u32RASPEng);
838 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head,MIU(u32StartAddr0));
839 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Head2,MIU(u32StartAddr1));
840 }
841
842 void HAL_NDSRASP_SetStr2Miu_MidAddr(MS_U32 u32RASPEng , MS_U32 u32MidAddr0, MS_U32 u32MidAddr1)
843 {
844 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x \n",u32RASPEng);
845 RASP_NUM_CHECK(u32RASPEng);
846 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid,MIU(u32MidAddr0));
847 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid2,MIU(u32MidAddr1));
848 }
849
850 void HAL_NDSRASP_SetStr2Miu_EndAddr(MS_U32 u32RASPEng , MS_U32 u32EndAddr0, MS_U32 u32EndAddr1)
851 {
852 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x \n",u32RASPEng);
853 RASP_NUM_CHECK(u32RASPEng);
854 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail,MIU(u32EndAddr0));
855 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Tail2,MIU(u32EndAddr1));
856 }
857
858 void HAL_NDSRASP_SetPayload_StartAddr(MS_U32 u32RASPEng , MS_U32 u32StartAddr0, MS_U32 u32StartAddr1)
859 {
860 RASP_NUM_CHECK(u32RASPEng);
861 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head,MIU(u32StartAddr0));
862 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Head2,MIU(u32StartAddr1));
863 }
864
865 void HAL_NDSRASP_SetPayload_MidAddr(MS_U32 u32RASPEng , MS_U32 u32MidAddr0, MS_U32 u32MidAddr1)
866 {
867 RASP_NUM_CHECK(u32RASPEng);
868 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid,MIU(u32MidAddr0));
869 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Mid2,MIU(u32MidAddr1));
870 }
871
872 void HAL_NDSRASP_SetPayload_EndAddr(MS_U32 u32RASPEng , MS_U32 u32EndAddr0, MS_U32 u32EndAddr1)
873 {
874 RASP_NUM_CHECK(u32RASPEng);
875 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Tail,MIU(u32EndAddr0));
876 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Payload2miu_Tail2,MIU(u32EndAddr1));
877 }
878
879 void HAL_NDSRASP_SetECM_StartAddr(MS_U32 u32RASPEng , MS_U32 u32StartAddr)
880 {
881 RASP_NUM_CHECK(u32RASPEng);
882 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Ecm2miu_Head,MIU(u32StartAddr));
883 }
884
885 void HAL_NDSRASP_SetECM_MidAddr(MS_U32 u32RASPEng , MS_U32 u32MidAddr)
886 {
887 RASP_NUM_CHECK(u32RASPEng);
888 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Ecm2miu_Mid,MIU(u32MidAddr));
889 }
890
891 void HAL_NDSRASP_SetECM_EndAddr(MS_U32 u32RASPEng , MS_U32 u32EndAddr)
892 {
893 RASP_NUM_CHECK(u32RASPEng);
894 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_Ecm2miu_Tail,MIU(u32EndAddr));
895 }
896 #endif
897
HAL_NDSRASP_GetWritePtr(MS_U32 u32RASPEng)898 MS_U32 HAL_NDSRASP_GetWritePtr(MS_U32 u32RASPEng)
899 {
900 MS_U32 WritePtr;
901
902 RASP_NUM_CHECK_RET(u32RASPEng);
903 MS_U16 HWCtrl4;
904
905 HWCtrl4 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL4);
906 #if 1
907 HAL_RASP_WriteReg_Word(u32RASPEng,REG_RASP_HW_CTRL4, (HWCtrl4 | RASP_TS_STR2MI_WP_LD_DIS) );
908 WritePtr = (HAL_RASP_ReadReg_DWord(u32RASPEng,REG_RASP_STR2MIU_MID1_L) << 4 );
909 HAL_RASP_WriteReg_Word(u32RASPEng,REG_RASP_HW_CTRL4, (HWCtrl4 & (~RASP_TS_STR2MI_WP_LD_DIS)) );
910 #else
911 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4,
912 SET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4) , RASP_TS_STR2MI_WP_LD_DIS));
913
914 WritePtr = ((_HAL_REG32_R(&_RASPReg[u32RASPEng][0].RASP_Str2miu_Mid)) << 4);
915
916 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4,
917 RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4) , RASP_TS_STR2MI_WP_LD_DIS));
918 #endif
919 //HALRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x, WritePtr = %x\n", u32RASPEng,WritePtr);
920 return WritePtr;
921 }
922
HAL_NDSRASP_GetPayloadWritePtr(MS_U32 u32RASPEng)923 MS_U32 HAL_NDSRASP_GetPayloadWritePtr(MS_U32 u32RASPEng)
924 {
925 RASP_NUM_CHECK_RET(u32RASPEng);
926 return (HAL_RASP_ReadReg_DWord(u32RASPEng,REG_RASP_PAYLOAD2MIU_MID1_L) << 4 );
927 }
928
HAL_NDSRASP_GetECMWritePtr(MS_U32 u32RASPEng)929 MS_U32 HAL_NDSRASP_GetECMWritePtr(MS_U32 u32RASPEng)
930 {
931 RASP_NUM_CHECK_RET(u32RASPEng);
932 return (HAL_RASP_ReadReg_DWord(u32RASPEng,REG_RASP_ECM2MIU_MID1_L) << 4 );
933 }
934
935
936 //change the BOOL bSet to MS_U32, the packet size maybe more than two choice
HAL_NDSRASP_SetStrPacketMode(MS_U32 u32RASPEng,MS_BOOL bSet)937 void HAL_NDSRASP_SetStrPacketMode(MS_U32 u32RASPEng , MS_BOOL bSet)
938 {
939 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x \n",u32RASPEng);
940 RASP_NUM_CHECK(u32RASPEng);
941
942 MS_U16 u16RegCtrl4,u16RegCtrl1;
943 u16RegCtrl4 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL4);
944 if (bSet)
945 {
946 u16RegCtrl4 |= RASP_STREAM_192_EN;
947 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL4, u16RegCtrl4);
948
949 //set the burst length.
950 u16RegCtrl1 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL1);
951 u16RegCtrl1 = (u16RegCtrl1 & (~RASP_BURST_LEN_MASK)) | ( 0x02 <<RASP_BURST_LEN_SHIFT) ;
952 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, u16RegCtrl1);
953 }
954 else
955 {
956 u16RegCtrl4 &= (~RASP_STREAM_192_EN);
957 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL4, u16RegCtrl4);
958
959 }
960 }
961
962
HAL_NDSRASP_PowerCtrl(MS_U32 u32RASPEng,MS_BOOL bSet)963 void HAL_NDSRASP_PowerCtrl(MS_U32 u32RASPEng , MS_BOOL bSet)
964 {
965
966 }
967
HAL_NDSRASP_GetPVRTimeStamp(MS_U32 u32RASPEng)968 MS_U32 HAL_NDSRASP_GetPVRTimeStamp(MS_U32 u32RASPEng)
969 {
970 RASP_NUM_CHECK_RET(u32RASPEng);
971 //return _HAL_REG32_R(&_RASPReg[u32RASPEng][0].RASP_StrLPCR1);
972 return HAL_RASP_ReadReg_DWord(u32RASPEng, REG_RASP_STR_LPCR1_L);
973 }
974
HAL_NDSRASP_GetECMTimeStamp(MS_U32 u32RASPEng)975 MS_U32 HAL_NDSRASP_GetECMTimeStamp(MS_U32 u32RASPEng)
976 {
977 RASP_NUM_CHECK_RET(u32RASPEng);
978 return HAL_RASP_ReadReg_DWord(u32RASPEng,REG_RASP_ECM_LPCR1_L);
979 }
980
HAL_NDSRASP_GetPayloadTimeStamp(MS_U32 u32RASPEng)981 MS_U32 HAL_NDSRASP_GetPayloadTimeStamp(MS_U32 u32RASPEng)
982 {
983 RASP_NUM_CHECK_RET(u32RASPEng);
984 //return _HAL_REG32_R(&_RASPReg[u32RASPEng][0].RASP_PayLPCR1);
985 return HAL_RASP_ReadReg_DWord(u32RASPEng, REG_RASP_PAY_LPCR1_L);
986 }
987
HAL_NDSRASP_SetPVRTimeStamp(MS_U32 u32RASPEng,MS_U32 u32Stamp)988 void HAL_NDSRASP_SetPVRTimeStamp(MS_U32 u32RASPEng , MS_U32 u32Stamp)
989 {
990 RASP_NUM_CHECK(u32RASPEng);
991
992 HAL_RASP_WriteReg_DWord(u32RASPEng, REG_RASP_STR_LPCR1_BUF_L, u32Stamp);
993 MS_U16 HWCtrl4;
994
995 HWCtrl4 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL4);
996 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL4, (HWCtrl4 | RASP_STREAM_LPCR_WLD));
997 MsOS_DelayTaskUs(10);
998 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL4, (HWCtrl4 & (~RASP_STREAM_LPCR_WLD)));
999 }
1000
HAL_NDSRASP_SetECMTimeStamp(MS_U32 u32RASPEng,MS_U32 u32Stamp)1001 void HAL_NDSRASP_SetECMTimeStamp(MS_U32 u32RASPEng , MS_U32 u32Stamp)
1002 {
1003 RASP_NUM_CHECK(u32RASPEng);
1004 HAL_RASP_WriteReg_DWord(u32RASPEng, REG_RASP_ECM_LPCR1_BUF_L, u32Stamp);
1005
1006 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_EcmLPCR1Buf , u32Stamp);
1007
1008 MS_U16 HWCtrl3;
1009
1010 HWCtrl3 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL3);
1011 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 | RASP_ECM2MIU_LPCR_WT));
1012 MsOS_DelayTaskUs(10);
1013 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HWCtrl3 & (~RASP_ECM2MIU_LPCR_WT)));
1014 }
1015
HAL_NDSRASP_SetPayloadTimeStamp(MS_U32 u32RASPEng,MS_U32 u32Stamp)1016 void HAL_NDSRASP_SetPayloadTimeStamp(MS_U32 u32RASPEng , MS_U32 u32Stamp)
1017 {
1018 RASP_NUM_CHECK(u32RASPEng);
1019 #if 1
1020 MS_U16 HW_CTRL3;
1021 HAL_RASP_WriteReg_DWord(u32RASPEng, REG_RASP_PAY_LPCR1_BUF_L, u32Stamp);
1022
1023 HW_CTRL3 = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL3);
1024
1025 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HW_CTRL3 | RASP_PAYLD2MIU_LPCR_WT) );
1026 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL3, (HW_CTRL3 & (~RASP_PAYLD2MIU_LPCR_WT)) );
1027
1028 #else
1029 _HAL_REG32_W(&_RASPReg[u32RASPEng][0].RASP_PayLPCR1Buf , u32Stamp);
1030
1031 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3,
1032 SET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3) , RASP_PAYLD2MIU_LPCR_WT));
1033 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3,
1034 RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL3) , RASP_PAYLD2MIU_LPCR_WT));
1035 #endif
1036 }
1037
1038
1039
HAL_NDSRASP_SetWaterMark(MS_U32 u32RASPEng)1040 void HAL_NDSRASP_SetWaterMark(MS_U32 u32RASPEng)
1041 {
1042 }
1043
1044 #if 0 //EEGII: REFINED API ==>HAL_NDSRASP_EVENT_SetThreshold, HAL_NDSRASP_SetTime_Timeout
1045 void HAL_NDSRASP_SetTimerWaterMark(MS_U32 u32RASPEng, MS_U16 u16TimerWaterMask)
1046 {
1047 MS_U16 HWCtrl2;
1048
1049 HWCtrl2 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL2);
1050 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, (HWCtrl2 | (u16TimerWaterMask<<RASP_INT_TIMER_SHIFT)) );
1051 }
1052
1053 void HAL_NDSRASP_SetEventWaterMark(MS_U32 u32RASPEng, MS_U16 u16EventWaterMask)
1054 {
1055 MS_U16 HWCtrl2;
1056
1057 HWCtrl2 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL2);
1058 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, (HWCtrl2 | (u16EventWaterMask<<RASP_INT_EVENT_SHIFT)) );
1059 }
1060 #endif
1061
HAL_NDSRASP_SetTSIF(MS_U32 u32RASPEng,MS_BOOL bPara,MS_BOOL bExtSync,MS_BOOL bDataSWP)1062 void HAL_NDSRASP_SetTSIF(MS_U32 u32RASPEng , MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP)
1063 {
1064 RASP_NUM_CHECK(u32RASPEng);
1065 MS_U16 HWCtrl0,HWCtrl1;
1066
1067 HALRASP_DBG(RASP_DBGLV_DEBUG, "RASPEng = 0x%x, bPara = %d, bExtSync = %d, bDataSWP = %d\n",u32RASPEng, bPara, bExtSync, bDataSWP);
1068
1069 HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL0);
1070 HWCtrl1 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL1);
1071
1072 if (bPara)
1073 {
1074 HWCtrl0 |= RASP_TSIF2_PARA_SEL;
1075 }
1076 else
1077 {
1078 HWCtrl0 &= (~RASP_TSIF2_PARA_SEL);
1079 HWCtrl0 |= (RASP_RISING_SYNC_DETECT | RASP_FALLING_VALID_DETECT);
1080
1081 HWCtrl1 |= 0x0400;
1082 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, HWCtrl1);
1083
1084 MS_U16 PktSet;
1085 PktSet = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_PKT_SET);
1086 PktSet |= 0x0080;
1087 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_PKT_SET, PktSet);
1088 }
1089
1090 if (bExtSync)
1091 {
1092 HWCtrl0 |= RASP_TSIF2_EXT_SYNC;
1093 }
1094 else
1095 {
1096 HWCtrl0 &= (~RASP_TSIF2_EXT_SYNC);
1097 }
1098
1099 if (bDataSWP)
1100 {
1101 HWCtrl0 |= RASP_TSIF2_DATA_SWP;
1102 }
1103 else
1104 {
1105 HWCtrl0 &= (~RASP_TSIF2_DATA_SWP);
1106 }
1107
1108 HALRASP_DBG(RASP_DBGLV_DEBUG, "RASPEng = 0x%x, HWCtrl0 = %x, HWCtrl1 = %x\n",u32RASPEng, HWCtrl0, HWCtrl1);
1109
1110 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, HWCtrl0);
1111 }
1112
HAL_NDSRASP_GetTSIF(MS_U32 u32RASPEng,MS_BOOL * pbPara,MS_BOOL * pbExtSync,MS_BOOL * pbDataSWP)1113 void HAL_NDSRASP_GetTSIF(MS_U32 u32RASPEng , MS_BOOL* pbPara, MS_BOOL* pbExtSync, MS_BOOL* pbDataSWP)
1114 {
1115 RASP_NUM_CHECK(u32RASPEng);
1116 MS_U16 HWCtrl0;
1117
1118 HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL0);
1119
1120 *pbPara = (HWCtrl0 & RASP_TSIF2_PARA_SEL)? 1:0;
1121
1122 *pbExtSync = (HWCtrl0 & RASP_TSIF2_EXT_SYNC)? 1:0;
1123
1124 *pbDataSWP = (HWCtrl0 & RASP_TSIF2_DATA_SWP)? 1:0;
1125 }
1126
1127 #define REG16(addr) (*(volatile unsigned short *) (addr)) //temporary hardcode
1128
1129 //bank 0x101E
1130 #define CHIP_REG(addr) (*((volatile MS_U16*)(_gChipTp_Addr + ((addr)<<2))))
1131
1132 //0x100A
1133 #define CLKGEN2_REG(addr) (*((volatile MS_U16*)(_gClkGen2_Addr + ((addr)<<2))))
1134
1135 //0x100B
1136 #define CLKGEN0_REG(addr) (*((volatile MS_U16*)(_gClkGen_Addr + ((addr)<<2))))
1137
1138
1139
HAL_NDSRASP_Livein_Config(MS_U32 rasp_eng,RASP_LIVEIN_SRC_e InputSrc)1140 MS_BOOL HAL_NDSRASP_Livein_Config(MS_U32 rasp_eng, RASP_LIVEIN_SRC_e InputSrc)
1141 {
1142 MS_U16 u16Reg;
1143
1144 HALRASP_DBG(RASP_DBGLV_DEBUG,"InputSrc = %d\n",InputSrc);
1145 //pad set to TS0
1146 u16Reg = CHIP_REG(0x39);
1147 u16Reg &= ~(0xf<<(rasp_eng*4));
1148 u16Reg |= (InputSrc<<(rasp_eng*4));
1149 CHIP_REG(0x39) = u16Reg;
1150
1151
1152 u16Reg = CLKGEN2_REG(0x02+rasp_eng);
1153 u16Reg &= (~0x001f);
1154 u16Reg |= (InputSrc<<2);
1155 CLKGEN2_REG(0x02+rasp_eng) = u16Reg;
1156
1157
1158 u16Reg = CLKGEN0_REG(0x29);
1159 u16Reg &= ~(0x3F00);
1160 u16Reg |= (InputSrc<<10);
1161 CLKGEN0_REG(0x26) = u16Reg;
1162
1163 HALRASP_DBG(RASP_DBGLV_DEBUG, "RASPEng = 0x%x, CHIP_REG(0x39) = %x, CLKGEN2_REG = %x\n",rasp_eng, CHIP_REG(0x39), CLKGEN2_REG(0x02+rasp_eng));
1164
1165 return TRUE;
1166 }
1167
HAL_NDSRASP_SetFileinStart(MS_U32 u32RASPEng,MS_BOOL bEn)1168 void HAL_NDSRASP_SetFileinStart(MS_U32 u32RASPEng , MS_BOOL bEn)
1169 {
1170 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x \n",u32RASPEng);
1171 RASP_NUM_CHECK(u32RASPEng);
1172 //jamietest, FileIn Enable is always 0 on Keres
1173
1174 MS_U16 HWCtrl0;
1175
1176 HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL0);
1177 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 & (~RASP_FILEIN_EN)) );
1178
1179 if (bEn)
1180 {
1181 //Set RASP buffer full level to 0b100
1182 HAL_NDSRASP_SetBufferBlockLevel(u32RASPEng, 0x4);
1183 }
1184 else
1185 {
1186 HAL_NDSRASP_SetBufferBlockLevel(u32RASPEng, 0x0);
1187 }
1188 }
1189
HAL_NDSRASP_GetFileinStart(MS_U32 u32RASPEng)1190 MS_BOOL HAL_NDSRASP_GetFileinStart(MS_U32 u32RASPEng)
1191 {
1192 RASP_NUM_CHECK_RET(u32RASPEng);
1193 if(HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL0) & RASP_FILEIN_EN)
1194 return TRUE;
1195 else
1196 return FALSE;
1197 }
1198
HAL_NDSRASP_INT_GetHW(MS_U32 u32RASPEng)1199 MS_U16 HAL_NDSRASP_INT_GetHW(MS_U32 u32RASPEng)
1200 {
1201 RASP_NUM_CHECK_RET(u32RASPEng);
1202 return HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_INT_STATUS);
1203 }
1204
HAL_NDSRASP_INT_ClrHW(MS_U32 u32RASPEng,MS_U16 u16Mask)1205 void HAL_NDSRASP_INT_ClrHW(MS_U32 u32RASPEng, MS_U16 u16Mask)
1206 {
1207 RASP_NUM_CHECK(u32RASPEng);
1208 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_INT_CLR, u16Mask);
1209 MsOS_DelayTaskUs(1);
1210 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_INT_CLR, 0x0000);
1211 }
1212
HAL_NDSRASP_INT_Enable(MS_U32 u32RASPEng,MS_U16 u16Mask)1213 void HAL_NDSRASP_INT_Enable(MS_U32 u32RASPEng, MS_U16 u16Mask)
1214 {
1215 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_INT_ENABLE, u16Mask );
1216 }
1217
HAL_NDSRASP_INT_Disable(MS_U32 u32RASPEng,MS_U16 u16Mask)1218 void HAL_NDSRASP_INT_Disable(MS_U32 u32RASPEng, MS_U16 u16Mask)
1219 {
1220 MS_U16 IntEn;
1221
1222 IntEn = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_INT_ENABLE);
1223 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_INT_ENABLE, (IntEn & (~u16Mask)) );
1224 }
1225
1226
HAL_NDSRASP_EVENT_EventWM_Enable(MS_U32 u32RASPEng,MS_BOOL enable)1227 void HAL_NDSRASP_EVENT_EventWM_Enable(MS_U32 u32RASPEng, MS_BOOL enable)
1228 {
1229 MS_U16 HWCtrl0,HWCtrl2;
1230
1231 HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL0);
1232 HWCtrl2 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL2);
1233
1234 if (enable)
1235 {
1236 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 | RASP_REC_EVENT_FIFO_EN) );
1237 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, (HWCtrl2 | RASP_INT_EVENT_EN) );
1238 }
1239 else
1240 {
1241 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 & (~RASP_REC_EVENT_FIFO_EN)) );
1242 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, (HWCtrl2 & (~RASP_INT_EVENT_EN)) );
1243 }
1244 }
1245
HAL_NDSRASP_EVENT_SetEventThreshold(MS_U32 u32RASPEng,MS_U32 u32threshold)1246 MS_BOOL HAL_NDSRASP_EVENT_SetEventThreshold(MS_U32 u32RASPEng, MS_U32 u32threshold)
1247 {
1248 MS_U16 HWCtrl2;
1249 HALRASP_DBG(RASP_DBGLV_ERR, "Rasp ID [0x%x]\n", u32RASPEng);
1250
1251 RASP_NUM_CHECK_RET(u32RASPEng);
1252
1253 if (u32threshold > 31)
1254 {
1255 HALRASP_DBG(RASP_DBGLV_ERR, "THRESHOLD Value exceeds maximum value\n");
1256 return FALSE;
1257 }
1258
1259 HWCtrl2 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL2);
1260
1261 HWCtrl2 &= (~RASP_INT_EVENT_MASK);
1262 u32threshold <<= RASP_INT_EVENT_SHIFT;
1263 u32threshold &= RASP_INT_EVENT_MASK;
1264
1265 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, HWCtrl2 | u32threshold );
1266 return TRUE;
1267
1268 }
1269
HAL_NDSRASP_EVENT_TimeWM_Enable(MS_U32 u32RASPEng,MS_BOOL enable)1270 void HAL_NDSRASP_EVENT_TimeWM_Enable(MS_U32 u32RASPEng, MS_BOOL enable)
1271 {
1272
1273 MS_U16 HWCtrl2;
1274 //MS_U16 HWCtrl0;
1275
1276 //HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL0);
1277 HWCtrl2 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL2);
1278
1279 if (enable)
1280 {
1281 //HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 | RASP_REC_EVENT_FIFO_EN) );
1282 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, (HWCtrl2 | RASP_INT_TIMER_EN) );
1283 }
1284 else
1285 {
1286 //HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 & (~RASP_REC_EVENT_FIFO_EN)) );
1287 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, (HWCtrl2 & (~RASP_INT_TIMER_EN)) );
1288 }
1289
1290 }
1291
HAL_NDSRASP_EVENT_SetTimerThreshold(MS_U32 u32RASPEng,MS_U16 u16timeout)1292 MS_BOOL HAL_NDSRASP_EVENT_SetTimerThreshold(MS_U32 u32RASPEng, MS_U16 u16timeout)
1293 {
1294 MS_U16 HWCtrl2;
1295 HALRASP_DBG(RASP_DBGLV_ERR, "Rasp ID [0x%x]\n", u32RASPEng);
1296
1297 RASP_NUM_CHECK_RET(u32RASPEng);
1298
1299 if (u16timeout > 3)
1300 {
1301 HALRASP_DBG(RASP_DBGLV_ERR, "TIMEOUT Value exceeds maximum value\n");
1302 return FALSE;
1303 }
1304
1305 HWCtrl2 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL2);
1306
1307 HWCtrl2 &= (~RASP_INT_TIMER_MASK);
1308 u16timeout <<= RASP_INT_TIMER_SHIFT;
1309 u16timeout &= RASP_INT_TIMER_MASK;
1310
1311 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL2, HWCtrl2 | u16timeout );
1312 return TRUE;
1313
1314 }
1315
HAL_NDSRASP_EVENT_GetEventNum(MS_U32 u32RASPEng)1316 MS_U16 HAL_NDSRASP_EVENT_GetEventNum(MS_U32 u32RASPEng)
1317 {
1318 MS_U16 FifoStatus = 0 ;
1319
1320 RASP_NUM_CHECK_RET(u32RASPEng);
1321 FifoStatus = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_EVENTLOG_STATUS);
1322
1323 //Current amount of stored evens in the FIFO
1324 return (FifoStatus & RASP_EVENT_FIFO_NUM_MASK);
1325 }
1326
HAL_NDSRASP_EVENT_GetEventDescriptor(MS_U32 u32RASPEng,MS_U32 * DataArray,MS_U32 ArrSize)1327 MS_BOOL HAL_NDSRASP_EVENT_GetEventDescriptor(MS_U32 u32RASPEng,MS_U32 *DataArray , MS_U32 ArrSize )
1328 {
1329 MS_U16 FifoStatus = 0;
1330
1331 FifoStatus = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_EVENTLOG_STATUS);
1332 HALRASP_DBG(RASP_DBGLV_INFO, "FifoStatus = [%x]\n", (MS_U32)FifoStatus);
1333
1334 if (FifoStatus & RASP_EVENT_FIFO_NUM_MASK)
1335 {
1336 HAL_NDSRASP_EVENT_EFrame_Read(u32RASPEng); // read event from event FIFO
1337
1338 if (ArrSize >= 5 )
1339 {
1340 // [NOTE] NDS structure for 20 bytes..
1341 DataArray[0] = HAL_RASP_ReadReg_DWord(u32RASPEng, REG_RASP_EVENT_DESCR_L);
1342 DataArray[1] = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_EVENT_PKT_PID);
1343 DataArray[2] = HAL_RASP_ReadReg_DWord(u32RASPEng, REG_RASP_EVENT_PKT_NUM_L);
1344 DataArray[3] = HAL_RASP_ReadReg_DWord(u32RASPEng, REG_RASP_EVENT_PKT_TIMER_L);
1345 DataArray[4] = HAL_RASP_ReadReg_DWord(u32RASPEng, REG_RASP_EVENT_PKT_PCR_L);
1346 //DataArray[5] = FifoStatus;
1347 return TRUE;
1348 }
1349 else
1350 {
1351 HALRASP_DBG(RASP_DBGLV_ERR, "Even descriptor size not enough.\n");
1352 return FALSE;
1353 }
1354 }
1355 else
1356 {
1357 HALRASP_DBG(RASP_DBGLV_ERR, "No event in Event FIFO.\n");
1358 return FALSE;
1359 }
1360
1361 return FALSE;
1362 }
1363
1364 //Reset Event Counter in Event FIFO
HAL_NDSRASP_EVENT_RstCounter(MS_U32 u32RASPEng)1365 MS_BOOL HAL_NDSRASP_EVENT_RstCounter(MS_U32 u32RASPEng)
1366 {
1367 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x \n",u32RASPEng);
1368
1369 MS_U32 addr;
1370
1371 addr = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_PKT_SET);
1372 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_PKT_SET, (addr & ~RASP_PKT_RESET_NUMBER));
1373 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_PKT_SET, (addr | RASP_PKT_RESET_NUMBER));
1374 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_PKT_SET, (addr & ~RASP_PKT_RESET_NUMBER));
1375
1376 return TRUE;
1377 }
1378
1379 //Reset Event Timer in Event FIFO
HAL_NDSRASP_EVENT_RstTimer(MS_U32 u32RASPEng)1380 MS_BOOL HAL_NDSRASP_EVENT_RstTimer(MS_U32 u32RASPEng)
1381 {
1382 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x \n",u32RASPEng);
1383
1384 MS_U32 addr;
1385
1386 addr = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_PKT_SET);
1387 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_PKT_SET, (addr & ~RASP_PKT_RESET_TIMER));
1388 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_PKT_SET, (addr | RASP_PKT_RESET_TIMER));
1389 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_PKT_SET, (addr & ~RASP_PKT_RESET_TIMER));
1390
1391 return TRUE;
1392 }
1393
1394 // It reads event FIFO into offset 0x50-0x0x59. Per read, event buffer level decreased.
HAL_NDSRASP_EVENT_EFrame_Read(MS_U32 u32RASPEng)1395 MS_BOOL HAL_NDSRASP_EVENT_EFrame_Read(MS_U32 u32RASPEng)
1396 {
1397 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x \n",u32RASPEng);
1398
1399 MS_U32 addr;
1400
1401 addr = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_HW_CTRL1);
1402 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (addr & ~RASP_EVENT_FIFO_READ));
1403 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (addr | RASP_EVENT_FIFO_READ));
1404 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL1, (addr & ~RASP_EVENT_FIFO_READ));
1405
1406 return TRUE;
1407 }
1408
HAL_NDSRASP_SetDataSwap(MS_U32 u32RASPEng,MS_BOOL bEn)1409 void HAL_NDSRASP_SetDataSwap(MS_U32 u32RASPEng, MS_BOOL bEn)
1410 {
1411 MS_U16 HWCtrl0;
1412
1413 HWCtrl0 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL0);
1414
1415 if(bEn)
1416 {
1417 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 | RASP_TSIF2_DATA_SWP) );
1418 }
1419 else
1420 {
1421 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL0, (HWCtrl0 & (~RASP_TSIF2_DATA_SWP)) );
1422 }
1423 }
1424
1425
1426 //TODO:what this function for
HAL_NDSRASP_SetStream_47_48(MS_U32 u32RASPEng,MS_U32 StreamSel)1427 MS_BOOL HAL_NDSRASP_SetStream_47_48(MS_U32 u32RASPEng, MS_U32 StreamSel)
1428 {
1429 if(0x47 == StreamSel)
1430 {
1431 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4,
1432 RESET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4), RASP_AUTO_STREAM_47_48)); // '0' for 47, '1' for 48
1433 return TRUE;
1434 }
1435 else if(0x48 == StreamSel)
1436 {
1437 _HAL_REG16_W(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4,
1438 SET_FLAG1(_HAL_REG16_R(&_RASPReg[u32RASPEng][0].RASP_HW_CTRL4), RASP_AUTO_STREAM_47_48));// '0' for 47, '1' for 48
1439 return TRUE;
1440 }
1441 else
1442 {
1443 return FALSE;
1444 }
1445 }
1446
HAL_NDSRASP_GetPktTimer(MS_U32 u32RASPEng)1447 MS_U32 HAL_NDSRASP_GetPktTimer(MS_U32 u32RASPEng)
1448 {
1449 RASP_NUM_CHECK_RET(u32RASPEng);
1450 return HAL_RASP_ReadReg_DWord(u32RASPEng, REG_RASP_PKT_TIMER_L);
1451 }
1452
HAL_NDSRASP_GetPktNum(MS_U32 u32RASPEng)1453 MS_U32 HAL_NDSRASP_GetPktNum(MS_U32 u32RASPEng)
1454 {
1455 RASP_NUM_CHECK_RET(u32RASPEng);
1456 return HAL_RASP_ReadReg_DWord(u32RASPEng, REG_RASP_PKT_NUM_L);
1457 }
1458
HAL_NDSRASP_GetEcmPktNum(MS_U32 u32RASPEng)1459 MS_U32 HAL_NDSRASP_GetEcmPktNum(MS_U32 u32RASPEng)
1460 {
1461 RASP_NUM_CHECK_RET(u32RASPEng);
1462 return HAL_RASP_ReadReg_DWord(u32RASPEng, REG_RASP_ECM_PACKET_NUM_L);
1463 }
1464
HAL_NDSRASP_SetBufferBlockLevel(MS_U32 u32RASPEng,MS_U32 bufBlockLv)1465 void HAL_NDSRASP_SetBufferBlockLevel(MS_U32 u32RASPEng, MS_U32 bufBlockLv)
1466 {
1467 MS_U16 HWCtrl4;
1468
1469 HWCtrl4 = HAL_RASP_ReadReg_Word(u32RASPEng,REG_RASP_HW_CTRL4);
1470
1471 HWCtrl4 &= (~RASP_TS_FF_FULL_SEL_MASK);
1472 HWCtrl4 |= (bufBlockLv<<RASP_TS_FF_FULL_SEL_SHFT);
1473
1474 HAL_RASP_WriteReg_Word(u32RASPEng, REG_RASP_HW_CTRL4, HWCtrl4 );
1475 }
1476
HAL_NDSRASP_GetEVENT_Status(MS_U32 u32RASPEng,MS_U16 * pEventLog,MS_U32 * pEventDescr)1477 MS_U32 HAL_NDSRASP_GetEVENT_Status(MS_U32 u32RASPEng, MS_U16 *pEventLog , MS_U32 *pEventDescr) // [NOTE] NDS structure for 20 bytes..
1478 {
1479 RASP_NUM_CHECK_RET(u32RASPEng);
1480 *pEventLog = HAL_RASP_ReadReg_Word(u32RASPEng, REG_RASP_EVENTLOG_STATUS);
1481 *pEventDescr = HAL_RASP_ReadReg_DWord(u32RASPEng, REG_RASP_EVENT_DESCR_L);
1482 return TRUE;
1483 }
1484
HAL_NDSRASP_FileIn_Init(MS_U32 u32RASPEng,MS_U8 u8PacketLength)1485 MS_BOOL HAL_NDSRASP_FileIn_Init(MS_U32 u32RASPEng, MS_U8 u8PacketLength)
1486 {
1487 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x \n",u32RASPEng);
1488 MS_U16 i;
1489 MS_U32 addr;
1490
1491
1492 //for(i=0 ; i<2; i++)
1493 i = u32RASPEng;
1494 {
1495 // reset
1496 HAL_RFILEIN_WriteReg_Word(i, REG_RFILEIN_RESET, REG_RFILEIN_RESET_ALL);
1497 MsOS_DelayTaskUs(10);
1498 HAL_RFILEIN_WriteReg_Word(i, REG_RFILEIN_RESET, 0x0000);
1499
1500
1501 //188 mode, Filein enable
1502 addr = HAL_RFILEIN_ReadReg_Word(i, REG_RFILEIN_CTRL_0);
1503 addr &= ~REG_RFILEIN_PKT_CHK_SIZE;
1504
1505 if (188 == u8PacketLength)
1506 {
1507 addr |= (RASP_RFILEIN_PORT_SEL_FILE|RASP_RFILEIN_ALIGN_EN|RASP_RFILEIN_INPUT_EN /*| REG_RFILEIN_PKT_CHK_SIZE_188*/); //test, moving it to different api: NDS_RASP_SetFileIn_PktSize
1508 }
1509
1510 else if (192 == u8PacketLength)
1511 {
1512 addr |= (RASP_RFILEIN_PORT_SEL_FILE|RASP_RFILEIN_ALIGN_EN|RASP_RFILEIN_INPUT_EN /*| REG_RFILEIN_PKT_CHK_SIZE_192*/);
1513 }
1514
1515 HAL_RFILEIN_WriteReg_Word(i, REG_RFILEIN_CTRL_0, addr);
1516
1517 HALRASP_DBG(RASP_DBGLV_INFO, "offset CTRL_0 [0x%x]\n", (MS_U32)HAL_RFILEIN_ReadReg_Word(i, REG_RFILEIN_CTRL_0) );
1518
1519 //auto flush
1520 HAL_RFILEIN_WriteReg_Word(i, REG_RFILEIN_CTRL_1, HAL_RFILEIN_ReadReg_Word(i,REG_RFILEIN_CTRL_1) | REG_RFILEIN_FLUSH_AUTO);
1521 }
1522
1523 // MIU Xbar
1524 //addr = 0xbf000000 + (0x161300*2 + 0x00*4);
1525 //(*((volatile MS_U16*)(addr))) = 0x0F;
1526
1527
1528 return TRUE;
1529 }
1530
1531
HAL_NDSRASP_LiveIn_Init(MS_U32 u32RASPEng,MS_U8 u8PacketLength)1532 MS_BOOL HAL_NDSRASP_LiveIn_Init(MS_U32 u32RASPEng, MS_U8 u8PacketLength)
1533 {
1534 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x \n",u32RASPEng);
1535 MS_U16 i;
1536 MS_U32 addr;
1537
1538
1539 for(i=0 ; i<2; i++)
1540 {
1541 // reset
1542 HAL_RFILEIN_WriteReg_Word(i, REG_RFILEIN_RESET, REG_RFILEIN_RESET_ALL);
1543 MsOS_DelayTaskUs(10);
1544 HAL_RFILEIN_WriteReg_Word(i, REG_RFILEIN_RESET, 0x0000);
1545
1546
1547 //188 mode, Filein disable
1548 addr = HAL_RFILEIN_ReadReg_Word(i, REG_RFILEIN_CTRL_0);
1549 addr &= ~(RASP_RFILEIN_PORT_SEL_FILE|RASP_RFILEIN_ALIGN_EN|RASP_RFILEIN_INPUT_EN /* | REG_RFILEIN_PKT_CHK_SIZE*/); //disable filein
1550
1551 #if 0
1552 if (188==u8PacketLength){
1553 addr |= REG_RFILEIN_PKT_CHK_SIZE_188; //188
1554 }
1555 else if (192==u8PacketLength){
1556 addr |= REG_RFILEIN_PKT_CHK_SIZE_192;
1557 }
1558 #endif
1559
1560 HAL_RFILEIN_WriteReg_Word(i, REG_RFILEIN_CTRL_0, addr);
1561
1562 //auto flush
1563 HAL_RFILEIN_WriteReg_Word(i, REG_RFILEIN_CTRL_1, HAL_RFILEIN_ReadReg_Word(i,REG_RFILEIN_CTRL_1) | REG_RFILEIN_FLUSH_AUTO);
1564
1565 }
1566
1567 // MIU Xbar
1568 //addr = 0xbf000000 + (0x161300*2 + 0x00*4);
1569 //(*((volatile MS_U16*)(addr))) = 0x0F;
1570
1571 return TRUE;
1572 }
1573
HAL_RASP_SetFileIn_Config(MS_U32 RaspEng,MS_U32 StartAddr,MS_U32 FileInSize)1574 MS_U32 HAL_RASP_SetFileIn_Config(MS_U32 RaspEng, MS_U32 StartAddr, MS_U32 FileInSize)
1575 {
1576 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x, StartAddr = %x, FileInSize = %x\n", RaspEng, StartAddr, FileInSize);
1577 RASP_NUM_CHECK_RET(RaspEng);
1578
1579
1580 HAL_NDSRASP_FileIn_Init(RaspEng, 188);
1581
1582 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_ADDR_L, (MS_U16) (StartAddr&0xFFFF));
1583 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_ADDR_H, (MS_U16) ((StartAddr>>16)&0xFFFF));
1584 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_SIZE_L, (MS_U16) (FileInSize&0xFFFF));
1585 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_SIZE_H, (MS_U16) ((FileInSize>>16)&0xFFFF));
1586 return TRUE;
1587 }
1588
HAL_RASP_FileIn_Start(MS_U32 RaspEng)1589 MS_U32 HAL_RASP_FileIn_Start(MS_U32 RaspEng)
1590 {
1591 HALRASP_DBG(RASP_DBGLV_INFO, "%s: RaspEng = 0x%x\n", __FUNCTION__, RaspEng);
1592 RASP_NUM_CHECK_RET(RaspEng);
1593 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_START, RASP_FILEIN_START);
1594 return TRUE;
1595 }
1596
HAL_RASP_SetFileIn_Timer(MS_U32 RaspEng,MS_U16 u16Timer)1597 MS_U32 HAL_RASP_SetFileIn_Timer(MS_U32 RaspEng, MS_U16 u16Timer)
1598 {
1599
1600 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x, u16Timer = %x\n", RaspEng,u16Timer);
1601 RASP_NUM_CHECK_RET(RaspEng);
1602
1603 /*FileIn speed. By Byte delay*/
1604 MS_U16 u16Reg;
1605 u16Reg = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CTRL_0);
1606 u16Reg |= 0x0400;
1607 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_0, u16Reg);
1608
1609 //file timer
1610 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_TIMER, u16Timer);
1611
1612 return TRUE;
1613 }
1614
1615
1616 //TODO: this API not necessary, flowset and filein_packetmode can do it
HAL_RASP_SetFileIn_PktSize(MS_U32 RaspEng,MS_U16 PktSize)1617 MS_U32 HAL_RASP_SetFileIn_PktSize(MS_U32 RaspEng, MS_U16 PktSize)
1618 {
1619 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x, PktSize = %x\n", RaspEng,PktSize);
1620 RASP_NUM_CHECK_RET(RaspEng);
1621 MS_U16 u16Reg;
1622
1623 u16Reg = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CTRL_0);
1624
1625 if(PktSize == 188)
1626 {
1627 // 188-Mode
1628 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_0, u16Reg | REG_RFILEIN_PKT_CHK_SIZE_188 ); //hard code first
1629 }
1630 else if(PktSize == 192)
1631 {
1632 // 192-Mode
1633 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_0, u16Reg | REG_RFILEIN_PKT_CHK_SIZE_192); //hard code first
1634 }
1635
1636 return TRUE;
1637 }
1638
HAL_RASP_IsFileIn_Done(MS_U32 RaspEng)1639 MS_BOOL HAL_RASP_IsFileIn_Done(MS_U32 RaspEng)
1640 {
1641 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x\n", RaspEng);
1642 RASP_NUM_CHECK_RET(RaspEng);
1643
1644 MS_U16 u16FileInStatus = 0;
1645 MS_U16 u16CMDQStatus = 0;
1646
1647 // trigger
1648 u16FileInStatus = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_START);
1649 u16FileInStatus &= 0x1;
1650
1651 u16CMDQStatus = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CMDQ_STATUS);
1652 HALRASP_DBG(RASP_DBGLV_INFO, "FileInStat[%x], CMDQStat[%x]\n", (MS_U32)u16FileInStatus, (MS_U32)u16CMDQStatus);
1653
1654 if( (u16FileInStatus == 0) && (u16CMDQStatus & RFILEIN_CMD_FIFO_EMPTY) )
1655 {
1656 return TRUE;
1657 }
1658 else
1659 {
1660 return FALSE;
1661 }
1662
1663 }
1664
HAL_RASP_FileIn_IsCMDQ_Full(MS_U32 RaspEng)1665 MS_BOOL HAL_RASP_FileIn_IsCMDQ_Full (MS_U32 RaspEng)
1666
1667 {
1668 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x\n", RaspEng);
1669 MS_U16 u16CMDQStatus = 0;
1670
1671 u16CMDQStatus = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CMDQ_STATUS);
1672 if( u16CMDQStatus & RFILEIN_CMD_FIFO_FULL )
1673 {
1674 return TRUE;
1675 }
1676 else
1677 {
1678 return FALSE;
1679 }
1680
1681 }
1682
HAL_RASP_FileIn_IsCMDQ_Empty(MS_U32 RaspEng)1683 MS_BOOL HAL_RASP_FileIn_IsCMDQ_Empty (MS_U32 RaspEng)
1684
1685 {
1686 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x\n", RaspEng);
1687 MS_U16 u16CMDQStatus = 0;
1688
1689 u16CMDQStatus = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CMDQ_STATUS);
1690 if( u16CMDQStatus & RFILEIN_CMD_FIFO_EMPTY )
1691 {
1692 return TRUE;
1693 }
1694 else
1695 {
1696 return FALSE;
1697 }
1698 }
1699
HAL_RASP_FileIn_GetCmdQueueLevel(MS_U32 RaspEng,MS_U8 * CmdQLvl)1700 MS_BOOL HAL_RASP_FileIn_GetCmdQueueLevel (MS_U32 RaspEng, MS_U8 *CmdQLvl)
1701
1702 {
1703 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x\n", RaspEng);
1704 MS_U16 u16CMDQStatus = 0;
1705
1706 u16CMDQStatus = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CMDQ_STATUS);
1707 HALRASP_DBG(RASP_DBGLV_INFO, "CMDQStatus = %x\n", (MS_U32)u16CMDQStatus);
1708
1709 u16CMDQStatus &= RFILEIN_CMD_WR_LEVEL_MASK;
1710 u16CMDQStatus >>= 8;
1711
1712 *CmdQLvl = (MS_U8) u16CMDQStatus;
1713 return TRUE;
1714 }
1715
HAL_RASP_FileIn_GetEmptyNum(MS_U32 RaspEng,MS_U8 * CmdQLvl)1716 MS_BOOL HAL_RASP_FileIn_GetEmptyNum (MS_U32 RaspEng, MS_U8 *CmdQLvl)
1717
1718 {
1719 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x\n", RaspEng);
1720 MS_U16 u16CMDQStatus = 0;
1721
1722 u16CMDQStatus = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CMDQ_STATUS);
1723 u16CMDQStatus &= RFILEIN_CMD_WR_COUNT_MASK;
1724
1725 *CmdQLvl = (MS_U8) (16 - u16CMDQStatus); //we have 16slots in CMDQ
1726 return TRUE;
1727 }
1728
1729
1730
HAL_RASP_FileIn_Flush(MS_U32 RaspEng)1731 MS_U32 HAL_RASP_FileIn_Flush(MS_U32 RaspEng)
1732 {
1733 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x\n", RaspEng);
1734 RASP_NUM_CHECK_RET(RaspEng);
1735
1736 MS_U16 u16Reg;
1737
1738 // flush data
1739 u16Reg = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CTRL_1);
1740
1741 u16Reg &= ~REG_RFILEIN_FLUSH;
1742 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, u16Reg);
1743
1744 u16Reg |= REG_RFILEIN_FLUSH;
1745 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, u16Reg);
1746
1747 u16Reg &= ~REG_RFILEIN_FLUSH;
1748 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, u16Reg);
1749
1750 return TRUE;
1751 }
1752
HAL_RASP_FileIn_BlockTimeStamp(MS_U32 RaspEng,MS_BOOL enbl)1753 MS_U32 HAL_RASP_FileIn_BlockTimeStamp(MS_U32 RaspEng, MS_BOOL enbl)
1754 {
1755 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x\n", RaspEng);
1756 RASP_NUM_CHECK_RET(RaspEng);
1757
1758 MS_U16 u16Reg, u16Reg2, u16Reg3, u16Reg4;
1759
1760 u16Reg = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CTRL_0);
1761
1762 if(enbl)
1763 {
1764 u16Reg |= RASP_RFILEIN_PKT192_EN; //enable 192, but timestamp blocked
1765 u16Reg &= ~RASP_RFILEIN_PKT192_BLK_DIS; //enable timestamp block scheme
1766
1767 // patch, 20150519
1768 u16Reg2 = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CTRL_1);
1769 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (u16Reg2|REG_RFILEIN_LPCR2_LOAD|REG_RFILEIN_TIMER_192FIX) ); //4 please remain it as set, HW patch
1770
1771 //set RST_PKT_TSTAMP to reset packet timestamp to zero, and check
1772 u16Reg2 = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_CTRL_1);
1773 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (u16Reg2 | REG_RFILEIN_RST_PKT_TSTAMP) );
1774
1775 u16Reg3 = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_STREAM_TIMESTAMP_L);
1776 u16Reg4 = HAL_RFILEIN_ReadReg_Word(RaspEng, REG_RFILEIN_STREAM_TIMESTAMP_H);
1777 if ( (u16Reg3 == 0x0) && (u16Reg4 == 0x0) )
1778 {
1779 printf("==========bank, 0x2f[0], 0x30[0]\n");
1780 //if equal to zero, reset RST_PKT_TSTAMP register
1781 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (u16Reg2 & ~REG_RFILEIN_RST_PKT_TSTAMP) );
1782 }
1783 else
1784 {
1785 printf("==========bank, 0x2f[%x], 0x30[%x], FAIL\n", (MS_U32)u16Reg3, (MS_U32)u16Reg4);
1786 }
1787 // patch ends, 20150519
1788
1789 }
1790 else
1791 {
1792 u16Reg &= ~RASP_RFILEIN_PKT192_EN; //disable 192
1793 u16Reg |= RASP_RFILEIN_PKT192_BLK_DIS; //disable timestamp block scheme
1794 }
1795 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_0, u16Reg);
1796
1797 return TRUE;
1798 }
1799
HAL_RASP_FileIn_SetPlaybackTimeStamp(MS_U32 RaspEng,MS_U32 u32Stamp)1800 MS_U32 HAL_RASP_FileIn_SetPlaybackTimeStamp(MS_U32 RaspEng , MS_U32 u32Stamp)
1801 {
1802 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x\n", RaspEng);
1803 RASP_NUM_CHECK_RET(RaspEng);
1804 MS_U16 HWCtrl4;
1805
1806 HAL_RFILEIN_WriteReg_DWord(RaspEng, REG_RFILEIN_LPCR2_BUF_L, u32Stamp);
1807 HWCtrl4 = HAL_RFILEIN_ReadReg_Word(RaspEng,REG_RFILEIN_CTRL_1);
1808
1809 //send initial value to lpcr2 timer
1810 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (HWCtrl4 | REG_RFILEIN_LPCR2_WLD) );
1811 MsOS_DelayTaskUs(10);
1812
1813 //Read lpcr2 initial timer before start
1814 HAL_RASP_FileIn_GetPlaybackTimeStamp(RaspEng);
1815
1816 //start lpcr2 timer
1817 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (HWCtrl4 & ~REG_RFILEIN_LPCR2_WLD) );
1818 MsOS_DelayTaskUs(10);
1819
1820 return TRUE;
1821 }
1822
HAL_RASP_FileIn_GetPlaybackTimeStamp(MS_U32 RaspEng)1823 MS_U32 HAL_RASP_FileIn_GetPlaybackTimeStamp(MS_U32 RaspEng)
1824 {
1825 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x\n", RaspEng);
1826 RASP_NUM_CHECK_RET(RaspEng);
1827
1828 MS_U16 u16value;
1829 MS_U32 u32TimeStamp;
1830
1831 u16value = HAL_RFILEIN_ReadReg_Word(RaspEng,REG_RFILEIN_CTRL_1);
1832
1833 //update 90k ctr for read
1834 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (u16value | REG_RFILEIN_LPCR2_LOAD));
1835
1836 //latch 90k ctr
1837 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (u16value & (~REG_RFILEIN_LPCR2_LOAD) ));
1838
1839 //get counter
1840 u32TimeStamp = HAL_RFILEIN_ReadReg_DWord(RaspEng, REG_RFILEIN_LPCR2_RD_L);
1841
1842 HALRASP_DBG(RASP_DBGLV_INFO, "u32TimeStamp = 0x%x\n", u32TimeStamp);
1843 return u32TimeStamp;
1844
1845 }
1846
1847
HAL_RASP_FileIn_Timer(MS_U32 RaspEng,MS_BOOL bEnFileinTimer,MS_U16 u16TimerValue)1848 MS_U32 HAL_RASP_FileIn_Timer(MS_U32 RaspEng, MS_BOOL bEnFileinTimer, MS_U16 u16TimerValue)
1849 {
1850 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x, TimerValue = 0x%x\n", RaspEng, (MS_U32)u16TimerValue);
1851 RASP_NUM_CHECK_RET(RaspEng);
1852
1853 MS_U16 u16value, u16value2;
1854
1855 u16value = HAL_RFILEIN_ReadReg_Word(RaspEng,REG_RFILEIN_CTRL_0);
1856
1857 if (TRUE == bEnFileinTimer)
1858 {
1859 //enable delay timer
1860 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_0, (u16value | RASP_RFILEIN_TIMER_EN));
1861
1862 //set timer value
1863 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_TIMER, u16TimerValue );
1864
1865 //patch, since Kris
1866 u16value2 = HAL_RFILEIN_ReadReg_Word(RaspEng,REG_RFILEIN_CTRL_1);
1867 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, u16value2 | REG_RFILEIN_TIMER_192FIX );
1868 }
1869 else
1870 {
1871 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_0, (u16value & ~RASP_RFILEIN_TIMER_EN));
1872 }
1873
1874 return TRUE;
1875
1876 }
1877
HAL_RASP_FileIn_Reset_TStamp(MS_U32 RaspEng,MS_BOOL bResetPktTimeStamp)1878 MS_U32 HAL_RASP_FileIn_Reset_TStamp(MS_U32 RaspEng, MS_BOOL bResetPktTimeStamp)
1879 {
1880 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x\n", RaspEng);
1881 RASP_NUM_CHECK_RET(RaspEng);
1882
1883 MS_U16 u16value;
1884
1885 u16value = HAL_RFILEIN_ReadReg_Word(RaspEng,REG_RFILEIN_CTRL_1);
1886
1887 if (TRUE == bResetPktTimeStamp)
1888 {
1889 //@ IMPORTANT: Initialize timestamp latch buffer to zero
1890 //@ IMPORTANT: In normal scenario, timestamp latch buffer is updated by Filein packet timestamp
1891
1892 //HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (u16value & ~REG_RFILEIN_RST_PKT_TSTAMP));
1893 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (u16value | REG_RFILEIN_RST_PKT_TSTAMP));
1894 //HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (u16value & ~REG_RFILEIN_RST_PKT_TSTAMP));
1895 }
1896 else
1897 {
1898 HAL_RFILEIN_WriteReg_Word(RaspEng, REG_RFILEIN_CTRL_1, (u16value & ~REG_RFILEIN_RST_PKT_TSTAMP));
1899 }
1900
1901 return TRUE;
1902
1903 }
1904
1905
1906 /**************************************************************************************************************************/
1907
1908
HAL_RASP_SetPVRDstBuf(MS_U32 RaspEng,MS_U32 u32StartAddr0,MS_U32 u32EndAddr0,MS_U32 u32StartAddr1,MS_U32 u32EndAddr1)1909 MS_U32 HAL_RASP_SetPVRDstBuf(MS_U32 RaspEng, MS_U32 u32StartAddr0, MS_U32 u32EndAddr0, MS_U32 u32StartAddr1, MS_U32 u32EndAddr1)
1910 {
1911 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x, u32StartAddr0 = %x, u32EndAddr0 = %x\n", RaspEng,u32StartAddr0,u32EndAddr0);
1912 RASP_NUM_CHECK_RET(RaspEng);
1913
1914 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_STR2MIU_HEAD1_L, MIU(u32StartAddr0));
1915 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_STR2MIU_MID1_L, MIU(u32EndAddr0));
1916 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_STR2MIU_TAIL1_L, MIU(u32EndAddr0));
1917
1918 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_STR2MIU_HEAD2_L, MIU(u32StartAddr1));
1919 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_STR2MIU_MID2_L, MIU(u32EndAddr1));
1920 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_STR2MIU_TAIL2_L, MIU(u32EndAddr1));
1921
1922 MsOS_DelayTaskUs(10);
1923 HAL_NDSRASP_Str2MIU_Reset(RaspEng);
1924 return TRUE;
1925 }
1926
HAL_RASP_SetPayloadDstBuf(MS_U32 RaspEng,MS_U32 u32StartAddr0,MS_U32 u32MidAddr0,MS_U32 u32EndAddr0,MS_U32 u32StartAddr1,MS_U32 u32MidAddr1,MS_U32 u32EndAddr1)1927 MS_U32 HAL_RASP_SetPayloadDstBuf(MS_U32 RaspEng, MS_U32 u32StartAddr0, MS_U32 u32MidAddr0, MS_U32 u32EndAddr0, MS_U32 u32StartAddr1, MS_U32 u32MidAddr1, MS_U32 u32EndAddr1)
1928 {
1929 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x, u32StartAddr0 = %x, u32EndAddr0 = %x\n",RaspEng,u32StartAddr0,u32EndAddr0);
1930 RASP_NUM_CHECK_RET(RaspEng);
1931
1932 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_PAYLOAD2MIU_HEAD1_L, MIU(u32StartAddr0));
1933 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_PAYLOAD2MIU_MID1_L, MIU(u32MidAddr0));
1934 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_PAYLOAD2MIU_TAIL1_L, MIU(u32EndAddr0));
1935
1936 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_PAYLOAD2MIU_HEAD2_L, MIU(u32StartAddr1));
1937 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_PAYLOAD2MIU_MID2_L, MIU(u32MidAddr1));
1938 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_PAYLOAD2MIU_TAIL2_L, MIU(u32EndAddr1));
1939
1940 MsOS_DelayTaskUs(10);
1941 HAL_NDSRASP_PAYLD2MIU_Reset(RaspEng);
1942 return TRUE;
1943 }
1944
HAL_RASP_SetECMDstBuf(MS_U32 RaspEng,MS_U32 u32StartAddr0,MS_U32 u32MidAddr0,MS_U32 u32EndAddr0)1945 MS_U32 HAL_RASP_SetECMDstBuf(MS_U32 RaspEng, MS_U32 u32StartAddr0, MS_U32 u32MidAddr0, MS_U32 u32EndAddr0)
1946 {
1947 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x, u32StartAddr0 = %x, u32EndAddr0 = %x\n",RaspEng,u32StartAddr0,u32EndAddr0);
1948 RASP_NUM_CHECK_RET(RaspEng);
1949
1950 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_ECM2MIU_HEAD1_L, MIU(u32StartAddr0));
1951 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_ECM2MIU_MID1_L, MIU(u32MidAddr0));
1952 HAL_RASP_WriteReg_DWord(RaspEng, REG_RASP_ECM2MIU_TAIL1_L, MIU(u32EndAddr0));
1953
1954 MsOS_DelayTaskUs(10);
1955 //HAL_NDSRASP_ECM2MIU_Reset(RaspEng);
1956 return TRUE;
1957 }
1958
1959
HAL_RASP_RecOpenPid(MS_U32 RaspEng,MS_U16 Pid,MS_U8 RaspFltId)1960 MS_U32 HAL_RASP_RecOpenPid(MS_U32 RaspEng, MS_U16 Pid, MS_U8 RaspFltId)
1961 {
1962 HALRASP_DBG(RASP_DBGLV_INFO, "RaspEng = 0x%x, Pid = %x, RaspFltId = %x\n", RaspEng,Pid,RaspFltId);
1963 RASP_NUM_CHECK_RET(RaspEng);
1964
1965 MS_U16 u16Reg;
1966
1967 // enable record....
1968 u16Reg = HAL_RASP_ReadReg_Word(RaspEng, REG_RASP_HW_CTRL1);
1969
1970 if(u16Reg & RASP_REC_PID)
1971 {
1972 //already enable...skip...
1973 }
1974 else
1975 {
1976 u16Reg |= RASP_REC_PID;
1977 HAL_RASP_WriteReg_Word(RaspEng, REG_RASP_HW_CTRL1, u16Reg);
1978 }
1979
1980 HAL_RASP_WriteReg_Word(RaspEng, REG_RASP_PIDFLT_N(RaspFltId), Pid);
1981
1982 return TRUE;
1983 }
1984
HAL_RASP_DisableRec(MS_U32 RaspEng)1985 MS_U32 HAL_RASP_DisableRec(MS_U32 RaspEng)
1986 {
1987 MS_U16 u16Reg;
1988
1989 // dsiable record....
1990 u16Reg = HAL_RASP_ReadReg_Word(RaspEng, REG_RASP_HW_CTRL1);
1991 u16Reg &= (~RASP_REC_PID);
1992 HAL_RASP_WriteReg_Word(RaspEng, REG_RASP_HW_CTRL1, u16Reg);
1993
1994 return TRUE;
1995 }
1996
1997 //ask Stephen what is the real trigger start register...
HAL_NDSRASP_SetFileinConfig(MS_U32 RaspEng,MS_BOOL bFileIn,MS_U16 BlockLevel)1998 MS_BOOL HAL_NDSRASP_SetFileinConfig(MS_U32 RaspEng, MS_BOOL bFileIn, MS_U16 BlockLevel)
1999 {
2000 HALRASP_DBG(RASP_DBGLV_INFO,"RaspEng = %x, bFileIn = %d, BlockLevel = %x\n",RaspEng, bFileIn, BlockLevel);
2001 RASP_NUM_CHECK_RET(RaspEng);
2002
2003 MS_U16 u16RegCtrl0, u16RegBlockLevel;
2004
2005 // read control 0....
2006 u16RegCtrl0 = HAL_RASP_ReadReg_Word(RaspEng, REG_RASP_HW_CTRL0);
2007 u16RegBlockLevel = HAL_RASP_ReadReg_Word(RaspEng, REG_RASP_HW_CTRL4);
2008
2009 if(bFileIn)
2010 {
2011 u16RegCtrl0 &= (~RASP_FILEIN_EN);
2012
2013 u16RegBlockLevel = (u16RegBlockLevel & ~RASP_TS_FF_FULL_SEL_MASK) | (BlockLevel<<RASP_TS_FF_FULL_SEL_SHFT);
2014 HAL_RASP_WriteReg_Word(RaspEng, REG_RASP_HW_CTRL4, u16RegBlockLevel);
2015 }
2016 else
2017 {
2018 //u16RegCtrl0 |= RASP_FILEIN_EN;
2019 u16RegCtrl0 &= (~RASP_FILEIN_EN); // always 0 on keres
2020
2021 u16RegBlockLevel = (u16RegBlockLevel & ~RASP_TS_FF_FULL_SEL_MASK);
2022 HAL_RASP_WriteReg_Word(RaspEng, REG_RASP_HW_CTRL4, u16RegBlockLevel);
2023 }
2024
2025 HAL_RASP_WriteReg_Word(RaspEng, REG_RASP_HW_CTRL0, u16RegCtrl0);
2026
2027
2028
2029 return TRUE;
2030 }
2031
HAL_RASP_Close(MS_U32 RaspEng)2032 MS_U32 HAL_RASP_Close(MS_U32 RaspEng)
2033 {
2034 HALRASP_DBG(RASP_DBGLV_INFO, "u32RASPEng = 0x%x\n", RaspEng);
2035 RASP_NUM_CHECK_RET(RaspEng);
2036
2037 MS_U16 u16RegCtrl0;
2038
2039 // read control 0....
2040 u16RegCtrl0 = HAL_RASP_ReadReg_Word(RaspEng, REG_RASP_HW_CTRL0);
2041 u16RegCtrl0 |= RASP_SW_RESET;
2042 HAL_RASP_WriteReg_Word(RaspEng, REG_RASP_HW_CTRL0, u16RegCtrl0);
2043
2044 MsOS_DelayTaskUs(10);
2045 u16RegCtrl0 &= (~RASP_SW_RESET);
2046
2047 HAL_RASP_WriteReg_Word(RaspEng, REG_RASP_HW_CTRL0, u16RegCtrl0);
2048
2049 if(RaspEng == 1)
2050 {
2051 //K2 RASP1 MIU setting
2052 _HAL_REG16_W((REG16*)_REG_RASP1_MIU, RESET_FLAG1(_HAL_REG16_R((REG16*)_REG_RASP1_MIU), _RASP1_MIU_EN));
2053 }
2054
2055 return TRUE;
2056 }
2057
HAL_NDSRASP_SetDbgLevel(MS_U32 level)2058 void HAL_NDSRASP_SetDbgLevel(MS_U32 level)
2059 {
2060 _g32RASPHalDbgLv = level;
2061 }
2062
2063
HAL_NDSRASP_SetExtendConfig(MS_U32 RaspEng,MS_U16 type,MS_U16 extendbytes,MS_U16 syncbyte)2064 MS_U32 HAL_NDSRASP_SetExtendConfig(MS_U32 RaspEng, MS_U16 type, MS_U16 extendbytes, MS_U16 syncbyte)
2065 {
2066 MS_U16 Reg;
2067
2068 Reg = 0x204;
2069 Reg = (Reg&(~0x1f0)) | ((extendbytes&0x1f)<<4);
2070 printf("RASP HW Config 0 is %x\n",Reg);
2071 HAL_RFILEIN_WriteReg_DWord(RaspEng, 5, 0x2C4);
2072
2073
2074 //Reg = ((extendbytes + 188)<<0x8) | (syncbyte&0xff);
2075 printf("sync byte reg is %x\n",syncbyte);
2076 HAL_RFILEIN_WriteReg_DWord(RaspEng, 0xb, (syncbyte&0xff));
2077
2078 #if 0
2079 Reg = ((extendbytes + 188) + (syncbyte<<0x8));
2080 HAL_RASP_WriteReg_Word(RaspEng, REG_RASP_CONFIG_TSIF2, Reg);
2081 #endif
2082 return TRUE;
2083 }
2084
2085 #ifdef MSOS_TYPE_LINUX_KERNEL
2086 EXPORT_SYMBOL(HAL_NDSRASP_SetPayload_MidAddr);
2087 EXPORT_SYMBOL(HAL_NDSRASP_INT_Enable);
2088 EXPORT_SYMBOL(HAL_NDSRASP_SetECM_StartAddr);
2089 EXPORT_SYMBOL(HAL_NDSRASP_SetPayload_EndAddr);
2090 EXPORT_SYMBOL(HAL_NDSRASP_EVENT_TimeWM_Enable);
2091 EXPORT_SYMBOL(HAL_NDSRASP_GetPktTimer);
2092 EXPORT_SYMBOL(HAL_NDSRASP_SetPayloadMask);
2093 EXPORT_SYMBOL(HAL_NDSRASP_SetTimerWaterMark);
2094 EXPORT_SYMBOL(HAL_NDSRASP_GetPidflt);
2095 EXPORT_SYMBOL(HAL_NDSRASP_SetECM_MidAddr);
2096 EXPORT_SYMBOL(HAL_NDSRASP_Payload_Enable);
2097 EXPORT_SYMBOL(HAL_NDSRASP_SetEventMask);
2098 EXPORT_SYMBOL(HAL_NDSRASP_SetEventWaterMark);
2099 EXPORT_SYMBOL(HAL_NDSRASP_SetPayload_StartAddr);
2100 EXPORT_SYMBOL(HAL_NDSRASP_SetCorptFlt);
2101 EXPORT_SYMBOL(HAL_NDSRASP_EVENT_EventWM_Enable);
2102 EXPORT_SYMBOL(HAL_NDSRASP_SetCorptData);
2103 EXPORT_SYMBOL(HAL_NDSRASP_SWReset);
2104 EXPORT_SYMBOL(HAL_NDSRASP_EVENT_GetEventNum);
2105 EXPORT_SYMBOL(HAL_NDSRASP_EVENT_GetEventDescriptor);
2106 EXPORT_SYMBOL(HAL_NDSRASP_ECM_Enable);
2107 EXPORT_SYMBOL(HAL_NDSRASP_INT_ClrHW);
2108 EXPORT_SYMBOL(HAL_NDSRASP_GetPktNum);
2109 EXPORT_SYMBOL(HAL_NDSRASP_GetEcmPktNum);
2110 EXPORT_SYMBOL(HAL_NDSRASP_SetECM_EndAddr);
2111 EXPORT_SYMBOL(HAL_NDSRASP_INT_GetHW);
2112 EXPORT_SYMBOL(HAL_NDSRASP_SetEcmPidflt);
2113 #endif
2114
2115
2116