1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // ("MStar Confidential Information") by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halOTV.c
97 // @brief OTV HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #include "MsCommon.h"
101 #include "regOTV.h"
102 #include "halOTV.h"
103
104 //--------------------------------------------------------------------------------------------------
105 // Driver Compiler Option
106 //--------------------------------------------------------------------------------------------------
107
108
109 //--------------------------------------------------------------------------------------------------
110 // TSP Hardware Abstraction Layer
111 //--------------------------------------------------------------------------------------------------
112 static MS_VIRT _u32RegBase = 0;
113
114 static REG_OTV* _OTVReg[OTV_ENG_NUM] = {NULL , NULL, NULL, NULL};
115 static MS_VIRT _u32OTV_PidfltBase[OTV_ENG_NUM] = {NULL , NULL, NULL, NULL};
116 static MS_VIRT _u32OTV_EventMaskBase[OTV_ENG_NUM] = {NULL , NULL, NULL, NULL};
117 //static MS_U32 _u32OTV_PayloadMaskBase[OTV_ENG_NUM] = {NULL , NULL, NULL, NULL};
118
119 // Some register has write order, for example, writing PCR_L will disable PCR counter
120 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
121 #define _HAL_OTV_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFF); \
122 (reg)->H = ((value) >> 16); } while(0)
123
124 #define _HAL_OTV_REG16_W(reg, value) (reg)->data = ((value) & 0x0000FFFF);
125
126
127 #define OTV_NUM_CHECK(idx) if( (MS_U32)idx >= (MS_U32)OTV_ENG_NUM ) \
128 { printf("[OTV][ERR] OTV Engine [%d] not exist ! \n",(unsigned int)idx); \
129 return ; }
130
131 #define OTV_NUM_CHECK_RET(idx) if( (MS_U32)idx >= (MS_U32)OTV_ENG_NUM ) \
132 { printf("[OTV][ERR] OTV Engine [%d] not exist ! \n",(unsigned int)idx); \
133 return 0; }
134
135
136 //--------------------------------------------------------------------------------------------------
137 // Forward declaration
138 //--------------------------------------------------------------------------------------------------
139
140 //--------------------------------------------------------------------------------------------------
141 // Implementation
142 //--------------------------------------------------------------------------------------------------
143 #if 0
144 static void _delay(void)
145 {
146 volatile MS_U32 i;
147 for (i = 0; i< 0xFFFF; i++);
148 }
149 #endif
_HAL_OTV_REG32_R(OTV_REG32 * reg)150 static MS_U32 _HAL_OTV_REG32_R(OTV_REG32 *reg)
151 {
152 MS_U32 value = 0;
153 value = (reg)->H << 16;
154 value |= (reg)->L;
155 return value;
156 }
157
_HAL_OTV_REG16_R(OTV_REG16 * reg)158 static MS_U16 _HAL_OTV_REG16_R(OTV_REG16 *reg)
159 {
160 MS_U16 value;
161 value = (reg)->data;
162 return value;
163 }
164
165 //--------------------------------------------------------------------------------------------------
166 // For MISC part
167 //--------------------------------------------------------------------------------------------------
HAL_OTV_SetBank(MS_VIRT u32BankAddr)168 void HAL_OTV_SetBank(MS_VIRT u32BankAddr)
169 {
170 _u32RegBase = u32BankAddr;
171
172 _OTVReg[0] = (REG_OTV*)(_u32RegBase + OTV0_REG_CTRL_BASE);
173 _u32OTV_PidfltBase[0] = _u32RegBase + OTV0_PIDFLT_BASE;
174 _u32OTV_EventMaskBase[0] = _u32RegBase + OTV0_EVENT_MASK_BASE;
175 //_u32OTV_PayloadMaskBase[0] = _u32RegBase + OTV0_BANK1_PAYLOAD_MASK_BASE;
176
177 _OTVReg[1] = (REG_OTV*)(_u32RegBase + OTV1_REG_CTRL_BASE);
178 _u32OTV_PidfltBase[1] = _u32RegBase + OTV1_PIDFLT_BASE;
179 _u32OTV_EventMaskBase[1] = _u32RegBase + OTV1_EVENT_MASK_BASE;
180 //_u32OTV_PayloadMaskBase[1] = _u32RegBase + OTV1_BANK1_PAYLOAD_MASK_BASE;
181
182 _OTVReg[2] = (REG_OTV*)(_u32RegBase + OTV2_REG_CTRL_BASE);
183 _u32OTV_PidfltBase[2] = _u32RegBase + OTV2_PIDFLT_BASE;
184 _u32OTV_EventMaskBase[2] = _u32RegBase + OTV2_EVENT_MASK_BASE;
185
186 _OTVReg[3] = (REG_OTV*)(_u32RegBase + OTV3_REG_CTRL_BASE);
187 _u32OTV_PidfltBase[3] = _u32RegBase + OTV3_PIDFLT_BASE;
188 _u32OTV_EventMaskBase[3] = _u32RegBase + OTV3_EVENT_MASK_BASE;
189
190 }
191
192 // OTV Init
193
HAL_OTV_Init(MS_U32 u32OTVEng)194 void HAL_OTV_Init(MS_U32 u32OTVEng)
195 {
196 OTV_NUM_CHECK(u32OTVEng);
197
198 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET));
199 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET));
200
201 // filter event reset
202 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_EVENT_FLT_RST));
203 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_EVENT_FLT_RST));
204 }
205
206 #if 0
207 void HAL_OTV_Exit(MS_U32 u32OTVEng)
208 {
209 OTV_NUM_CHECK(u32OTVEng);
210
211 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET));
212 }
213 #endif
214
215 // OTV Config Setting
216
217 #if 0
218
219 void HAL_OTV_FirstPktTimerBase_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
220 {
221 OTV_NUM_CHECK(u32OTVEng);
222
223 if(bEnable) // packet timer will be (orginal timer - first pkt timer)
224 {
225 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_FIRST_PKT_TIMER_BASE_EN));
226 }
227 else // OTV packet timestamp will match OTV local timstamp
228 {
229 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_FIRST_PKT_TIMER_BASE_EN));
230 }
231 }
232
233 #endif
234
235
236
HAL_OTV_PktTimerSrcFromPVR_Enable(MS_U32 u32OTVEng,MS_BOOL bEnable)237 void HAL_OTV_PktTimerSrcFromPVR_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
238 {
239 OTV_NUM_CHECK(u32OTVEng);
240
241 if(bEnable) // OTV packet timer will match PVR timstamp
242 {
243 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_TIMESTAMP_PVR_TO_OTV_EN));
244 }
245 else // OTV packet timer will match OTV local timstamp
246 {
247 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_TIMESTAMP_PVR_TO_OTV_EN));
248 }
249 }
250
251
HAL_OTV_PktNumSrcFromPktDemux_Enable(MS_U32 u32OTVEng,MS_BOOL bEnable)252 void HAL_OTV_PktNumSrcFromPktDemux_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
253 {
254 OTV_NUM_CHECK(u32OTVEng);
255
256 if(bEnable) // OTV packet number will count by pkt dmx hit, pkt_num index start from 1,2,3,...etc
257 {
258 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_SRC_SEL));
259 }
260 else // OTV packet number will count by OTV pid hit, pkt_num index start from 0,1,2,...etc
261 {
262 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_SRC_SEL));
263 }
264 }
265
266
267
268 // OTV Interrupt
269
HAL_OTV_INT_Timer_Enable(MS_U32 u32OTVEng,MS_BOOL bEnable)270 void HAL_OTV_INT_Timer_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
271 {
272 OTV_NUM_CHECK(u32OTVEng);
273
274 if(bEnable)
275 {
276 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_INT_TIMER_EN));
277 }
278 else
279 {
280 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_INT_TIMER_EN));
281 }
282 }
283
HAL_OTV_INT_Event_Enable(MS_U32 u32OTVEng,MS_BOOL bEnable)284 void HAL_OTV_INT_Event_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
285 {
286 OTV_NUM_CHECK(u32OTVEng);
287
288 if(bEnable)
289 {
290 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_INT_EVENT_EN));
291 }
292 else
293 {
294 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_INT_EVENT_EN));
295 }
296 }
297
HAL_OTV_INT_SetEventWaterLevel(MS_U32 u32OTVEng,MS_U32 u32EventWaterLevel)298 void HAL_OTV_INT_SetEventWaterLevel(MS_U32 u32OTVEng, MS_U32 u32EventWaterLevel)
299 {
300 OTV_NUM_CHECK(u32OTVEng);
301
302 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2,
303 _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2),(u32EventWaterLevel<<OTV_INT_EVENT_WATER_SHIFT)&OTV_INT_EVENT_WATER_MASK));
304 }
305
HAL_OTV_INT_SetTimerWaterLevel(MS_U32 u32OTVEng,MS_U32 u32TimerWaterLevel)306 void HAL_OTV_INT_SetTimerWaterLevel(MS_U32 u32OTVEng, MS_U32 u32TimerWaterLevel)
307 {
308 OTV_NUM_CHECK(u32OTVEng);
309
310 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2,
311 _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2),(u32TimerWaterLevel<<OTV_INT_TIME_WATER_SHIFT)&OTV_INT_TIME_WATER_MASK));
312 }
313
HAL_OTV_INT_GetEventHW(MS_U32 u32OTVEng)314 MS_BOOL HAL_OTV_INT_GetEventHW(MS_U32 u32OTVEng)
315 {
316 OTV_NUM_CHECK_RET(u32OTVEng);
317
318 MS_U16 u16IntFlag; // OTV Interrupt Flag
319
320 u16IntFlag = _HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_INT_Flag) & OTV_INT_FLAG_MASK;
321
322 switch(u32OTVEng)
323 {
324 case 0:
325 if( u16IntFlag & OTV_INT_FROM_OTV0_EVENT )
326 return TRUE;
327 else
328 return FALSE;
329 case 1:
330 if( u16IntFlag & OTV_INT_FROM_OTV1_EVENT )
331 return TRUE;
332 else
333 return FALSE;
334 case 2:
335 if( u16IntFlag & OTV_INT_FROM_OTV2_EVENT )
336 return TRUE;
337 else
338 return FALSE;
339 case 3:
340 if( u16IntFlag & OTV_INT_FROM_OTV3_EVENT )
341 return TRUE;
342 else
343 return FALSE;
344 default:
345 return FALSE;
346 }
347 }
348
HAL_OTV_INT_GetTimerHW(MS_U32 u32OTVEng)349 MS_BOOL HAL_OTV_INT_GetTimerHW(MS_U32 u32OTVEng)
350 {
351 OTV_NUM_CHECK_RET(u32OTVEng);
352
353 MS_U16 u16IntFlag; // OTV Interrupt Flag
354
355 u16IntFlag = _HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_INT_Flag) & OTV_INT_FLAG_MASK;
356
357 switch(u32OTVEng)
358 {
359 case 0:
360 if( u16IntFlag & OTV_INT_FROM_OTV0_TIMER )
361 return TRUE;
362 else
363 return FALSE;
364 case 1:
365 if( u16IntFlag & OTV_INT_FROM_OTV1_TIMER )
366 return TRUE;
367 else
368 return FALSE;
369 case 2:
370 if( u16IntFlag & OTV_INT_FROM_OTV2_TIMER )
371 return TRUE;
372 else
373 return FALSE;
374 case 3:
375 if( u16IntFlag & OTV_INT_FROM_OTV3_TIMER )
376 return TRUE;
377 else
378 return FALSE;
379 default:
380 return FALSE;
381 }
382 }
383
384
HAL_OTV_INT_ClrEventHW(MS_U32 u32OTVEng)385 void HAL_OTV_INT_ClrEventHW(MS_U32 u32OTVEng)
386 {
387 OTV_NUM_CHECK(u32OTVEng);
388
389 switch(u32OTVEng)
390 {
391 case 0:
392 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV0_EVENT));
393 break;
394 case 1:
395 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV1_EVENT));
396 break;
397 case 2:
398 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV2_EVENT));
399 break;
400 case 3:
401 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV3_EVENT));
402 break;
403 default:
404 break;
405 }
406 }
407
HAL_OTV_INT_ClrTimerHW(MS_U32 u32OTVEng)408 void HAL_OTV_INT_ClrTimerHW(MS_U32 u32OTVEng)
409 {
410 OTV_NUM_CHECK(u32OTVEng);
411
412 switch(u32OTVEng)
413 {
414 case 0:
415 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV0_TIMER));
416 break;
417 case 1:
418 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV1_TIMER));
419 break;
420 case 2:
421 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV2_TIMER));
422 break;
423 case 3:
424 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV3_TIMER));
425 break;
426 default:
427 break;
428 }
429 }
430
431
432
433 // OTV Event Queue
434
HAL_OTV_EventQ_Enable(MS_U32 u32OTVEng,MS_BOOL bEnable)435 void HAL_OTV_EventQ_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
436 {
437 OTV_NUM_CHECK(u32OTVEng);
438
439 if(bEnable)
440 {
441 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_REC_EFRAME_EN));
442 }
443 else
444 {
445 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_REC_EFRAME_EN));
446 }
447 }
448
449
HAL_OTV_EventQ_GetEventNum(MS_U32 u32OTVEng,MS_U32 * pu32EventNum)450 void HAL_OTV_EventQ_GetEventNum(MS_U32 u32OTVEng, MS_U32 *pu32EventNum)
451 {
452 OTV_NUM_CHECK(u32OTVEng);
453
454 *pu32EventNum = _HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_EventLogCtrlStatus) & OTV_EVENT_FIFO_NUM_MASK;
455 }
456
457
HAL_OTV_EventQ_PopEvent(MS_U32 u32OTVEng)458 MS_BOOL HAL_OTV_EventQ_PopEvent(MS_U32 u32OTVEng)
459 {
460 OTV_NUM_CHECK_RET(u32OTVEng);
461
462 MS_U32 u32EventNum;
463
464 HAL_OTV_EventQ_GetEventNum(u32OTVEng, &u32EventNum);
465
466 if (u32EventNum != 0)
467 {
468 // Event Queue Read
469 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1), OTV_EFRAME_RD));
470 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1), OTV_EFRAME_RD));
471 return TRUE;
472 }
473 else
474 {
475 return FALSE;
476 }
477 }
478
479
HAL_OTV_EventQ_GetEventDesciptor(MS_U32 u32OTVEng,MS_U32 * pu32EventDesciptor)480 void HAL_OTV_EventQ_GetEventDesciptor(MS_U32 u32OTVEng, MS_U32 *pu32EventDesciptor)
481 {
482 OTV_NUM_CHECK(u32OTVEng);
483 *pu32EventDesciptor = _HAL_OTV_REG32_R(&_OTVReg[u32OTVEng][0].OTV_EventDescriptor);
484 }
485
HAL_OTV_EventQ_GetEventPktNum(MS_U32 u32OTVEng,MS_U32 * pu32EventPktNum)486 void HAL_OTV_EventQ_GetEventPktNum(MS_U32 u32OTVEng, MS_U32 *pu32EventPktNum)
487 {
488 OTV_NUM_CHECK(u32OTVEng);
489 *pu32EventPktNum = _HAL_OTV_REG32_R(&_OTVReg[u32OTVEng][0].OTV_EventPktNum);
490 }
491
492
HAL_OTV_EventQ_GetEventPktTimer(MS_U32 u32OTVEng,MS_U32 * pu32EventPktTimer)493 void HAL_OTV_EventQ_GetEventPktTimer(MS_U32 u32OTVEng, MS_U32 *pu32EventPktTimer)
494 {
495 OTV_NUM_CHECK(u32OTVEng);
496 *pu32EventPktTimer = _HAL_OTV_REG32_R(&_OTVReg[u32OTVEng][0].OTV_EventPktTimer);
497 }
498
499
HAL_OTV_EventQ_GetEventPktPCR(MS_U32 u32OTVEng,MS_U32 * pu32EventPktPCR)500 void HAL_OTV_EventQ_GetEventPktPCR(MS_U32 u32OTVEng, MS_U32 *pu32EventPktPCR)
501 {
502 OTV_NUM_CHECK(u32OTVEng);
503 *pu32EventPktPCR = _HAL_OTV_REG32_R(&_OTVReg[u32OTVEng][0].OTV_EventPktPCR);
504 }
505
506
HAL_OTV_EventQ_GetEventPktPID(MS_U32 u32OTVEng,MS_U16 * pu16EventPktPID)507 void HAL_OTV_EventQ_GetEventPktPID(MS_U32 u32OTVEng, MS_U16 *pu16EventPktPID)
508 {
509 OTV_NUM_CHECK(u32OTVEng);
510 *pu16EventPktPID = _HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_EventPktPID);
511 }
512
513
514
515
516
517 #if 0
518 MS_BOOL HAL_OTV_EventQ_Pop(MS_U32 u32OTVEng,MS_U32 *DataArray, MS_U32 ArrSize) // [NOTE] NDS structure for 20 bytes..
519 {
520 OTV_NUM_CHECK_RET(u32OTVEng);
521
522 MS_U32 u32EventNum;
523
524 HAL_OTV_EventQ_GetNum(u32OTVEng, &u32EventNum);
525
526 if (u32EventNum != 0)
527 {
528 // Event Queue Read
529 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1), OTV_EFRAME_RD));
530 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1), OTV_EFRAME_RD));
531
532 if (ArrSize >= 5 )
533 {
534 DataArray[0] = _HAL_OTV_REG32_R(&(_OTVReg[u32OTVEng][0].OTV_EventDescriptor));
535 DataArray[1] = _HAL_OTV_REG32_R(&(_OTVReg[u32OTVEng][0].OTV_EventPktNum));
536 DataArray[2] = _HAL_OTV_REG32_R(&(_OTVReg[u32OTVEng][0].OTV_EventPktTimer));
537 DataArray[3] = _HAL_OTV_REG32_R(&(_OTVReg[u32OTVEng][0].OTV_EventPktPCR));
538 DataArray[4] = (MS_U32)_HAL_OTV_REG16_R(&(_OTVReg[u32OTVEng][0].OTV_EventPktPID));
539 return TRUE;
540 }
541 else
542 {
543 // array size not enough
544 return FALSE;
545 }
546 }
547 else
548 {
549 return FALSE;
550 }
551 }
552 #endif
553
554
555 // OTV Get Current Packet Number/TimeStamp
556
HAL_OTV_GetCurPktTimer(MS_U32 u32OTVEng,MS_U32 * pu32PktTimer)557 void HAL_OTV_GetCurPktTimer(MS_U32 u32OTVEng, MS_U32 *pu32PktTimer)
558 {
559 OTV_NUM_CHECK(u32OTVEng);
560
561 // latch bit:pkt num/timer will be locked for reading if this bit is set to 1
562 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_TIMER_LOCK));
563
564 *pu32PktTimer = _HAL_OTV_REG32_R(&_OTVReg[u32OTVEng][0].OTV_PktTimer);
565
566 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_TIMER_LOCK));
567
568 }
569
HAL_OTV_GetCurPktNum(MS_U32 u32OTVEng,MS_U32 * pu32PktNum)570 void HAL_OTV_GetCurPktNum(MS_U32 u32OTVEng, MS_U32 *pu32PktNum)
571 {
572 OTV_NUM_CHECK(u32OTVEng);
573
574 // latch bit:pkt num/timer will be locked for reading if this bit is set to 1
575 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_TIMER_LOCK));
576
577 *pu32PktNum = _HAL_OTV_REG32_R(&(_OTVReg[u32OTVEng][0].OTV_PktNum));
578
579 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_TIMER_LOCK));
580 }
581
582 // OTV Pid Filter
583
HAL_OTV_SetFltPid(MS_U32 u32OTVEng,MS_U32 u32FltId,MS_U16 u16Pid)584 void HAL_OTV_SetFltPid(MS_U32 u32OTVEng , MS_U32 u32FltId , MS_U16 u16Pid)
585 {
586 OTV_NUM_CHECK(u32OTVEng);
587
588 MS_VIRT _u32PidFltReg = _u32OTV_PidfltBase[u32OTVEng] + (u32FltId*0x04);
589 _HAL_OTV_REG16_W((OTV_REG16 *)_u32PidFltReg, u16Pid);
590 }
591
HAL_OTV_GetFltPid(MS_U32 u32OTVEng,MS_U32 u32FltId,MS_U16 * pu16Pid)592 void HAL_OTV_GetFltPid(MS_U32 u32OTVEng , MS_U32 u32FltId , MS_U16 *pu16Pid)
593 {
594 OTV_NUM_CHECK(u32OTVEng);
595
596 MS_VIRT _u32PidfltReg = _u32OTV_PidfltBase[u32OTVEng] + (u32FltId*0x04);
597 *pu16Pid = _HAL_OTV_REG16_R((OTV_REG16 *)_u32PidfltReg);
598 }
599
600
HAL_OTV_SetFltEvent(MS_U32 u32OTVEng,MS_U32 u32FltId,MS_U32 u32FltEvent)601 void HAL_OTV_SetFltEvent(MS_U32 u32OTVEng , MS_U32 u32FltId, MS_U32 u32FltEvent)
602 {
603 OTV_NUM_CHECK(u32OTVEng);
604 MS_VIRT _u32EventMaskReg = _u32OTV_EventMaskBase[u32OTVEng] + (u32FltId*0x08);
605 _HAL_OTV_REG32_W((OTV_REG32 *)_u32EventMaskReg, u32FltEvent);
606
607 }
608
HAL_OTV_GetFltEvent(MS_U32 u32OTVEng,MS_U32 u32FltId,MS_U32 * pu32FltEvent)609 void HAL_OTV_GetFltEvent(MS_U32 u32OTVEng , MS_U32 u32FltId, MS_U32 *pu32FltEvent)
610 {
611 OTV_NUM_CHECK(u32OTVEng);
612 MS_VIRT _u32EventMaskReg = _u32OTV_EventMaskBase[u32OTVEng] + (u32FltId*0x08);
613 *pu32FltEvent = _HAL_OTV_REG32_R((OTV_REG32 *)_u32EventMaskReg) & OTV_EVENT_MASK ;
614
615 }
616
HAL_OTV_RstFltEvent(MS_U32 u32OTVEng)617 void HAL_OTV_RstFltEvent(MS_U32 u32OTVEng)
618 {
619 OTV_NUM_CHECK(u32OTVEng);
620 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_EVENT_FLT_RST));
621 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_EVENT_FLT_RST));
622 }
623