63 static  MS_VIRT               _u32RegBase = 0;  variable
598     _u32RegBase = u32BankAddr;  in HAL_CIPHER_SetBank()
599     _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);  in HAL_CIPHER_SetBank()
1178     MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR);  //MIU CrossBar Bank 0x1613  in HAL_CIPHER_DMA_Start()
1179     REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf);  //enable MIU crossbar  in HAL_CIPHER_DMA_Start()
1342     MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR);  //MIU CrossBar Bank 0x1613  in HAL_CIPHER_OTPHash_Start()
1343     REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf);  //enable MIU crossbar  in HAL_CIPHER_OTPHash_Start()
1578     MS_U16 u16MaskTmp = REG16_R(_u32RegBase + REG_HST0_FIQ_MASK_63_48);  in HAL_CIPHER_IntEnable()
1580     REG16_W(_u32RegBase + REG_HST0_FIQ_MASK_63_48, u16MaskTmp);  in HAL_CIPHER_IntEnable()
1585 …REG16_W(_u32RegBase + REG_HST0_FIQ_STATUS_63_48, REG_HTS0_FIQ_CRYPTODMA); //set 1 to clear interru…  in HAL_CIPHER_IntClear()
1986         MS_U32 MIUCrossBar = REG32_R(_u32RegBase + REG_MIU_CROSSBAR);  //MIU CrossBar Bank 0x1613  in HAL_CIPHER_Hash_Start()
1987         REG32_W(_u32RegBase + REG_MIU_CROSSBAR, MIUCrossBar | 0xf);  //enable MIU crossbar  in HAL_CIPHER_Hash_Start()
2487                 MS_U32 u32Tmp=REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU);  in HAL_CIPHER_Misc_Random()
2489                 REG32_W(_u32RegBase+REG_RNG_TRNG_SCPU, u32Tmp);  in HAL_CIPHER_Misc_Random()
2491             while( !(REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) );  in HAL_CIPHER_Misc_Random()
2493 …while( (u16TRN = (REG32_R(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN…  in HAL_CIPHER_Misc_Random()
2516                 MS_U32 u32Tmp=REG32_R(_u32RegBase+REG_RNG_TRNG_ACPU);  in HAL_CIPHER_Misc_Random()
2518                 REG32_W(_u32RegBase+REG_RNG_TRNG_ACPU, u32Tmp);  in HAL_CIPHER_Misc_Random()
2520             while( !(REG32_R(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_VALID_ACPU_MASK) );  in HAL_CIPHER_Misc_Random()
2522 …while( (u16TRN = (REG32_R(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_OUT_ACPU_MASK))==u16PreTRN…  in HAL_CIPHER_Misc_Random()