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77 //<MStar Software>
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halAESDMA.c
97 // @brief AESDMA HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100
101 #include "MsCommon.h"
102 #include "regAESDMA.h"
103 #include "halAESDMA.h"
104 #include "halCHIP.h"
105
106
107 //--------------------------------------------------------------------------------------------------
108 // Driver Compiler Option
109 //--------------------------------------------------------------------------------------------------
110
111 //--------------------------------------------------------------------------------------------------
112 // TSP Hardware Abstraction Layer
113 //--------------------------------------------------------------------------------------------------
114 static MS_VIRT _u32RegBase = NULL;
115 static MS_VIRT _u32PmRegBase = NULL;
116 static MS_U32 SECUREBASECtrl_Buffer;
117 static REG_AESDMACtrl *_AESDMACtrl = (REG_AESDMACtrl*)REG_AESDMACTRL_BASE;
118 static REG_SHARNGCtrl *_SHARNGCtrl = (REG_SHARNGCtrl*)REG_SHARNGCTRL_BASE;
119 static REG_AESDMAClk *_AESDMAClk = (REG_AESDMAClk*)REG_AESDMACLK_BASE;
120 static REG_AESDMAMbx *_AESDMAMbx = (REG_AESDMAMbx*)REG_AESDMAMBX_BASE;
121 static REG_PARSERCtrl *_PARSERCtrl = (REG_PARSERCtrl*)REG_PARSERCTRL_BASE;
122 static REG_CIPHERCtrl *_CIPHERCtrl = (REG_CIPHERCtrl*)REG_CIPHERCTRL_BASE;
123 static REG_DMASECURECtrl *_DMASECURECtrl = (REG_DMASECURECtrl*)REG_DMASECURE_BASE;
124 static REG_SECUREBASECtrl *_SECUREBASECtrl = (REG_SECUREBASECtrl*)REG_DMASECURE_CTRL_BASE;
125 static REG_AESDMACtrlEx *_AESDMACtrlEx = (REG_AESDMACtrlEx*)REG_AESDMAEXT_BASE;
126 static REG_TZPCCtrl *_TZPCCtrl = (REG_TZPCCtrl*)REG_TZPC_NONPM_BASE;
127 static REG_HDCP22Data *_HDCP22Data = (REG_HDCP22Data*)REG_HDCP22_BASE;
128 static REG_HDCP22SEKCtrl *_HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)REG_HDCP22_SEK;
129 static REG_HDCP14SEKCtrl *_HDCP14SekCtrl = (REG_HDCP14SEKCtrl*)REG_HDCP14_BASE;
130 static REG_ANAMISCBASECtrl *_ANAMISCCtrl = (REG_ANAMISCBASECtrl*)REG_ANA_MISC_BASE;
131 static REG_AES_DSCMB6Ctrl *_AESDSCMB6Ctrl = (REG_AES_DSCMB6Ctrl*)REG_AES_DSCMB6_BASE;
132 static REG_AES_DSCMB7Ctrl *_AESDSCMB7Ctrl = (REG_AES_DSCMB7Ctrl*)REG_AES_DSCMB7_BASE;
133
134 #define REG32_W(reg, value) do { \
135 (reg)->H = ((value) >> 16); \
136 (reg)->L = ((value) & 0x0000FFFF); \
137 } while(0)
138
139 //--------------------------------------------------------------------------------------------------
140 // Macro of bit operations
141 //--------------------------------------------------------------------------------------------------
142
_AESDMA_REG32_R(REG32 * reg)143 MS_U32 _AESDMA_REG32_R(REG32 *reg)
144 {
145 MS_U32 value;
146
147 value = (reg)->H << 16;
148 value |= (reg)->L;
149
150 return value;
151 }
152
153 //--------------------------------------------------------------------------------------------------
154 // Inline Function
155 //--------------------------------------------------------------------------------------------------
HAL_AESDMA_SetBank(MS_VIRT u32NonPmBankAddr,MS_VIRT u32PmBankAddr)156 void HAL_AESDMA_SetBank(MS_VIRT u32NonPmBankAddr, MS_VIRT u32PmBankAddr)
157 {
158 _u32RegBase = u32NonPmBankAddr;
159 _u32PmRegBase = u32PmBankAddr;
160 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE);
161 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE);
162 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE);
163 _AESDMAMbx = (REG_AESDMAMbx*)(_u32PmRegBase + REG_AESDMAMBX_BASE);
164 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE);
165 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);
166 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE);
167 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE);
168 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE);
169 _TZPCCtrl = (REG_TZPCCtrl*)(_u32RegBase + REG_TZPC_NONPM_BASE);
170 _HDCP22Data = (REG_HDCP22Data*)(_u32RegBase + REG_HDCP22_BASE);
171 _HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)(_u32RegBase + REG_HDCP22_SEK);
172 _HDCP14SekCtrl = (REG_HDCP14SEKCtrl*)(_u32RegBase + REG_HDCP14_BASE);
173 _ANAMISCCtrl = (REG_ANAMISCBASECtrl*)(_u32RegBase + REG_ANA_MISC_BASE);
174 _AESDSCMB6Ctrl = (REG_AES_DSCMB6Ctrl*)(_u32RegBase + REG_AES_DSCMB6_BASE);
175 _AESDSCMB7Ctrl = (REG_AES_DSCMB7Ctrl*)(_u32RegBase + REG_AES_DSCMB7_BASE);
176 }
177
AESDMA_GetMIU1Base(void)178 MS_PHY AESDMA_GetMIU1Base(void)
179 {
180 return HAL_MIU1_BASE;
181 }
182
AESDMA_GetMIU2Base(void)183 MS_PHY AESDMA_GetMIU2Base(void)
184 {
185 //not support
186 return FALSE;
187 }
188
AESDMA_Reset(void)189 void AESDMA_Reset(void)
190 {
191 MS_VIRT Reg_AESDMA;
192 MS_U32 i = 0;
193 Reg_AESDMA = (MS_VIRT)(&_AESDMACtrl[0].Dma_Ctrl);
194
195 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
196 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST)); // sw rst
197 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RST));
198
199 // reset all AESdma register
200 for (i = 0 ; i < 19 ; i++)
201 {
202 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
203 }
204 // reset secure_dma3_ctrl register
205 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
206
207 // reset hw_parser_ctrl register
208 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000);
209 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
210 }
211
AESDMA_Set_CipherKey(MS_U32 * cipherkey)212 void AESDMA_Set_CipherKey(MS_U32 *cipherkey)
213 {
214 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
215 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
216 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
217 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
218 }
219
AESDMA_Set_InitVector(MS_U32 * pInitVector)220 void AESDMA_Set_InitVector(MS_U32 *pInitVector)
221 {
222 REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_L), pInitVector[0]);
223 REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_H), pInitVector[1]);
224 REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_L), pInitVector[2]);
225 REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_H), pInitVector[3]);
226 }
227
AESDMA_Sel_Key(MS_BOOL keysel)228 void AESDMA_Sel_Key(MS_BOOL keysel)
229 {
230 }
231
AESDMA_Sel_SecureKey(void)232 void AESDMA_Sel_SecureKey(void)
233 {
234 MS_U32 u32Ctrl = _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2);
235 u32Ctrl |= AESDMA_USE_SECRET_KEY;
236 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), u32Ctrl);
237 }
238
AESDMA_Set_FileinDesc(MS_PHY FileinAddr,MS_PHY FileinNum)239 void AESDMA_Set_FileinDesc(MS_PHY FileinAddr , MS_PHY FileinNum)
240 {
241 REG32_W((&_AESDMACtrl[0].Dma_Filein_Addr), FileinAddr);
242 REG32_W((&_AESDMACtrl[0].Dma_Filein_Num), FileinNum);
243 }
244
AESDMA_Set_FileoutDesc(MS_PHY FileoutSAddr,MS_PHY FileoutEAddr)245 void AESDMA_Set_FileoutDesc(MS_PHY FileoutSAddr , MS_PHY FileoutEAddr)
246 {
247 REG32_W((&_AESDMACtrl[0].Dma_Fileout_SAddr), FileoutSAddr);
248 REG32_W((&_AESDMACtrl[0].Dma_Fileout_EAddr), FileoutEAddr);
249 }
250
AESDMA_Start(MS_BOOL AESDMAStart)251 void AESDMA_Start(MS_BOOL AESDMAStart)
252 {
253 if (AESDMAStart)
254 {
255 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) &~ AESDMA_CTRL_FILEOUT_START &~ AESDMA_CTRL_FILEIN_START));
256 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) | AESDMA_CTRL_FILEOUT_START | AESDMA_CTRL_FILEIN_START));
257 }
258 else
259 {
260 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_FILEOUT_START|AESDMA_CTRL_FILEIN_START));
261 }
262 }
263
AESDMA_Set_PS_PTN(MS_U32 MatchPTN)264 void AESDMA_Set_PS_PTN(MS_U32 MatchPTN)
265 {
266 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern) , MatchPTN);
267 }
268
AESDMA_Set_PS_Mask(MS_U32 MatchMask)269 void AESDMA_Set_PS_Mask(MS_U32 MatchMask)
270 {
271 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern_Mask) , MatchMask);
272 }
273
AESDMA_Set_PS_ENG(MS_BOOL PSin_en,MS_BOOL PSout_en)274 void AESDMA_Set_PS_ENG(MS_BOOL PSin_en, MS_BOOL PSout_en)
275 {
276 MS_U32 u32PSin, u32PSout;
277
278 u32PSin = AESDMA_ENG_PS_IN_EN & (PSin_en<<20);
279 u32PSout = AESDMA_ENG_PS_OUT_EN & (PSout_en<<21);
280
281 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(u32PSin|u32PSout));
282 }
283
AESDMA_Get_PS_MatchedBytecnt(void)284 MS_U32 AESDMA_Get_PS_MatchedBytecnt(void)
285 {
286 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Btyecnt);
287 }
288
AESDMA_Get_PS_MatchedPTN(void)289 MS_U32 AESDMA_Get_PS_MatchedPTN(void)
290 {
291 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Pat);
292 }
293
AESDMA_Set_PS_Release(void)294 void AESDMA_Set_PS_Release(void)
295 {
296 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ENG_PS_RELEASE);
297 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & ~AESDMA_ENG_PS_RELEASE);
298 }
299
AESDMA_Get_AESDMA_Status(void)300 MS_U32 AESDMA_Get_AESDMA_Status(void)
301 {
302 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status);
303 }
304
AESDMA_Get_AESDMA_IsFinished(void)305 MS_U32 AESDMA_Get_AESDMA_IsFinished(void)
306 {
307 return (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status) & AESDMA_IS_FINISHED);
308 }
309
AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode,MS_BOOL Descrypt)310 void AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode, MS_BOOL Descrypt)
311 {
312 MS_U32 u32Cmd = 0;
313
314 switch (eMode)
315 {
316 case E_AESDMA_CIPHER_ECB:
317 u32Cmd |= AESDMA_ENG_AES_EN;
318 break;
319
320 case E_AESDMA_CIPHER_CTR:
321 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTR_MODE);
322 break;
323
324 case E_AESDMA_CIPHER_CBC:
325 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CBC_MODE);
326 break;
327
328 case E_AESDMA_CIPHER_DES_ECB:
329 u32Cmd |= AESDMA_ENG_DES_EN;
330 break;
331
332 case E_AESDMA_CIPHER_DES_CTR:
333 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTR_MODE);
334 break;
335
336 case E_AESDMA_CIPHER_DES_CBC:
337 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CBC_MODE);
338 break;
339
340 case E_AESDMA_CIPHER_TDES_ECB:
341 u32Cmd |= AESDMA_ENG_TDES_EN;
342 break;
343
344 case E_AESDMA_CIPHER_TDES_CTR:
345 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTR_MODE);
346 break;
347
348 case E_AESDMA_CIPHER_TDES_CBC:
349 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CBC_MODE);
350 break;
351
352 case E_AESDMA_CIPHER_CTS_CBC:
353 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_CBC_MODE);
354 break;
355
356 case E_AESDMA_CIPHER_CTS_ECB:
357 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_ECB_MODE);
358 break;
359
360 case E_AESDMA_CIPHER_DES_CTS_CBC:
361 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_CBC_MODE);
362 break;
363
364 case E_AESDMA_CIPHER_DES_CTS_ECB:
365 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_ECB_MODE);
366 break;
367
368 case E_AESDMA_CIPHER_TDES_CTS_CBC:
369 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_CBC_MODE);
370 break;
371
372 case E_AESDMA_CIPHER_TDES_CTS_ECB:
373 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_ECB_MODE);
374 break;
375 default:
376 return;
377 }
378
379 if( eMode >= E_AESDMA_CIPHER_DES_ECB )
380 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) | AESDMA_DMA_USE_TDES_EN);
381
382 u32Cmd |= AESDMA_ENG_DESCRYPT & (Descrypt<<25);
383 REG32_W((&_AESDMACtrl[0].Dma_Ctrl),(( _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & (~DmaCtrlSet)) | u32Cmd ) );
384 }
385
AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)386 MS_U32 AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)
387 {
388 MS_U32 u32Result = 1;
389
390 switch (eMode)
391 {
392 case E_AESDMA_CIPHER_ECB:
393 case E_AESDMA_CIPHER_CTR:
394 case E_AESDMA_CIPHER_CBC:
395 case E_AESDMA_CIPHER_DES_ECB:
396 case E_AESDMA_CIPHER_DES_CTR:
397 case E_AESDMA_CIPHER_DES_CBC:
398 case E_AESDMA_CIPHER_TDES_ECB:
399 case E_AESDMA_CIPHER_TDES_CTR:
400 case E_AESDMA_CIPHER_TDES_CBC:
401 case E_AESDMA_CIPHER_CTS_CBC:
402 case E_AESDMA_CIPHER_CTS_ECB:
403 case E_AESDMA_CIPHER_DES_CTS_CBC:
404 case E_AESDMA_CIPHER_DES_CTS_ECB:
405 case E_AESDMA_CIPHER_TDES_CTS_CBC:
406 case E_AESDMA_CIPHER_TDES_CTS_ECB:
407 u32Result = 0;
408 break;
409 default:
410 break;
411 }
412 return u32Result;
413
414 }
415
AESDMA_Set_MIU_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)416 void AESDMA_Set_MIU_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
417 {
418 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_R));
419 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_W));
420
421 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_R & ((MS_U32)MIU_R << 4))));
422 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_W & ((MS_U32)MIU_W << 5))));
423 }
424
AESDMA_Set_MIU2_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)425 void AESDMA_Set_MIU2_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
426 {
427 // Not support
428 }
429
AESDMA_Enable_Int(void)430 void AESDMA_Enable_Int(void)
431 {
432 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)|AESDMA_INT_EN);
433 }
434
AESDMA_Disable_Int(void)435 void AESDMA_Disable_Int(void)
436 {
437 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)&~AESDMA_INT_EN);
438 }
439
AESDMA_Clear_Int(void)440 void AESDMA_Clear_Int(void)
441 {
442 //
443 // Since ISR Clear bit for Normal and Secured bank is independently, it must be reset individually
444 //
445
446 #if AESDMS_SECURED_BANK_EN
447 //
448 // For Secured Bank
449 //
450 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)|AESDMA_ISR_CLR);
451 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)&~AESDMA_ISR_CLR);
452 #else
453 //
454 // For Normal Bank
455 //
456 REG32_W((&_AESDSCMB7Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB7Ctrl[0].Reg0001)|AESDMA_ISR_CLR);
457 REG32_W((&_AESDSCMB7Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB7Ctrl[0].Reg0001)&~AESDMA_ISR_CLR);
458 #endif //#if AESDMS_SECURED_BANK_EN
459 }
460
AESDMA_HW_Patch(void)461 void AESDMA_HW_Patch(void)
462 {
463 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ECO_FIX_LAST_BYTE);
464 //REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_CTRL_BURST_LENGTH);
465 //REG32_W((&_AESDMACtrl[0].Dma_Eng3_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Eng3_Ctrl)|AESDMA_ENG_SPEEDUP);
466 }
467
AESDMA_Enable_Clk(void)468 void AESDMA_Enable_Clk(void)
469 {
470 MS_U32 u32Val;
471
472 //1. clk_aesdma, 0x100A_19[3:0] = 0
473 u32Val = _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA);
474 u32Val &= ~AESDMA_CLK_XTAL; //Clear Clk setting.
475 u32Val |= AESDMA_CLK_172M; //Set Clk to 172M
476 u32Val &= ~AESDMA_CLK_OFF_EN;//Enable Clk
477 REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , u32Val);
478
479 #if 0
480 //
481 // Due to the security concern
482 // Set this CLK at SBOOT
483 //
484 #if defined (__aarch64__)
485 //Enable clk_rc: 0x1239_0x03 = 0x004F
486 #else
487 //2. clk_rc
488 u32Val = _AESDMA_REG32_R(&_TZPCCtrl[0].Reg0203);
489 u32Val &= 0x0000FFFF; //Clear 0x3
490 u32Val |= 0x004F0000; //0x1239_0x03 = 0x004F
491 REG32_W((&_TZPCCtrl[0].Reg0203) , u32Val);
492 #endif
493 #endif
494
495 //3. Enable Rng
496 u32Val = _AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0001);
497 u32Val |= REG_RNG_EN;
498 REG32_W((&_SECUREBASECtrl[0].Reg0001) , u32Val);
499
500 //4. 0x110C_11[9], reg_mipspll_occclk2_en, For Random number Gen, Manhattan only
501 u32Val = _AESDMA_REG32_R(&_ANAMISCCtrl[0].Reg0001);
502 u32Val |= REG_MIPSPLL_OCCCLK2_EN;
503 REG32_W((&_ANAMISCCtrl[0].Reg0001) , u32Val);
504 }
505
AESDMA_Disable_Clk(void)506 void AESDMA_Disable_Clk(void)
507 {
508 REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) | AESDMA_CLK_OFF_EN);
509 }
510
AESDMA_Rand(void)511 MS_U8 AESDMA_Rand(void)
512 {
513 MS_U8 u8RN = 0x00;
514 u8RN = (MS_U8)_AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0203)&0xFF;
515
516 return u8RN;
517 }
518
SHA_Reset(void)519 void SHA_Reset(void)
520 {
521 MS_VIRT Reg_SHARNG;
522 MS_U32 i = 0;
523 Reg_SHARNG = (MS_VIRT)(&_SHARNGCtrl[0].Sha_Ctrl);
524 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , SHARNG_CTRL_SHA_RST); // 0->1
525 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&(~SHARNG_CTRL_SHA_RST))); // 1->0
526
527 // reset all SHA & RNG register
528 for (i = 0 ; i < 7 ; i++)
529 {
530 REG32_W((REG32 *)(Reg_SHARNG+(i*8)), 0x00000000);
531 }
532 }
533
SHA_Get_Status(void)534 MS_U32 SHA_Get_Status(void)
535 {
536 return _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Status);
537 }
538
SHA_SelMode(AESDMA_SHAMode eMode)539 void SHA_SelMode(AESDMA_SHAMode eMode)
540 {
541 MS_U32 u32Cmd = 0;
542
543 switch (eMode)
544 {
545 case E_AESDMA_SHA1:
546 u32Cmd |= (SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
547 break;
548
549 case E_AESDMA_SHA256:
550 u32Cmd |= (SHARNG_CTRL_SHA_SEL_SHA256 | SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
551 break;
552
553 default:
554 return;
555 }
556
557 //Turn off speedup mode
558 //u32Cmd |= SHARNG_CTRL_SPEED_MODE_N;
559
560 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl), _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl) | u32Cmd);
561 }
562
SHA_SetAddress(MS_PHY u32Addr)563 void SHA_SetAddress(MS_PHY u32Addr)
564 {
565 REG32_W((&_SHARNGCtrl[0].Sha_Start), u32Addr);
566 }
567
SHA_SetLength(MS_U32 u32Size)568 void SHA_SetLength(MS_U32 u32Size)
569 {
570 REG32_W((&_SHARNGCtrl[0].Sha_Length), u32Size);
571 }
572
SHA_Start(MS_BOOL SHAStart)573 void SHA_Start(MS_BOOL SHAStart)
574 {
575 if(SHAStart)
576 {
577 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
578 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_FIRE_ONCE));
579 }
580 else
581 {
582 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
583 }
584 }
585
SHA_Out(MS_VIRT u32Buf)586 void SHA_Out(MS_VIRT u32Buf)
587 {
588 MS_U32 Index, u32Size, u32offset;
589 MS_U32 eMode = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&SHARNG_CTRL_SHA_SEL_SHA256;
590
591 if(eMode == SHARNG_CTRL_SHA_SEL_SHA256)
592 {
593 u32Size = DIGEST_SIZE_SHA256;
594 u32offset = 0;
595 }
596 else
597 {
598 u32Size = DIGEST_SIZE_SHA1;
599 u32offset = 3;
600 }
601
602 for( Index = 0; Index < u32Size; Index++ )
603 {
604 *((MS_U32 *)u32Buf + Index) = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Out[Index + u32offset]);
605 }
606 //Set "1" to idle state after reg_read_sha_ready = 1
607 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_CLR));
608 }
609
610
611 //-------------------------------------------------------------------------------------------------
612 /// Enable mobf one way function
613 /// @param NULL
614
615 /// @note : disable read mobf key, and could not enable read mobf key anymore
616 //-------------------------------------------------------------------------------------------------
MOBF_OneWay(void)617 void MOBF_OneWay(void)
618 {
619 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_ONEWAY_EN));
620 }
621
622 //-------------------------------------------------------------------------------------------------
623 /// Set MOBF encrypt key
624 /// @param u32WriteKey \b IN: Encrypt Key
625
626 /// @note
627 //-------------------------------------------------------------------------------------------------
MOBF_WriteKey(MS_U32 u32WriteKey)628 void MOBF_WriteKey(MS_U32 u32WriteKey)
629 {
630 REG32_W((&_SHARNGCtrl[0].MOBF_KeyW) , u32WriteKey);
631 }
632
633 //-------------------------------------------------------------------------------------------------
634 /// Set MOBF decrypt key
635 /// @param u32ReadKey \b IN: Decrypt Key
636
637 /// @note
638 //-------------------------------------------------------------------------------------------------
MOBF_ReadKey(MS_U32 u32ReadKey)639 void MOBF_ReadKey(MS_U32 u32ReadKey)
640 {
641 REG32_W((&_SHARNGCtrl[0].MOBF_KeyR) , u32ReadKey);
642 }
643
644 //-------------------------------------------------------------------------------------------------
645 /// Enable MOBF in MIU write port
646 /// @param bEnable \b IN: Enable/Disable
647
648 /// @note : MOBF Encrypt
649 //-------------------------------------------------------------------------------------------------
MOBF_WriteEnable(MS_BOOL bEnable)650 void MOBF_WriteEnable(MS_BOOL bEnable)
651 {
652 if(bEnable)
653 {
654 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
655 }
656 else
657 {
658 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
659 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_WRITE_EN));
660 }
661 }
662
663 //-------------------------------------------------------------------------------------------------
664 /// Enable MOBF in MIU read port
665 /// @param bEnable \b IN: Enable/Disable
666
667 /// @note : MOBF Decrypt
668 //-------------------------------------------------------------------------------------------------
MOBF_ReadEnable(MS_BOOL bEnable)669 void MOBF_ReadEnable(MS_BOOL bEnable)
670 {
671 if(bEnable)
672 {
673 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
674 }
675 else
676 {
677 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
678 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_READ_EN));
679 }
680 }
681
682 //-------------------------------------------------------------------------------------------------
683 /// Disable TDES
684 ///
685
686 /// @note : MOBF Decrypt
687 //-------------------------------------------------------------------------------------------------
MOBF_DisableTDES(void)688 void MOBF_DisableTDES(void)
689 {
690 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) & (~AESDMA_DMA_USE_TDES_EN));
691 }
692
AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)693 void AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)
694 {
695 MS_U32 u32Cmd = 0;
696
697 switch (eMode)
698 {
699 case E_AESDMA_PARSER_TS_PKT192:
700 u32Cmd |= (TS_MODE | PKT192_MODE);
701 break;
702
703 case E_AESDMA_PARSER_TS_PKT192_CLEAR:
704 u32Cmd |= (TS_MODE | PKT192_MODE | CLEAR_MODE);
705 break;
706
707 case E_AESDMA_PARSER_TS_PKT188:
708 u32Cmd |= (TS_MODE);
709 u32Cmd &= (~PKT192_MODE);
710 break;
711
712 case E_AESDMA_PARSER_TS_PKT188_CLEAR:
713 u32Cmd |= (TS_MODE | CLEAR_MODE);
714 u32Cmd &= (~PKT192_MODE);
715 break;
716
717 case E_AESDMA_PARSER_HDCP20_PKT192:
718 u32Cmd |= (HDCP20_MODE | PKT192_MODE);
719 break;
720
721 case E_AESDMA_PARSER_HDCP20_PKT192_CLEAR:
722 u32Cmd |= (HDCP20_MODE | PKT192_MODE | CLEAR_MODE);
723 break;
724
725 case E_AESDMA_PARSER_HDCP20_PKT188:
726 u32Cmd |= (HDCP20_MODE);
727 u32Cmd &= (~PKT192_MODE);
728 break;
729
730 case E_AESDMA_PARSER_HDCP20_PKT188_CLEAR:
731 u32Cmd |= (HDCP20_MODE | CLEAR_MODE);
732 u32Cmd &= (~PKT192_MODE);
733 break;
734
735 default:
736 return;
737 }
738
739 u32Cmd |= (AUTO_MODE | INIT_TRUST);
740 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~ParserCtrlSet)) | u32Cmd ) );
741 }
742
743
AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)744 void AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)
745 {
746 if(bEnable)
747 {
748 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
749 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (INSERT_SCRMB)) );
750 }
751 else
752 {
753 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
754 }
755 }
756
AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)757 void AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)
758 {
759 if(bEnable)
760 {
761 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
762 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (REMOVE_SCRMB)) );
763 }
764 else
765 {
766 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
767 }
768 }
769
AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)770 void AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)
771 {
772 if(bEnable)
773 {
774 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
775 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (TS_SCRMB_MASK)) );
776 }
777 else
778 {
779 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
780 }
781 }
782
AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)783 void AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)
784 {
785 if(bEnable)
786 {
787 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
788 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (BYPASS_PID)) );
789 }
790 else
791 {
792 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
793 }
794 }
795
AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)796 void AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)
797 {
798 MS_U32 u32Cmd = 0;
799
800 switch (ePattern)
801 {
802 case E_AESDMA_PARSER_SCRMB_10:
803 u32Cmd |= (SCRMB_PATTERN10);
804 break;
805
806 case E_AESDMA_PARSER_SCRMB_11:
807 u32Cmd |= (SCRMB_PATTERN11);
808 break;
809
810 default:
811 u32Cmd &= ~(SCRMB_PATTERN11);
812 break;
813 }
814
815 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~SCRMB_INITVALUE)) | u32Cmd ) );
816
817 }
818
AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)819 void AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)
820 {
821 MS_U32 u32Cmd = 0;
822
823 switch (ePattern)
824 {
825 case E_AESDMA_PARSER_SCRMB_10:
826 u32Cmd |= (SCRMB_PATTERN10_ADD);
827 break;
828
829 case E_AESDMA_PARSER_SCRMB_11:
830 u32Cmd |= (SCRMB_PATTERN11_ADD);
831 break;
832
833 default:
834 return;
835 }
836
837 REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_INITVALUE_ADD)) | u32Cmd ) );
838
839 }
840
AESDMA_Parser_Set_Pid(MS_U8 u8Index,MS_U16 u16Pid)841 void AESDMA_Parser_Set_Pid(MS_U8 u8Index, MS_U16 u16Pid)
842 {
843 if(u8Index==0)
844 {
845 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~PARSER_PID0_MASK)) | (u16Pid<<16) ) );
846 }
847 else if(u8Index==1)
848 {
849 REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~PARSER_PID1_MASK)) | u16Pid ) );
850 }
851 else
852 {
853 printf("Edison do not support other PID\n");
854 }
855 }
856
AESDMA_Parser_Query_PidCount(void)857 MS_U8 AESDMA_Parser_Query_PidCount(void)
858 {
859 return PARSER_PID_COUNT;
860 }
861
AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)862 void AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)
863 {
864 #if AESDMS_SECURED_BANK_EN
865 //
866 // Set HW Parser controlled by DSCRMB3
867 //
868 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)|AESDMA_DSCRMB3_HW_PASER_EN);
869 #else
870 //
871 // Set HW Parser controlled by DSCRMB5
872 //
873 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)&~(AESDMA_DSCRMB3_HW_PASER_EN));
874 #endif //#if AESDMS_SECURED_BANK_EN
875
876 if(bEnable)
877 {
878 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE)) );
879 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (HW_PARSER_MODE)) );
880 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (ENABLE_LG_PATCH)) );
881 }
882 else
883 {
884 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE)) );
885 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~ENABLE_LG_PATCH)) );
886 }
887
888 //make sure CC_CTRL_BY_ACPU is set 0
889 REG32_W((&_CIPHERCtrl[0].Cipher_Ctrl),( _AESDMA_REG32_R(&_CIPHERCtrl[0].Cipher_Ctrl) & (~CC_CTRL_BY_ACPU)) );
890 }
891
RSA_ClearInt(void)892 void RSA_ClearInt(void)
893 {
894 //RSA interrupt clear
895 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_INT_CLR));
896 }
897
RSA_Reset(void)898 void RSA_Reset(void)
899 {
900 //RSA Rst
901 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_RSA_RST));
902 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_RSA_RST));
903
904 //add polling RSA status before load data to SRAM
905 while (( RSA_GetStatus() & RSA_STATUS_RSA_BUSY ) != 0);
906 }
907
RSA_Ind32Ctrl(MS_U8 u8dirction)908 void RSA_Ind32Ctrl(MS_U8 u8dirction)
909 {
910 //[1] reg_ind32_direction 0: Read. 1: Write
911 if(u8dirction==1)
912 {
913 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_DIRECTION_WRITE));
914 }
915 else
916 {
917 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)&(~RSA_IND32_CTRL_DIRECTION_WRITE));
918 }
919
920 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_ADDR_AUTO_INC|RSA_IND32_CTRL_ACCESS_AUTO_START));
921
922 }
923
RSA_LoadSram(MS_U32 * u32Buf,RSA_IND32Address eMode)924 void RSA_LoadSram(MS_U32 *u32Buf, RSA_IND32Address eMode)
925 {
926 MS_U32 u32Cmd = 0;
927 MS_U32 i = 0;
928 MS_U32 WData_H = 0;
929 MS_U32 WData_L = 0;
930
931 switch (eMode)
932 {
933 case E_RSA_ADDRESS_E:
934 u32Cmd |= (RSA_E_BASE_ADDR);
935 break;
936
937 case E_RSA_ADDRESS_N:
938 u32Cmd |= (RSA_N_BASE_ADDR);
939 break;
940
941 case E_RSA_ADDRESS_A:
942 u32Cmd |= (RSA_A_BASE_ADDR);
943 break;
944
945 default:
946 return;
947 }
948
949 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Cmd));
950 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
951
952 for( i = 0; i < 64; i++ )
953 {
954 if( eMode == E_RSA_ADDRESS_E )
955 {
956 WData_L = (((*(u32Buf+i))>>8)&0xFF00)|(((*(u32Buf+i))>>24)&0xFF);
957 WData_H = (((*(u32Buf+i))>>8)&0xFF)|(((*(u32Buf+i))<<8)&0xFF00);
958 }
959 else
960 {
961 WData_L = (((*(u32Buf-i))>>8)&0xFF00)|(((*(u32Buf-i))>>24)&0xFF);
962 WData_H = (((*(u32Buf-i))>>8)&0xFF)|(((*(u32Buf-i))<<8)&0xFF00);
963 }
964
965 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_WDATA_MASK_L))|(WData_L<<16)));
966 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_WData) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&(~RSA_WDATA_MASK_H))|WData_H));
967 }
968
969 }
970
RSA_SetKeyLength(MS_U32 u32keylen)971 void RSA_SetKeyLength(MS_U32 u32keylen)
972 {
973 //[13:8] n_len_e: key length
974 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_KEY_LENGTH_MASK))|(u32keylen<<8));
975 }
976
RSA_SetKeyType(MS_U8 u8hwkey,MS_U8 u8pubkey)977 void RSA_SetKeyType(MS_U8 u8hwkey, MS_U8 u8pubkey)
978 {
979 //[1] hw_key_e : 0 : software key, 1: hardware key
980 //[2] e_pub_e : 0: pvivate key, 1: public key
981 if(u8hwkey==1)
982 {
983 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_HW_KEY));
984 }
985 else
986 {
987 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_HW_KEY));
988 }
989
990 if(u8pubkey==1)
991 {
992 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_PUBLIC_KEY));
993 }
994 else
995 {
996 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_PUBLIC_KEY));
997 }
998
999 }
1000
RSA_ExponetialStart(void)1001 void RSA_ExponetialStart(void)
1002 {
1003 //RSA exp start
1004 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_EXP_START));
1005 }
1006
RSA_GetStatus(void)1007 MS_U32 RSA_GetStatus(void)
1008 {
1009 return _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl) & RSA_STATUS_MASK;
1010 }
1011
RSA_FileOutStart(void)1012 void RSA_FileOutStart(void)
1013 {
1014 //RSA ind32_start
1015 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
1016 }
1017
RSA_SetFileOutAddr(MS_U32 u32offset)1018 void RSA_SetFileOutAddr(MS_U32 u32offset)
1019 {
1020 MS_PHY u32Addr = 0;
1021 u32Addr = RSA_Z_BASE_ADDR + u32offset;
1022
1023 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Addr));
1024 }
1025
RSA_FileOut(void)1026 MS_U32 RSA_FileOut(void)
1027 {
1028 MS_U32 u32out_L = 0;
1029 MS_U32 u32out_H = 0;
1030
1031 u32out_L = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&RSA_RDATA_MASK_L)>>16;
1032 u32out_H = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)&RSA_RDATA_MASK_H)<<16;
1033
1034 return (u32out_H|u32out_L);
1035 }
1036
RSA_Get_RSA_IsFinished(void)1037 MS_U32 RSA_Get_RSA_IsFinished(void)
1038 {
1039 return (RSA_GetStatus()&RSA_STATUS_RSA_BUSY);
1040 }
1041
1042 //reserved for secure protect function
1043 /*
1044 void AESDMA_Secure_SetCipherKey(MS_U32 *cipherkey)
1045 {
1046 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_L.Key_L) , cipherkey[0]);
1047 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_L.Key_H) , cipherkey[1]);
1048 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_H.Key_L) , cipherkey[2]);
1049 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_H.Key_H) , cipherkey[3]);
1050 }
1051
1052 void AESDMA_Secure_SetInitVector(MS_U32 *pInitVector)
1053 {
1054 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_L.IV_L), pInitVector[0]);
1055 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_L.IV_H), pInitVector[1]);
1056 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_H.IV_L), pInitVector[2]);
1057 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_H.IV_H), pInitVector[3]);
1058 }
1059
1060 void AESDMA_SecureProtect(MS_BOOL bEnable)
1061 {
1062 if(bEnable)
1063 {
1064 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl)|(AESDMA_SECURE_PROTECT_S));
1065 }
1066 else
1067 {
1068 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl)&(~AESDMA_SECURE_PROTECT_S));
1069 }
1070 }
1071
1072 void AESDMA_Set_FileOutEnable(MS_BOOL bEnable)
1073 {
1074 if (bEnable)
1075 {
1076 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) |AESDMA_CTRL_FILEIN_START));
1077 }
1078 else
1079 {
1080 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) &~AESDMA_CTRL_FILEIN_START));
1081 }
1082 }
1083
1084 void AESDMA_Secure_Start(MS_BOOL AESDMAStart)
1085 {
1086 if (AESDMAStart)
1087 {
1088 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) &~AESDMA_SECURE_FILEIN_START));
1089 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) | AESDMA_SECURE_FILEIN_START));
1090 }
1091 else
1092 {
1093 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) &~AESDMA_SECURE_FILEIN_START));
1094 }
1095 }
1096
1097 MS_U32 AESDMA_Get_AESDMA_SecureIsFinished(void)
1098 {
1099 return (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_status) & AESDMA_DONE_S);
1100 }
1101
1102 */
1103
1104 //-------------------------------------------------------------------------------------------------
1105 /// Get status of Secret Key in Normal bank
1106 /// @param N/A
1107 /// @note : Get Status
1108 //-------------------------------------------------------------------------------------------------
AESDMA_IsSecretKeyInNormalBank(void)1109 MS_U32 AESDMA_IsSecretKeyInNormalBank(void)
1110 {
1111 return (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl) & (SECRET_KEY_IN_NORMAL_BANK));
1112 }
1113
1114 //-------------------------------------------------------------------------------------------------
1115 /// Enable Two keys (Odd/Even) in using HW auto select key.
1116 /// @param bEnable \b IN: Enable/Disable
1117
1118 /// @note : Hardware Parser Decrypt
1119 //-------------------------------------------------------------------------------------------------
AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)1120 void AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)
1121 {
1122 if(bEnable)
1123 {
1124 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (SCRMB_ENABLE_TWO_KEY) );
1125 }
1126 else
1127 {
1128 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_ENABLE_TWO_KEY) );
1129 }
1130 }
1131
1132 //-------------------------------------------------------------------------------------------------
1133 /// Set Odd keys in using HW auto select key.
1134 /// @param cipherkey
1135 /// @note : Hardware Parser Decrypt
1136 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherOddKey(MS_U32 * cipherkey)1137 void AESDMA_Set_CipherOddKey(MS_U32 *cipherkey)
1138 {
1139 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
1140 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
1141 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
1142 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
1143 }
1144
1145 //-------------------------------------------------------------------------------------------------
1146 /// Set Odd IVs in using HW auto select key.
1147 /// @param cipherkey
1148 /// @note : Hardware Parser Decrypt
1149 //-------------------------------------------------------------------------------------------------
AESDMA_Set_OddInitVector(MS_U32 * pInitVector)1150 void AESDMA_Set_OddInitVector(MS_U32 *pInitVector)
1151 {
1152 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_L), pInitVector[0]);
1153 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_H), pInitVector[1]);
1154 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_L), pInitVector[2]);
1155 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_H), pInitVector[3]);
1156 }
1157
1158 //-------------------------------------------------------------------------------------------------
1159 /// Set Even keys in using HW auto select key.
1160 /// @param cipherkey
1161 /// @note : Hardware Parser Decrypt
1162 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherEvenKey(MS_U32 * cipherkey)1163 void AESDMA_Set_CipherEvenKey(MS_U32 *cipherkey)
1164 {
1165 AESDMA_Set_CipherKey(cipherkey);
1166 }
1167
1168 //-------------------------------------------------------------------------------------------------
1169 /// Set Even IVs in using HW auto select key.
1170 /// @param cipherkey
1171 /// @note : Hardware Parser Decrypt
1172 //-------------------------------------------------------------------------------------------------
AESDMA_Set_EvenInitVector(MS_U32 * pInitVector)1173 void AESDMA_Set_EvenInitVector(MS_U32 *pInitVector)
1174 {
1175 AESDMA_Set_InitVector(pInitVector);
1176 }
1177
1178 //-------------------------------------------------------------------------------------------------
1179 /// Set HDCP Data
1180 /// @param u8Idx \b IN: Index
1181 /// @param pu8Data \b IN: Content Keys
1182 /// @param pu8privData \b IN: RIV
1183 /// @note : Set HDCP2.2
1184 //-------------------------------------------------------------------------------------------------
HDCP_ProcessCipher(MS_U8 u8Idx,MS_U8 * pu8Data,MS_U8 * pu8privData)1185 void HDCP_ProcessCipher (MS_U8 u8Idx, MS_U8 *pu8Data, MS_U8* pu8privData)
1186 {
1187 REG_HDCP22Data *pData = NULL;
1188 REG_HDCP22SEKCtrl *pCtrl = NULL;
1189 MS_U16 offset = 0;
1190 MS_U16 BKOffset = 0;
1191
1192 MS_U32 *cipherkey = (MS_U32 *)pu8Data;
1193 MS_U32 *riv = (MS_U32 *)pu8privData;
1194
1195 offset = u8Idx * (sizeof(REG_HDCP22Data) >> 1);
1196 BKOffset = u8Idx * 0x300;
1197
1198 pData = (REG_HDCP22Data*)((MS_U16*)_HDCP22Data + offset);
1199 pCtrl = (REG_HDCP22SEKCtrl*)((MS_U16*)_HDCP22SekCtrl + BKOffset);
1200
1201 //Content Keys
1202 REG32_W((&pData[0].Hdcp22_ContentKey[0]) , cipherkey[0]);
1203 REG32_W((&pData[0].Hdcp22_ContentKey[1]) , cipherkey[1]);
1204 REG32_W((&pData[0].Hdcp22_ContentKey[2]) , cipherkey[2]);
1205 REG32_W((&pData[0].Hdcp22_ContentKey[3]) , cipherkey[3]);
1206
1207 //RIV
1208 REG32_W((&pData[0].Hdcp22_Riv[0]) , riv[0]);
1209 REG32_W((&pData[0].Hdcp22_Riv[1]) , riv[1]);
1210
1211 //Set SKE successful
1212 REG32_W((&pCtrl[0].SEK), (_AESDMA_REG32_R(&pCtrl[0].SEK) | HDCP_SEK_BIT0));
1213 }
1214
1215 //-------------------------------------------------------------------------------------------------
1216 /// Get the status of HW supports HDCP2.2
1217 /// @param N/A
1218 /// @note : Support HDCP2.2
1219 //-------------------------------------------------------------------------------------------------
HDCP_GetHdcpCipherState(MS_U8 u8Idx,MS_U8 * pu8State)1220 void HDCP_GetHdcpCipherState(MS_U8 u8Idx, MS_U8 *pu8State)
1221 {
1222 #define HDCP_SUPPORT_EN 0x00000001
1223 REG_HDCP22SEKCtrl *pCtrl = NULL;
1224 MS_U16 offset = 0;
1225 MS_U16 BKOffset = 0;
1226
1227 offset = u8Idx * (sizeof(REG_HDCP22Data) >> 1);
1228 BKOffset = u8Idx * 0x300;
1229
1230 pCtrl = (REG_HDCP22SEKCtrl*)((MS_U16*)_HDCP22SekCtrl + BKOffset);
1231
1232 *pu8State = (MS_U8)(_AESDMA_REG32_R(&pCtrl[0].SEK) & HDCP_SUPPORT_EN);
1233 }
1234
1235 //-------------------------------------------------------------------------------------------------
1236 /// Reset AESDMA
1237 /// @param N/A
1238 /// @note : Clear Registers, not to do sw reset
1239 //-------------------------------------------------------------------------------------------------
AESDMA_NormalReset(void)1240 void AESDMA_NormalReset(void)
1241 {
1242 MS_VIRT Reg_AESDMA;
1243 MS_U32 i = 0;
1244 Reg_AESDMA = (MS_VIRT)(&_AESDMACtrl[0].Dma_Ctrl);
1245
1246 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
1247
1248 // reset all AESdma register
1249 for (i = 0 ; i < 19 ; i++)
1250 {
1251 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
1252 }
1253 // reset secure_dma3_ctrl register
1254 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
1255
1256 // reset hw_parser_ctrl register
1257 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000);
1258 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
1259 }
1260
AESDMA_Set_SecureBankEnable(MS_BOOL bEnable)1261 void AESDMA_Set_SecureBankEnable (MS_BOOL bEnable)
1262 {
1263 #ifdef MSOS_TYPE_NUTTX
1264 if ( bEnable == TRUE)
1265 {
1266 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl) |(AESDMA_SECURE_PROTECT_S | AESDMA_SECURE_PROTECT_SHA_S | AESDMA_SECURE_PROTECT_RSA_S));
1267 }
1268 else
1269 {
1270 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl) &~(AESDMA_SECURE_PROTECT_S | AESDMA_SECURE_PROTECT_SHA_S | AESDMA_SECURE_PROTECT_RSA_S));
1271 }
1272 #endif
1273 }
1274
HAL_AESDMA_HDMI_GetM0(AESDMA_HDMI_INPUT_PORT enInputPortType,MS_U8 * pu8Data)1275 void HAL_AESDMA_HDMI_GetM0(AESDMA_HDMI_INPUT_PORT enInputPortType, MS_U8 *pu8Data)
1276 {
1277 MS_U16 u16bank_offset;
1278 MS_U32 m0[2];
1279 MS_U8* buf = (MS_U8*)m0;
1280 int i;
1281
1282 switch(enInputPortType)
1283 {
1284 default:
1285 case E_AESDMA_HDMI_INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200
1286 case E_AESDMA_HDMI_INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500
1287 case E_AESDMA_HDMI_INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800
1288 case E_AESDMA_HDMI_INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00
1289 }
1290
1291 // read 8 bytes
1292 for(i = 0; i < 2; ++i)
1293 {
1294 m0[i] = _AESDMA_REG32_R(&((REG_HDCP14SEKCtrl*)((MS_U16*)_HDCP14SekCtrl + u16bank_offset))[i].REG_0001);
1295 }
1296 for (i = 0; i < 8; ++i)
1297 {
1298 pu8Data[i] = buf[i];
1299 }
1300 }
1301
1302 //-------------------------------------------------------------------------------------------------
1303 /// Set Index of KSlot
1304 /// @param u32Index
1305 /// @param bEnable \b IN: TRUE: For Odd Key/FALSE: For Even Key
1306 /// @note : AESDMA AES CTR64
1307 //-------------------------------------------------------------------------------------------------
AESDMA_SetKeyIndex(MS_U32 u32Index,MS_BOOL bIsOddKey)1308 void AESDMA_SetKeyIndex (MS_U32 u32Index, MS_BOOL bIsOddKey)
1309 {
1310 }
1311
1312 //-------------------------------------------------------------------------------------------------
1313 /// Enable AES CTR64
1314 /// @param bEnable \b IN: Enable/Disable
1315 /// @note : AESDMA AES CTR64
1316 //-------------------------------------------------------------------------------------------------
AESDMA_SET_CTR64(MS_BOOL bEnable)1317 void AESDMA_SET_CTR64(MS_BOOL bEnable)
1318 {
1319 }
1320
1321 //-------------------------------------------------------------------------------------------------
1322 /// Select Efuse key
1323 /// @param u8KeyIdx \b IN: the index of efuse key
1324 /// @note : Select Efuse Key
1325 //-------------------------------------------------------------------------------------------------
AESDMA_SetSecureKeyIdx(MS_U8 u8KeyIdx)1326 void AESDMA_SetSecureKeyIdx (MS_U8 u8KeyIdx)
1327 {
1328 }
1329
AESDMA_POWER_SUSPEND(void)1330 MS_BOOL AESDMA_POWER_SUSPEND(void)
1331 {
1332 SECUREBASECtrl_Buffer = _AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0001);
1333 return TRUE;
1334 }
1335
AESDMA_POWER_RESUME(void)1336 MS_BOOL AESDMA_POWER_RESUME(void)
1337 {
1338 REG32_W((&_SECUREBASECtrl[0].Reg0001), SECUREBASECtrl_Buffer);
1339 return TRUE;
1340 }
1341