1 //<MStar Software>
2 //******************************************************************************
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halOTV.c
97 // @brief OTV HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 #include "MsCommon.h"
101 #include "regOTV.h"
102 #include "halOTV.h"
103
104 //--------------------------------------------------------------------------------------------------
105 // Driver Compiler Option
106 //--------------------------------------------------------------------------------------------------
107
108
109 //--------------------------------------------------------------------------------------------------
110 // TSP Hardware Abstraction Layer
111 //--------------------------------------------------------------------------------------------------
112 static MS_VIRT _u32RegBase = 0;
113
114 static REG_OTV* _OTVReg[OTV_ENG_NUM] = {NULL , NULL};
115 static MS_VIRT _u32OTV_PidfltBase[OTV_ENG_NUM] = {NULL , NULL};
116 static MS_VIRT _u32OTV_EventMaskBase[OTV_ENG_NUM] = {NULL , NULL};
117 //static MS_U32 _u32OTV_PayloadMaskBase[OTV_ENG_NUM] = {NULL , NULL, NULL, NULL};
118
119 // Some register has write order, for example, writing PCR_L will disable PCR counter
120 // writing PCR_M trigger nothing, writing PCR_H will enable PCR counter
121 #define _HAL_OTV_REG32_W(reg, value) do { (reg)->L = ((value) & 0x0000FFFF); \
122 (reg)->H = ((value) >> 16); } while(0)
123
124 #define _HAL_OTV_REG16_W(reg, value) (reg)->data = ((value) & 0x0000FFFF);
125
126
127 #define OTV_NUM_CHECK(idx) if( (MS_U32)idx >= (MS_U32)OTV_ENG_NUM ) \
128 { printf("[OTV][ERR] OTV Engine [%d] not exist ! \n",(unsigned int)idx); \
129 return ; }
130
131 #define OTV_NUM_CHECK_RET(idx) if( (MS_U32)idx >= (MS_U32)OTV_ENG_NUM ) \
132 { printf("[OTV][ERR] OTV Engine [%d] not exist ! \n",(unsigned int)idx); \
133 return 0; }
134
135
136 //--------------------------------------------------------------------------------------------------
137 // Forward declaration
138 //--------------------------------------------------------------------------------------------------
139
140 //--------------------------------------------------------------------------------------------------
141 // Implementation
142 //--------------------------------------------------------------------------------------------------
143 #if 0
144 static void _delay(void)
145 {
146 volatile MS_U32 i;
147 for (i = 0; i< 0xFFFF; i++);
148 }
149 #endif
_HAL_OTV_REG32_R(OTV_REG32 * reg)150 static MS_U32 _HAL_OTV_REG32_R(OTV_REG32 *reg)
151 {
152 MS_U32 value = 0;
153 value = (reg)->H << 16;
154 value |= (reg)->L;
155 return value;
156 }
157
_HAL_OTV_REG16_R(OTV_REG16 * reg)158 static MS_U16 _HAL_OTV_REG16_R(OTV_REG16 *reg)
159 {
160 MS_U16 value;
161 value = (reg)->data;
162 return value;
163 }
164
165 //--------------------------------------------------------------------------------------------------
166 // For MISC part
167 //--------------------------------------------------------------------------------------------------
HAL_OTV_SetBank(MS_VIRT u32BankAddr)168 void HAL_OTV_SetBank(MS_VIRT u32BankAddr)
169 {
170 _u32RegBase = u32BankAddr;
171
172 _OTVReg[0] = (REG_OTV*)(_u32RegBase + OTV0_REG_CTRL_BASE);
173 _u32OTV_PidfltBase[0] = _u32RegBase + OTV0_PIDFLT_BASE;
174 _u32OTV_EventMaskBase[0] = _u32RegBase + OTV0_EVENT_MASK_BASE;
175 //_u32OTV_PayloadMaskBase[0] = _u32RegBase + OTV0_BANK1_PAYLOAD_MASK_BASE;
176
177 _OTVReg[1] = (REG_OTV*)(_u32RegBase + OTV1_REG_CTRL_BASE);
178 _u32OTV_PidfltBase[1] = _u32RegBase + OTV1_PIDFLT_BASE;
179 _u32OTV_EventMaskBase[1] = _u32RegBase + OTV1_EVENT_MASK_BASE;
180 //_u32OTV_PayloadMaskBase[1] = _u32RegBase + OTV1_BANK1_PAYLOAD_MASK_BASE;
181
182 }
183
184 // OTV Init
185
HAL_OTV_Init(MS_U32 u32OTVEng)186 void HAL_OTV_Init(MS_U32 u32OTVEng)
187 {
188 OTV_NUM_CHECK(u32OTVEng);
189
190 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET));
191 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET));
192
193 // filter event reset
194 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_EVENT_FLT_RST));
195 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_EVENT_FLT_RST));
196 }
197
198 #if 0
199 void HAL_OTV_Exit(MS_U32 u32OTVEng)
200 {
201 OTV_NUM_CHECK(u32OTVEng);
202
203 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_SW_RESET));
204 }
205 #endif
206
207 // OTV Config Setting
208
209 #if 0
210
211 void HAL_OTV_FirstPktTimerBase_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
212 {
213 OTV_NUM_CHECK(u32OTVEng);
214
215 if(bEnable) // packet timer will be (orginal timer - first pkt timer)
216 {
217 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_FIRST_PKT_TIMER_BASE_EN));
218 }
219 else // OTV packet timestamp will match OTV local timstamp
220 {
221 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_FIRST_PKT_TIMER_BASE_EN));
222 }
223 }
224
225 #endif
226
227
228
HAL_OTV_PktTimerSrcFromPVR_Enable(MS_U32 u32OTVEng,MS_BOOL bEnable)229 void HAL_OTV_PktTimerSrcFromPVR_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
230 {
231 OTV_NUM_CHECK(u32OTVEng);
232
233 if(bEnable) // OTV packet timer will match PVR timstamp
234 {
235 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_TIMESTAMP_PVR_TO_OTV_EN));
236 }
237 else // OTV packet timer will match OTV local timstamp
238 {
239 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_TIMESTAMP_PVR_TO_OTV_EN));
240 }
241 }
242
243
HAL_OTV_PktNumSrcFromPktDemux_Enable(MS_U32 u32OTVEng,MS_BOOL bEnable)244 void HAL_OTV_PktNumSrcFromPktDemux_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
245 {
246 OTV_NUM_CHECK(u32OTVEng);
247
248 if(bEnable) // OTV packet number will count by pkt dmx hit, pkt_num index start from 1,2,3,...etc
249 {
250 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_SRC_SEL));
251 }
252 else // OTV packet number will count by OTV pid hit, pkt_num index start from 0,1,2,...etc
253 {
254 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_SRC_SEL));
255 }
256 }
257
258
259
260 // OTV Interrupt
261
HAL_OTV_INT_Timer_Enable(MS_U32 u32OTVEng,MS_BOOL bEnable)262 void HAL_OTV_INT_Timer_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
263 {
264 OTV_NUM_CHECK(u32OTVEng);
265
266 if(bEnable)
267 {
268 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_INT_TIMER_EN));
269 }
270 else
271 {
272 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_INT_TIMER_EN));
273 }
274 }
275
HAL_OTV_INT_Event_Enable(MS_U32 u32OTVEng,MS_BOOL bEnable)276 void HAL_OTV_INT_Event_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
277 {
278 OTV_NUM_CHECK(u32OTVEng);
279
280 if(bEnable)
281 {
282 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_INT_EVENT_EN));
283 }
284 else
285 {
286 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2), OTV_INT_EVENT_EN));
287 }
288 }
289
HAL_OTV_INT_SetEventWaterLevel(MS_U32 u32OTVEng,MS_U32 u32EventWaterLevel)290 void HAL_OTV_INT_SetEventWaterLevel(MS_U32 u32OTVEng, MS_U32 u32EventWaterLevel)
291 {
292 OTV_NUM_CHECK(u32OTVEng);
293
294 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2,
295 _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2),(u32EventWaterLevel<<OTV_INT_EVENT_WATER_SHIFT)&OTV_INT_EVENT_WATER_MASK));
296 }
297
HAL_OTV_INT_SetTimerWaterLevel(MS_U32 u32OTVEng,MS_U32 u32TimerWaterLevel)298 void HAL_OTV_INT_SetTimerWaterLevel(MS_U32 u32OTVEng, MS_U32 u32TimerWaterLevel)
299 {
300 OTV_NUM_CHECK(u32OTVEng);
301
302 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2,
303 _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL2),(u32TimerWaterLevel<<OTV_INT_TIME_WATER_SHIFT)&OTV_INT_TIME_WATER_MASK));
304 }
305
HAL_OTV_INT_GetEventHW(MS_U32 u32OTVEng)306 MS_BOOL HAL_OTV_INT_GetEventHW(MS_U32 u32OTVEng)
307 {
308 OTV_NUM_CHECK_RET(u32OTVEng);
309
310 MS_U16 u16IntFlag; // OTV Interrupt Flag
311
312 u16IntFlag = _HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_INT_Flag) & OTV_INT_FLAG_MASK;
313
314 switch(u32OTVEng)
315 {
316 case 0:
317 if( u16IntFlag & OTV_INT_FROM_OTV0_EVENT )
318 return TRUE;
319 else
320 return FALSE;
321 case 1:
322 if( u16IntFlag & OTV_INT_FROM_OTV1_EVENT )
323 return TRUE;
324 else
325 return FALSE;
326 case 2:
327 if( u16IntFlag & OTV_INT_FROM_OTV2_EVENT )
328 return TRUE;
329 else
330 return FALSE;
331 case 3:
332 if( u16IntFlag & OTV_INT_FROM_OTV3_EVENT )
333 return TRUE;
334 else
335 return FALSE;
336 default:
337 return FALSE;
338 }
339 }
340
HAL_OTV_INT_GetTimerHW(MS_U32 u32OTVEng)341 MS_BOOL HAL_OTV_INT_GetTimerHW(MS_U32 u32OTVEng)
342 {
343 OTV_NUM_CHECK_RET(u32OTVEng);
344
345 MS_U16 u16IntFlag; // OTV Interrupt Flag
346
347 u16IntFlag = _HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_INT_Flag) & OTV_INT_FLAG_MASK;
348
349 switch(u32OTVEng)
350 {
351 case 0:
352 if( u16IntFlag & OTV_INT_FROM_OTV0_TIMER )
353 return TRUE;
354 else
355 return FALSE;
356 case 1:
357 if( u16IntFlag & OTV_INT_FROM_OTV1_TIMER )
358 return TRUE;
359 else
360 return FALSE;
361 case 2:
362 if( u16IntFlag & OTV_INT_FROM_OTV2_TIMER )
363 return TRUE;
364 else
365 return FALSE;
366 case 3:
367 if( u16IntFlag & OTV_INT_FROM_OTV3_TIMER )
368 return TRUE;
369 else
370 return FALSE;
371 default:
372 return FALSE;
373 }
374 }
375
376
HAL_OTV_INT_ClrEventHW(MS_U32 u32OTVEng)377 void HAL_OTV_INT_ClrEventHW(MS_U32 u32OTVEng)
378 {
379 OTV_NUM_CHECK(u32OTVEng);
380
381 switch(u32OTVEng)
382 {
383 case 0:
384 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV0_EVENT));
385 break;
386 case 1:
387 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV1_EVENT));
388 break;
389 case 2:
390 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV2_EVENT));
391 break;
392 case 3:
393 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV3_EVENT));
394 break;
395 default:
396 break;
397 }
398 }
399
HAL_OTV_INT_ClrTimerHW(MS_U32 u32OTVEng)400 void HAL_OTV_INT_ClrTimerHW(MS_U32 u32OTVEng)
401 {
402 OTV_NUM_CHECK(u32OTVEng);
403
404 switch(u32OTVEng)
405 {
406 case 0:
407 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV0_TIMER));
408 break;
409 case 1:
410 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV1_TIMER));
411 break;
412 case 2:
413 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV2_TIMER));
414 break;
415 case 3:
416 _HAL_OTV_REG16_W(&_OTVReg[0][0].OTV_INT_Flag, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[0][0].OTV_INT_Flag), OTV_INT_FROM_OTV3_TIMER));
417 break;
418 default:
419 break;
420 }
421 }
422
423
424
425 // OTV Event Queue
426
HAL_OTV_EventQ_Enable(MS_U32 u32OTVEng,MS_BOOL bEnable)427 void HAL_OTV_EventQ_Enable(MS_U32 u32OTVEng, MS_BOOL bEnable)
428 {
429 OTV_NUM_CHECK(u32OTVEng);
430
431 if(bEnable)
432 {
433 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_REC_EFRAME_EN));
434 }
435 else
436 {
437 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL0), OTV_REC_EFRAME_EN));
438 }
439 }
440
441
HAL_OTV_EventQ_GetEventNum(MS_U32 u32OTVEng,MS_U32 * pu32EventNum)442 void HAL_OTV_EventQ_GetEventNum(MS_U32 u32OTVEng, MS_U32 *pu32EventNum)
443 {
444 OTV_NUM_CHECK(u32OTVEng);
445
446 *pu32EventNum = _HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_EventLogCtrlStatus) & OTV_EVENT_FIFO_NUM_MASK;
447 }
448
449
HAL_OTV_EventQ_PopEvent(MS_U32 u32OTVEng)450 MS_BOOL HAL_OTV_EventQ_PopEvent(MS_U32 u32OTVEng)
451 {
452 OTV_NUM_CHECK_RET(u32OTVEng);
453
454 MS_U32 u32EventNum;
455
456 HAL_OTV_EventQ_GetEventNum(u32OTVEng, &u32EventNum);
457
458 if (u32EventNum != 0)
459 {
460 // Event Queue Read
461 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1), OTV_EFRAME_RD));
462 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1), OTV_EFRAME_RD));
463 return TRUE;
464 }
465 else
466 {
467 return FALSE;
468 }
469 }
470
471
HAL_OTV_EventQ_GetEventDesciptor(MS_U32 u32OTVEng,MS_U32 * pu32EventDesciptor)472 void HAL_OTV_EventQ_GetEventDesciptor(MS_U32 u32OTVEng, MS_U32 *pu32EventDesciptor)
473 {
474 OTV_NUM_CHECK(u32OTVEng);
475 *pu32EventDesciptor = _HAL_OTV_REG32_R(&_OTVReg[u32OTVEng][0].OTV_EventDescriptor);
476 }
477
HAL_OTV_EventQ_GetEventPktNum(MS_U32 u32OTVEng,MS_U32 * pu32EventPktNum)478 void HAL_OTV_EventQ_GetEventPktNum(MS_U32 u32OTVEng, MS_U32 *pu32EventPktNum)
479 {
480 OTV_NUM_CHECK(u32OTVEng);
481 *pu32EventPktNum = _HAL_OTV_REG32_R(&_OTVReg[u32OTVEng][0].OTV_EventPktNum);
482 }
483
484
HAL_OTV_EventQ_GetEventPktTimer(MS_U32 u32OTVEng,MS_U32 * pu32EventPktTimer)485 void HAL_OTV_EventQ_GetEventPktTimer(MS_U32 u32OTVEng, MS_U32 *pu32EventPktTimer)
486 {
487 OTV_NUM_CHECK(u32OTVEng);
488 *pu32EventPktTimer = _HAL_OTV_REG32_R(&_OTVReg[u32OTVEng][0].OTV_EventPktTimer);
489 }
490
491
HAL_OTV_EventQ_GetEventPktPCR(MS_U32 u32OTVEng,MS_U32 * pu32EventPktPCR)492 void HAL_OTV_EventQ_GetEventPktPCR(MS_U32 u32OTVEng, MS_U32 *pu32EventPktPCR)
493 {
494 OTV_NUM_CHECK(u32OTVEng);
495 *pu32EventPktPCR = _HAL_OTV_REG32_R(&_OTVReg[u32OTVEng][0].OTV_EventPktPCR);
496 }
497
498
HAL_OTV_EventQ_GetEventPktPID(MS_U32 u32OTVEng,MS_U16 * pu16EventPktPID)499 void HAL_OTV_EventQ_GetEventPktPID(MS_U32 u32OTVEng, MS_U16 *pu16EventPktPID)
500 {
501 OTV_NUM_CHECK(u32OTVEng);
502 *pu16EventPktPID = _HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_EventPktPID);
503 }
504
505
506
507
508
509 #if 0
510 MS_BOOL HAL_OTV_EventQ_Pop(MS_U32 u32OTVEng,MS_U32 *DataArray, MS_U32 ArrSize) // [NOTE] NDS structure for 20 bytes..
511 {
512 OTV_NUM_CHECK_RET(u32OTVEng);
513
514 MS_U32 u32EventNum;
515
516 HAL_OTV_EventQ_GetNum(u32OTVEng, &u32EventNum);
517
518 if (u32EventNum != 0)
519 {
520 // Event Queue Read
521 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1), OTV_EFRAME_RD));
522 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL1), OTV_EFRAME_RD));
523
524 if (ArrSize >= 5 )
525 {
526 DataArray[0] = _HAL_OTV_REG32_R(&(_OTVReg[u32OTVEng][0].OTV_EventDescriptor));
527 DataArray[1] = _HAL_OTV_REG32_R(&(_OTVReg[u32OTVEng][0].OTV_EventPktNum));
528 DataArray[2] = _HAL_OTV_REG32_R(&(_OTVReg[u32OTVEng][0].OTV_EventPktTimer));
529 DataArray[3] = _HAL_OTV_REG32_R(&(_OTVReg[u32OTVEng][0].OTV_EventPktPCR));
530 DataArray[4] = (MS_U32)_HAL_OTV_REG16_R(&(_OTVReg[u32OTVEng][0].OTV_EventPktPID));
531 return TRUE;
532 }
533 else
534 {
535 // array size not enough
536 return FALSE;
537 }
538 }
539 else
540 {
541 return FALSE;
542 }
543 }
544 #endif
545
546
547 // OTV Get Current Packet Number/TimeStamp
548
HAL_OTV_GetCurPktTimer(MS_U32 u32OTVEng,MS_U32 * pu32PktTimer)549 void HAL_OTV_GetCurPktTimer(MS_U32 u32OTVEng, MS_U32 *pu32PktTimer)
550 {
551 OTV_NUM_CHECK(u32OTVEng);
552
553 // latch bit:pkt num/timer will be locked for reading if this bit is set to 1
554 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_TIMER_LOCK));
555
556 *pu32PktTimer = _HAL_OTV_REG32_R(&_OTVReg[u32OTVEng][0].OTV_PktTimer);
557
558 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_TIMER_LOCK));
559
560 }
561
HAL_OTV_GetCurPktNum(MS_U32 u32OTVEng,MS_U32 * pu32PktNum)562 void HAL_OTV_GetCurPktNum(MS_U32 u32OTVEng, MS_U32 *pu32PktNum)
563 {
564 OTV_NUM_CHECK(u32OTVEng);
565
566 // latch bit:pkt num/timer will be locked for reading if this bit is set to 1
567 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_TIMER_LOCK));
568
569 *pu32PktNum = _HAL_OTV_REG32_R(&(_OTVReg[u32OTVEng][0].OTV_PktNum));
570
571 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_PKT_NUM_TIMER_LOCK));
572 }
573
574 // OTV Pid Filter
575
HAL_OTV_SetFltPid(MS_U32 u32OTVEng,MS_U32 u32FltId,MS_U16 u16Pid)576 void HAL_OTV_SetFltPid(MS_U32 u32OTVEng , MS_U32 u32FltId , MS_U16 u16Pid)
577 {
578 OTV_NUM_CHECK(u32OTVEng);
579
580 MS_VIRT _u32PidFltReg = _u32OTV_PidfltBase[u32OTVEng] + (u32FltId*0x04);
581 _HAL_OTV_REG16_W((OTV_REG16 *)_u32PidFltReg, u16Pid);
582 }
583
HAL_OTV_GetFltPid(MS_U32 u32OTVEng,MS_U32 u32FltId,MS_U16 * pu16Pid)584 void HAL_OTV_GetFltPid(MS_U32 u32OTVEng , MS_U32 u32FltId , MS_U16 *pu16Pid)
585 {
586 OTV_NUM_CHECK(u32OTVEng);
587
588 MS_VIRT _u32PidfltReg = _u32OTV_PidfltBase[u32OTVEng] + (u32FltId*0x04);
589 *pu16Pid = _HAL_OTV_REG16_R((OTV_REG16 *)_u32PidfltReg);
590 }
591
592
HAL_OTV_SetFltEvent(MS_U32 u32OTVEng,MS_U32 u32FltId,MS_U32 u32FltEvent)593 void HAL_OTV_SetFltEvent(MS_U32 u32OTVEng , MS_U32 u32FltId, MS_U32 u32FltEvent)
594 {
595 OTV_NUM_CHECK(u32OTVEng);
596 MS_VIRT _u32EventMaskReg = _u32OTV_EventMaskBase[u32OTVEng] + (u32FltId*0x08);
597 _HAL_OTV_REG32_W((OTV_REG32 *)_u32EventMaskReg, u32FltEvent);
598
599 }
600
HAL_OTV_GetFltEvent(MS_U32 u32OTVEng,MS_U32 u32FltId,MS_U32 * pu32FltEvent)601 void HAL_OTV_GetFltEvent(MS_U32 u32OTVEng , MS_U32 u32FltId, MS_U32 *pu32FltEvent)
602 {
603 OTV_NUM_CHECK(u32OTVEng);
604 MS_VIRT _u32EventMaskReg = _u32OTV_EventMaskBase[u32OTVEng] + (u32FltId*0x08);
605 *pu32FltEvent = _HAL_OTV_REG32_R((OTV_REG32 *)_u32EventMaskReg) & OTV_EVENT_MASK ;
606
607 }
608
HAL_OTV_RstFltEvent(MS_U32 u32OTVEng)609 void HAL_OTV_RstFltEvent(MS_U32 u32OTVEng)
610 {
611 OTV_NUM_CHECK(u32OTVEng);
612 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _SET_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_EVENT_FLT_RST));
613 _HAL_OTV_REG16_W(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3, _CLR_(_HAL_OTV_REG16_R(&_OTVReg[u32OTVEng][0].OTV_HW_CTRL3), OTV_EVENT_FLT_RST));
614 }
615