130 static MS_U32       _u32RegBase = 0;  variable
201 #define TSP_INT_REG(addr)           (*((volatile MS_U16*)(_u32RegBase + 0x3200 + ((addr)<<2))))
203 #define TSP_CLKGEN0_REG(addr)       (*((volatile MS_U16*)(_u32RegBase + 0x1600 + ((addr)<<2))))
243 #define TSP_CLKGEN1_REG(addr)       (*((volatile MS_U16*)(_u32RegBase + 0x6600 + ((addr)<<2))))
254 #define TSP_TOP_REG(addr)           (*((volatile MS_U16*)(_u32RegBase + 0x3c00 + ((addr)<<2))))
281 #define TSP_TSO0_REG(addr)           (*((volatile MS_U16*)(_u32RegBase + 0x27400UL + ((addr)<<2UL))…
292 #define TSP_TS_SAMPLE_REG(addr)           (*((volatile MS_U16*)(_u32RegBase + 0x21600 + ((addr)<<2)…
371 #define ADDR_INDR_CTRL          (_u32RegBase+ 0x2b20)
372 #define ADDR_INDR_ADDR0         (_u32RegBase+ 0x2b24)
373 #define ADDR_INDR_ADDR1         (_u32RegBase+ 0x2b28)
374 #define ADDR_INDR_WRITE0        (_u32RegBase+ 0x2b2c)
375 #define ADDR_INDR_WRITE1        (_u32RegBase+ 0x2b30)
376 #define ADDR_INDR_READ0         (_u32RegBase+ 0x2b34)
377 #define ADDR_INDR_READ1         (_u32RegBase+ 0x2b38)
379 #define ADDR_MOBF_FILEIN        (_u32RegBase+ 0x2a2cUL)
382 #define XBYTE_1591              (_u32RegBase+ 0x2a0c)  // TsRec_Head21_Mid20
383 #define XBYTE_15A4              (_u32RegBase+ 0x2a10)  // TsRec_Mid21_Tail20
384 #define XBYTE_15A6              (_u32RegBase+ 0x2b48)  // TsRec_Mid
422 #define TSP_SEM_AEON              (_u32RegBase+ 0xC1480)  //sw_mail_box0
423 #define TSP_SEM_ORDER             (_u32RegBase+ 0xC1484)  // sw_mail_box1
424 #define TSP_SEM_MIPS              (_u32RegBase+ 0xC1488)  // sw_mail_box2
628 #define ADDR_HWINT2         (_u32RegBase+ 0x2db0)
1160 #define ADDR_SWINT2_L           (_u32RegBase+ 0x2db4)
1161 #define ADDR_SWINT2_H           (_u32RegBase+ 0x2db8)
1482 #define ADDR_PVR_HEAD20         (_u32RegBase+ 0x2a04)  in HAL_TSP_PVR_SetBuffer()
1483 #define ADDR_PVR_HEAD21         (_u32RegBase+ 0x2a08)  in HAL_TSP_PVR_SetBuffer()
1484 #define ADDR_PVR_MID20          (_u32RegBase+ 0x2a0c)  in HAL_TSP_PVR_SetBuffer()
1485 #define ADDR_PVR_MID21          (_u32RegBase+ 0x2a10)  in HAL_TSP_PVR_SetBuffer()
1486 #define ADDR_PVR_TAIL20         (_u32RegBase+ 0x2a14)  in HAL_TSP_PVR_SetBuffer()
1487 #define ADDR_PVR_TAIL21         (_u32RegBase+ 0x2a18)  in HAL_TSP_PVR_SetBuffer()
2772     _u32RegBase = u32BankAddr;  in HAL_TSP_SetBank()
2774     _TspCtrl   = (REG_Ctrl*)(_u32RegBase+ REG_CTRL_BASE);  in HAL_TSP_SetBank()
2775     _TspCtrl2  = (REG_Ctrl2*)(_u32RegBase + REG_CTRL_MMFIBASE);  in HAL_TSP_SetBank()
2776     _TspCtrl3  = (REG_Ctrl3*)(_u32RegBase + REG_CTRL_TSP3);  in HAL_TSP_SetBank()
2777     _TspCtrl4  = (REG_Ctrl4*)(_u32RegBase + REG_CTRL_TSP4);  in HAL_TSP_SetBank()
2778     _TspCtrl5  = (REG_Ctrl5*)(_u32RegBase + REG_CTRL_TSP5);  in HAL_TSP_SetBank()
2779     _TspSample = (REG_TS_Sample*)(_u32RegBase + REG_CTRL_TS_SAMPLE);  in HAL_TSP_SetBank()
3356 #define ADDR_SWINT2_L           (_u32RegBase+ 0x2db4)
3357 #define ADDR_SWINT2_H           (_u32RegBase+ 0x2db8)
3897 …_HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TS2_TS4), RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegB…  in HAL_TSP_PowerCtrl()
3900         _HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
3901 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBase+CKG_TSP_STC0)), (CLK_TSP_DISABLE|CLK_TSP_INVERT|…  in HAL_TSP_PowerCtrl()
3904 …_HAL_REG32L_W((REG32_L *)(_u32RegBase+CHIP_TSP_BOOT_CLK_SEL), RESET_FLAG1(_HAL_REG32L_R((REG32_L *…  in HAL_TSP_PowerCtrl()
3910 …_HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TSP_SW_CLK), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32Reg…  in HAL_TSP_PowerCtrl()
3913          _HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_CLK_STCSYN),  in HAL_TSP_PowerCtrl()
3914 …(_HAL_REG32L_R((REG32_L *)(_u32RegBase+CKG_CLK_STCSYN)) & ~CKG_CLK_STCSYN_MASK) | CKG_CLK_STCSYN_4…  in HAL_TSP_PowerCtrl()
3917         _HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
3918 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBase+CKG_TSP_STC0)), (CLK_PAR_DISABLE|CLK_PAR_INVERT|…  in HAL_TSP_PowerCtrl()
3921         _HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TS0_TS1),  in HAL_TSP_PowerCtrl()
3922 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBase+CKG_TS0_TS1)), (CLK_TS0_DISABLE|CLK_TS0_INVERT|C…  in HAL_TSP_PowerCtrl()
3925         _HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TS0_TS1),  in HAL_TSP_PowerCtrl()
3926 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBase+CKG_TS0_TS1)), (CLK_TS1_DISABLE|CLK_TS1_INVERT|C…  in HAL_TSP_PowerCtrl()
3929         _HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TSP_STC0),  in HAL_TSP_PowerCtrl()
3930 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBase+CKG_TSP_STC0)), (CLK_STC_DISABLE|CLK_STC_INVERT|…  in HAL_TSP_PowerCtrl()
3933         _HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TSP_STAMP),  in HAL_TSP_PowerCtrl()
3934 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBase+CKG_TSP_STAMP)), (CLK_STAM_DISABLE|CLK_STAM_INVE…  in HAL_TSP_PowerCtrl()
3937         _HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG1_TS_SAMPLE),  in HAL_TSP_PowerCtrl()
3938 …RESET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBase+CKG1_TS_SAMPLE)), (CLK_TS_SAMPLE_DISABLE|CLK_TS_…  in HAL_TSP_PowerCtrl()
3944 …_HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TS2_TS4), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBas…  in HAL_TSP_PowerCtrl()
3947 …_HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG1_TS_SAMPLE), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32Reg…  in HAL_TSP_PowerCtrl()
3950 …_HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBas…  in HAL_TSP_PowerCtrl()
3953 …_HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TS0_TS1), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBas…  in HAL_TSP_PowerCtrl()
3956 …_HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBa…  in HAL_TSP_PowerCtrl()
3959 …_HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TSP_STC0), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegBa…  in HAL_TSP_PowerCtrl()
3962 …_HAL_REG32L_W((REG32_L *)(_u32RegBase+CKG_TSP_STAMP), SET_FLAG1(_HAL_REG32L_R((REG32_L *)(_u32RegB…  in HAL_TSP_PowerCtrl()