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77 //<MStar Software>
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halAESDMA.c
97 // @brief AESDMA HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100
101 #include "MsCommon.h"
102 #include "regAESDMA.h"
103 #include "halAESDMA.h"
104 #include "halCHIP.h"
105
106
107 //--------------------------------------------------------------------------------------------------
108 // Driver Compiler Option
109 //--------------------------------------------------------------------------------------------------
110
111 //--------------------------------------------------------------------------------------------------
112 // TSP Hardware Abstraction Layer
113 //--------------------------------------------------------------------------------------------------
114 static MS_VIRT _u32RegBase = NULL;
115 static MS_VIRT _u32PmRegBase = NULL;
116 static MS_U32 SECUREBASECtrl_Buffer;
117 static REG_AESDMACtrl *_AESDMACtrl = (REG_AESDMACtrl*)REG_AESDMACTRL_BASE;
118 static REG_SHARNGCtrl *_SHARNGCtrl = (REG_SHARNGCtrl*)REG_SHARNGCTRL_BASE;
119 static REG_AESDMAClk *_AESDMAClk = (REG_AESDMAClk*)REG_AESDMACLK_BASE;
120 static REG_AESDMAMbx *_AESDMAMbx = (REG_AESDMAMbx*)REG_AESDMAMBX_BASE;
121 static REG_PARSERCtrl *_PARSERCtrl = (REG_PARSERCtrl*)REG_PARSERCTRL_BASE;
122 static REG_CIPHERCtrl *_CIPHERCtrl = (REG_CIPHERCtrl*)REG_CIPHERCTRL_BASE;
123 static REG_DMASECURECtrl *_DMASECURECtrl = (REG_DMASECURECtrl*)REG_DMASECURE_BASE;
124 static REG_SECUREBASECtrl *_SECUREBASECtrl = (REG_SECUREBASECtrl*)REG_DMASECURE_CTRL_BASE;
125 static REG_AESDMACtrlEx *_AESDMACtrlEx = (REG_AESDMACtrlEx*)REG_AESDMAEXT_BASE;
126 static REG_TZPCCtrl *_TZPCCtrl = (REG_TZPCCtrl*)REG_TZPC_NONPM_BASE;
127 static REG_HDCP22Data *_HDCP22Data = (REG_HDCP22Data*)REG_HDCP22_BASE;
128 static REG_HDCP22SEKCtrl *_HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)REG_HDCP22_SEK;
129 static REG_HDCP14SEKCtrl *_HDCP14SekCtrl = (REG_HDCP14SEKCtrl*)REG_HDCP14_BASE;
130 static REG_ANAMISCBASECtrl *_ANAMISCCtrl = (REG_ANAMISCBASECtrl*)REG_ANA_MISC_BASE;
131 static REG_AES_DSCMB6Ctrl *_AESDSCMB6Ctrl = (REG_AES_DSCMB6Ctrl*)REG_AES_DSCMB6_BASE;
132 static REG_AES_DSCMB7Ctrl *_AESDSCMB7Ctrl = (REG_AES_DSCMB7Ctrl*)REG_AES_DSCMB7_BASE;
133
134 #define REG32_W(reg, value) do { \
135 (reg)->H = ((value) >> 16); \
136 (reg)->L = ((value) & 0x0000FFFF); \
137 } while(0)
138
139 //--------------------------------------------------------------------------------------------------
140 // Macro of bit operations
141 //--------------------------------------------------------------------------------------------------
142
_AESDMA_REG32_R(REG32 * reg)143 MS_U32 _AESDMA_REG32_R(REG32 *reg)
144 {
145 MS_U32 value;
146
147 value = (reg)->H << 16;
148 value |= (reg)->L;
149
150 return value;
151 }
152
153 //--------------------------------------------------------------------------------------------------
154 // Inline Function
155 //--------------------------------------------------------------------------------------------------
HAL_AESDMA_SetBank(MS_VIRT u32NonPmBankAddr,MS_VIRT u32PmBankAddr)156 void HAL_AESDMA_SetBank(MS_VIRT u32NonPmBankAddr, MS_VIRT u32PmBankAddr)
157 {
158 _u32RegBase = u32NonPmBankAddr;
159 _u32PmRegBase = u32PmBankAddr;
160 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE);
161 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE);
162 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE);
163 _AESDMAMbx = (REG_AESDMAMbx*)(_u32PmRegBase + REG_AESDMAMBX_BASE);
164 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE);
165 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);
166 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE);
167 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE);
168 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE);
169 _TZPCCtrl = (REG_TZPCCtrl*)(_u32RegBase + REG_TZPC_NONPM_BASE);
170 _HDCP22Data = (REG_HDCP22Data*)(_u32RegBase + REG_HDCP22_BASE);
171 _HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)(_u32RegBase + REG_HDCP22_SEK);
172 _HDCP14SekCtrl = (REG_HDCP14SEKCtrl*)(_u32RegBase + REG_HDCP14_BASE);
173 _ANAMISCCtrl = (REG_ANAMISCBASECtrl*)(_u32RegBase + REG_ANA_MISC_BASE);
174 _AESDSCMB6Ctrl = (REG_AES_DSCMB6Ctrl*)(_u32RegBase + REG_AES_DSCMB6_BASE);
175 _AESDSCMB7Ctrl = (REG_AES_DSCMB7Ctrl*)(_u32RegBase + REG_AES_DSCMB7_BASE);
176 }
177
AESDMA_GetMIU1Base(void)178 MS_PHY AESDMA_GetMIU1Base(void)
179 {
180 return HAL_MIU1_BASE;
181 }
182
AESDMA_GetMIU2Base(void)183 MS_PHY AESDMA_GetMIU2Base(void)
184 {
185 //not support
186 return FALSE;
187 }
188
AESDMA_Reset(void)189 void AESDMA_Reset(void)
190 {
191 AESDMA_NormalReset ();
192 #if 0
193 MS_VIRT Reg_AESDMA;
194 MS_U32 i = 0;
195 Reg_AESDMA = (MS_VIRT)(&_AESDMACtrl[0].Dma_Ctrl);
196
197 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
198 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST)); // sw rst
199 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RST));
200
201 // reset all AESdma register
202 for (i = 0 ; i < 19 ; i++)
203 {
204 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
205 }
206 // reset secure_dma3_ctrl register
207 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
208
209 // reset hw_parser_ctrl register
210 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000);
211 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
212 #endif
213 }
214
AESDMA_Set_CipherKey(MS_U32 * cipherkey)215 void AESDMA_Set_CipherKey(MS_U32 *cipherkey)
216 {
217 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
218 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
219 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
220 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
221 }
222
AESDMA_Set_InitVector(MS_U32 * pInitVector)223 void AESDMA_Set_InitVector(MS_U32 *pInitVector)
224 {
225 REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_L), pInitVector[0]);
226 REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_H), pInitVector[1]);
227 REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_L), pInitVector[2]);
228 REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_H), pInitVector[3]);
229 }
230
AESDMA_Sel_Key(MS_BOOL keysel)231 void AESDMA_Sel_Key(MS_BOOL keysel)
232 {
233 }
234
AESDMA_Sel_SecureKey(void)235 void AESDMA_Sel_SecureKey(void)
236 {
237 MS_U32 u32Ctrl = _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2);
238 u32Ctrl |= AESDMA_USE_SECRET_KEY;
239 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), u32Ctrl);
240 }
241
AESDMA_Set_FileinDesc(MS_PHY FileinAddr,MS_PHY FileinNum)242 void AESDMA_Set_FileinDesc(MS_PHY FileinAddr , MS_PHY FileinNum)
243 {
244 REG32_W((&_AESDMACtrl[0].Dma_Filein_Addr), FileinAddr);
245 REG32_W((&_AESDMACtrl[0].Dma_Filein_Num), FileinNum);
246 }
247
AESDMA_Set_FileoutDesc(MS_PHY FileoutSAddr,MS_PHY FileoutEAddr)248 void AESDMA_Set_FileoutDesc(MS_PHY FileoutSAddr , MS_PHY FileoutEAddr)
249 {
250 REG32_W((&_AESDMACtrl[0].Dma_Fileout_SAddr), FileoutSAddr);
251 REG32_W((&_AESDMACtrl[0].Dma_Fileout_EAddr), FileoutEAddr);
252 }
253
AESDMA_Start(MS_BOOL AESDMAStart)254 void AESDMA_Start(MS_BOOL AESDMAStart)
255 {
256 if (AESDMAStart)
257 {
258 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) &~ AESDMA_CTRL_FILEOUT_START &~ AESDMA_CTRL_FILEIN_START));
259 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) | AESDMA_CTRL_FILEOUT_START | AESDMA_CTRL_FILEIN_START));
260 }
261 else
262 {
263 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_FILEOUT_START|AESDMA_CTRL_FILEIN_START));
264 }
265 }
266
AESDMA_Set_PS_PTN(MS_U32 MatchPTN)267 void AESDMA_Set_PS_PTN(MS_U32 MatchPTN)
268 {
269 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern) , MatchPTN);
270 }
271
AESDMA_Set_PS_Mask(MS_U32 MatchMask)272 void AESDMA_Set_PS_Mask(MS_U32 MatchMask)
273 {
274 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern_Mask) , MatchMask);
275 }
276
AESDMA_Set_PS_ENG(MS_BOOL PSin_en,MS_BOOL PSout_en)277 void AESDMA_Set_PS_ENG(MS_BOOL PSin_en, MS_BOOL PSout_en)
278 {
279 MS_U32 u32PSin, u32PSout;
280
281 u32PSin = AESDMA_ENG_PS_IN_EN & (PSin_en<<20);
282 u32PSout = AESDMA_ENG_PS_OUT_EN & (PSout_en<<21);
283
284 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(u32PSin|u32PSout));
285 }
286
AESDMA_Get_PS_MatchedBytecnt(void)287 MS_U32 AESDMA_Get_PS_MatchedBytecnt(void)
288 {
289 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Btyecnt);
290 }
291
AESDMA_Get_PS_MatchedPTN(void)292 MS_U32 AESDMA_Get_PS_MatchedPTN(void)
293 {
294 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Pat);
295 }
296
AESDMA_Set_PS_Release(void)297 void AESDMA_Set_PS_Release(void)
298 {
299 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ENG_PS_RELEASE);
300 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & ~AESDMA_ENG_PS_RELEASE);
301 }
302
AESDMA_Get_AESDMA_Status(void)303 MS_U32 AESDMA_Get_AESDMA_Status(void)
304 {
305 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status);
306 }
307
AESDMA_Get_AESDMA_IsFinished(void)308 MS_U32 AESDMA_Get_AESDMA_IsFinished(void)
309 {
310 return (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status) & AESDMA_IS_FINISHED);
311 }
312
AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode,MS_BOOL Descrypt)313 void AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode, MS_BOOL Descrypt)
314 {
315 MS_U32 u32Cmd = 0;
316
317 switch (eMode)
318 {
319 case E_AESDMA_CIPHER_ECB:
320 u32Cmd |= AESDMA_ENG_AES_EN;
321 break;
322
323 case E_AESDMA_CIPHER_CTR:
324 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTR_MODE);
325 break;
326
327 case E_AESDMA_CIPHER_CBC:
328 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CBC_MODE);
329 break;
330
331 case E_AESDMA_CIPHER_DES_ECB:
332 u32Cmd |= AESDMA_ENG_DES_EN;
333 break;
334
335 case E_AESDMA_CIPHER_DES_CTR:
336 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTR_MODE);
337 break;
338
339 case E_AESDMA_CIPHER_DES_CBC:
340 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CBC_MODE);
341 break;
342
343 case E_AESDMA_CIPHER_TDES_ECB:
344 u32Cmd |= AESDMA_ENG_TDES_EN;
345 break;
346
347 case E_AESDMA_CIPHER_TDES_CTR:
348 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTR_MODE);
349 break;
350
351 case E_AESDMA_CIPHER_TDES_CBC:
352 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CBC_MODE);
353 break;
354
355 case E_AESDMA_CIPHER_CTS_CBC:
356 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_CBC_MODE);
357 break;
358
359 case E_AESDMA_CIPHER_CTS_ECB:
360 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_ECB_MODE);
361 break;
362
363 case E_AESDMA_CIPHER_DES_CTS_CBC:
364 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_CBC_MODE);
365 break;
366
367 case E_AESDMA_CIPHER_DES_CTS_ECB:
368 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_ECB_MODE);
369 break;
370
371 case E_AESDMA_CIPHER_TDES_CTS_CBC:
372 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_CBC_MODE);
373 break;
374
375 case E_AESDMA_CIPHER_TDES_CTS_ECB:
376 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_ECB_MODE);
377 break;
378 default:
379 return;
380 }
381
382 if( eMode >= E_AESDMA_CIPHER_DES_ECB )
383 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) | AESDMA_DMA_USE_TDES_EN);
384
385 u32Cmd |= AESDMA_ENG_DESCRYPT & (Descrypt<<25);
386 REG32_W((&_AESDMACtrl[0].Dma_Ctrl),(( _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & (~DmaCtrlSet)) | u32Cmd ) );
387 }
388
AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)389 MS_U32 AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)
390 {
391 MS_U32 u32Result = 1;
392
393 switch (eMode)
394 {
395 case E_AESDMA_CIPHER_ECB:
396 case E_AESDMA_CIPHER_CTR:
397 case E_AESDMA_CIPHER_CBC:
398 case E_AESDMA_CIPHER_DES_ECB:
399 case E_AESDMA_CIPHER_DES_CTR:
400 case E_AESDMA_CIPHER_DES_CBC:
401 case E_AESDMA_CIPHER_TDES_ECB:
402 case E_AESDMA_CIPHER_TDES_CTR:
403 case E_AESDMA_CIPHER_TDES_CBC:
404 case E_AESDMA_CIPHER_CTS_CBC:
405 case E_AESDMA_CIPHER_CTS_ECB:
406 case E_AESDMA_CIPHER_DES_CTS_CBC:
407 case E_AESDMA_CIPHER_DES_CTS_ECB:
408 case E_AESDMA_CIPHER_TDES_CTS_CBC:
409 case E_AESDMA_CIPHER_TDES_CTS_ECB:
410 u32Result = 0;
411 break;
412 default:
413 break;
414 }
415 return u32Result;
416
417 }
418
AESDMA_Set_MIU_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)419 void AESDMA_Set_MIU_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
420 {
421 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_R));
422 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_W));
423
424 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_R & ((MS_U32)MIU_R << 4))));
425 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_W & ((MS_U32)MIU_W << 5))));
426 }
427
AESDMA_Set_MIU2_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)428 void AESDMA_Set_MIU2_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
429 {
430 // Not support
431 }
432
AESDMA_Enable_Int(void)433 void AESDMA_Enable_Int(void)
434 {
435 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)|AESDMA_INT_EN);
436 }
437
AESDMA_Disable_Int(void)438 void AESDMA_Disable_Int(void)
439 {
440 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)&~AESDMA_INT_EN);
441 }
442
AESDMA_Clear_Int(void)443 void AESDMA_Clear_Int(void)
444 {
445 //
446 // Since ISR Clear bit for Normal and Secured bank is independently, it must be reset individually
447 //
448
449 #if AESDMS_SECURED_BANK_EN
450 //
451 // For Secured Bank
452 //
453 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)|AESDMA_ISR_CLR);
454 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)&~AESDMA_ISR_CLR);
455 #else
456 //
457 // For Normal Bank
458 //
459 REG32_W((&_AESDSCMB7Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB7Ctrl[0].Reg0001)|AESDMA_ISR_CLR);
460 REG32_W((&_AESDSCMB7Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB7Ctrl[0].Reg0001)&~AESDMA_ISR_CLR);
461 #endif //#if AESDMS_SECURED_BANK_EN
462 }
463
AESDMA_HW_Patch(void)464 void AESDMA_HW_Patch(void)
465 {
466 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ECO_FIX_LAST_BYTE);
467 //REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_CTRL_BURST_LENGTH);
468 //REG32_W((&_AESDMACtrl[0].Dma_Eng3_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Eng3_Ctrl)|AESDMA_ENG_SPEEDUP);
469 }
470
AESDMA_Enable_Clk(void)471 void AESDMA_Enable_Clk(void)
472 {
473 MS_U32 u32Val;
474
475 //1. clk_aesdma, 0x100A_19[3:0] = 0
476 u32Val = _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA);
477 u32Val &= ~AESDMA_CLK_XTAL; //Clear Clk setting.
478 u32Val |= AESDMA_CLK_172M; //Set Clk to 172M
479 u32Val &= ~AESDMA_CLK_OFF_EN;//Enable Clk
480 REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , u32Val);
481
482 }
483
AESDMA_Disable_Clk(void)484 void AESDMA_Disable_Clk(void)
485 {
486 REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) | AESDMA_CLK_OFF_EN);
487 }
488
AESDMA_Rand(void)489 MS_U8 AESDMA_Rand(void)
490 {
491 MS_U8 u8RN = 0x00;
492 u8RN = (MS_U8)_AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0203)&0xFF;
493
494 return u8RN;
495 }
496
SHA_Reset(void)497 void SHA_Reset(void)
498 {
499 MS_VIRT Reg_SHARNG;
500 MS_U32 i = 0;
501 Reg_SHARNG = (MS_VIRT)(&_SHARNGCtrl[0].Sha_Ctrl);
502 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , SHARNG_CTRL_SHA_RST); // 0->1
503 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&(~SHARNG_CTRL_SHA_RST))); // 1->0
504
505 // reset all SHA & RNG register
506 for (i = 0 ; i < 7 ; i++)
507 {
508 REG32_W((REG32 *)(Reg_SHARNG+(i*8)), 0x00000000);
509 }
510 }
511
SHA_Get_Status(void)512 MS_U32 SHA_Get_Status(void)
513 {
514 return _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Status);
515 }
516
SHA_SelMode(AESDMA_SHAMode eMode)517 void SHA_SelMode(AESDMA_SHAMode eMode)
518 {
519 MS_U32 u32Cmd = 0;
520
521 switch (eMode)
522 {
523 case E_AESDMA_SHA1:
524 u32Cmd |= (SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
525 break;
526
527 case E_AESDMA_SHA256:
528 u32Cmd |= (SHARNG_CTRL_SHA_SEL_SHA256 | SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
529 break;
530
531 default:
532 return;
533 }
534
535 //Turn off speedup mode
536 //u32Cmd |= SHARNG_CTRL_SPEED_MODE_N;
537
538 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl), _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl) | u32Cmd);
539 }
540
SHA_SetAddress(MS_PHY u32Addr)541 void SHA_SetAddress(MS_PHY u32Addr)
542 {
543 REG32_W((&_SHARNGCtrl[0].Sha_Start), u32Addr);
544 }
545
SHA_SetLength(MS_U32 u32Size)546 void SHA_SetLength(MS_U32 u32Size)
547 {
548 REG32_W((&_SHARNGCtrl[0].Sha_Length), u32Size);
549 }
550
SHA_Start(MS_BOOL SHAStart)551 void SHA_Start(MS_BOOL SHAStart)
552 {
553 if(SHAStart)
554 {
555 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
556 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_FIRE_ONCE));
557 }
558 else
559 {
560 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
561 }
562 }
563
SHA_Out(MS_VIRT u32Buf)564 void SHA_Out(MS_VIRT u32Buf)
565 {
566 MS_U32 Index, u32Size, u32offset;
567 MS_U32 eMode = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&SHARNG_CTRL_SHA_SEL_SHA256;
568
569 if(eMode == SHARNG_CTRL_SHA_SEL_SHA256)
570 {
571 u32Size = DIGEST_SIZE_SHA256;
572 u32offset = 0;
573 }
574 else
575 {
576 u32Size = DIGEST_SIZE_SHA1;
577 u32offset = 3;
578 }
579
580 for( Index = 0; Index < u32Size; Index++ )
581 {
582 *((MS_U32 *)u32Buf + Index) = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Out[Index + u32offset]);
583 }
584 //Set "1" to idle state after reg_read_sha_ready = 1
585 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_CLR));
586 }
587
588
589 //-------------------------------------------------------------------------------------------------
590 /// Enable mobf one way function
591 /// @param NULL
592
593 /// @note : disable read mobf key, and could not enable read mobf key anymore
594 //-------------------------------------------------------------------------------------------------
MOBF_OneWay(void)595 void MOBF_OneWay(void)
596 {
597 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_ONEWAY_EN));
598 }
599
600 //-------------------------------------------------------------------------------------------------
601 /// Set MOBF encrypt key
602 /// @param u32WriteKey \b IN: Encrypt Key
603
604 /// @note
605 //-------------------------------------------------------------------------------------------------
MOBF_WriteKey(MS_U32 u32WriteKey)606 void MOBF_WriteKey(MS_U32 u32WriteKey)
607 {
608 REG32_W((&_SHARNGCtrl[0].MOBF_KeyW) , u32WriteKey);
609 }
610
611 //-------------------------------------------------------------------------------------------------
612 /// Set MOBF decrypt key
613 /// @param u32ReadKey \b IN: Decrypt Key
614
615 /// @note
616 //-------------------------------------------------------------------------------------------------
MOBF_ReadKey(MS_U32 u32ReadKey)617 void MOBF_ReadKey(MS_U32 u32ReadKey)
618 {
619 REG32_W((&_SHARNGCtrl[0].MOBF_KeyR) , u32ReadKey);
620 }
621
622 //-------------------------------------------------------------------------------------------------
623 /// Enable MOBF in MIU write port
624 /// @param bEnable \b IN: Enable/Disable
625
626 /// @note : MOBF Encrypt
627 //-------------------------------------------------------------------------------------------------
MOBF_WriteEnable(MS_BOOL bEnable)628 void MOBF_WriteEnable(MS_BOOL bEnable)
629 {
630 if(bEnable)
631 {
632 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
633 }
634 else
635 {
636 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
637 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_WRITE_EN));
638 }
639 }
640
641 //-------------------------------------------------------------------------------------------------
642 /// Enable MOBF in MIU read port
643 /// @param bEnable \b IN: Enable/Disable
644
645 /// @note : MOBF Decrypt
646 //-------------------------------------------------------------------------------------------------
MOBF_ReadEnable(MS_BOOL bEnable)647 void MOBF_ReadEnable(MS_BOOL bEnable)
648 {
649 if(bEnable)
650 {
651 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
652 }
653 else
654 {
655 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
656 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_READ_EN));
657 }
658 }
659
660 //-------------------------------------------------------------------------------------------------
661 /// Disable TDES
662 ///
663
664 /// @note : MOBF Decrypt
665 //-------------------------------------------------------------------------------------------------
MOBF_DisableTDES(void)666 void MOBF_DisableTDES(void)
667 {
668 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) & (~AESDMA_DMA_USE_TDES_EN));
669 }
670
AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)671 void AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)
672 {
673 MS_U32 u32Cmd = 0;
674
675 switch (eMode)
676 {
677 case E_AESDMA_PARSER_TS_PKT192:
678 u32Cmd |= (TS_MODE | PKT192_MODE);
679 break;
680
681 case E_AESDMA_PARSER_TS_PKT192_CLEAR:
682 u32Cmd |= (TS_MODE | PKT192_MODE | CLEAR_MODE);
683 break;
684
685 case E_AESDMA_PARSER_TS_PKT188:
686 u32Cmd |= (TS_MODE);
687 u32Cmd &= (~PKT192_MODE);
688 break;
689
690 case E_AESDMA_PARSER_TS_PKT188_CLEAR:
691 u32Cmd |= (TS_MODE | CLEAR_MODE);
692 u32Cmd &= (~PKT192_MODE);
693 break;
694
695 case E_AESDMA_PARSER_HDCP20_PKT192:
696 u32Cmd |= (HDCP20_MODE | PKT192_MODE);
697 break;
698
699 case E_AESDMA_PARSER_HDCP20_PKT192_CLEAR:
700 u32Cmd |= (HDCP20_MODE | PKT192_MODE | CLEAR_MODE);
701 break;
702
703 case E_AESDMA_PARSER_HDCP20_PKT188:
704 u32Cmd |= (HDCP20_MODE);
705 u32Cmd &= (~PKT192_MODE);
706 break;
707
708 case E_AESDMA_PARSER_HDCP20_PKT188_CLEAR:
709 u32Cmd |= (HDCP20_MODE | CLEAR_MODE);
710 u32Cmd &= (~PKT192_MODE);
711 break;
712
713 default:
714 return;
715 }
716
717 u32Cmd |= (AUTO_MODE | INIT_TRUST);
718 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~ParserCtrlSet)) | u32Cmd ) );
719 }
720
721
AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)722 void AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)
723 {
724 if(bEnable)
725 {
726 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
727 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (INSERT_SCRMB)) );
728 }
729 else
730 {
731 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
732 }
733 }
734
AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)735 void AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)
736 {
737 if(bEnable)
738 {
739 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
740 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (REMOVE_SCRMB)) );
741 }
742 else
743 {
744 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
745 }
746 }
747
AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)748 void AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)
749 {
750 if(bEnable)
751 {
752 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
753 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (TS_SCRMB_MASK)) );
754 }
755 else
756 {
757 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
758 }
759 }
760
AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)761 void AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)
762 {
763 if(bEnable)
764 {
765 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
766 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (BYPASS_PID)) );
767 }
768 else
769 {
770 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
771 }
772 }
773
AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)774 void AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)
775 {
776 MS_U32 u32Cmd = 0;
777
778 switch (ePattern)
779 {
780 case E_AESDMA_PARSER_SCRMB_10:
781 u32Cmd |= (SCRMB_PATTERN10);
782 break;
783
784 case E_AESDMA_PARSER_SCRMB_11:
785 u32Cmd |= (SCRMB_PATTERN11);
786 break;
787
788 default:
789 u32Cmd &= ~(SCRMB_PATTERN11);
790 break;
791 }
792
793 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~SCRMB_INITVALUE)) | u32Cmd ) );
794
795 }
796
AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)797 void AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)
798 {
799 MS_U32 u32Cmd = 0;
800
801 switch (ePattern)
802 {
803 case E_AESDMA_PARSER_SCRMB_10:
804 u32Cmd |= (SCRMB_PATTERN10_ADD);
805 break;
806
807 case E_AESDMA_PARSER_SCRMB_11:
808 u32Cmd |= (SCRMB_PATTERN11_ADD);
809 break;
810
811 default:
812 return;
813 }
814
815 REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_INITVALUE_ADD)) | u32Cmd ) );
816
817 }
818
AESDMA_Parser_Set_Pid(MS_U8 u8Index,MS_U16 u16Pid)819 void AESDMA_Parser_Set_Pid(MS_U8 u8Index, MS_U16 u16Pid)
820 {
821 if(u8Index==0)
822 {
823 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~PARSER_PID0_MASK)) | (u16Pid<<16) ) );
824 }
825 else if(u8Index==1)
826 {
827 REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~PARSER_PID1_MASK)) | u16Pid ) );
828 }
829 else
830 {
831 printf("Edison do not support other PID\n");
832 }
833 }
834
AESDMA_Parser_Query_PidCount(void)835 MS_U8 AESDMA_Parser_Query_PidCount(void)
836 {
837 return PARSER_PID_COUNT;
838 }
839
AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)840 void AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)
841 {
842 #if AESDMS_SECURED_BANK_EN
843 //
844 // Set HW Parser controlled by DSCRMB3
845 //
846 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)|AESDMA_DSCRMB3_HW_PASER_EN);
847 #else
848 //
849 // Set HW Parser controlled by DSCRMB5
850 //
851 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)&~(AESDMA_DSCRMB3_HW_PASER_EN));
852 #endif //#if AESDMS_SECURED_BANK_EN
853
854 if(bEnable)
855 {
856 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE)) );
857 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (HW_PARSER_MODE)) );
858 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (ENABLE_LG_PATCH)) );
859 }
860 else
861 {
862 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE)) );
863 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~ENABLE_LG_PATCH)) );
864 }
865
866 //make sure CC_CTRL_BY_ACPU is set 0
867 REG32_W((&_CIPHERCtrl[0].Cipher_Ctrl),( _AESDMA_REG32_R(&_CIPHERCtrl[0].Cipher_Ctrl) & (~CC_CTRL_BY_ACPU)) );
868 }
869
RSA_ClearInt(void)870 void RSA_ClearInt(void)
871 {
872 //RSA interrupt clear
873 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_INT_CLR));
874 }
875
RSA_Reset(void)876 void RSA_Reset(void)
877 {
878 //RSA Rst
879 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_RSA_RST));
880 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_RSA_RST));
881
882 //add polling RSA status before load data to SRAM
883 while (( RSA_GetStatus() & RSA_STATUS_RSA_BUSY ) != 0);
884 }
885
RSA_Ind32Ctrl(MS_U8 u8dirction)886 void RSA_Ind32Ctrl(MS_U8 u8dirction)
887 {
888 //[1] reg_ind32_direction 0: Read. 1: Write
889 if(u8dirction==1)
890 {
891 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_DIRECTION_WRITE));
892 }
893 else
894 {
895 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)&(~RSA_IND32_CTRL_DIRECTION_WRITE));
896 }
897
898 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_ADDR_AUTO_INC|RSA_IND32_CTRL_ACCESS_AUTO_START));
899
900 }
901
RSA_LoadSram(MS_U32 * u32Buf,RSA_IND32Address eMode)902 void RSA_LoadSram(MS_U32 *u32Buf, RSA_IND32Address eMode)
903 {
904 MS_U32 u32Cmd = 0;
905 MS_U32 i = 0;
906 MS_U32 WData_H = 0;
907 MS_U32 WData_L = 0;
908
909 switch (eMode)
910 {
911 case E_RSA_ADDRESS_E:
912 u32Cmd |= (RSA_E_BASE_ADDR);
913 break;
914
915 case E_RSA_ADDRESS_N:
916 u32Cmd |= (RSA_N_BASE_ADDR);
917 break;
918
919 case E_RSA_ADDRESS_A:
920 u32Cmd |= (RSA_A_BASE_ADDR);
921 break;
922
923 default:
924 return;
925 }
926
927 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Cmd));
928 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
929
930 for( i = 0; i < 64; i++ )
931 {
932 if( eMode == E_RSA_ADDRESS_E )
933 {
934 WData_L = (((*(u32Buf+i))>>8)&0xFF00)|(((*(u32Buf+i))>>24)&0xFF);
935 WData_H = (((*(u32Buf+i))>>8)&0xFF)|(((*(u32Buf+i))<<8)&0xFF00);
936 }
937 else
938 {
939 WData_L = (((*(u32Buf-i))>>8)&0xFF00)|(((*(u32Buf-i))>>24)&0xFF);
940 WData_H = (((*(u32Buf-i))>>8)&0xFF)|(((*(u32Buf-i))<<8)&0xFF00);
941 }
942
943 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_WDATA_MASK_L))|(WData_L<<16)));
944 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_WData) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&(~RSA_WDATA_MASK_H))|WData_H));
945 }
946
947 }
948
RSA_SetKeyLength(MS_U32 u32keylen)949 void RSA_SetKeyLength(MS_U32 u32keylen)
950 {
951 //[13:8] n_len_e: key length
952 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_KEY_LENGTH_MASK))|(u32keylen<<8));
953 }
954
RSA_SetKeyType(MS_U8 u8hwkey,MS_U8 u8pubkey)955 void RSA_SetKeyType(MS_U8 u8hwkey, MS_U8 u8pubkey)
956 {
957 //[1] hw_key_e : 0 : software key, 1: hardware key
958 //[2] e_pub_e : 0: pvivate key, 1: public key
959 if(u8hwkey==1)
960 {
961 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_HW_KEY));
962 }
963 else
964 {
965 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_HW_KEY));
966 }
967
968 if(u8pubkey==1)
969 {
970 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_PUBLIC_KEY));
971 }
972 else
973 {
974 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_PUBLIC_KEY));
975 }
976
977 }
978
RSA_ExponetialStart(void)979 void RSA_ExponetialStart(void)
980 {
981 //RSA exp start
982 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_EXP_START));
983 }
984
RSA_GetStatus(void)985 MS_U32 RSA_GetStatus(void)
986 {
987 return _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl) & RSA_STATUS_MASK;
988 }
989
RSA_FileOutStart(void)990 void RSA_FileOutStart(void)
991 {
992 //RSA ind32_start
993 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
994 }
995
RSA_SetFileOutAddr(MS_U32 u32offset)996 void RSA_SetFileOutAddr(MS_U32 u32offset)
997 {
998 MS_PHY u32Addr = 0;
999 u32Addr = RSA_Z_BASE_ADDR + u32offset;
1000
1001 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Addr));
1002 }
1003
RSA_FileOut(void)1004 MS_U32 RSA_FileOut(void)
1005 {
1006 MS_U32 u32out_L = 0;
1007 MS_U32 u32out_H = 0;
1008
1009 u32out_L = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&RSA_RDATA_MASK_L)>>16;
1010 u32out_H = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)&RSA_RDATA_MASK_H)<<16;
1011
1012 return (u32out_H|u32out_L);
1013 }
1014
RSA_Get_RSA_IsFinished(void)1015 MS_U32 RSA_Get_RSA_IsFinished(void)
1016 {
1017 return (RSA_GetStatus()&RSA_STATUS_RSA_BUSY);
1018 }
1019
1020 //reserved for secure protect function
1021 /*
1022 void AESDMA_Secure_SetCipherKey(MS_U32 *cipherkey)
1023 {
1024 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_L.Key_L) , cipherkey[0]);
1025 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_L.Key_H) , cipherkey[1]);
1026 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_H.Key_L) , cipherkey[2]);
1027 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_H.Key_H) , cipherkey[3]);
1028 }
1029
1030 void AESDMA_Secure_SetInitVector(MS_U32 *pInitVector)
1031 {
1032 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_L.IV_L), pInitVector[0]);
1033 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_L.IV_H), pInitVector[1]);
1034 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_H.IV_L), pInitVector[2]);
1035 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_H.IV_H), pInitVector[3]);
1036 }
1037
1038 void AESDMA_SecureProtect(MS_BOOL bEnable)
1039 {
1040 if(bEnable)
1041 {
1042 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl)|(AESDMA_SECURE_PROTECT_S));
1043 }
1044 else
1045 {
1046 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl)&(~AESDMA_SECURE_PROTECT_S));
1047 }
1048 }
1049
1050 void AESDMA_Set_FileOutEnable(MS_BOOL bEnable)
1051 {
1052 if (bEnable)
1053 {
1054 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) |AESDMA_CTRL_FILEIN_START));
1055 }
1056 else
1057 {
1058 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) &~AESDMA_CTRL_FILEIN_START));
1059 }
1060 }
1061
1062 void AESDMA_Secure_Start(MS_BOOL AESDMAStart)
1063 {
1064 if (AESDMAStart)
1065 {
1066 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) &~AESDMA_SECURE_FILEIN_START));
1067 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) | AESDMA_SECURE_FILEIN_START));
1068 }
1069 else
1070 {
1071 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) &~AESDMA_SECURE_FILEIN_START));
1072 }
1073 }
1074
1075 MS_U32 AESDMA_Get_AESDMA_SecureIsFinished(void)
1076 {
1077 return (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_status) & AESDMA_DONE_S);
1078 }
1079
1080 */
1081
1082 //-------------------------------------------------------------------------------------------------
1083 /// Get status of Secret Key in Normal bank
1084 /// @param N/A
1085 /// @note : Get Status
1086 //-------------------------------------------------------------------------------------------------
AESDMA_IsSecretKeyInNormalBank(void)1087 MS_U32 AESDMA_IsSecretKeyInNormalBank(void)
1088 {
1089 return (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl) & (SECRET_KEY_IN_NORMAL_BANK));
1090 }
1091
1092 //-------------------------------------------------------------------------------------------------
1093 /// Enable Two keys (Odd/Even) in using HW auto select key.
1094 /// @param bEnable \b IN: Enable/Disable
1095
1096 /// @note : Hardware Parser Decrypt
1097 //-------------------------------------------------------------------------------------------------
AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)1098 void AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)
1099 {
1100 if(bEnable)
1101 {
1102 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (SCRMB_ENABLE_TWO_KEY) );
1103 }
1104 else
1105 {
1106 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_ENABLE_TWO_KEY) );
1107 }
1108 }
1109
1110 //-------------------------------------------------------------------------------------------------
1111 /// Set Odd keys in using HW auto select key.
1112 /// @param cipherkey
1113 /// @note : Hardware Parser Decrypt
1114 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherOddKey(MS_U32 * cipherkey)1115 void AESDMA_Set_CipherOddKey(MS_U32 *cipherkey)
1116 {
1117 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
1118 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
1119 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
1120 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
1121 }
1122
1123 //-------------------------------------------------------------------------------------------------
1124 /// Set Odd IVs in using HW auto select key.
1125 /// @param cipherkey
1126 /// @note : Hardware Parser Decrypt
1127 //-------------------------------------------------------------------------------------------------
AESDMA_Set_OddInitVector(MS_U32 * pInitVector)1128 void AESDMA_Set_OddInitVector(MS_U32 *pInitVector)
1129 {
1130 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_L), pInitVector[0]);
1131 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_H), pInitVector[1]);
1132 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_L), pInitVector[2]);
1133 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_H), pInitVector[3]);
1134 }
1135
1136 //-------------------------------------------------------------------------------------------------
1137 /// Set Even keys in using HW auto select key.
1138 /// @param cipherkey
1139 /// @note : Hardware Parser Decrypt
1140 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherEvenKey(MS_U32 * cipherkey)1141 void AESDMA_Set_CipherEvenKey(MS_U32 *cipherkey)
1142 {
1143 AESDMA_Set_CipherKey(cipherkey);
1144 }
1145
1146 //-------------------------------------------------------------------------------------------------
1147 /// Set Even IVs in using HW auto select key.
1148 /// @param cipherkey
1149 /// @note : Hardware Parser Decrypt
1150 //-------------------------------------------------------------------------------------------------
AESDMA_Set_EvenInitVector(MS_U32 * pInitVector)1151 void AESDMA_Set_EvenInitVector(MS_U32 *pInitVector)
1152 {
1153 AESDMA_Set_InitVector(pInitVector);
1154 }
1155
1156 //-------------------------------------------------------------------------------------------------
1157 /// Set HDCP Data
1158 /// @param u8Idx \b IN: Index
1159 /// @param pu8Data \b IN: Content Keys
1160 /// @param pu8privData \b IN: RIV
1161 /// @note : Set HDCP2.2
1162 //-------------------------------------------------------------------------------------------------
HDCP_ProcessCipher(MS_U8 u8Idx,MS_U8 * pu8Data,MS_U8 * pu8privData)1163 void HDCP_ProcessCipher (MS_U8 u8Idx, MS_U8 *pu8Data, MS_U8* pu8privData)
1164 {
1165 REG_HDCP22Data *pData = NULL;
1166 REG_HDCP22SEKCtrl *pCtrl = NULL;
1167 MS_U16 offset = 0;
1168 MS_U16 BKOffset = 0;
1169
1170 MS_U32 *cipherkey = (MS_U32 *)((void *)pu8Data);
1171 MS_U32 *riv = (MS_U32 *)((void *)pu8privData);
1172
1173 offset = u8Idx * (sizeof(REG_HDCP22Data) >> 1);
1174 BKOffset = u8Idx * 0x300;
1175
1176 pData = (REG_HDCP22Data*)((MS_U16*)_HDCP22Data + offset);
1177 pCtrl = (REG_HDCP22SEKCtrl*)((MS_U16*)_HDCP22SekCtrl + BKOffset);
1178
1179 //Content Keys
1180 REG32_W((&pData[0].Hdcp22_ContentKey[0]) , cipherkey[0]);
1181 REG32_W((&pData[0].Hdcp22_ContentKey[1]) , cipherkey[1]);
1182 REG32_W((&pData[0].Hdcp22_ContentKey[2]) , cipherkey[2]);
1183 REG32_W((&pData[0].Hdcp22_ContentKey[3]) , cipherkey[3]);
1184
1185 //RIV
1186 REG32_W((&pData[0].Hdcp22_Riv[0]) , riv[0]);
1187 REG32_W((&pData[0].Hdcp22_Riv[1]) , riv[1]);
1188
1189 //Set SKE successful
1190 REG32_W((&pCtrl[0].SEK), (_AESDMA_REG32_R(&pCtrl[0].SEK) | HDCP_SEK_BIT0));
1191 }
1192
1193 //-------------------------------------------------------------------------------------------------
1194 /// Get the status of HW supports HDCP2.2
1195 /// @param N/A
1196 /// @note : Support HDCP2.2
1197 //-------------------------------------------------------------------------------------------------
HDCP_GetHdcpCipherState(MS_U8 u8Idx,MS_U8 * pu8State)1198 void HDCP_GetHdcpCipherState(MS_U8 u8Idx, MS_U8 *pu8State)
1199 {
1200 #define HDCP_SUPPORT_EN 0x00000001
1201 REG_HDCP22SEKCtrl *pCtrl = NULL;
1202 MS_U16 offset = 0;
1203 MS_U16 BKOffset = 0;
1204
1205 offset = u8Idx * (sizeof(REG_HDCP22Data) >> 1);
1206 BKOffset = u8Idx * 0x300;
1207
1208 pCtrl = (REG_HDCP22SEKCtrl*)((MS_U16*)_HDCP22SekCtrl + BKOffset);
1209
1210 *pu8State = (MS_U8)(_AESDMA_REG32_R(&pCtrl[0].SEK) & HDCP_SUPPORT_EN);
1211 }
1212
1213 //-------------------------------------------------------------------------------------------------
1214 /// Reset AESDMA
1215 /// @param N/A
1216 /// @note : Clear Registers, not to do sw reset
1217 //-------------------------------------------------------------------------------------------------
AESDMA_NormalReset(void)1218 void AESDMA_NormalReset(void)
1219 {
1220 MS_VIRT Reg_AESDMA;
1221 MS_U32 i = 0;
1222 Reg_AESDMA = (MS_VIRT)(&_AESDMACtrl[0].Dma_Ctrl);
1223
1224 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
1225
1226 // reset all AESdma register
1227 for (i = 0 ; i < 19 ; i++)
1228 {
1229 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
1230 }
1231 // reset secure_dma3_ctrl register
1232 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
1233
1234 // reset hw_parser_ctrl register
1235 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000);
1236 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
1237 }
1238
AESDMA_Set_SecureBankEnable(MS_BOOL bEnable)1239 void AESDMA_Set_SecureBankEnable (MS_BOOL bEnable)
1240 {
1241 #ifdef MSOS_TYPE_NUTTX
1242 if ( bEnable == TRUE)
1243 {
1244 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl) |(AESDMA_SECURE_PROTECT_S | AESDMA_SECURE_PROTECT_SHA_S | AESDMA_SECURE_PROTECT_RSA_S));
1245 }
1246 else
1247 {
1248 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl) &~(AESDMA_SECURE_PROTECT_S | AESDMA_SECURE_PROTECT_SHA_S | AESDMA_SECURE_PROTECT_RSA_S));
1249 }
1250 #endif
1251 }
1252
HAL_AESDMA_HDMI_GetM0(AESDMA_HDMI_INPUT_PORT enInputPortType,MS_U8 * pu8Data)1253 void HAL_AESDMA_HDMI_GetM0(AESDMA_HDMI_INPUT_PORT enInputPortType, MS_U8 *pu8Data)
1254 {
1255 MS_U16 u16bank_offset;
1256 MS_U32 m0[2];
1257 MS_U8* buf = (MS_U8*)m0;
1258 int i;
1259
1260 switch(enInputPortType)
1261 {
1262 default:
1263 case E_AESDMA_HDMI_INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200
1264 case E_AESDMA_HDMI_INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500
1265 case E_AESDMA_HDMI_INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800
1266 case E_AESDMA_HDMI_INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00
1267 }
1268
1269 // read 8 bytes
1270 for(i = 0; i < 2; ++i)
1271 {
1272 m0[i] = _AESDMA_REG32_R(&((REG_HDCP14SEKCtrl*)((MS_U16*)_HDCP14SekCtrl + u16bank_offset))[i].REG_0001);
1273 }
1274 for (i = 0; i < 8; ++i)
1275 {
1276 pu8Data[i] = buf[i];
1277 }
1278 }
1279
1280 //-------------------------------------------------------------------------------------------------
1281 /// Set Index of KSlot
1282 /// @param u32Index
1283 /// @param bEnable \b IN: TRUE: For Odd Key/FALSE: For Even Key
1284 /// @note : AESDMA AES CTR64
1285 //-------------------------------------------------------------------------------------------------
AESDMA_SetKeyIndex(MS_U32 u32Index,MS_BOOL bIsOddKey)1286 void AESDMA_SetKeyIndex (MS_U32 u32Index, MS_BOOL bIsOddKey)
1287 {
1288 if ( (u32Index < 0x10 || u32Index > 0x1F) && (u32Index != 0)) {
1289 return;
1290 }
1291 MS_U32 u32Value = 0;
1292 #if AESDMS_SECURED_BANK_EN
1293 //
1294 // For Secured Bank
1295 //
1296 if (bIsOddKey == FALSE) {
1297 //Even Key (default key), [7:0]
1298 u32Value = _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001) & 0xFFFFFF00;
1299 //Set Key Index, 0 = Default key
1300 u32Value = u32Index == 0 ? (u32Value | 0x1) : (u32Value | u32Index);
1301 }
1302 else {
1303 //Odd Key (HW Parser key)
1304 u32Value = _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001) & 0xFFFF00FF;
1305 //Set Key Index, 0 = Default key
1306 u32Value = u32Index == 0 ? (u32Value | 0x2) : (u32Value | ((u32Index<<8) & 0xFF00));
1307 }
1308 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , u32Value);
1309 #else
1310 //
1311 // For Normal Bank
1312 //
1313 if (bIsOddKey == FALSE) {
1314 //Even Key (default key), [7:0]
1315 u32Value = _AESDMA_REG32_R(&_AESDSCMB7Ctrl[0].Reg0001) & 0xFFFFFF00;
1316 //Set Key Index, 0 = Default key
1317 u32Value = u32Index == 0 ? (u32Value | 0x0) : (u32Value | u32Index);
1318 }
1319 else {
1320 //Odd Key (HW Parser key)
1321 u32Value = _AESDMA_REG32_R(&_AESDSCMB7Ctrl[0].Reg0001) & 0xFFFF00FF;
1322 //Set Key Index, 0 = Default key
1323 u32Value = u32Index == 0 ? (u32Value | 0x2) : (u32Value | ((u32Index<<8) & 0xFF00));
1324 }
1325 REG32_W((&_AESDSCMB7Ctrl[0].Reg0001) , u32Value);
1326 #endif //#if AESDMS_SECURED_BANK_EN
1327 }
1328
1329 //-------------------------------------------------------------------------------------------------
1330 /// Enable AES CTR64
1331 /// @param bEnable \b IN: Enable/Disable
1332 /// @note : AESDMA AES CTR64
1333 //-------------------------------------------------------------------------------------------------
AESDMA_SET_CTR64(MS_BOOL bEnable)1334 void AESDMA_SET_CTR64(MS_BOOL bEnable)
1335 {
1336 if(bEnable)
1337 {
1338 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern_Mask), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PS_Pattern_Mask)|AESDMA_CTR_IV_LSB64);
1339 }
1340 else
1341 {
1342 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern_Mask), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PS_Pattern_Mask) & ~AESDMA_CTR_IV_LSB64);
1343 }
1344 }
1345
1346 //-------------------------------------------------------------------------------------------------
1347 /// Select Efuse key
1348 /// @param u8KeyIdx \b IN: the index of efuse key
1349 /// @note : Select Efuse Key
1350 //-------------------------------------------------------------------------------------------------
AESDMA_SetSecureKeyIdx(MS_U8 u8KeyIdx)1351 void AESDMA_SetSecureKeyIdx (MS_U8 u8KeyIdx)
1352 {
1353 MS_U32 u32Ctrl;
1354 u32Ctrl = _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2);
1355
1356 switch (u8KeyIdx)
1357 {
1358 case 1:
1359 u32Ctrl &= ~AESDMA_USE_SECRET_KEY2;
1360 u32Ctrl |= AESDMA_USE_SECRET_KEY;
1361 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), u32Ctrl);
1362 break;
1363 case 2:
1364 u32Ctrl |= AESDMA_USE_SECRET_KEY2;
1365 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), u32Ctrl);
1366 break;
1367 }
1368 }
1369
AESDMA_POWER_SUSPEND(void)1370 MS_BOOL AESDMA_POWER_SUSPEND(void)
1371 {
1372 SECUREBASECtrl_Buffer = _AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0001);
1373 return TRUE;
1374 }
1375
AESDMA_POWER_RESUME(void)1376 MS_BOOL AESDMA_POWER_RESUME(void)
1377 {
1378 REG32_W((&_SECUREBASECtrl[0].Reg0001), SECUREBASECtrl_Buffer);
1379 return TRUE;
1380 }
1381