1 ////////////////////////////////////////////////////////////////////////////////
2 //
3 // Copyright (c) 2006-2013 MStar Semiconductor, Inc.
4 // All rights reserved.
5 //
6 // Unless otherwise stipulated in writing, any and all information contained
7 // herein regardless in any format shall remain the sole proprietary of
8 // MStar Semiconductor Inc. and be kept in strict confidence
9 // ("MStar Confidential Information") by the recipient.
10 // Any unauthorized act including without limitation unauthorized disclosure,
11 // copying, use, reproduction, sale, distribution, modification, disassembling,
12 // reverse engineering and compiling of the contents of MStar Confidential
13 // Information is unlawful and strictly prohibited. MStar hereby reserves the
14 // rights to any and all damages, losses, costs and expenses resulting therefrom.
15 //
16 ////////////////////////////////////////////////////////////////////////////////
17
18 ////////////////////////////////////////////////////////////////////////////////////////////////////
19 // file halCIPHER.c
20 // @brief CIPHER HAL
21 // @author MStar Semiconductor,Inc.
22 ////////////////////////////////////////////////////////////////////////////////////////////////////
23 #ifdef MSOS_TYPE_LINUX_KERNEL
24 #include <linux/string.h>
25 #include <linux/uaccess.h>
26 #include <linux/compat.h>
27 #else
28 #include <stdio.h>
29 #include <string.h>
30 #endif
31
32
33 #include "MsCommon.h"
34 #include "regCIPHER.h"
35 #include "halCIPHER.h"
36 #include "drvCIPHER.h"
37 #include "halCHIP.h"
38
39 #ifndef MSOS_TYPE_LINUX_KERNEL
40 extern void * memset ( void * ptr, int value, size_t num );
41 extern void * memcpy ( void * destination, const void * source, size_t num );
42 extern int printf ( const char * format, ... );
43 #endif
44 //--------------------------------------------------------------------------------------------------
45 // Driver Compiler Option
46 //--------------------------------------------------------------------------------------------------
47
48 //--------------------------------------------------------------------------------------------------
49 // Macro of bit operations
50 //--------------------------------------------------------------------------------------------------
51 #define DELAY_WAITING 1UL
52 #define DELAY_RESCHEDULE 10UL
53 #define COMQ_AVALIABLE 0x10UL
54 #define CIPHER_KEY_SIZE 16UL
55 #define CRYPTODMA_DEBUG_SIZE 32UL
56 #define HASH_MANUAL_BLOCK_SIZE 64UL
57 #define PID_SIZE 2UL
58 #define MIU_SELECT_BIT 0x80000000UL
59
60 //--------------------------------------------------------------------------------------------------
61 // TSP Hardware Abstraction Layer
62 //--------------------------------------------------------------------------------------------------
63 static MS_VIRT _u32RegBase = 0;
64 static REG_AESDMACtrl *_AESDMACtrl = 0 ;
65 static CIPHER_DBGMSG_LEVEL _HAL_CIPHERDBGLevel = CIPHER_DBG_ERR;
66
67 // Algorithm Table for AES/TDES/DES
68 static MS_BOOL _CryptodMA_AlgoTable[4][E_DMA_MODE_NUM][E_DMA_RESIDUE_NUM][E_DMA_SB_NUM];
69
70
71 #define REG32_W(reg, value) do { \
72 (reg)->H = ((value) >> 16); \
73 (reg)->L = ((value) & 0x0000FFFF); \
74 } while(0)
75
76 #define REG32(addr) (*(volatile MS_U32 *) (addr))
77 #define REG16(add) *((volatile MS_U16 *)(add))
78
79 #ifdef CIPHER_NO_PRINTF
80 #define HAL_DEBUG_CIPHER(debug_level, x)
81 #else
82 #define HAL_DEBUG_CIPHER(debug_level, x) do { if (_HAL_CIPHERDBGLevel >= (debug_level)) (x); } while(0)
83 #endif
84 //--------------------------------------------------------------------------------------------------
85 // Local Variable
86 //--------------------------------------------------------------------------------------------------
87
88 MS_PHY _u32DmaInAddr;
89 MS_U32 _u32DmaInNum;
90 MS_PHY _u32DmaOut_StartAddr;
91 MS_PHY _u32DmaOut_EndAddr;
92 MS_PHY _u32ReportAddr;
93 MS_U32 _u32OTPHashLengthPadding;
94
95 MS_U8 _pu8CipherKey[CIPHER_KEY_SIZE];
96 MS_U8 _pu8CipherKey2[CIPHER_KEY_SIZE];
97 MS_U8 _pu8IV[CIPHER_KEY_SIZE];
98 MS_U8 _pu8IV2[CIPHER_KEY_SIZE];
99 MS_U8 _pu8Data[CIPHER_KEY_SIZE];
100 MS_U8 _pu8PID0[PID_SIZE];
101 MS_U8 _pu8PID1[PID_SIZE];
102
103 MS_U32 _u32CmdLen = 0 ;
104
105 // [NOTE] Solve Strict-Aliasing //
106 union {
107 CMD_DmaFormat0 DmaCtrl0;
108 MS_U32 u32DmaCtrl0;
109 }_uDmaCtrl0;
110
111 union{
112 CMD_DmaFormat1 DmaCtrl1;
113 MS_U32 u32DmaCtrl1;
114 }_uDmaCtrl1;
115
116 union{
117 CMD_DmaFormat2 DmaCtrl2;
118 MS_U32 u32DmaCtrl2;
119 }_uDmaCtrl2;
120
121 union{
122 CMD_DmaFormat3 DmaCtrl3;
123 MS_U32 u32DmaCtrl3;
124 }_uDmaCtrl3;
125
126 union{
127 Hash_DmaFormat0 HashCtrl0;
128 MS_U32 u32HashCtrl0;
129 }_uHashCtrl0;
130
131 union{
132 Hash_DmaFormat1 HashCtrl1;
133 MS_U32 u32HashCtrl1;
134 }_uHashCtrl1;
135
136 union{
137 CMD_HashFormat2 HashCtrl2;
138 MS_U32 u32HashCtrl2;
139 }_uHashCtrl2;
140
141 MS_PHY _u32HashSrcAddr;
142 MS_PHY _u32HashDestAddr;
143 MS_U32 _u32InitWordCnt;
144 MS_U32 _u32HashMsgLen;
145
146 MS_U8 _pu8HashIV[HASH_CMD_IV_SIZE];
147 MS_U8 _pu8HashMsg[HASH_CMD_MSG_SIZE];
148 MS_U8 _pu8HashHMACHostKey[HASH_CMD_HMAC_HOSTKEY_SIZE];
149
150 static MS_U32 _CIPHER_CAVid = 0x0F;
151
152 //--------------------------------------------------------------------------------------------------
153 // Inline Function
154 //--------------------------------------------------------------------------------------------------
WRITE_CMDQ(MS_U32 u32Value)155 void WRITE_CMDQ(MS_U32 u32Value)
156 {
157 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s] = 0x%08X \n",__func__, (unsigned int)(u32Value)));
158 REG32(&_AESDMACtrl->Cmd_Queue) = (u32Value) ;
159 }
160
_HAL_CIPHER_TransMIUAddr(MS_PHY * phyAddr)161 MS_BOOL _HAL_CIPHER_TransMIUAddr(MS_PHY* phyAddr)
162 {
163 CHIP_MIU_ID eMIUSel;
164 MS_PHY phyOffset;
165
166 if(NULL == phyAddr)
167 {
168 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]NULL Address!\n",__func__, __LINE__));
169 return FALSE;
170 }
171
172 _phy_to_miu_offset(eMIUSel,phyOffset,*phyAddr);
173
174 if(E_CHIP_MIU_0 == eMIUSel)
175 {
176 *phyAddr = phyOffset;
177 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Physical address trans to MIU0\n",__func__, __LINE__));
178 }
179 else
180 {
181 *phyAddr = (phyOffset | MIU_SELECT_BIT);
182 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Physical address trans to MIU1\n",__func__, __LINE__));
183 }
184
185 return TRUE;
186 }
187
_HAL_CIPHER_GetCmdLen(HAL_CIPHER_CMDTYPE CmdType)188 MS_U32 _HAL_CIPHER_GetCmdLen(HAL_CIPHER_CMDTYPE CmdType)
189 {
190
191 MS_U32 u32CmdLen = 0 ;
192
193
194 if ( E_CIPHER_TYPE_DMA == CmdType )
195 {
196 u32CmdLen = 7;
197
198 if ( _uDmaCtrl1.DmaCtrl1.RR == TRUE )
199 {
200 u32CmdLen += 1 ;
201 }
202 if ( _uDmaCtrl0.DmaCtrl0.DIV == TRUE )
203 {
204 u32CmdLen += 4 ;
205 }
206 if ( _uDmaCtrl1.DmaCtrl1.SD == E_DMA_SRC_DIRECT )
207 {
208 u32CmdLen += 4 ;
209 }
210 if ( _uDmaCtrl0.DmaCtrl0.DK == TRUE )
211 {
212 u32CmdLen += 4 ;
213 }
214 if ( _uDmaCtrl2.DmaCtrl2.HP == TRUE )
215 {
216 u32CmdLen += 1 ;
217 }
218 if ( _uDmaCtrl3.DmaCtrl3.DK2 == TRUE )
219 {
220 u32CmdLen += 4 ;
221 }
222 if ( _uDmaCtrl3.DmaCtrl3.DIV2 == TRUE )
223 {
224 u32CmdLen += 4 ;
225 }
226
227 return u32CmdLen ;
228 }
229
230
231 if ( E_CIPHER_TYPE_SHA == CmdType )
232 {
233
234 u32CmdLen = 3 ;
235
236 if (_uHashCtrl0.HashCtrl0.CMD == CMD_HASH_START_RR )
237 {
238 u32CmdLen += 1 ;
239 }
240
241 if (_uHashCtrl0.HashCtrl0.Src != CMD_HASH_SRC_REG )
242 {
243 u32CmdLen += 1 ;
244 }
245
246 if(_uHashCtrl2.HashCtrl2.RR == TRUE)
247 {
248 u32CmdLen += 1 ;
249 }
250
251 if (_uHashCtrl0.HashCtrl0.IWC_Sel == CMD_HASH_IWC_CMDQ )
252 {
253 u32CmdLen += 1 ;
254 }
255
256 if ((_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_DRAM ) || (_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_R2 ))
257 {
258 u32CmdLen += 1 ;
259 }
260
261 if (_uHashCtrl0.HashCtrl0.InitHashSel == CMD_HASH_IV_CMD )
262 {
263 u32CmdLen += 8 ;
264 }
265
266 if (_uHashCtrl0.HashCtrl0.Src == CMD_HASH_SRC_REG )
267 {
268 u32CmdLen += 16 ;
269 }
270
271 if((_uHashCtrl0.HashCtrl0.HMAC_KeySel == CMD_HMAC_KSEL_HK) && (_uHashCtrl0.HashCtrl0.DK == CMD_HMAC_KSEL_DIR_HK))
272 {
273 u32CmdLen += 4 ;
274 }
275
276 return u32CmdLen ;
277
278 }
279
280 if ( E_CIPHER_TYPE_OTPHASH == CmdType )
281 {
282 u32CmdLen = 7 ;
283
284 if ( _uDmaCtrl1.DmaCtrl1.NL == TRUE )
285 {
286 u32CmdLen += 1 ;
287 }
288 if ( _uDmaCtrl1.DmaCtrl1.RR == TRUE )
289 {
290 u32CmdLen += 1 ;
291 }
292 if ( _uDmaCtrl3.DmaCtrl3.AP == TRUE && _uDmaCtrl3.DmaCtrl3.IK == FALSE)
293 {
294 u32CmdLen += 1 ;
295 }
296
297 return u32CmdLen ;
298 }
299
300
301 return 0 ;
302
303 }
304
_HAL_CIPHER_TransKey(CIPHER_KEY_SRC src,MS_U32 idx)305 HAL_CIPHER_KEYSRC _HAL_CIPHER_TransKey(CIPHER_KEY_SRC src, MS_U32 idx)
306 {
307 HAL_CIPHER_KEYSRC KeySrc = E_DMA_KSEL_REGKEY;
308
309 if(src == E_CIPHER_KSRC_KL)
310 {
311 KeySrc = E_DMA_KSEL_SK0 + idx;
312 }
313 else if(src == E_CIPHER_KSRC_OTP)
314 {
315 KeySrc = E_DMA_KSEL_MK0 + idx;
316 }
317 else if(src == E_CIPHER_KSRC_CPU)
318 {
319 KeySrc = E_DMA_KSEL_REGKEY;
320 }
321 else if(src == E_CIPHER_KSRC_CAIP)
322 {
323 KeySrc = E_DMA_KSEL_CAIP;
324 }
325
326 return KeySrc;
327 }
328
_HAL_CIPHER_TransMainAlgo(CIPHER_MAIN_ALGO algo)329 HAL_CIPHER_ALGO _HAL_CIPHER_TransMainAlgo(CIPHER_MAIN_ALGO algo)
330 {
331 HAL_CIPHER_ALGO hal_algo;
332 switch(algo)
333 {
334 case E_CIPHER_MAIN_AES:
335 hal_algo = E_DMA_ALGO_AES;
336 break;
337 case E_CIPHER_MAIN_DES:
338 hal_algo = E_DMA_ALGO_DES;
339 break;
340 case E_CIPHER_MAIN_TDES:
341 hal_algo = E_DMA_ALGO_TDES;
342 break;
343 case E_CIPHER_MAIN_M6_S56_CCBC:
344 hal_algo = E_DMA_ALGO_M6_S56_CCBC;
345 break;
346 case E_CIPHER_MAIN_M6_S56:
347 hal_algo = E_DMA_ALGO_M6_S56;
348 break;
349 case E_CIPHER_MAIN_M6_KE56:
350 hal_algo = E_DMA_ALGO_M6_KE56;
351 break;
352 case E_CIPHER_MAIN_RC4:
353 hal_algo = E_DMA_ALGO_RC4;
354 break;
355 default:
356 hal_algo = E_DMA_ALGO_NONE;
357 }
358
359 return hal_algo;
360 }
361
_HAL_CIPHER_TransSubAlgo(CIPHER_SUB_ALGO algo)362 HAL_CIPHER_MODE _HAL_CIPHER_TransSubAlgo(CIPHER_SUB_ALGO algo)
363 {
364 HAL_CIPHER_MODE hal_algo;
365 switch(algo)
366 {
367 case E_CIPHER_SUB_ECB:
368 hal_algo = E_DMA_MODE_ECB;
369 break;
370 case E_CIPHER_SUB_CBC:
371 hal_algo = E_DMA_MODE_CBC;
372 break;
373 case E_CIPHER_SUB_CTR:
374 hal_algo = E_DMA_MODE_CTR;
375 break;
376 case E_CIPHER_SUB_CBC_MAC:
377 hal_algo = E_DMA_MODE_CBC_MAC;
378 break;
379 case E_CIPHER_SUB_CTR_64:
380 hal_algo = E_DMA_MODE_CTR_64;
381 break;
382 case E_CIPHER_SUB_CMAC_Key:
383 hal_algo = E_DMA_MODE_CMAC_Key;
384 break;
385 case E_CIPHER_SUB_CMAC_Algo:
386 hal_algo = E_DMA_MODE_CMAC_Algo;
387 break;
388 case E_CIPHER_SUB_PCBC_ADD:
389 hal_algo = E_DMA_MODE_PCBC_ADD;
390 break;
391 case E_CIPHER_SUB_PCBC_XOR:
392 hal_algo = E_DMA_MODE_PCBC_XOR;
393 break;
394 case E_CIPHER_SUB_OTPHASH:
395 hal_algo = E_DMA_MODE_OTPHASH;
396 break;
397 default:
398 hal_algo = E_DMA_MODE_NONE;
399 }
400
401 return hal_algo;
402
403 }
404
_HAL_CIPHER_TransResAlgo(CIPHER_RES_ALGO algo)405 HAL_CIPHER_RESIDUE _HAL_CIPHER_TransResAlgo(CIPHER_RES_ALGO algo)
406 {
407 HAL_CIPHER_RESIDUE hal_algo;
408 switch(algo)
409 {
410 case E_CIPHER_RES_CLR:
411 hal_algo = E_DMA_RESIDUE_CLR;
412 break;
413 case E_CIPHER_RES_CTS:
414 hal_algo = E_DMA_RESIDUE_CTS;
415 break;
416 case E_CIPHER_RES_SCTE52:
417 hal_algo = E_DMA_RESIDUE_SCTE52;
418 break;
419 default:
420 hal_algo = E_DMA_RESIDUE_NONE;
421 }
422
423 return hal_algo;
424 }
425
_HAL_CIPHER_TransSBAlgo(CIPHER_SB_ALGO algo)426 HAL_CIPHER_SHORTBLOCK _HAL_CIPHER_TransSBAlgo(CIPHER_SB_ALGO algo)
427 {
428 HAL_CIPHER_SHORTBLOCK hal_algo;
429 switch(algo)
430 {
431 case E_CIPHER_SB_CLR:
432 hal_algo = E_DMA_SB_CLR;
433 break;
434 case E_CIPHER_SB_IV1:
435 hal_algo = E_DMA_SB_IV1;
436 break;
437 case E_CIPHER_SB_IV2:
438 hal_algo = E_DMA_SB_IV2;
439 break;
440 default:
441 hal_algo = E_DMA_SB_NONE;
442 }
443
444 return hal_algo;
445
446 }
447
_HAL_CIPHER_TransHASHAlgo(CIPHER_HASH_ALGO algo)448 HAL_CIPHER_HASHMODE _HAL_CIPHER_TransHASHAlgo(CIPHER_HASH_ALGO algo)
449 {
450 HAL_CIPHER_HASHMODE hal_algo;
451 switch(algo)
452 {
453 case E_CIPHER_HASH_ALGO_SHA1:
454 hal_algo = E_HASH_SHA1;
455 break;
456 case E_CIPHER_HASH_ALGO_SHA256:
457 hal_algo = E_HASH_SHA256;
458 break;
459 case E_CIPHER_HASH_ALGO_MD5:
460 hal_algo = E_HASH_MD5;
461 break;
462 default:
463 hal_algo = E_HASH_SHA256;
464 }
465
466 return hal_algo;
467 }
468
HAL_CIPHER_DMA_AlgoTable_Init(void)469 void HAL_CIPHER_DMA_AlgoTable_Init(void)
470 {
471
472 memset(_CryptodMA_AlgoTable , 0x0 , sizeof(_CryptodMA_AlgoTable));
473
474 // AES algorithms //
475 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
476 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
477 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
478 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
479 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
480 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
481 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
482 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CBC_MAC][E_DMA_RESIDUE_CLR][E_DMA_RESIDUE_CLR] = TRUE ;
483 _CryptodMA_AlgoTable[E_DMA_ALGO_AES][E_DMA_MODE_CTR][E_DMA_RESIDUE_NONE][E_DMA_SB_NONE] = TRUE ; // residue & sb don't care
484
485 // DES Algorithms //
486 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
487 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
488 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
489 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
490 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
491 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
492 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV2] = TRUE ;
493 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
494 _CryptodMA_AlgoTable[E_DMA_ALGO_DES][E_DMA_MODE_CTR][E_DMA_RESIDUE_NONE][E_DMA_SB_NONE] = TRUE ; // residue & sb don't care
495
496 // TDES Algorithm //
497 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
498 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_ECB][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
499 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CTR][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
500 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_CLR] = TRUE ;
501 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CTS][E_DMA_SB_IV1] = TRUE ;
502 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_CLR][E_DMA_SB_CLR] = TRUE ;
503 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV1] = TRUE ;
504 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_IV2] = TRUE ;
505 _CryptodMA_AlgoTable[E_DMA_ALGO_TDES][E_DMA_MODE_CBC][E_DMA_RESIDUE_SCTE52][E_DMA_SB_CLR] = TRUE ;
506
507 }
508
509
HAL_CIPHER_DMA_CheckAlgo(HAL_CIPHER_ALGO eAlgo,HAL_CIPHER_MODE eMode,HAL_CIPHER_RESIDUE eRes,HAL_CIPHER_SHORTBLOCK eSB)510 MS_BOOL HAL_CIPHER_DMA_CheckAlgo(HAL_CIPHER_ALGO eAlgo, HAL_CIPHER_MODE eMode, HAL_CIPHER_RESIDUE eRes, HAL_CIPHER_SHORTBLOCK eSB)
511 {
512 // Special Cases //
513 if (eAlgo > E_DMA_ALGO_TDES )
514 {
515 if ((E_DMA_ALGO_RC4==eAlgo)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR == eSB)&&(E_DMA_MODE_NONE==eMode))
516 { //RC4/none/none/none
517 return TRUE ;
518 }
519 if ((E_DMA_ALGO_M6_KE56==eAlgo)&&(E_DMA_MODE_ECB==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
520 { //M6_KE56/ecb/none/clr
521 return TRUE;
522 }
523 if ((E_DMA_ALGO_M6_S56==eAlgo)&&(E_DMA_MODE_ECB==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
524 { //M6_S56/ecb/none/clr
525 return TRUE;
526 }
527 if ((E_DMA_ALGO_M6_S56_CCBC==eAlgo)&&(E_DMA_MODE_NONE==eMode)&&(E_DMA_RESIDUE_NONE==eRes)&&(E_DMA_SB_CLR==eSB))
528 { //M6_S56_CCBC/none/none/clr
529 return TRUE;
530 }
531 return FALSE ;
532 }
533
534 // Reference table for Algorithm AES/TDES/DES //
535 return _CryptodMA_AlgoTable[eAlgo][eMode][eRes][eSB] ;
536 }
537
HAL_CIPHER_SetBank(MS_VIRT u32BankAddr)538 void HAL_CIPHER_SetBank(MS_VIRT u32BankAddr)
539 {
540 _u32RegBase = u32BankAddr;
541 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);
542
543 }
544
HAL_CIPHER_SetDbgLevel(CIPHER_DBGMSG_LEVEL eDBGMsgLevel)545 void HAL_CIPHER_SetDbgLevel(CIPHER_DBGMSG_LEVEL eDBGMsgLevel)
546 {
547 _HAL_CIPHERDBGLevel = eDBGMsgLevel;
548 }
549
HAL_CIPHER_ResetStatus(MS_BOOL RstDma,MS_BOOL RstHash)550 void HAL_CIPHER_ResetStatus(MS_BOOL RstDma , MS_BOOL RstHash)
551 {
552 if (RstDma)
553 {
554 _uDmaCtrl0.u32DmaCtrl0 = 0 ;
555 _uDmaCtrl1.u32DmaCtrl1 = 0 ;
556 _uDmaCtrl2.u32DmaCtrl2 = 0 ;
557 _uDmaCtrl3.u32DmaCtrl3 = 0 ;
558
559 _u32DmaInAddr = 0;
560 _u32DmaInNum = 0 ;
561 _u32OTPHashLengthPadding = 0;
562 _u32DmaOut_StartAddr = 0;
563 _u32DmaOut_EndAddr = 0;
564 _u32ReportAddr = 0 ;
565 memset(&_pu8CipherKey , 0x0, CIPHER_KEY_SIZE );
566 memset(&_pu8IV , 0x0, CIPHER_KEY_SIZE );
567 memset(&_pu8CipherKey2 , 0x0, CIPHER_KEY_SIZE );
568 memset(&_pu8IV2 , 0x0, CIPHER_KEY_SIZE );
569 memset(&_pu8Data , 0x0, CIPHER_KEY_SIZE );
570 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Reset DMA value\n", __FUNCTION__, __LINE__));
571
572 }
573
574 if (RstHash)
575 {
576 (_uHashCtrl0.u32HashCtrl0) = 0 ;
577 (_uHashCtrl1.u32HashCtrl1) = 0 ;
578 (_uHashCtrl2.u32HashCtrl2) = 0 ;
579
580 _u32HashSrcAddr = 0 ;
581 _u32InitWordCnt = 0 ;
582 _u32HashDestAddr = 0 ;
583 _u32HashMsgLen = 0 ;
584
585 memset(_pu8HashIV, 0x0 ,HASH_CMD_IV_SIZE);
586 memset(_pu8HashMsg, 0x0 , HASH_CMD_MSG_SIZE);
587 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Reset HASH value\n", __FUNCTION__, __LINE__));
588 }
589
590 }
591
HAL_CIPHER_ResetException(void)592 void HAL_CIPHER_ResetException(void)
593 {
594 MS_U32 u32DMACtrl = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);
595 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl | REG_EXCEPT_FLAG_CLEAR; //clear all except flag
596 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = u32DMACtrl & ~REG_EXCEPT_FLAG_CLEAR; //enable acpu except flag
597 }
598
HAL_CIPHER_ResetKey(MS_U32 u32KeyIdx)599 MS_BOOL HAL_CIPHER_ResetKey(MS_U32 u32KeyIdx)
600 {
601 HAL_CIPHER_KEYSRC KeySrc;
602
603 //Check Key Index
604 if(u32KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)
605 {
606 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid Key Index[%u]\n",
607 __func__, __LINE__, u32KeyIdx));
608 return FALSE;
609 }
610
611 KeySrc = _HAL_CIPHER_TransKey(E_CIPHER_KSRC_KL, u32KeyIdx);
612
613 _uDmaCtrl0.DmaCtrl0.DK = FALSE;
614 _uDmaCtrl0.DmaCtrl0.KeySel = KeySrc|CMD_DMA_KSEL_CLR_SK;
615
616 return TRUE;
617
618 }
HAL_CIPHER_SWReset(void)619 void HAL_CIPHER_SWReset(void)
620 {
621 MS_U32 DMA_CTRL = REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]);
622 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL | REG_DMA_SW_RESET; //reset CryptoDMA
623 REG32(&_AESDMACtrl->Dma_Ctrl[REG_DMA_CTRL]) = DMA_CTRL & ~REG_DMA_SW_RESET; //enable CryptoDMA
624
625 }
626
HAL_CIPHER_Set_OBFIdx(MS_BOOL bDMA,MS_U8 u8ReadIdx,MS_U8 u8WriteIdx)627 MS_BOOL HAL_CIPHER_Set_OBFIdx(MS_BOOL bDMA, MS_U8 u8ReadIdx, MS_U8 u8WriteIdx)
628 {
629 if(bDMA)
630 {
631 _uDmaCtrl2.DmaCtrl2.OBF_IDX_READ = u8ReadIdx;
632 _uDmaCtrl2.DmaCtrl2.OBF_IDX_WRITE = u8WriteIdx;
633 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Set DMA Obf Index Read:[%u], Write:[%u]\n",
634 __func__, __LINE__, u8ReadIdx, u8WriteIdx));
635 }
636 else
637 {
638 _uHashCtrl1.HashCtrl1.OBF_IDX_READ = u8ReadIdx;
639 _uHashCtrl1.HashCtrl1.OBF_IDX_WRITE = u8WriteIdx;
640 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Set HASH Obf Index Read:[%u], Write:[%u]\n",
641 __func__, __LINE__, u8ReadIdx, u8WriteIdx));
642 }
643
644 return TRUE;
645 }
646
HAL_CIPHER_DMA_Set_InputSrcFrom(CIPHER_MEM_TYPE InputSrcFrom,MS_U8 * pu8Data,MS_U32 u32Size)647 void HAL_CIPHER_DMA_Set_InputSrcFrom(CIPHER_MEM_TYPE InputSrcFrom, MS_U8* pu8Data, MS_U32 u32Size)
648 {
649 HAL_CIPHER_DATASRC src = E_DMA_SRC_DRAM;
650
651 switch(InputSrcFrom)
652 {
653 case E_CIPHER_DRAM:
654 _u32DmaInAddr = 0;
655 src = E_DMA_SRC_DRAM;
656 break;
657
658 case E_CIPHER_DQMEM://only for R2
659 _u32DmaInAddr = HAL_CIPHER_BASE_DQMEM;
660 src = E_DMA_SRC_DQMEM;
661 break;
662
663 case E_CIPHER_IQMEM://only for R2
664 _u32DmaInAddr = HAL_CIPHER_BASE_IQMEM;
665 src = E_DMA_SRC_IQMEM;
666 break;
667
668 // TODO: future work, DIRECT data from pu8Data
669 #if 0
670 case E_CIPHER_DIRECT:
671 HAL_CIPHER_DMA_Set_Data(pu8Data, u32Size);
672 src = E_DMA_SRC_DIRECT;
673 break;
674 #endif
675
676 case E_CIPHER_OTP: //only for OTPHASH
677 _u32DmaInAddr = 0;
678 src = E_DMA_SRC_HW_INPUT;
679 break;
680
681 default:
682 _u32DmaInAddr = 0;
683 src = E_DMA_SRC_DRAM;
684 break;
685 }
686
687 _uDmaCtrl1.DmaCtrl1.SD = (MS_U32)src;
688
689 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set input source from [%d]\n", __func__, __LINE__, src));
690 }
691
HAL_CIPHER_DMA_Set_OutputDstTo(CIPHER_MEM_TYPE OutputDstTo,MS_U8 * pu8Data,MS_U32 u32Size)692 MS_BOOL HAL_CIPHER_DMA_Set_OutputDstTo(CIPHER_MEM_TYPE OutputDstTo, MS_U8* pu8Data, MS_U32 u32Size)
693 {
694 HAL_CIPHER_DATADST dst = E_DMA_DST_DRAM;
695 MS_BOOL bDstKL = FALSE;
696
697 switch(OutputDstTo)
698 {
699 case E_CIPHER_DRAM:
700 _u32DmaOut_StartAddr = 0;
701 _u32DmaOut_EndAddr = 0;
702 dst = E_DMA_DST_DRAM;
703 break;
704
705 case E_CIPHER_DQMEM: //only for R2
706 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_DQMEM;
707 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_DQMEM;
708 dst = E_DMA_DST_DQMEM;
709 break;
710
711 case E_CIPHER_IQMEM: //only for R2
712 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_IQMEM;
713 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_IQMEM;
714 dst = E_DMA_DST_IQMEM;
715 break;
716
717 case E_CIPHER_DIRECT: //for ACPU, OTPHASH
718 dst = E_DMA_DST_REGFILE;
719 break;
720
721 case E_CIPHER_KL_LUT: //for KL transform algorithm
722 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_LUT;
723 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_LUT;
724 dst = E_DMA_DST_DRAM;
725 bDstKL = TRUE;
726 break;
727
728 case E_CIPHER_KL_M: //for KL transform algorithm
729 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_M;
730 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_M;
731 dst = E_DMA_DST_DRAM;
732 bDstKL = TRUE;
733 break;
734
735 case E_CIPHER_KL_BC: //for KL transform algorithm
736 _u32DmaOut_StartAddr = HAL_CIPHER_BASE_BC;
737 _u32DmaOut_EndAddr = HAL_CIPHER_BASE_BC;
738 dst = E_DMA_DST_DRAM;
739 bDstKL = TRUE;
740 break;
741
742 default:
743 _u32DmaOut_StartAddr = 0;
744 _u32DmaOut_EndAddr = 0;
745 dst = E_DMA_DST_DRAM;
746 break;
747 }
748
749 _uDmaCtrl1.DmaCtrl1.Dest= (MS_U32)dst;
750
751 if(bDstKL)
752 {
753 HAL_CIPHER_DMA_Set_OutputDstKL(TRUE);
754 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set output destination to KL [0x%4x]\n", __func__, __LINE__, (unsigned int)_u32DmaOut_StartAddr));
755 }
756 else
757 {
758 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set output destination to [%d]\n", __func__, __LINE__, dst));
759 }
760
761 return TRUE;
762 }
763
HAL_CIPHER_DMA_Set_OutputDstKL(MS_BOOL bDstKL)764 void HAL_CIPHER_DMA_Set_OutputDstKL(MS_BOOL bDstKL)
765 {
766 if(bDstKL)
767 {
768 _uDmaCtrl1.DmaCtrl1.DestKL = CMD_DMA_OUTPUT_SRAM_KL;
769 _uDmaCtrl0.DmaCtrl0.DK = TRUE;
770 }
771 else
772 {
773 _uDmaCtrl1.DmaCtrl1.DestKL = CMD_DMA_OUTPUT_DEST;
774 }
775 }
776
HAL_CIPHER_DMA_Set_FileinDesc(MS_PHY u32FileinAddr,MS_U32 u32FileinNum)777 void HAL_CIPHER_DMA_Set_FileinDesc(MS_PHY u32FileinAddr, MS_U32 u32FileinNum)
778 {
779
780 _u32DmaInAddr += u32FileinAddr;
781 _u32DmaInNum = u32FileinNum ;
782 }
783
HAL_CIPHER_DMA_Set_FileoutDesc(MS_PHY u32FileoutSAddr,MS_PHY u32phyFileoutEAddr)784 void HAL_CIPHER_DMA_Set_FileoutDesc(MS_PHY u32FileoutSAddr, MS_PHY u32phyFileoutEAddr)
785 {
786 _u32DmaOut_StartAddr += u32FileoutSAddr;
787 _u32DmaOut_EndAddr += u32phyFileoutEAddr;
788
789 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d] _u32DmaOut_StartAddr = %x _u32DmaOut_EndAddr = %x\n", __func__, __LINE__, (unsigned int)_u32DmaOut_StartAddr, (unsigned int)_u32DmaOut_EndAddr));
790 }
791
HAL_CIPHER_OTPHash_Set_FileinDesc(MS_PHY u32FileinAddr,MS_U32 u32FileinNum,MS_U32 u32CurrentRound,CIPHER_MEM_TYPE eInputSrcFrom)792 void HAL_CIPHER_OTPHash_Set_FileinDesc(MS_PHY u32FileinAddr, MS_U32 u32FileinNum, MS_U32 u32CurrentRound, CIPHER_MEM_TYPE eInputSrcFrom)
793 {
794 if(E_CIPHER_OTP == eInputSrcFrom)
795 {
796 _u32DmaInAddr = u32CurrentRound;
797 }
798 else
799 {
800 _u32DmaInAddr = u32FileinAddr + u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT;
801 }
802
803 _u32OTPHashLengthPadding = u32FileinNum;
804 if((u32FileinNum - u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT) >= HAL_CRYPTODMA_OTPHASH_UNIT)
805 {
806 _u32DmaInNum = HAL_CRYPTODMA_OTPHASH_UNIT;
807 }
808 else
809 {
810 _u32DmaInNum = u32FileinNum - u32CurrentRound*HAL_CRYPTODMA_OTPHASH_UNIT;
811 }
812
813 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d] _u32DmaInAddr = %x _u32DmaInNum = %x _u32OTPHashLengthPadding = %x\n", __func__, __LINE__, (unsigned int)_u32DmaInAddr, (unsigned int)_u32DmaInNum, (unsigned int)_u32OTPHashLengthPadding));
814 }
815
HAL_CIPHER_DMA_Set_Key(DRV_CIPHER_KEY stKey)816 MS_BOOL HAL_CIPHER_DMA_Set_Key(DRV_CIPHER_KEY stKey)
817 {
818 HAL_CIPHER_KEYSRC KeySrc = 0;
819 HAL_CIPHER_ALGO algo = 0;
820 MS_BOOL bDK = FALSE;
821
822 algo = _uDmaCtrl0.DmaCtrl0.Algo;
823
824 if(E_DMA_ALGO_NONE == algo)
825 {
826 //No key
827 bDK = TRUE;
828 memset(_pu8CipherKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
829 goto SET_KEY_DONE;
830 }
831 //Check Key Source, Index
832 if(((E_CIPHER_KSRC_KL == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
833 ((E_CIPHER_KSRC_OTP == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
834 {
835 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
836 __func__, __LINE__, stKey.eKeySrc, stKey.u8KeyIdx));
837 return FALSE;
838 }
839
840 //DRV to HAL Type transfer
841 KeySrc = _HAL_CIPHER_TransKey(stKey.eKeySrc, stKey.u8KeyIdx);
842
843 // key from CPU
844 if(E_DMA_KSEL_REGKEY == KeySrc)
845 {
846 if ((NULL != stKey.pu8KeyData) && (stKey.u8KeyLen != 0) && (stKey.u8KeyLen <= HAL_CRYPTODMA_KEYLEN_MAX) )
847 {
848 memset(_pu8CipherKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
849 memcpy(_pu8CipherKey, (MS_U8 *)stKey.pu8KeyData , stKey.u8KeyLen);
850 bDK = TRUE ;
851 KeySrc = 0;
852 }
853 else
854 {
855 return FALSE ;
856 }
857
858 }
859 else if(E_DMA_KSEL_CAIP == KeySrc)
860 {
861 bDK = FALSE ;
862 KeySrc = 0 ;
863 }
864 else// key from KL or OTP
865 {
866 bDK = FALSE;
867 }
868
869 SET_KEY_DONE:
870
871 _uDmaCtrl0.DmaCtrl0.DK = bDK;
872 _uDmaCtrl0.DmaCtrl0.KeySel = KeySrc;
873
874 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DK[%d], KeySel[%d]\n",
875 __func__, __LINE__, bDK, KeySrc));
876
877 return TRUE ;
878 }
879
HAL_CIPHER_DMA_Set_IV(MS_U8 * pu8IV,MS_U32 u32Size)880 void HAL_CIPHER_DMA_Set_IV(MS_U8* pu8IV, MS_U32 u32Size)
881 {
882 MS_BOOL bDIV = FALSE;
883
884 if ((NULL != pu8IV) && (u32Size != 0) && (u32Size <= HAL_CRYPTODMA_KEYLEN_MAX) )
885 {
886 memset(_pu8IV, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
887 memcpy(_pu8IV, (MS_U8 *)pu8IV, u32Size);
888 bDIV = TRUE;
889 }
890 else // Data from Dram
891 {
892 memset(_pu8IV, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
893 bDIV = FALSE;
894 }
895
896 _uDmaCtrl0.DmaCtrl0.DIV = bDIV ;
897
898 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DIV[%d]\n",
899 __func__, __LINE__, bDIV));
900 }
901
902
903 // Set Direct Data to Register Input, if Dram input, set pu8Data = NULL ;
HAL_CIPHER_DMA_Set_Data(MS_U8 * pu8Data,MS_U32 u32Size)904 MS_BOOL HAL_CIPHER_DMA_Set_Data(MS_U8* pu8Data, MS_U32 u32Size)
905 {
906 HAL_CIPHER_DATASRC eDataSrc = E_DMA_SRC_DRAM;
907
908 // Data size can't be zero //
909 if (( 0 == u32Size ) && (NULL != pu8Data ))
910 {
911 return FALSE ;
912 }
913
914 if (NULL != pu8Data ) // Data from CMDQ
915 {
916 _u32DmaInNum = u32Size ;
917 memset(_pu8Data, 0x0, HAL_CRYPTODMA_DIRDATA_MAX);
918 memcpy(_pu8Data, (MS_U8 *)pu8Data, u32Size);
919 eDataSrc = E_DMA_SRC_DIRECT ;
920 }
921 else // Data from Dram
922 {
923 memset(_pu8Data, 0x0 , HAL_CRYPTODMA_DIRDATA_MAX );
924 eDataSrc = E_DMA_SRC_DRAM ;
925 }
926
927 _uDmaCtrl1.DmaCtrl1.SD = (MS_U32)eDataSrc ;
928
929 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set SD[%d]\n",
930 __func__, __LINE__, eDataSrc));
931
932 return TRUE ;
933 }
934
HAL_CIPHER_DMA_Set_CaVid(MS_U32 u32CAVid)935 MS_BOOL HAL_CIPHER_DMA_Set_CaVid(MS_U32 u32CAVid)
936 {
937 MS_U32 u32Tmp = u32CAVid;
938
939 if(u32Tmp > HAL_CRYPTODMA_CAVID_MAX)
940 {
941 return FALSE;
942 }
943
944 if(u32Tmp == 0)
945 {
946 u32Tmp = _CIPHER_CAVid ;
947 }
948 else
949 {
950 u32Tmp = u32CAVid ;
951 }
952
953 _uDmaCtrl1.DmaCtrl1.CaVid = u32Tmp ;
954
955 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set CAVid [0x%x]\n",
956 __func__, __LINE__, (unsigned int)u32Tmp));
957
958 return TRUE;
959 }
960
HAL_CIPHER_DMA_Set_Config(MS_BOOL OutputReg)961 void HAL_CIPHER_DMA_Set_Config(MS_BOOL OutputReg)
962 {
963 _uDmaCtrl1.DmaCtrl1.Dest= OutputReg ;
964 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set dest[%d]\n",
965 __func__, __LINE__, OutputReg));
966 }
967
968
HAL_CIPHER_DMA_Set_ReportMode(MS_BOOL RptInDram,MS_PHY u32DramAddr)969 void HAL_CIPHER_DMA_Set_ReportMode(MS_BOOL RptInDram, MS_PHY u32DramAddr)
970 {
971 MS_BOOL bRR = FALSE;
972
973 if (RptInDram)
974 {
975 bRR = TRUE ;
976 _u32ReportAddr = u32DramAddr;
977
978 }
979 else
980 {
981 bRR = FALSE ;
982 _u32ReportAddr = 0;
983
984 }
985
986 _uDmaCtrl1.DmaCtrl1.RR = bRR;
987
988 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set report mode[%d], report address[0x%08x]\n",
989 __func__, __LINE__, bRR, (unsigned int)_u32ReportAddr));
990 }
991
992 // [NOTE] HW Bug, the DMA can't support DRAM Data Swap, Data Error for input and output
HAL_CIPHER_DMA_Set_DataSwap(MS_BOOL InDataSwap,MS_BOOL OutDataSwap,MS_BOOL DInByteSwap,MS_BOOL DOutByteSwap)993 void HAL_CIPHER_DMA_Set_DataSwap(MS_BOOL InDataSwap , MS_BOOL OutDataSwap,
994 MS_BOOL DInByteSwap, MS_BOOL DOutByteSwap )
995 {
996 _uDmaCtrl1.DmaCtrl1.CIS = InDataSwap ;
997 _uDmaCtrl1.DmaCtrl1.COS = OutDataSwap ;
998 //_uDmaCtrl1.DmaCtrl1.DODS = DOutBitSwap ;
999 _uDmaCtrl1.DmaCtrl1.DOBS = DOutByteSwap ;
1000 _uDmaCtrl1.DmaCtrl1.DIBS = DInByteSwap;
1001
1002 }
1003
1004
1005 //void HAL_CIPHER_DMA_Set_Algo(CipherAlgo algo , CipherMode subalgo , Cipher_Residue eRes , Cipher_ShortBlock eSB )
HAL_CIPHER_DMA_Set_Algo(DRV_CIPHER_ALGO stAlgo)1006 void HAL_CIPHER_DMA_Set_Algo(DRV_CIPHER_ALGO stAlgo)
1007 {
1008 HAL_CIPHER_ALGO algo;
1009 HAL_CIPHER_MODE subalgo;
1010 HAL_CIPHER_RESIDUE eRes;
1011 HAL_CIPHER_SHORTBLOCK eSB;
1012
1013 if(_uDmaCtrl1.DmaCtrl1.CaVid == E_CIPHER_CAVID1)
1014 {
1015 algo = (HAL_CIPHER_ALGO)stAlgo.eMainAlgo;
1016 subalgo = (HAL_CIPHER_MODE)stAlgo.eSubAlgo;
1017
1018 // For OTPHASH in E_CIPHER_CAVID1
1019 if(stAlgo.eSubAlgo == E_CIPHER_SUB_OTPHASH)
1020 subalgo = E_DMA_MODE_OTPHASH;
1021 }
1022 else
1023 {
1024 algo = _HAL_CIPHER_TransMainAlgo(stAlgo.eMainAlgo);
1025 subalgo = _HAL_CIPHER_TransSubAlgo(stAlgo.eSubAlgo);
1026 }
1027
1028 eRes = _HAL_CIPHER_TransResAlgo(stAlgo.eResAlgo);
1029 eSB = _HAL_CIPHER_TransSBAlgo(stAlgo.eSBAlgo);
1030
1031 _uDmaCtrl0.DmaCtrl0.Algo= algo ;
1032 _uDmaCtrl0.DmaCtrl0.SubAlgo= subalgo ;
1033 _uDmaCtrl0.DmaCtrl0.Residue = eRes ;
1034 _uDmaCtrl0.DmaCtrl0.SB = eSB ;
1035
1036 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set algorithm, MAIN[%d], SUB[%d], RES[%d], SB[%d]\n",
1037 __func__, __LINE__, algo, subalgo, eRes, eSB));
1038 }
1039
HAL_CIPHER_DMA_Set_OTPHash(MS_U32 u32CurrentRound,MS_U32 u32OTPHashRound)1040 void HAL_CIPHER_DMA_Set_OTPHash(MS_U32 u32CurrentRound, MS_U32 u32OTPHashRound)
1041 {
1042 _uDmaCtrl3.DmaCtrl3.AP = 0;
1043 _uDmaCtrl3.DmaCtrl3.IK = 0;
1044 // First OTPHASH enable IK, other disable IK
1045 if(u32CurrentRound == 0)
1046 {
1047 _uDmaCtrl3.DmaCtrl3.IK = 1;
1048 }
1049 // Final OTPHASH enable AP, other disable AP
1050 if(u32CurrentRound == u32OTPHashRound)
1051 {
1052 _uDmaCtrl3.DmaCtrl3.AP = 1;
1053 }
1054
1055 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set OTPHASH, AP[%d], IK[%d]\n",
1056 __func__, __LINE__, _uDmaCtrl3.DmaCtrl3.AP, _uDmaCtrl3.DmaCtrl3.IK));
1057 }
1058
HAL_CIPHER_DMA_WriteCMDQ(MS_U32 u32Cmd)1059 void HAL_CIPHER_DMA_WriteCMDQ(MS_U32 u32Cmd)
1060 {
1061 WRITE_CMDQ(u32Cmd) ;
1062 }
1063
HAL_CIPHER_DMA_GetData(MS_U8 * u8Data)1064 void HAL_CIPHER_DMA_GetData(MS_U8 *u8Data)
1065 {
1066
1067 MS_U32 tmp ;
1068
1069 // [Note] for u8Data is not always 4 bytes alignment.
1070 tmp = REG32(&_AESDMACtrl->Dma_Out[0]);
1071 u8Data[0] = (tmp >> 0) & 0xFF ;
1072 u8Data[1] = (tmp >> 8) & 0xFF ;
1073 u8Data[2] = (tmp >> 16) & 0xFF ;
1074 u8Data[3] = (tmp >> 24) & 0xFF ;
1075
1076 tmp = REG32(&_AESDMACtrl->Dma_Out[1]);
1077 u8Data[4] = (tmp >> 0) & 0xFF ;
1078 u8Data[5] = (tmp >> 8) & 0xFF ;
1079 u8Data[6] = (tmp >> 16) & 0xFF ;
1080 u8Data[7] = (tmp >> 24) & 0xFF ;
1081
1082 tmp = REG32(&_AESDMACtrl->Dma_Out[2]);
1083 u8Data[8] = (tmp >> 0) & 0xFF ;
1084 u8Data[9] = (tmp >> 8) & 0xFF ;
1085 u8Data[10] = (tmp >> 16) & 0xFF ;
1086 u8Data[11] = (tmp >> 24) & 0xFF ;
1087
1088 tmp = REG32(&_AESDMACtrl->Dma_Out[3]);
1089 u8Data[12] = (tmp >> 0) & 0xFF ;
1090 u8Data[13] = (tmp >> 8) & 0xFF ;
1091 u8Data[14] = (tmp >> 16) & 0xFF ;
1092 u8Data[15] = (tmp >> 24) & 0xFF ;
1093
1094 }
1095
HAL_CIPHER_DMA_GetRpt(MS_U32 * DmaRpt)1096 void HAL_CIPHER_DMA_GetRpt(MS_U32 *DmaRpt)
1097 {
1098 MS_U32 i ;
1099
1100 for (i = 0 ; i < DMA_RPT_REG_SIZE ; i++)
1101 {
1102 DmaRpt[i] = REG32(&_AESDMACtrl->Dma_Reportp[i]);
1103 }
1104 }
1105
HAL_CIPHER_DMA_Start(MS_BOOL Decrypt,HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_U16 u16CmdID)1106 MS_BOOL HAL_CIPHER_DMA_Start(MS_BOOL Decrypt, HAL_CIPHER_INTMODE IntMode, MS_BOOL bWaitCmdQ, MS_U16 u16CmdID)
1107 {
1108 MS_U32 u32SpareCnt = 0 , CmdLen = 0 ;
1109
1110 _uDmaCtrl0.DmaCtrl0.OVT = FALSE ;
1111
1112 //Set Thread Id
1113 _uDmaCtrl1.DmaCtrl1.TID = u16CmdID ;
1114
1115 _uDmaCtrl1.DmaCtrl1.IntM = IntMode ;
1116
1117 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_DMA);
1118
1119 _uDmaCtrl0.DmaCtrl0.CL = CmdLen & CMD_LEN_MASK ;
1120 _uDmaCtrl0.DmaCtrl0.CMD = ((Decrypt?0x3:0x2) & 0xF);
1121
1122 _uDmaCtrl2.DmaCtrl2.NS = 0;
1123 _uDmaCtrl1.DmaCtrl1.NL = CMD_NEW_LINE;
1124
1125 //Parser patch
1126 if(TRUE == _uDmaCtrl2.DmaCtrl2.HP)
1127 {
1128 MS_U32 u32Tmp = 0;
1129 u32Tmp = _AESDMACtrl->Dma_Ctrl[1];
1130 u32Tmp |= REG_PARSER_LG_PATH_EN;
1131 _AESDMACtrl->Dma_Ctrl[1] = u32Tmp;
1132 }
1133
1134 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1135 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar
1136
1137
1138 if(_uDmaCtrl1.DmaCtrl1.SD == CMD_DMA_DATA_DRAM)
1139 {
1140 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaInAddr) == FALSE)
1141 {
1142 return FALSE;
1143 }
1144 }
1145
1146 if(_uDmaCtrl1.DmaCtrl1.Dest == CMD_DMA_OUTPUT_DRAM)
1147 {
1148 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaOut_StartAddr) == FALSE)
1149 {
1150 return FALSE;
1151 }
1152 if(_HAL_CIPHER_TransMIUAddr(&_u32DmaOut_EndAddr) == FALSE)
1153 {
1154 return FALSE;
1155 }
1156 }
1157
1158 DMA_RETRY:
1159 // [HW] Hardware will check Current spare count first, and others read spare count will be zero!
1160 u32SpareCnt = REG32(&_AESDMACtrl->SpareCnt) ;
1161
1162 if (u32SpareCnt > CmdLen)
1163 {
1164 u32SpareCnt -= CmdLen ;
1165
1166 WRITE_CMDQ( (_uDmaCtrl0.u32DmaCtrl0)) ;
1167 WRITE_CMDQ( (_uDmaCtrl1.u32DmaCtrl1)) ;
1168 WRITE_CMDQ( (_uDmaCtrl2.u32DmaCtrl2)) ;
1169 WRITE_CMDQ( (_uDmaCtrl3.u32DmaCtrl3)) ;
1170
1171 WRITE_CMDQ((MS_U32)_u32DmaInAddr) ;
1172 WRITE_CMDQ(_u32DmaInNum) ;
1173 WRITE_CMDQ((MS_U32)_u32DmaOut_StartAddr);
1174 WRITE_CMDQ((MS_U32)_u32DmaOut_EndAddr);
1175
1176 if (_uDmaCtrl1.DmaCtrl1.RR == TRUE )
1177 {
1178 WRITE_CMDQ((MS_U32)_u32ReportAddr);
1179 }
1180
1181 // DMA Initial Vector from CmdQ
1182 if (_uDmaCtrl0.DmaCtrl0.DIV == TRUE )
1183 {
1184 #if 0
1185 WRITE_CMDQ(_pu8IV[15]<<24 |_pu8IV[14]<<16 | _pu8IV[13]<<8 | _pu8IV[12]);
1186 WRITE_CMDQ(_pu8IV[11]<<24 |_pu8IV[10]<<16 | _pu8IV[ 9]<<8 | _pu8IV[ 8]);
1187 WRITE_CMDQ(_pu8IV[ 3]<<24 |_pu8IV[ 2]<<16 | _pu8IV[ 1]<<8 | _pu8IV[ 0]);
1188 WRITE_CMDQ(_pu8IV[ 7]<<24 |_pu8IV[ 6]<<16 | _pu8IV[ 5]<<8 | _pu8IV[ 4]);
1189 #else
1190 WRITE_CMDQ(_pu8IV[ 0]<<24 |_pu8IV[ 1]<<16 | _pu8IV[ 2]<<8 | _pu8IV[ 3]);
1191 WRITE_CMDQ(_pu8IV[ 4]<<24 |_pu8IV[ 5]<<16 | _pu8IV[ 6]<<8 | _pu8IV[ 7]);
1192 WRITE_CMDQ(_pu8IV[ 8]<<24 |_pu8IV[ 9]<<16 | _pu8IV[10]<<8 | _pu8IV[11]);
1193 WRITE_CMDQ(_pu8IV[12]<<24 |_pu8IV[13]<<16 | _pu8IV[14]<<8 | _pu8IV[15]);
1194 #endif
1195 }
1196
1197 // DMA Data from CmdQ
1198 if (_uDmaCtrl1.DmaCtrl1.SD == CMD_DMA_DATA_REG )
1199 {
1200 #if 0
1201 WRITE_CMDQ(_pu8Data[15]<<24 |_pu8Data[14]<<16 | _pu8Data[13]<<8 | _pu8Data[12]);
1202 WRITE_CMDQ(_pu8Data[11]<<24 |_pu8Data[10]<<16 | _pu8Data[ 9]<<8 | _pu8Data[ 8]);
1203 WRITE_CMDQ(_pu8Data[ 7]<<24 |_pu8Data[ 6]<<16 | _pu8Data[ 5]<<8 | _pu8Data[ 4]);
1204 WRITE_CMDQ(_pu8Data[ 3]<<24 |_pu8Data[ 2]<<16 | _pu8Data[ 1]<<8 | _pu8Data[ 0]);
1205 #else
1206 WRITE_CMDQ(_pu8Data[ 0]<<24 |_pu8Data[ 1]<<16 | _pu8Data[ 2]<<8 | _pu8Data[ 3]);
1207 WRITE_CMDQ(_pu8Data[ 4]<<24 |_pu8Data[ 5]<<16 | _pu8Data[ 6]<<8 | _pu8Data[ 7]);
1208 WRITE_CMDQ(_pu8Data[ 8]<<24 |_pu8Data[ 9]<<16 | _pu8Data[10]<<8 | _pu8Data[11]);
1209 WRITE_CMDQ(_pu8Data[12]<<24 |_pu8Data[13]<<16 | _pu8Data[14]<<8 | _pu8Data[15]);
1210 #endif
1211 }
1212
1213 // DMA Key from CmdQ
1214 if (_uDmaCtrl0.DmaCtrl0.DK == TRUE )
1215 {
1216 #if 0
1217 WRITE_CMDQ(_pu8CipherKey[15]<<24 |_pu8CipherKey[14]<<16 | _pu8CipherKey[13]<<8 | _pu8CipherKey[12]);
1218 WRITE_CMDQ(_pu8CipherKey[11]<<24 |_pu8CipherKey[10]<<16 | _pu8CipherKey[ 9]<<8 | _pu8CipherKey[ 8]);
1219 WRITE_CMDQ(_pu8CipherKey[ 7]<<24 |_pu8CipherKey[ 6]<<16 | _pu8CipherKey[ 5]<<8 | _pu8CipherKey[ 4]);
1220 WRITE_CMDQ(_pu8CipherKey[ 3]<<24 |_pu8CipherKey[ 2]<<16 | _pu8CipherKey[ 1]<<8 | _pu8CipherKey[ 0]);
1221 #else
1222 WRITE_CMDQ(_pu8CipherKey[ 0]<<24 |_pu8CipherKey[ 1]<<16 | _pu8CipherKey[ 2]<<8 | _pu8CipherKey[ 3]);
1223 WRITE_CMDQ(_pu8CipherKey[ 4]<<24 |_pu8CipherKey[ 5]<<16 | _pu8CipherKey[ 6]<<8 | _pu8CipherKey[ 7]);
1224 WRITE_CMDQ(_pu8CipherKey[ 8]<<24 |_pu8CipherKey[ 9]<<16 | _pu8CipherKey[10]<<8 | _pu8CipherKey[11]);
1225 WRITE_CMDQ(_pu8CipherKey[12]<<24 |_pu8CipherKey[13]<<16 | _pu8CipherKey[14]<<8 | _pu8CipherKey[15]);
1226 #endif
1227 }
1228
1229 // PID for HW parser
1230 if (_uDmaCtrl2.DmaCtrl2.HP == TRUE )
1231 {
1232 WRITE_CMDQ(_pu8PID0[ 0]<<27 |_pu8PID0[ 1]<<19 | _pu8PID1[ 0]<<14 | _pu8PID1[ 1]<<6);
1233
1234 }
1235
1236 if (_uDmaCtrl3.DmaCtrl3.DIV2 == TRUE )
1237 {
1238 WRITE_CMDQ(_pu8IV2[ 0]<<24 |_pu8IV2[ 1]<<16 | _pu8IV2[ 2]<<8 | _pu8IV2[ 3]);
1239 WRITE_CMDQ(_pu8IV2[ 4]<<24 |_pu8IV2[ 5]<<16 | _pu8IV2[ 6]<<8 | _pu8IV2[ 7]);
1240 WRITE_CMDQ(_pu8IV2[ 8]<<24 |_pu8IV2[ 9]<<16 | _pu8IV2[10]<<8 | _pu8IV2[11]);
1241 WRITE_CMDQ(_pu8IV2[12]<<24 |_pu8IV2[13]<<16 | _pu8IV2[14]<<8 | _pu8IV2[15]);
1242 }
1243
1244 if (_uDmaCtrl3.DmaCtrl3.DK2 == TRUE )
1245 {
1246 WRITE_CMDQ(_pu8CipherKey2[ 0]<<24 |_pu8CipherKey2[ 1]<<16 | _pu8CipherKey2[ 2]<<8 | _pu8CipherKey2[ 3]);
1247 WRITE_CMDQ(_pu8CipherKey2[ 4]<<24 |_pu8CipherKey2[ 5]<<16 | _pu8CipherKey2[ 6]<<8 | _pu8CipherKey2[ 7]);
1248 WRITE_CMDQ(_pu8CipherKey2[ 8]<<24 |_pu8CipherKey2[ 9]<<16 | _pu8CipherKey2[10]<<8 | _pu8CipherKey2[11]);
1249 WRITE_CMDQ(_pu8CipherKey2[12]<<24 |_pu8CipherKey2[13]<<16 | _pu8CipherKey2[14]<<8 | _pu8CipherKey2[15]);
1250 }
1251
1252 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
1253 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1254 return TRUE ;
1255
1256 }
1257 else
1258 {
1259 // [HW] Check Current spare count == Write back Spare count to start wait cmd
1260 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1261 if (bWaitCmdQ)
1262 {
1263 // Retry until CMDQ avaliable
1264 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA retry!\n",__func__, __LINE__));
1265 goto DMA_RETRY;
1266 }
1267 else
1268 {
1269 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Fail!\n",__func__, __LINE__));
1270 // Return Fail, Command abort
1271 return FALSE ;
1272 }
1273 }
1274 //DMA_FAIL:
1275
1276 }
1277
HAL_CIPHER_OTPHash_Start(HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_U16 u16CmdID)1278 MS_BOOL HAL_CIPHER_OTPHash_Start(HAL_CIPHER_INTMODE IntMode, MS_BOOL bWaitCmdQ, MS_U16 u16CmdID)
1279 {
1280 MS_U32 u32SpareCnt = 0 , CmdLen = 0 ;
1281
1282 _uDmaCtrl0.DmaCtrl0.OVT = FALSE ;
1283
1284 //Set Thread Id
1285 _uDmaCtrl1.DmaCtrl1.TID = u16CmdID ;
1286
1287 _uDmaCtrl1.DmaCtrl1.IntM = IntMode ;
1288
1289 _uDmaCtrl1.DmaCtrl1.NL = CMD_NEW_LINE;
1290
1291 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_OTPHASH);
1292
1293 _uDmaCtrl0.DmaCtrl0.CL = CmdLen & CMD_LEN_MASK ;
1294 _uDmaCtrl0.DmaCtrl0.CMD = CMD_DMA_ENCRYPT;
1295
1296 _uDmaCtrl2.DmaCtrl2.NS = 0;
1297
1298 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1299 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar
1300
1301 DMA_RETRY:
1302 // [HW] Hardware will check Current spare count first, and others read spare count will be zero!
1303 u32SpareCnt = REG32(&_AESDMACtrl->SpareCnt) ;
1304
1305 if (u32SpareCnt > CmdLen)
1306 {
1307 u32SpareCnt -= CmdLen ;
1308
1309 WRITE_CMDQ( (_uDmaCtrl0.u32DmaCtrl0)) ;
1310 WRITE_CMDQ( (_uDmaCtrl1.u32DmaCtrl1)) ;
1311 WRITE_CMDQ( (_uDmaCtrl2.u32DmaCtrl2)) ;
1312 WRITE_CMDQ( (_uDmaCtrl3.u32DmaCtrl3)) ;
1313
1314 WRITE_CMDQ((MS_U32)_u32DmaInAddr) ;
1315 WRITE_CMDQ(_u32DmaInNum) ;
1316 WRITE_CMDQ((MS_U32)_u32DmaOut_StartAddr);
1317 WRITE_CMDQ((MS_U32)_u32DmaOut_EndAddr);
1318
1319 if(_uDmaCtrl3.DmaCtrl3.AP == TRUE && _uDmaCtrl3.DmaCtrl3.IK == FALSE)
1320 {
1321 WRITE_CMDQ(_u32OTPHashLengthPadding);
1322 }
1323
1324 if (_uDmaCtrl1.DmaCtrl1.RR == TRUE )
1325 {
1326 WRITE_CMDQ((MS_U32)_u32ReportAddr);
1327 }
1328
1329 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
1330 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1331 return TRUE ;
1332 }
1333 else
1334 {
1335 // [HW] Check Current spare count == Write back Spare count to start wait cmd
1336 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
1337 if (bWaitCmdQ)
1338 {
1339 // Retry until CMDQ avaliable
1340 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA retry!\n",__func__, __LINE__));
1341 goto DMA_RETRY;
1342 }
1343 else
1344 {
1345 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Fail!\n",__func__, __LINE__));
1346 // Return Fail, Command abort
1347 return FALSE ;
1348 }
1349 }
1350
1351 }
1352
HAL_CIPHER_DMA_CmdDone(MS_U32 u32CmdID,MS_U32 * u32Ret)1353 MS_BOOL HAL_CIPHER_DMA_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret)
1354 {
1355 MS_U32 u32ExcTmp = 0;
1356 MS_U32 u32Rpt = REG32(&_AESDMACtrl->Dma_Reportp[0]) ;
1357 MS_U32 u32RptId = u32Rpt & REG_CIPHER_RPT_THREAD_MSK;
1358
1359 if(u32RptId == u32CmdID)
1360 {
1361 u32ExcTmp = (MS_U32) REG32(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
1362 *u32Ret = u32ExcTmp;
1363 }
1364 else
1365 {
1366 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]DMA Cmd[%u] Not done!ReportId[%u]\n",
1367 __func__, __LINE__, u32CmdID, u32RptId));
1368 return FALSE;
1369 }
1370
1371 return TRUE;
1372
1373 }
1374
HAL_CIPHER_GetException(MS_U32 * pu32ExcFlag)1375 void HAL_CIPHER_GetException(MS_U32 *pu32ExcFlag)
1376 {
1377 MS_U32 u32ExcTmp = (MS_U32) REG32(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
1378 *pu32ExcFlag = u32ExcTmp;
1379 }
1380
HAL_CIPHER_ReadException(MS_U32 u32ExcTmp)1381 MS_U32 HAL_CIPHER_ReadException(MS_U32 u32ExcTmp)
1382 {
1383 MS_U32 i = 0;
1384 MS_U32 u32ExcOut = 0;
1385
1386 for(i = 0;i<CRYPTODMA_DEBUG_SIZE;i++) //check each error flag
1387 {
1388 if((u32ExcTmp & (1 << i)) >> i)
1389 {
1390 switch(i)
1391 {
1392 case E_CIPHER_NDS_Region_fail:
1393 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_NDS_Region_fail\n", __func__, __LINE__));
1394 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1395 break;
1396 case E_CIPHER_NDS_keyoff:
1397 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_NDS_keyoff\n", __func__, __LINE__));
1398 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1399 break;
1400 case E_CIPHER_sha_write_scr:
1401 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_write_scr\n", __func__, __LINE__));
1402 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1403 break;
1404 case E_CIPHER_sha_read_scr:
1405 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_read_scr\n", __func__, __LINE__));
1406 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1407 break;
1408 case E_CIPHER_sha_error_flag:
1409 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_error_flag\n", __func__, __LINE__));
1410 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1411 break;
1412 case E_CIPHER_except_read_scr:
1413 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_read_scr\n", __func__, __LINE__));
1414 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1415 break;
1416 case E_CIPHER_except_key:
1417 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key\n", __func__, __LINE__));
1418 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1419 break;
1420 case E_CIPHER_except_CAVid:
1421 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_CAVid\n", __func__, __LINE__));
1422 u32ExcOut |= HAL_CIPHER_EXCEPT_CAVID;
1423 break;
1424 case E_CIPHER_except_des:
1425 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_des\n", __func__, __LINE__));
1426 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1427 break;
1428 case E_CIPHER_except_NDS:
1429 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_NDS\n", __func__, __LINE__));
1430 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1431 break;
1432 case E_CIPHER_except_chain:
1433 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_chain\n", __func__, __LINE__));
1434 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1435 break;
1436 case E_CIPHER_except_algo:
1437 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_algo\n", __func__, __LINE__));
1438 u32ExcOut |= HAL_CIPHER_EXCEPT_ALGO;
1439 break;
1440 case E_CIPHER_except_key_HID:
1441 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key_HID\n", __func__, __LINE__));
1442 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1443 break;
1444 case E_CIPHER_except_key_cbc_mac:
1445 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_key_cbc_mac\n", __func__, __LINE__));
1446 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1447 break;
1448 case E_CIPHER_except_file_dqmem:
1449 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_file_dqmem\n", __func__, __LINE__));
1450 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1451 break;
1452 case E_CIPHER_except_hash_dqmem:
1453 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_hash_dqmem\n", __func__, __LINE__));
1454 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1455 break;
1456 case E_CIPHER_disable_masterkey0:
1457 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_masterkey0\n", __func__, __LINE__));
1458 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1459 break;
1460 case E_CIPHER_disable_masterkey1:
1461 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_masterkey1\n", __func__, __LINE__));
1462 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1463 break;
1464 case E_CIPHER_disable_cck:
1465 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_cck\n", __func__, __LINE__));
1466 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1467 break;
1468 case E_CIPHER_disable_reg_key_0:
1469 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_0\n", __func__, __LINE__));
1470 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1471 break;
1472 case E_CIPHER_disable_reg_key_1:
1473 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_1\n", __func__, __LINE__));
1474 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1475 break;
1476 case E_CIPHER_disable_reg_key_2:
1477 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_2\n", __func__, __LINE__));
1478 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1479 break;
1480 case E_CIPHER_disable_reg_key_3:
1481 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_disable_reg_key_3\n", __func__, __LINE__));
1482 u32ExcOut |= HAL_CIPHER_EXCEPT_HMAC_KEY;
1483 break;
1484 case E_CIPHER_dma_forbid_qmem2dram:
1485 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_dma_forbid_qmem2dram\n", __func__, __LINE__));
1486 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1487 break;
1488 case E_CIPHER_dma_forbid_cryptodma_keyslot_qmem:
1489 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_dma_forbid_cryptodma_keyslot_qmem\n", __func__, __LINE__));
1490 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1491 break;
1492 case E_CIPHER_sha_forbid_qmem2dram:
1493 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_forbid_qmem2dram\n", __func__, __LINE__));
1494 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1495 break;
1496 case E_CIPHER_sha_forbid_cryptodma_keyslot_qmem:
1497 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_sha_forbid_cryptodma_keyslot_qmem\n", __func__, __LINE__));
1498 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1499 break;
1500 case E_CIPHER_tdes_key_error:
1501 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_tdes_key_error\n", __func__, __LINE__));
1502 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1503 break;
1504 case E_CIPHER_write_address_error:
1505 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_write_address_error\n", __func__, __LINE__));
1506 u32ExcOut |= HAL_CIPHER_EXCEPT_DATA;
1507 break;
1508 case E_CIPHER_except_str:
1509 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_str\n", __func__, __LINE__));
1510 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1511 break;
1512 case E_CIPHER_except_sha_str:
1513 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] E_CIPHER_except_sha_str\n", __func__, __LINE__));
1514 u32ExcOut |= HAL_CIPHER_EXCEPT_DMA_KEY;
1515 break;
1516 default:
1517 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d] Unknown error \n", __func__, __LINE__));
1518 break;
1519
1520 }
1521
1522 }
1523
1524 }
1525
1526 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]Exception out [0x%08x]\n", __func__, __LINE__, (unsigned int)u32ExcOut));
1527
1528 return u32ExcOut;
1529
1530 }
1531
HAL_CIPHER_IntEnable(void)1532 void HAL_CIPHER_IntEnable(void)
1533 {
1534 MS_U16 u16MaskTmp = REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48);
1535 u16MaskTmp &= REG_HTS0_FIQ_MASK_CRYPTODMA; //FIQ 56 in reg_hst0_fiq_mask_63_48_
1536 REG16(_u32RegBase + REG_HST0_FIQ_MASK_63_48) = u16MaskTmp;
1537 }
1538
HAL_CIPHER_IntClear(void)1539 void HAL_CIPHER_IntClear(void)
1540 {
1541 REG16(_u32RegBase + REG_HST0_FIQ_STATUS_63_48) = REG_HTS0_FIQ_CRYPTODMA; //set 1 to clear interrupt
1542 }
1543
1544 //======================================================================
1545
HAL_CIPHER_Hash_GetRpt(MS_U32 * HashRpt,MS_U32 u32Size)1546 void HAL_CIPHER_Hash_GetRpt(MS_U32 *HashRpt, MS_U32 u32Size)
1547 {
1548 MS_U32 i , tmp;
1549
1550 if (u32Size < HASH_RPT_REG_SIZE )
1551 {
1552 tmp = u32Size ;
1553 }
1554 else
1555 {
1556 tmp = HASH_RPT_REG_SIZE ;
1557 }
1558
1559 for (i = 0 ; i < tmp ; i++)
1560 {
1561 HashRpt[i] = REG32(&_AESDMACtrl->Hash_Reportp[i]);
1562 }
1563 }
1564
HAL_CIPHER_Hash_Set_Config(CIPHER_HASH_ALGO algo,MS_BOOL bAutoPad,MS_BOOL bInv16)1565 void HAL_CIPHER_Hash_Set_Config(CIPHER_HASH_ALGO algo , MS_BOOL bAutoPad , MS_BOOL bInv16)
1566 {
1567 HAL_CIPHER_HASHMODE hash_mode = E_HASH_SHA1;
1568 hash_mode = _HAL_CIPHER_TransHASHAlgo(algo);
1569
1570 _uHashCtrl0.HashCtrl0.HashSel = hash_mode ;
1571 _uHashCtrl0.HashCtrl0.AutoPad = bAutoPad ;
1572 _uHashCtrl0.HashCtrl0.Inv16 = bInv16; //Inverse the byte order per 16 bytes
1573
1574 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH Mode[%d], AutoPad[%d], Inverse16[%d]!\n",
1575 __func__, __LINE__, hash_mode, bAutoPad, bInv16));
1576 }
1577
HAL_CIPHER_Hash_Set_ReportMode(MS_BOOL RptInDram,MS_U32 u32DramAddr)1578 void HAL_CIPHER_Hash_Set_ReportMode(MS_BOOL RptInDram, MS_U32 u32DramAddr)
1579 {
1580 if (RptInDram)
1581 {
1582 _u32ReportAddr = u32DramAddr;
1583
1584 }
1585 else
1586 {
1587 _u32ReportAddr = 0;
1588 }
1589
1590 _uHashCtrl2.HashCtrl2.RR = RptInDram ;
1591
1592 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set report mode[%d], report address[0x%08x]\n",
1593 __func__, __LINE__, RptInDram, (unsigned int)_u32ReportAddr));
1594 }
1595
HAL_CIPHER_Hash_SetHMACKey(DRV_CIPHER_HMAC_KEY stHMACKey,CIPHER_HMAC_KPAD eKpad,MS_BOOL bClear)1596 MS_BOOL HAL_CIPHER_Hash_SetHMACKey(DRV_CIPHER_HMAC_KEY stHMACKey, CIPHER_HMAC_KPAD eKpad, MS_BOOL bClear)
1597 {
1598 MS_BOOL bHMAC = TRUE;
1599 MS_U32 u32HMACKeySel = 0;
1600 MS_U32 u32Kpad = CMD_HASH_IKP;
1601 HAL_CIPHER_KEYSRC KeySrc;
1602
1603 //Check Key Source, Index
1604 if(((E_CIPHER_KSRC_KL == stHMACKey.eKeySrc) && (stHMACKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
1605 ((E_CIPHER_KSRC_OTP == stHMACKey.eKeySrc) && (stHMACKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
1606 {
1607 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
1608 __func__, __LINE__, stHMACKey.eKeySrc, stHMACKey.u8KeyIdx));
1609 return FALSE;
1610 }
1611
1612 //DRV to HAL Type transfer
1613 KeySrc = _HAL_CIPHER_TransKey(stHMACKey.eKeySrc, stHMACKey.u8KeyIdx);
1614
1615 switch(KeySrc)
1616 {
1617 case E_DMA_KSEL_REGKEY:
1618 u32HMACKeySel = CMD_HMAC_KSEL_HK;
1619 break;
1620 case E_DMA_KSEL_STRN:
1621 u32HMACKeySel = CMD_HMAC_KSEL_STRN;
1622 break;
1623 case E_DMA_KSEL_MK0:
1624 u32HMACKeySel = CMD_HMAC_KSEL_MK0;
1625 break;
1626 case E_DMA_KSEL_MK1:
1627 u32HMACKeySel = CMD_HMAC_KSEL_MK1;
1628 break;
1629 case E_DMA_KSEL_CCCK:
1630 u32HMACKeySel = CMD_HMAC_KSEL_CCCK;
1631 break;
1632 case E_DMA_KSEL_SK0:
1633 u32HMACKeySel = CMD_HMAC_KSEL_SK0;
1634 break;
1635 case E_DMA_KSEL_SK1:
1636 u32HMACKeySel = CMD_HMAC_KSEL_SK1;
1637 break;
1638 case E_DMA_KSEL_SK2:
1639 u32HMACKeySel = CMD_HMAC_KSEL_SK2;
1640 break;
1641 case E_DMA_KSEL_SK3:
1642 u32HMACKeySel = CMD_HMAC_KSEL_SK3;
1643 break;
1644 default:
1645 u32HMACKeySel = 0;
1646 break;
1647 }
1648
1649 if(eKpad == E_CIPHER_HMAC_OKPAD)
1650 {
1651 u32Kpad = CMD_HASH_OKP;
1652 }
1653
1654 if(bClear)
1655 {
1656 u32HMACKeySel += (MS_U32)CMD_HMAC_KSEL_CLR_SK;
1657 }
1658
1659 if(KeySrc == E_DMA_KSEL_REGKEY)
1660 {
1661 //command mode
1662 if (0 != stHMACKey.pu8KeyData)
1663 {
1664 memset(_pu8HashHMACHostKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
1665 memcpy(_pu8HashHMACHostKey, (MS_U8 *)stHMACKey.pu8KeyData , stHMACKey.u8KeyLen);
1666 _uHashCtrl0.HashCtrl0.DK = CMD_HMAC_KSEL_DIR_HK;
1667 }
1668 else
1669 {
1670 memset(_pu8HashHMACHostKey, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
1671 bHMAC = FALSE;
1672 }
1673 }
1674
1675 _uHashCtrl0.HashCtrl0.HMAC = bHMAC;
1676 _uHashCtrl0.HashCtrl0.KPAD = u32Kpad;
1677 _uHashCtrl0.HashCtrl0.HMAC_KeySel = u32HMACKeySel;
1678
1679 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HMAC[%d], HMAC KPAD[%u] HMAC KeySel[%u]!\n",
1680 __func__, __LINE__, bHMAC, u32Kpad, u32HMACKeySel));
1681
1682 return TRUE;
1683 }
1684
HAL_CIPHER_Hash_Set_CaVid(MS_U32 u32CAVid)1685 MS_BOOL HAL_CIPHER_Hash_Set_CaVid(MS_U32 u32CAVid)
1686 {
1687 MS_U32 u32Tmp = u32CAVid;
1688
1689 if(u32Tmp > HAL_CRYPTODMA_CAVID_MAX)
1690 {
1691 return FALSE;
1692 }
1693
1694 if(u32Tmp == 0)
1695 {
1696 u32Tmp = _CIPHER_CAVid ;
1697 }
1698 else
1699 {
1700 u32Tmp = u32CAVid;
1701 }
1702
1703 _uHashCtrl1.HashCtrl1.CaVid = u32Tmp;
1704
1705 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set CAVid [0x%x]\n",
1706 __func__, __LINE__, (unsigned int)u32Tmp));
1707
1708 return TRUE;
1709 }
1710
HAL_CIPHER_Hash_Set_IV(MS_U8 * pu8IV,MS_U32 u32IVSize,MS_U32 u32IVSel)1711 MS_BOOL HAL_CIPHER_Hash_Set_IV(MS_U8* pu8IV, MS_U32 u32IVSize ,MS_U32 u32IVSel)
1712 {
1713 // 256 bits for sha256 , 160 bits for sha1
1714 _uHashCtrl0.HashCtrl0.InitHashSel = u32IVSel ;
1715
1716 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH IVSel [%u]\n",
1717 __func__, __LINE__, u32IVSel));
1718
1719 if(u32IVSel == CMD_HASH_IV_CMD)
1720 {
1721 if((pu8IV != NULL) && (u32IVSize > 0))
1722 {
1723 memset(_pu8HashIV, 0x0, HASH_CMD_IV_SIZE);
1724 memcpy(_pu8HashIV, (MS_U8 *)pu8IV , u32IVSize);
1725
1726 return TRUE;
1727 }
1728 else
1729 {
1730 return FALSE;
1731 }
1732 }
1733
1734 return TRUE;
1735 }
1736
1737
HAL_CIPHER_Hash_Set_InitWordCnt(HAL_CIPHER_IWCTYPE eIWCType,MS_U32 u32StartBytes)1738 MS_BOOL HAL_CIPHER_Hash_Set_InitWordCnt(HAL_CIPHER_IWCTYPE eIWCType, MS_U32 u32StartBytes)
1739 {
1740 MS_U32 u32IWCType = 0;
1741 MS_U32 u32IWC = 0;
1742 MS_U32 Rpt[2] = {0};
1743
1744 if(eIWCType == E_CIPHER_HASH_IWC_PRV) //Init Word Count from report
1745 {
1746 u32IWCType = CMD_HASH_IWC_RPT;
1747 HAL_CIPHER_Hash_GetRpt(Rpt, 2); //For debug
1748 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IWC from report is [%u]\n",
1749 __func__, __LINE__, Rpt[1]>>2));
1750 }
1751 else
1752 {
1753 u32IWCType = CMD_HASH_IWC_CMDQ;
1754 if((u32StartBytes % HASH_MANUAL_BLOCK_SIZE) != 0)
1755 {
1756 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Init word count is 64 bytes alignment!\n",
1757 __func__, __LINE__));
1758 return FALSE;
1759 }
1760
1761 if(u32StartBytes != 0)
1762 {
1763 u32IWC = u32StartBytes/4; //Init Word Count
1764 }
1765 else
1766 {
1767 u32IWC = 0;
1768 }
1769 }
1770
1771 _u32InitWordCnt = u32IWC;
1772 _uHashCtrl0.HashCtrl0.IWC_Sel = u32IWCType;
1773
1774 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IWC type[%u], IWC[%u]\n",
1775 __func__, __LINE__, u32IWCType, _u32InitWordCnt));
1776
1777 return TRUE;
1778 }
1779
HAL_CIPHER_Hash_Set_MsgSrcFrom(CIPHER_MEM_TYPE eMemType,MS_U32 * u32HashSrc)1780 MS_BOOL HAL_CIPHER_Hash_Set_MsgSrcFrom(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashSrc)
1781 {
1782 MS_U32 u32SrcTmp = 0;
1783 switch(eMemType)
1784 {
1785 case E_CIPHER_DRAM:
1786 u32SrcTmp = CMD_HASH_SRC_DRAM;
1787 _u32HashSrcAddr = 0;
1788 break;
1789 case E_CIPHER_DQMEM:
1790 u32SrcTmp = CMD_HASH_SRC_R2;
1791 _u32HashSrcAddr = HAL_CIPHER_BASE_DQMEM;
1792 break;
1793 case E_CIPHER_IQMEM:
1794 u32SrcTmp = CMD_HASH_SRC_R2;
1795 _u32HashSrcAddr = HAL_CIPHER_BASE_IQMEM;
1796 break;
1797 case E_CIPHER_DIRECT:
1798 u32SrcTmp = CMD_HASH_SRC_REG;
1799 _u32HashSrcAddr = 0;
1800 break;
1801 default:
1802 u32SrcTmp = CMD_HASH_SRC_DRAM;
1803 _u32HashSrcAddr = 0;
1804 break;
1805 }
1806
1807 *u32HashSrc = u32SrcTmp;
1808
1809 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH source from [%u]\n",
1810 __func__, __LINE__, u32SrcTmp));
1811
1812 return TRUE;
1813 }
1814
HAL_CIPHER_Hash_Set_OutputDstTo(CIPHER_MEM_TYPE eMemType,MS_U32 * u32HashDst)1815 MS_BOOL HAL_CIPHER_Hash_Set_OutputDstTo(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashDst)
1816 {
1817 MS_U32 u32DstTmp = 0;
1818 switch(eMemType)
1819 {
1820 case E_CIPHER_DRAM:
1821 u32DstTmp = CMD_HASH_OUTPUT_DRAM;
1822 _u32HashDestAddr = 0;
1823 break;
1824 case E_CIPHER_DQMEM:
1825 u32DstTmp = CMD_HASH_OUTPUT_R2;
1826 _u32HashDestAddr = HAL_CIPHER_BASE_DQMEM;
1827 break;
1828 case E_CIPHER_IQMEM:
1829 u32DstTmp = CMD_HASH_OUTPUT_R2;
1830 _u32HashDestAddr = HAL_CIPHER_BASE_IQMEM;
1831 break;
1832 case E_CIPHER_DIRECT:
1833 u32DstTmp = CMD_HASH_OUTPUT_RPT;
1834 _u32HashDestAddr = 0;
1835 break;
1836 default:
1837 u32DstTmp = CMD_HASH_OUTPUT_RPT;
1838 _u32HashDestAddr = 0;
1839 break;
1840 }
1841
1842 *u32HashDst = u32DstTmp;
1843 _uHashCtrl0.HashCtrl0.Dest = u32DstTmp;
1844 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH destination[%u]\n",
1845 __func__, __LINE__, u32DstTmp));
1846
1847 return TRUE;
1848 }
1849
HAL_CIPHER_Hash_Set_OuputAddr(MS_PHY u32OutputPAddr,MS_U32 u32DstSel)1850 MS_BOOL HAL_CIPHER_Hash_Set_OuputAddr(MS_PHY u32OutputPAddr, MS_U32 u32DstSel)
1851 {
1852 if ((CMD_HASH_OUTPUT_DRAM == u32DstSel) || (CMD_HASH_OUTPUT_R2 == u32DstSel))
1853 {
1854 if (0 != u32OutputPAddr)
1855 {
1856 _u32HashDestAddr += u32OutputPAddr;
1857 }
1858 else
1859 {
1860 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Hash output address is NULL\n",__func__, __LINE__));
1861 return FALSE;
1862 }
1863 }
1864 return TRUE;
1865 }
1866
HAL_CIPHER_Hash_SetMsgLength(MS_U32 u32Size)1867 void HAL_CIPHER_Hash_SetMsgLength( MS_U32 u32Size )
1868 {
1869 _u32HashMsgLen = u32Size;
1870
1871 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH message length[%u]\n",
1872 __func__, __LINE__, u32Size));
1873
1874 return ;
1875 }
1876
HAL_CIPHER_Hash_SetHOS(MS_BOOL bHos)1877 void HAL_CIPHER_Hash_SetHOS(MS_BOOL bHos)
1878 {
1879 _uHashCtrl0.HashCtrl0.HOS = bHos;
1880
1881 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HOS[%d]\n",
1882 __func__, __LINE__, bHos));
1883
1884 return ;
1885 }
1886
1887
HAL_CIPHER_Hash_SetMsg(MS_PHY u32MsgPAddr,MS_U32 u32Size,MS_U32 u32SrcSel)1888 MS_BOOL HAL_CIPHER_Hash_SetMsg(MS_PHY u32MsgPAddr, MS_U32 u32Size ,MS_U32 u32SrcSel )
1889 {
1890 _uHashCtrl0.HashCtrl0.Src = u32SrcSel;
1891 _u32HashMsgLen = u32Size;
1892
1893 if ((CMD_HASH_SRC_DRAM == u32SrcSel) || (CMD_HASH_SRC_R2 == u32SrcSel))
1894 {
1895 if (0 != u32MsgPAddr)
1896 {
1897 _u32HashSrcAddr += u32MsgPAddr;
1898 }
1899 else
1900 {
1901 return FALSE;
1902 }
1903 }
1904 else if (CMD_HASH_SRC_REG == u32SrcSel)
1905 {
1906 if((u32MsgPAddr == 0) || (u32Size > HASH_CMD_MSG_SIZE))
1907 {
1908 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Error:Set HASH direct message size[%u] over 64 bytes\n",
1909 __func__, __LINE__, u32Size));
1910 return FALSE;
1911 }
1912 _u32HashSrcAddr = 0;
1913 memset(_pu8HashMsg , 0x0 , HASH_CMD_MSG_SIZE);
1914 memcpy(_pu8HashMsg , (MS_U8 *)(MsOS_PA2KSEG1(u32MsgPAddr)) , u32Size);
1915 }
1916
1917 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set HASH message source[%u], size[%u]\n",
1918 __func__, __LINE__, u32SrcSel, _u32HashMsgLen));
1919
1920 return TRUE;
1921
1922 }
1923
1924
HAL_CIPHER_Hash_Start(HAL_CIPHER_INTMODE IntMode,MS_BOOL bWaitCmdQ,MS_BOOL bRst,MS_U16 u16CmdID)1925 MS_BOOL HAL_CIPHER_Hash_Start(HAL_CIPHER_INTMODE IntMode , MS_BOOL bWaitCmdQ , MS_BOOL bRst, MS_U16 u16CmdID)
1926 {
1927 MS_U32 u32SpareCnt = 0 , CmdLen = 0 , i = 0 ;
1928 MS_U32 u32Tmp;
1929
1930 _uHashCtrl1.HashCtrl1.TID = u16CmdID;
1931 _uHashCtrl0.HashCtrl0.CMD = CMD_HASH_START_RR ;
1932
1933 _uHashCtrl0.HashCtrl0.OVT = FALSE ;
1934 _uHashCtrl0.HashCtrl0.IntM = IntMode ;
1935
1936 CmdLen = _HAL_CIPHER_GetCmdLen(E_CIPHER_TYPE_SHA);
1937
1938 _uHashCtrl0.HashCtrl0.CL = CmdLen & CMD_LEN_MASK ;
1939
1940 _uHashCtrl1.HashCtrl1.NS = 0;
1941
1942 MS_U32 MIUCrossBar = REG32(_u32RegBase + REG_MIU_CROSSBAR); //MIU CrossBar Bank 0x1613
1943 REG32(_u32RegBase + REG_MIU_CROSSBAR) = MIUCrossBar | 0xf; //enable MIU crossbar
1944
1945
1946 SHA_RETRY:
1947 u32SpareCnt = REG32(&_AESDMACtrl->SpareCnt) ;
1948
1949 if (u32SpareCnt > CmdLen)
1950 {
1951 u32SpareCnt -= CmdLen ;
1952
1953 WRITE_CMDQ( (_uHashCtrl0.u32HashCtrl0)) ;
1954
1955 WRITE_CMDQ( (_uHashCtrl1.u32HashCtrl1)) ;
1956
1957 WRITE_CMDQ( (_uHashCtrl2.u32HashCtrl2)) ;
1958
1959 WRITE_CMDQ(_u32HashMsgLen) ;
1960
1961 //SRC
1962 if (_uHashCtrl0.HashCtrl0.Src != CMD_HASH_SRC_REG)
1963 {
1964 WRITE_CMDQ(_u32HashSrcAddr) ;
1965 }
1966
1967 //RR address
1968 if (_uHashCtrl2.HashCtrl2.RR == TRUE)
1969 {
1970 WRITE_CMDQ(_u32ReportAddr) ;
1971 }
1972
1973 // IWC
1974 if (CMD_HASH_IWC_CMDQ == _uHashCtrl0.HashCtrl0.IWC_Sel)
1975 {
1976 WRITE_CMDQ(_u32InitWordCnt);
1977 }
1978 else
1979 {
1980 REG32(&_AESDMACtrl->Hash_Reportp[1]) = _u32InitWordCnt;
1981 }
1982
1983 // DST
1984 if ((CMD_HASH_OUTPUT_DRAM == _uHashCtrl0.HashCtrl0.Dest) || (_uHashCtrl0.HashCtrl0.Dest == CMD_HASH_OUTPUT_R2 ))
1985 {
1986 WRITE_CMDQ(_u32HashDestAddr);
1987 }
1988
1989 // HASH Initial Vector from CmdQ
1990 if (CMD_HASH_IV_CMD == _uHashCtrl0.HashCtrl0.InitHashSel )
1991 {
1992 for ( i = 0 ; i < (HASH_CMD_IV_SIZE/4) ; i ++ )
1993 {
1994 u32Tmp = ((_pu8HashIV[4*i+0]<<24)|(_pu8HashIV[4*i+1]<<16)|(_pu8HashIV[4*i+2]<<8)|(_pu8HashIV[4*i+3]) );
1995
1996 WRITE_CMDQ(u32Tmp);
1997 }
1998 }
1999
2000 // HASH Data from CmdQ
2001 if ( CMD_HASH_SRC_REG == _uHashCtrl0.HashCtrl0.Src )
2002 {
2003 for ( i = 0 ; i < (HASH_CMD_MSG_SIZE/4) ; i ++ )
2004 {
2005 u32Tmp = ( (_pu8HashMsg[i*4+0]<<24)
2006 |(_pu8HashMsg[i*4+1]<<16)
2007 |(_pu8HashMsg[i*4+2]<<8)
2008 |(_pu8HashMsg[i*4+3]<<0)
2009 );
2010
2011 WRITE_CMDQ(u32Tmp);
2012 }
2013 }
2014
2015 if((CMD_HMAC_KSEL_HK == _uHashCtrl0.HashCtrl0.HMAC_KeySel) && (CMD_HMAC_KSEL_DIR_HK == _uHashCtrl0.HashCtrl0.DK))
2016 {
2017 for ( i = 0 ; i < (HASH_CMD_HMAC_HOSTKEY_SIZE/4) ; i ++ )
2018 {
2019 u32Tmp = ((_pu8HashHMACHostKey[4*i+0]<<24)|(_pu8HashHMACHostKey[4*i+1]<<16)|(_pu8HashHMACHostKey[4*i+2]<<8)|(_pu8HashHMACHostKey[4*i+3]) );
2020
2021 WRITE_CMDQ(u32Tmp);
2022 }
2023 }
2024 // [HW] Hardware will check Current spare count != Write back Spare count to start operation.
2025 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
2026 return TRUE ;
2027
2028 }
2029 else
2030 {
2031 // [HW] Check Current spare count == Write back Spare count to start wait cmd
2032 REG32(&_AESDMACtrl->SpareCnt) = u32SpareCnt ;
2033
2034 if (bWaitCmdQ)
2035 {
2036 // Retry until CMDQ avaliable
2037 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]HASH cmd retry!\n",
2038 __func__, __LINE__));
2039 goto SHA_RETRY;
2040 }
2041 else
2042 {
2043 // Return Fail, Command abort
2044 return FALSE ;
2045 }
2046 }
2047 }
2048
HAL_CIPHER_Hash_CmdDone(MS_U32 u32CmdID,MS_U32 * u32Ret)2049 MS_BOOL HAL_CIPHER_Hash_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret)
2050 {
2051 MS_U32 u32ExcTmp = 0;
2052
2053 MS_U32 u32Tmp = REG32(&_AESDMACtrl->Hash_Reportp[0]) ;
2054 MS_U32 u32RptId = u32Tmp & REG_CIPHER_RPT_THREAD_MSK;
2055
2056 if(u32RptId == u32CmdID)
2057 {
2058 u32ExcTmp = (MS_U32)REG32(&_AESDMACtrl->Dma_Ctrl[REG_EXCEPT_FLAG]);
2059 *u32Ret = u32ExcTmp;
2060 }
2061 else
2062 {
2063 HAL_DEBUG_CIPHER(CIPHER_DBG_WARN, printf("[%s][%d]HASH Cmd[%u] Not done!ReportId[%u]\n",
2064 __func__, __LINE__, u32CmdID, u32RptId));
2065 return FALSE;
2066 }
2067
2068 return TRUE;
2069 }
2070
HAL_CIPHER_Hash_ExceptFilter(MS_U32 * pu32Exception,CIPHER_KEY_SRC eKeySrc,MS_U8 u8KeyIdx)2071 void HAL_CIPHER_Hash_ExceptFilter(MS_U32 *pu32Exception, CIPHER_KEY_SRC eKeySrc, MS_U8 u8KeyIdx)
2072 {
2073 //Because CryptoDMA will check every key slot usage for HMAC
2074 //We need to filter out the correct key exception
2075 MS_U32 u32ExcTmp = 0;
2076 HAL_CIPHER_KEYSRC KeySrc = 0;
2077 MS_U32 i = 0;
2078
2079 u32ExcTmp = *pu32Exception;
2080
2081 //DRV to HAL Type transfer
2082 KeySrc = _HAL_CIPHER_TransKey(eKeySrc, u8KeyIdx);
2083
2084 //Only check HMAC key exception
2085 for(i = E_CIPHER_disable_masterkey0;i<=E_CIPHER_disable_reg_key_3;i++) //check each error flag
2086 {
2087 if((u32ExcTmp & (1 << i)) >> i)
2088 {
2089 switch(i)
2090 {
2091 case E_CIPHER_disable_masterkey0:
2092 if(E_DMA_KSEL_MK0 != KeySrc)
2093 u32ExcTmp &= (~(1 << E_CIPHER_disable_masterkey0));
2094 break;
2095
2096 case E_CIPHER_disable_masterkey1:
2097 if(E_DMA_KSEL_MK1 != KeySrc)
2098 u32ExcTmp &= (~(1 << E_CIPHER_disable_masterkey1));
2099 break;
2100
2101 case E_CIPHER_disable_cck:
2102 if(E_DMA_KSEL_CCCK != KeySrc)
2103 u32ExcTmp &= (~(1 << E_CIPHER_disable_cck));
2104 break;
2105
2106 case E_CIPHER_disable_reg_key_0:
2107 if(E_DMA_KSEL_SK0 != KeySrc)
2108 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_0));
2109 break;
2110
2111 case E_CIPHER_disable_reg_key_1:
2112 if(E_DMA_KSEL_SK1 != KeySrc)
2113 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_1));
2114 break;
2115
2116 case E_CIPHER_disable_reg_key_2:
2117 if(E_DMA_KSEL_SK2 != KeySrc)
2118 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_2));
2119 break;
2120
2121 case E_CIPHER_disable_reg_key_3:
2122 if(E_DMA_KSEL_SK3 != KeySrc)
2123 u32ExcTmp &= (~(1 << E_CIPHER_disable_reg_key_3));
2124 break;
2125
2126 default:
2127 break;
2128 }
2129 }
2130 }
2131
2132 *pu32Exception = u32ExcTmp;
2133
2134 return;
2135
2136 }
2137 // =====================================
2138 // Parser function implementation
2139 // =====================================
HAL_CIPHER_PARSER_Set_Mode(CIPHER_PARSER_MODE eMode)2140 void HAL_CIPHER_PARSER_Set_Mode(CIPHER_PARSER_MODE eMode)
2141
2142 {
2143 HAL_CIPHER_PARSER_HDCPMODE eHDCPMode = 0;
2144 HAL_CIPHER_PARSER_TSMODE eTSMode = 0;
2145 HAL_CIPHER_PARSER_PKTMODE ePKTMode = 0;
2146 HAL_CIPHER_PARSER_AUTOMODE eAutoMode = 0;
2147 HAL_CIPHER_PARSER_ITMODE eITMode = 0;
2148 HAL_CIPHER_PARSER_CLEARMODE eClearMode = 0;
2149
2150 switch(eMode)
2151 {
2152 case E_CIPHER_PARSER_TS_PKT192:
2153 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2154 eTSMode = E_PARSER_TSMODE_TS;
2155 ePKTMode = E_PARSER_PKTMODE_192;
2156 eAutoMode = E_PARSER_AUTOMODE_EN;
2157 eITMode = E_PARSER_ITMODE_EN;
2158 eClearMode = E_PARSER_CLEARMODE_NONE;
2159 break;
2160 case E_CIPHER_PARSER_TS_PKT192_CLEAR:
2161 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2162 eTSMode = E_PARSER_TSMODE_TS;
2163 ePKTMode = E_PARSER_PKTMODE_192;
2164 eAutoMode = E_PARSER_AUTOMODE_EN;
2165 eITMode = E_PARSER_ITMODE_EN;
2166 eClearMode = E_PARSER_CLEARMODE_EN;
2167 break;
2168 case E_CIPHER_PARSER_TS_PKT188:
2169 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2170 eTSMode = E_PARSER_TSMODE_TS;
2171 ePKTMode = E_PARSER_PKTMODE_188;
2172 eAutoMode = E_PARSER_AUTOMODE_EN;
2173 eITMode = E_PARSER_ITMODE_EN;
2174 eClearMode = E_PARSER_CLEARMODE_NONE;
2175 break;
2176 case E_CIPHER_PARSER_TS_PKT188_CLEAR:
2177 eHDCPMode = E_PARSER_HDCPMODE_NONE;
2178 eTSMode = E_PARSER_TSMODE_TS;
2179 ePKTMode = E_PARSER_PKTMODE_188;
2180 eAutoMode = E_PARSER_AUTOMODE_EN;
2181 eITMode = E_PARSER_ITMODE_EN;
2182 eClearMode = E_PARSER_CLEARMODE_EN;
2183 break;
2184 case E_CIPHER_PARSER_HDCP20_PKT192:
2185 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2186 eTSMode = E_PARSER_TSMODE_PES;
2187 ePKTMode = E_PARSER_PKTMODE_192;
2188 eAutoMode = E_PARSER_AUTOMODE_EN;
2189 eITMode = E_PARSER_ITMODE_EN;
2190 eClearMode = E_PARSER_CLEARMODE_NONE;
2191 break;
2192 case E_CIPHER_PARSER_HDCP20_PKT192_CLEAR:
2193 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2194 eTSMode = E_PARSER_TSMODE_PES;
2195 ePKTMode = E_PARSER_PKTMODE_192;
2196 eAutoMode = E_PARSER_AUTOMODE_EN;
2197 eITMode = E_PARSER_ITMODE_NONE;
2198 eClearMode = E_PARSER_CLEARMODE_EN;
2199 break;
2200 case E_CIPHER_PARSER_HDCP20_PKT188:
2201 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2202 eTSMode = E_PARSER_TSMODE_PES;
2203 ePKTMode = E_PARSER_PKTMODE_188;
2204 eAutoMode = E_PARSER_AUTOMODE_EN;
2205 eITMode = E_PARSER_ITMODE_EN;
2206 eClearMode = E_PARSER_CLEARMODE_NONE;
2207 break;
2208 case E_CIPHER_PARSER_HDCP20_PKT188_CLEAR:
2209 eHDCPMode = E_PARSER_HDCPMODE_HDCP20;
2210 eTSMode = E_PARSER_TSMODE_PES;
2211 ePKTMode = E_PARSER_PKTMODE_188;
2212 eAutoMode = E_PARSER_AUTOMODE_EN;
2213 eITMode = E_PARSER_ITMODE_NONE;
2214 eClearMode = E_PARSER_CLEARMODE_EN;
2215 break;
2216 default:
2217 printf("Error: Not suport parser mode!\n");
2218 break;
2219 }
2220
2221 _uDmaCtrl2.DmaCtrl2.HP = TRUE;
2222 _uDmaCtrl2.DmaCtrl2.HDCP = eHDCPMode;
2223 _uDmaCtrl2.DmaCtrl2.TS = eTSMode;
2224 _uDmaCtrl2.DmaCtrl2.P192 = ePKTMode;
2225 _uDmaCtrl2.DmaCtrl2.AT = eAutoMode;
2226 _uDmaCtrl2.DmaCtrl2.IT = eITMode;
2227 _uDmaCtrl2.DmaCtrl2.CR = eClearMode;
2228
2229 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Parser config:HDCP[%d], TS[%d], P192[%d], AT[%d], IT[%d], ClearMode[%d]\n",
2230 __func__, __LINE__, eHDCPMode, eTSMode, ePKTMode, eAutoMode, eITMode, eClearMode));
2231
2232
2233 }
2234
HAL_CIPHER_PARSER_Set_MaskSCB(MS_BOOL bEnable)2235 void HAL_CIPHER_PARSER_Set_MaskSCB(MS_BOOL bEnable)
2236 {
2237 _uDmaCtrl2.DmaCtrl2.TsSbMk = bEnable;
2238 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Enable MaskSCB[%d]!\n",
2239 __func__, __LINE__, bEnable));
2240 }
2241
HAL_CIPHER_PARSER_Set_SCB(CIPHER_PARSER_SCB eSCB)2242 void HAL_CIPHER_PARSER_Set_SCB(CIPHER_PARSER_SCB eSCB)
2243 {
2244 MS_U8 u8SCB = 0;
2245
2246 if(eSCB == E_CIPHER_PARSER_SCB_10)
2247 {
2248 u8SCB = CMD_PARSER_SCB10;
2249 }
2250 else if(eSCB == E_CIPHER_PARSER_SCB_11)
2251 {
2252 u8SCB = CMD_PARSER_SCB11;
2253 }
2254 else
2255 {
2256 u8SCB = 0;
2257 }
2258 _uDmaCtrl2.DmaCtrl2.TsSbPn = u8SCB;
2259 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set SCB[%u]!\n",
2260 __func__, __LINE__, u8SCB));
2261 }
2262
HAL_CIPHER_PARSER_Set_ForceSCB(MS_BOOL bInsert,CIPHER_PARSER_SCB eSCB)2263 void HAL_CIPHER_PARSER_Set_ForceSCB(MS_BOOL bInsert, CIPHER_PARSER_SCB eSCB)
2264 {
2265 MS_U8 u8SCB = 0;
2266
2267 if(bInsert)
2268 {
2269 if(eSCB == E_CIPHER_PARSER_SCB_10)
2270 {
2271 u8SCB = CMD_PARSER_SCB10;
2272 }
2273 else if(eSCB == E_CIPHER_PARSER_SCB_11)
2274 {
2275 u8SCB = CMD_PARSER_SCB11;
2276 }
2277 else
2278 {
2279 u8SCB = 0;
2280 }
2281 }
2282
2283 _uDmaCtrl2.DmaCtrl2.InSb = bInsert;
2284 _uDmaCtrl2.DmaCtrl2.TsInSb = u8SCB;
2285
2286 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set Insert Enable[%d], SCB[%u]!\n",
2287 __func__, __LINE__, bInsert, u8SCB));
2288
2289 }
2290
HAL_CIPHER_PARSER_Rmv_SCB(MS_BOOL bRemove)2291 void HAL_CIPHER_PARSER_Rmv_SCB(MS_BOOL bRemove)
2292 {
2293 _uDmaCtrl2.DmaCtrl2.RmSb = bRemove;
2294 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Remove SCB[%d]!\n",
2295 __func__, __LINE__, bRemove));
2296 }
2297
HAL_CIPHER_PARSER_BypassPid(MS_BOOL bEnable)2298 void HAL_CIPHER_PARSER_BypassPid(MS_BOOL bEnable)
2299 {
2300 _uDmaCtrl2.DmaCtrl2.BPS = bEnable;
2301 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Bypass PID[%d]!\n",
2302 __func__, __LINE__, bEnable));
2303 }
2304
HAL_CIPHER_PARSER_Set_PID(CIPHER_PARSER_PID stPID)2305 void HAL_CIPHER_PARSER_Set_PID(CIPHER_PARSER_PID stPID)
2306 {
2307 if(stPID.pu8PID0 != NULL)
2308 {
2309 memset(_pu8PID0, 0x0 , PID_SIZE );
2310 memcpy(_pu8PID0, stPID.pu8PID0, PID_SIZE);
2311 }
2312 else
2313 {
2314 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set PID0 NULL!\n",
2315 __func__, __LINE__));
2316 }
2317
2318 if(stPID.pu8PID1 != NULL)
2319 {
2320 memset(_pu8PID1, 0x0 , PID_SIZE );
2321 memcpy(_pu8PID1, stPID.pu8PID1 , PID_SIZE);
2322 }
2323 else
2324 {
2325 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set PID1 NULL!\n",
2326 __func__, __LINE__));
2327 }
2328 }
2329
HAL_CIPHER_PARSER_Set_Key2(DRV_CIPHER_KEY stKey)2330 MS_BOOL HAL_CIPHER_PARSER_Set_Key2(DRV_CIPHER_KEY stKey)
2331 {
2332 HAL_CIPHER_KEYSRC KeySrc = 0;
2333 HAL_CIPHER_ALGO algo = 0;
2334 MS_BOOL bDK2 = FALSE;
2335 MS_BOOL bTwoKey = FALSE;
2336
2337 algo = _uDmaCtrl0.DmaCtrl0.Algo;
2338
2339 if(E_DMA_ALGO_NONE == algo)
2340 {
2341 //No key
2342 bDK2 = FALSE;
2343 bTwoKey = FALSE;
2344 memset(_pu8CipherKey2, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX);
2345 goto SET_KEY_DONE;
2346 }
2347
2348 //Check Key Source, Index
2349 if(((E_CIPHER_KSRC_KL == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_DMA_KEY_SLOT-1)) ||
2350 ((E_CIPHER_KSRC_OTP == stKey.eKeySrc) && (stKey.u8KeyIdx > HAL_CRYPTODMA_OTP_SCK_NUM-1)))
2351 {
2352 HAL_DEBUG_CIPHER(CIPHER_DBG_ERR, printf("[%s][%d]Invalid KeySrc[%d], Index[%d]\n",
2353 __func__, __LINE__, stKey.eKeySrc, stKey.u8KeyIdx));
2354 return FALSE;
2355 }
2356
2357 //DRV to HAL Type transfer
2358 KeySrc = _HAL_CIPHER_TransKey(stKey.eKeySrc, stKey.u8KeyIdx);
2359
2360 // key from CPU
2361 if(E_DMA_KSEL_REGKEY == KeySrc)
2362 {
2363 if ((0 != stKey.pu8KeyData) && (stKey.u8KeyLen != 0) && (stKey.u8KeyLen <= HAL_CRYPTODMA_KEYLEN_MAX) )
2364 {
2365 memset(_pu8CipherKey2, 0x0 , HAL_CRYPTODMA_KEYLEN_MAX );
2366 memcpy(_pu8CipherKey2, (MS_U8 *)stKey.pu8KeyData , stKey.u8KeyLen);
2367 bDK2 = TRUE;
2368 KeySrc = 0;
2369 }
2370 else
2371 {
2372 return FALSE ;
2373 }
2374 }
2375 else if(E_DMA_KSEL_CAIP == KeySrc)
2376 {
2377 bDK2 = FALSE ;
2378 KeySrc = 0 ;
2379 }
2380 else// key from KL or OTP
2381 {
2382 bDK2 = FALSE;
2383 }
2384
2385 bTwoKey = TRUE;
2386
2387 SET_KEY_DONE:
2388
2389 _uDmaCtrl3.DmaCtrl3.DK2 = bDK2;
2390 _uDmaCtrl3.DmaCtrl3.KeySel2 = KeySrc;
2391 _uDmaCtrl2.DmaCtrl2.TK = bTwoKey;
2392
2393 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set DK2[%d], KeySel2[%d]\n",
2394 __func__, __LINE__, bDK2, KeySrc));
2395
2396 return TRUE ;
2397
2398 }
2399
HAL_CIPHER_PARSER_Set_IV2(MS_U8 * pu8IV2,MS_U8 u8IVLen)2400 MS_BOOL HAL_CIPHER_PARSER_Set_IV2(MS_U8 *pu8IV2, MS_U8 u8IVLen)
2401 {
2402 if((pu8IV2 != NULL) && (u8IVLen != 0))
2403 {
2404 memset(_pu8IV2, 0, CIPHER_KEY_SIZE);
2405 memcpy(_pu8IV2, pu8IV2, u8IVLen);
2406 _uDmaCtrl3.DmaCtrl3.DIV2 = TRUE;
2407
2408 return TRUE;
2409 }
2410 else
2411 {
2412 HAL_DEBUG_CIPHER(CIPHER_DBG_INFO, printf("[%s][%d]Set IV2 NULL!\n",
2413 __func__, __LINE__));
2414 return FALSE;
2415 }
2416
2417 }
2418
HAL_CIPHER_PARSER_Set_ClearStartMode(MS_BOOL bEnable)2419 void HAL_CIPHER_PARSER_Set_ClearStartMode(MS_BOOL bEnable)
2420 {
2421 _uDmaCtrl3.DmaCtrl3.CRS = bEnable;
2422 }
2423
2424 // =====================================
2425 // MISC function implementation
2426 // =====================================
HAL_CIPHER_Misc_Random(MS_U8 * pu8Buf,MS_U32 u32Size)2427 MS_BOOL HAL_CIPHER_Misc_Random(MS_U8 *pu8Buf, MS_U32 u32Size)
2428 {
2429 MS_U16 u16TRN = 0;
2430 MS_U16 u16PreTRN = 0;
2431 MS_U32 u32Count = 0;
2432
2433 if(NULL == pu8Buf || 0 == u32Size)
2434 return FALSE;
2435
2436 #if defined (MCU_AEON)
2437
2438 while(u32Count < u32Size)
2439 {
2440 do{
2441 do{
2442 //Toggle random number bit
2443 REG32(_u32RegBase+REG_RNG_TRNG_SCPU) ^= REG_RNG_TRNG_ACK_SCPU;
2444 }//Read random number valid
2445 while( !(REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_VALID_SCPU_MASK) );
2446 }
2447 while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_SCPU) & REG_RNG_TRNG_OUT_SCPU_MASK))==u16PreTRN );
2448 u16PreTRN = u16TRN;
2449
2450 if(0 == ((u32Size - u32Count)%2UL))
2451 {
2452 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2453 *(pu8Buf+u32Count+1) = (u16TRN & 0xFF00UL) >> 8;
2454 u32Count += 2;
2455 }
2456 else
2457 {
2458 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2459 u32Count += 1;
2460 }
2461 }
2462
2463 #else
2464
2465 while(u32Count < u32Size)
2466 {
2467 do{
2468 do{
2469 //Toggle random number bit
2470 REG32(_u32RegBase+REG_RNG_TRNG_ACPU) ^= REG_RNG_TRNG_ACK_ACPU;
2471 }//Read random number valid
2472 while( !(REG32(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_VALID_ACPU_MASK) );
2473 }
2474 while( (u16TRN = (REG32(_u32RegBase+REG_RNG_TRNG_ACPU) & REG_RNG_TRNG_OUT_ACPU_MASK))==u16PreTRN );
2475 u16PreTRN = u16TRN;
2476
2477 if(0 == ((u32Size - u32Count)%2UL))
2478 {
2479 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2480 *(pu8Buf+u32Count+1) = (u16TRN & 0xFF00UL) >> 8;
2481 u32Count += 2;
2482 }
2483 else
2484 {
2485 *(pu8Buf+u32Count) = u16TRN & 0xFFUL;
2486 u32Count += 1;
2487 }
2488 }
2489 #endif
2490
2491 return TRUE;
2492 }
2493
2494
2495