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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file halAESDMA.c
97 // @brief AESDMA HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100
101 #include "MsCommon.h"
102 #include "regAESDMA.h"
103 #include "halAESDMA.h"
104 #include "halCHIP.h"
105 #include "drvAESDMA.h"
106
107
108 //--------------------------------------------------------------------------------------------------
109 // Driver Compiler Option
110 //--------------------------------------------------------------------------------------------------
111
112 //--------------------------------------------------------------------------------------------------
113 // Type and Struct
114 //--------------------------------------------------------------------------------------------------
115 typedef struct
116 {
117 MS_U32 Dma_Ctrl[19];
118 MS_U32 Secure_dma3_ctrl;
119 MS_U32 Parser_Pid1;
120 MS_U32 Parser_Ctrl;
121 MS_U32 Kslot_Index;
122 } AESDMA_REGISTER_BACKUP ;
123
124 static AESDMA_REGISTER_BACKUP _gAESDMARegisterBackup;
125
126
127 //--------------------------------------------------------------------------------------------------
128 // TSP Hardware Abstraction Layer
129 //--------------------------------------------------------------------------------------------------
130 static MS_VIRT _u32RegBase = NULL;
131 static MS_VIRT _u32PmRegBase = NULL;
132 static MS_U32 SECUREBASECtrl_Buffer;
133 static REG_AESDMACtrl *_AESDMACtrl = (REG_AESDMACtrl*)REG_AESDMACTRL_BASE;
134 static REG_SHARNGCtrl *_SHARNGCtrl = (REG_SHARNGCtrl*)REG_SHARNGCTRL_BASE;
135 static REG_AESDMAClk *_AESDMAClk = (REG_AESDMAClk*)REG_AESDMACLK_BASE;
136 static REG_AESDMAMbx *_AESDMAMbx = (REG_AESDMAMbx*)REG_AESDMAMBX_BASE;
137 static REG_PARSERCtrl *_PARSERCtrl = (REG_PARSERCtrl*)REG_PARSERCTRL_BASE;
138 static REG_CIPHERCtrl *_CIPHERCtrl = (REG_CIPHERCtrl*)REG_CIPHERCTRL_BASE;
139 static REG_DMASECURECtrl *_DMASECURECtrl = (REG_DMASECURECtrl*)REG_DMASECURE_BASE;
140 static REG_SECUREBASECtrl *_SECUREBASECtrl = (REG_SECUREBASECtrl*)REG_DMASECURE_CTRL_BASE;
141 static REG_AESDMACtrlEx *_AESDMACtrlEx = (REG_AESDMACtrlEx*)REG_AESDMAEXT_BASE;
142 static REG_TZPCCtrl *_TZPCCtrl = (REG_TZPCCtrl*)REG_TZPC_NONPM_BASE;
143 static REG_HDCP22Data *_HDCP22Data = (REG_HDCP22Data*)REG_HDCP22_BASE;
144 static REG_HDCP22SEKCtrl *_HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)REG_HDCP22_SEK;
145 static REG_HDCP14SEKCtrl *_HDCP14SekCtrl = (REG_HDCP14SEKCtrl*)REG_HDCP14_BASE;
146 static REG_ANAMISCBASECtrl *_ANAMISCCtrl = (REG_ANAMISCBASECtrl*)REG_ANA_MISC_BASE;
147 static REG_AES_DSCMB6Ctrl *_AESDSCMB6Ctrl = (REG_AES_DSCMB6Ctrl*)REG_AES_DSCMB6_BASE;
148 static REG_AES_DSCMB7Ctrl *_AESDSCMB7Ctrl = (REG_AES_DSCMB7Ctrl*)REG_AES_DSCMB7_BASE;
149
150 #define REG32_W(reg, value) do { \
151 (reg)->H = ((value) >> 16); \
152 (reg)->L = ((value) & 0x0000FFFF); \
153 } while(0)
154
155 //--------------------------------------------------------------------------------------------------
156 // Macro of bit operations
157 //--------------------------------------------------------------------------------------------------
158
_AESDMA_REG32_R(REG32 * reg)159 MS_U32 _AESDMA_REG32_R(REG32 *reg)
160 {
161 MS_U32 value;
162
163 value = (reg)->H << 16;
164 value |= (reg)->L;
165
166 return value;
167 }
168
169 //--------------------------------------------------------------------------------------------------
170 // Inline Function
171 //--------------------------------------------------------------------------------------------------
HAL_AESDMA_SetBank(MS_VIRT u32NonPmBankAddr,MS_VIRT u32PmBankAddr)172 void HAL_AESDMA_SetBank(MS_VIRT u32NonPmBankAddr, MS_VIRT u32PmBankAddr)
173 {
174 _u32RegBase = u32NonPmBankAddr;
175 _u32PmRegBase = u32PmBankAddr;
176 _AESDMACtrl = (REG_AESDMACtrl*)(_u32RegBase + REG_AESDMACTRL_BASE);
177 _SHARNGCtrl = (REG_SHARNGCtrl*)(_u32RegBase + REG_SHARNGCTRL_BASE);
178 _AESDMAClk = (REG_AESDMAClk*)(_u32RegBase + REG_AESDMACLK_BASE);
179 _AESDMAMbx = (REG_AESDMAMbx*)(_u32PmRegBase + REG_AESDMAMBX_BASE);
180 _PARSERCtrl = (REG_PARSERCtrl*)(_u32RegBase + REG_PARSERCTRL_BASE);
181 _CIPHERCtrl = (REG_CIPHERCtrl*)(_u32RegBase + REG_CIPHERCTRL_BASE);
182 _DMASECURECtrl = (REG_DMASECURECtrl*)(_u32RegBase + REG_DMASECURE_BASE);
183 _SECUREBASECtrl = (REG_SECUREBASECtrl*)(_u32RegBase + REG_DMASECURE_CTRL_BASE);
184 _AESDMACtrlEx = (REG_AESDMACtrlEx*)(_u32RegBase + REG_AESDMAEXT_BASE);
185 _TZPCCtrl = (REG_TZPCCtrl*)(_u32RegBase + REG_TZPC_NONPM_BASE);
186 _HDCP22Data = (REG_HDCP22Data*)(_u32RegBase + REG_HDCP22_BASE);
187 _HDCP22SekCtrl = (REG_HDCP22SEKCtrl*)(_u32RegBase + REG_HDCP22_SEK);
188 _HDCP14SekCtrl = (REG_HDCP14SEKCtrl*)(_u32RegBase + REG_HDCP14_BASE);
189 _ANAMISCCtrl = (REG_ANAMISCBASECtrl*)(_u32RegBase + REG_ANA_MISC_BASE);
190 _AESDSCMB6Ctrl = (REG_AES_DSCMB6Ctrl*)(_u32RegBase + REG_AES_DSCMB6_BASE);
191 _AESDSCMB7Ctrl = (REG_AES_DSCMB7Ctrl*)(_u32RegBase + REG_AES_DSCMB7_BASE);
192 }
193
AESDMA_GetMIU1Base(void)194 MS_PHY AESDMA_GetMIU1Base(void)
195 {
196 return HAL_MIU1_BASE;
197 }
198
AESDMA_GetMIU2Base(void)199 MS_PHY AESDMA_GetMIU2Base(void)
200 {
201 //not support
202 return FALSE;
203 }
204
AESDMA_Reset(void)205 void AESDMA_Reset(void)
206 {
207 AESDMA_NormalReset ();
208 #if 0
209 MS_VIRT Reg_AESDMA;
210 MS_U32 i = 0;
211 Reg_AESDMA = (MS_VIRT)(&_AESDMACtrl[0].Dma_Ctrl);
212
213 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
214 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(AESDMA_CTRL_SW_RST)); // sw rst
215 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_SW_RST));
216
217 // reset all AESdma register
218 for (i = 0 ; i < 19 ; i++)
219 {
220 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
221 }
222 // reset secure_dma3_ctrl register
223 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
224
225 // reset hw_parser_ctrl register
226 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000);
227 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
228 #endif
229 }
230
AESDMA_Set_CipherKey(MS_U32 * cipherkey)231 void AESDMA_Set_CipherKey(MS_U32 *cipherkey)
232 {
233 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
234 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
235 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
236 REG32_W((&_AESDMACtrl[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
237 }
238
AESDMA_Set_InitVector(MS_U32 * pInitVector)239 void AESDMA_Set_InitVector(MS_U32 *pInitVector)
240 {
241 REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_L), pInitVector[0]);
242 REG32_W((&_AESDMACtrl[0].Dma_InitVector_L.IV_H), pInitVector[1]);
243 REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_L), pInitVector[2]);
244 REG32_W((&_AESDMACtrl[0].Dma_InitVector_H.IV_H), pInitVector[3]);
245 }
246
AESDMA_Sel_Key(MS_BOOL keysel)247 void AESDMA_Sel_Key(MS_BOOL keysel)
248 {
249 }
250
AESDMA_Sel_SecureKey(void)251 void AESDMA_Sel_SecureKey(void)
252 {
253 MS_U32 u32Ctrl = _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2);
254 u32Ctrl |= AESDMA_USE_SECRET_KEY;
255 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), u32Ctrl);
256 }
257
AESDMA_Set_FileinDesc(MS_PHY FileinAddr,MS_PHY FileinNum)258 void AESDMA_Set_FileinDesc(MS_PHY FileinAddr , MS_PHY FileinNum)
259 {
260 REG32_W((&_AESDMACtrl[0].Dma_Filein_Addr), FileinAddr);
261 REG32_W((&_AESDMACtrl[0].Dma_Filein_Num), FileinNum);
262 }
263
AESDMA_Set_FileoutDesc(MS_PHY FileoutSAddr,MS_PHY FileoutEAddr)264 void AESDMA_Set_FileoutDesc(MS_PHY FileoutSAddr , MS_PHY FileoutEAddr)
265 {
266 REG32_W((&_AESDMACtrl[0].Dma_Fileout_SAddr), FileoutSAddr);
267 REG32_W((&_AESDMACtrl[0].Dma_Fileout_EAddr), FileoutEAddr);
268 }
269
AESDMA_Start(MS_BOOL AESDMAStart)270 void AESDMA_Start(MS_BOOL AESDMAStart)
271 {
272 if (AESDMAStart)
273 {
274 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) &~ AESDMA_CTRL_FILEOUT_START &~ AESDMA_CTRL_FILEIN_START));
275 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) | AESDMA_CTRL_FILEOUT_START | AESDMA_CTRL_FILEIN_START));
276 }
277 else
278 {
279 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)&~(AESDMA_CTRL_FILEOUT_START|AESDMA_CTRL_FILEIN_START));
280 }
281 }
282
AESDMA_Set_PS_PTN(MS_U32 MatchPTN)283 void AESDMA_Set_PS_PTN(MS_U32 MatchPTN)
284 {
285 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern) , MatchPTN);
286 }
287
AESDMA_Set_PS_Mask(MS_U32 MatchMask)288 void AESDMA_Set_PS_Mask(MS_U32 MatchMask)
289 {
290 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern_Mask) , MatchMask);
291 }
292
AESDMA_Set_PS_ENG(MS_BOOL PSin_en,MS_BOOL PSout_en)293 void AESDMA_Set_PS_ENG(MS_BOOL PSin_en, MS_BOOL PSout_en)
294 {
295 MS_U32 u32PSin, u32PSout;
296
297 u32PSin = AESDMA_ENG_PS_IN_EN & (PSin_en<<20);
298 u32PSout = AESDMA_ENG_PS_OUT_EN & (PSout_en<<21);
299
300 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|(u32PSin|u32PSout));
301 }
302
AESDMA_Get_PS_MatchedBytecnt(void)303 MS_U32 AESDMA_Get_PS_MatchedBytecnt(void)
304 {
305 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Btyecnt);
306 }
307
AESDMA_Get_PS_MatchedPTN(void)308 MS_U32 AESDMA_Get_PS_MatchedPTN(void)
309 {
310 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Pat);
311 }
312
AESDMA_Set_PS_Release(void)313 void AESDMA_Set_PS_Release(void)
314 {
315 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ENG_PS_RELEASE);
316 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & ~AESDMA_ENG_PS_RELEASE);
317 }
318
AESDMA_Get_AESDMA_Status(void)319 MS_U32 AESDMA_Get_AESDMA_Status(void)
320 {
321 return _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status);
322 }
323
AESDMA_Get_AESDMA_IsFinished(void)324 MS_U32 AESDMA_Get_AESDMA_IsFinished(void)
325 {
326 return (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PVR_Status) & AESDMA_IS_FINISHED);
327 }
328
AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode,MS_BOOL Descrypt)329 void AESDMA_Set_CIPHER_ENG(AESDMA_CipherMode eMode, MS_BOOL Descrypt)
330 {
331 MS_U32 u32Cmd = 0;
332
333 switch (eMode)
334 {
335 case E_AESDMA_CIPHER_ECB:
336 u32Cmd |= AESDMA_ENG_AES_EN;
337 break;
338
339 case E_AESDMA_CIPHER_CTR:
340 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTR_MODE);
341 break;
342
343 case E_AESDMA_CIPHER_CBC:
344 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CBC_MODE);
345 break;
346
347 case E_AESDMA_CIPHER_DES_ECB:
348 u32Cmd |= AESDMA_ENG_DES_EN;
349 break;
350
351 case E_AESDMA_CIPHER_DES_CTR:
352 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTR_MODE);
353 break;
354
355 case E_AESDMA_CIPHER_DES_CBC:
356 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CBC_MODE);
357 break;
358
359 case E_AESDMA_CIPHER_TDES_ECB:
360 u32Cmd |= AESDMA_ENG_TDES_EN;
361 break;
362
363 case E_AESDMA_CIPHER_TDES_CTR:
364 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTR_MODE);
365 break;
366
367 case E_AESDMA_CIPHER_TDES_CBC:
368 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CBC_MODE);
369 break;
370
371 case E_AESDMA_CIPHER_CTS_CBC:
372 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_CBC_MODE);
373 break;
374
375 case E_AESDMA_CIPHER_CTS_ECB:
376 u32Cmd |= (AESDMA_ENG_AES_EN | AESDMA_ENG_CTS_ECB_MODE);
377 break;
378
379 case E_AESDMA_CIPHER_DES_CTS_CBC:
380 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_CBC_MODE);
381 break;
382
383 case E_AESDMA_CIPHER_DES_CTS_ECB:
384 u32Cmd |= (AESDMA_ENG_DES_EN | AESDMA_ENG_CTS_ECB_MODE);
385 break;
386
387 case E_AESDMA_CIPHER_TDES_CTS_CBC:
388 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_CBC_MODE);
389 break;
390
391 case E_AESDMA_CIPHER_TDES_CTS_ECB:
392 u32Cmd |= (AESDMA_ENG_TDES_EN | AESDMA_ENG_CTS_ECB_MODE);
393 break;
394 default:
395 return;
396 }
397
398 if( eMode >= E_AESDMA_CIPHER_DES_ECB )
399 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) | AESDMA_DMA_USE_TDES_EN);
400
401 u32Cmd |= AESDMA_ENG_DESCRYPT & (Descrypt<<25);
402 REG32_W((&_AESDMACtrl[0].Dma_Ctrl),(( _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & (~DmaCtrlSet)) | u32Cmd ) );
403 }
404
AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)405 MS_U32 AESDMA_QueryCipherMode(AESDMA_CipherMode eMode)
406 {
407 MS_U32 u32Result = 1;
408
409 switch (eMode)
410 {
411 case E_AESDMA_CIPHER_ECB:
412 case E_AESDMA_CIPHER_CTR:
413 case E_AESDMA_CIPHER_CBC:
414 case E_AESDMA_CIPHER_DES_ECB:
415 case E_AESDMA_CIPHER_DES_CTR:
416 case E_AESDMA_CIPHER_DES_CBC:
417 case E_AESDMA_CIPHER_TDES_ECB:
418 case E_AESDMA_CIPHER_TDES_CTR:
419 case E_AESDMA_CIPHER_TDES_CBC:
420 case E_AESDMA_CIPHER_CTS_CBC:
421 case E_AESDMA_CIPHER_CTS_ECB:
422 case E_AESDMA_CIPHER_DES_CTS_CBC:
423 case E_AESDMA_CIPHER_DES_CTS_ECB:
424 case E_AESDMA_CIPHER_TDES_CTS_CBC:
425 case E_AESDMA_CIPHER_TDES_CTS_ECB:
426 u32Result = 0;
427 break;
428 default:
429 break;
430 }
431 return u32Result;
432
433 }
434
AESDMA_Set_MIU_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)435 void AESDMA_Set_MIU_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
436 {
437 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_R));
438 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), RESET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), AESDMA_CTRL_BANK_W));
439
440 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_R & ((MS_U32)MIU_R << 4))));
441 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), SET_FLAG1(_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2), (AESDMA_CTRL_BANK_W & ((MS_U32)MIU_W << 5))));
442 }
443
AESDMA_Set_MIU2_Path(MS_BOOL MIU_R,MS_BOOL MIU_W)444 void AESDMA_Set_MIU2_Path(MS_BOOL MIU_R, MS_BOOL MIU_W)
445 {
446 // Not support
447 }
448
AESDMA_Enable_Int(void)449 void AESDMA_Enable_Int(void)
450 {
451 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)|AESDMA_INT_EN);
452 }
453
AESDMA_Disable_Int(void)454 void AESDMA_Disable_Int(void)
455 {
456 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2)&~AESDMA_INT_EN);
457 }
458
AESDMA_Clear_Int(void)459 void AESDMA_Clear_Int(void)
460 {
461 //
462 // Since ISR Clear bit for Normal and Secured bank is independently, it must be reset individually
463 //
464
465 #if AESDMS_SECURED_BANK_EN
466 //
467 // For Secured Bank
468 //
469 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)|AESDMA_ISR_CLR);
470 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)&~AESDMA_ISR_CLR);
471 #else
472 //
473 // For Normal Bank
474 //
475 REG32_W((&_AESDSCMB7Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB7Ctrl[0].Reg0001)|AESDMA_ISR_CLR);
476 REG32_W((&_AESDSCMB7Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB7Ctrl[0].Reg0001)&~AESDMA_ISR_CLR);
477 #endif //#if AESDMS_SECURED_BANK_EN
478 }
479
AESDMA_HW_Patch(void)480 void AESDMA_HW_Patch(void)
481 {
482 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_ECO_FIX_LAST_BYTE);
483 //REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl)|AESDMA_CTRL_BURST_LENGTH);
484 //REG32_W((&_AESDMACtrl[0].Dma_Eng3_Ctrl) , _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Eng3_Ctrl)|AESDMA_ENG_SPEEDUP);
485 }
486
AESDMA_Enable_Clk(void)487 void AESDMA_Enable_Clk(void)
488 {
489 MS_U32 u32Val;
490
491 //1. clk_aesdma, 0x100A_19[3:0] = 0
492 u32Val = _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA);
493 u32Val &= ~AESDMA_CLK_XTAL; //Clear Clk setting.
494 u32Val |= AESDMA_CLK_288M; //Set Clk to 288M
495 u32Val &= ~AESDMA_CLK_OFF_EN;//Enable Clk
496 REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , u32Val);
497
498 }
499
AESDMA_Disable_Clk(void)500 void AESDMA_Disable_Clk(void)
501 {
502 REG32_W((&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) , _AESDMA_REG32_R(&_AESDMAClk[0].Reg_Gate_Clk_AESDMA) | AESDMA_CLK_OFF_EN);
503 }
504
AESDMA_Rand(void)505 MS_U8 AESDMA_Rand(void)
506 {
507 MS_U8 u8RN = 0x00;
508 u8RN = (MS_U8)_AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0203)&0xFF;
509
510 return u8RN;
511 }
512
SHA_Reset(void)513 void SHA_Reset(void)
514 {
515 MS_VIRT Reg_SHARNG;
516 MS_U32 i = 0;
517 Reg_SHARNG = (MS_VIRT)(&_SHARNGCtrl[0].Sha_Ctrl);
518 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , SHARNG_CTRL_SHA_RST); // 0->1
519 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&(~SHARNG_CTRL_SHA_RST))); // 1->0
520
521 // reset all SHA & RNG register
522 for (i = 0 ; i < 7 ; i++)
523 {
524 REG32_W((REG32 *)(Reg_SHARNG+(i*8)), 0x00000000);
525 }
526 }
527
SHA_Get_Status(void)528 MS_U32 SHA_Get_Status(void)
529 {
530 return _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Status);
531 }
532
SHA_SelMode(AESDMA_SHAMode eMode)533 void SHA_SelMode(AESDMA_SHAMode eMode)
534 {
535 MS_U32 u32Cmd = 0;
536
537 switch (eMode)
538 {
539 case E_AESDMA_SHA1:
540 u32Cmd |= (SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
541 break;
542
543 case E_AESDMA_SHA256:
544 u32Cmd |= (SHARNG_CTRL_SHA_SEL_SHA256 | SHARNG_CTRL_SHA_MSG_BLOCK_NUM);
545 break;
546
547 default:
548 return;
549 }
550
551 //Turn off speedup mode
552 //u32Cmd |= SHARNG_CTRL_SPEED_MODE_N;
553
554 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl), _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl) | u32Cmd);
555 }
556
SHA_SetAddress(MS_PHY u32Addr)557 void SHA_SetAddress(MS_PHY u32Addr)
558 {
559 REG32_W((&_SHARNGCtrl[0].Sha_Start), u32Addr);
560 }
561
SHA_SetLength(MS_U32 u32Size)562 void SHA_SetLength(MS_U32 u32Size)
563 {
564 REG32_W((&_SHARNGCtrl[0].Sha_Length), u32Size);
565 }
566
SHA_Start(MS_BOOL SHAStart)567 void SHA_Start(MS_BOOL SHAStart)
568 {
569 if(SHAStart)
570 {
571 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
572 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_FIRE_ONCE));
573 }
574 else
575 {
576 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&~(SHARNG_CTRL_SHA_FIRE_ONCE));
577 }
578 }
579
SHA_Out(MS_VIRT u32Buf)580 void SHA_Out(MS_VIRT u32Buf)
581 {
582 MS_U32 Index, u32Size, u32offset;
583 MS_U32 eMode = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)&SHARNG_CTRL_SHA_SEL_SHA256;
584
585 if(eMode == SHARNG_CTRL_SHA_SEL_SHA256)
586 {
587 u32Size = DIGEST_SIZE_SHA256;
588 u32offset = 0;
589 }
590 else
591 {
592 u32Size = DIGEST_SIZE_SHA1;
593 u32offset = 3;
594 }
595
596 for( Index = 0; Index < u32Size; Index++ )
597 {
598 *((MS_U32 *)u32Buf + Index) = _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Out[Index + u32offset]);
599 }
600 //Set "1" to idle state after reg_read_sha_ready = 1
601 REG32_W((&_SHARNGCtrl[0].Sha_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Sha_Ctrl)|(SHARNG_CTRL_SHA_CLR));
602 }
603
604
605 //-------------------------------------------------------------------------------------------------
606 /// Enable mobf one way function
607 /// @param NULL
608
609 /// @note : disable read mobf key, and could not enable read mobf key anymore
610 //-------------------------------------------------------------------------------------------------
MOBF_OneWay(void)611 void MOBF_OneWay(void)
612 {
613 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_ONEWAY_EN));
614 }
615
616 //-------------------------------------------------------------------------------------------------
617 /// Set MOBF encrypt key
618 /// @param u32WriteKey \b IN: Encrypt Key
619
620 /// @note
621 //-------------------------------------------------------------------------------------------------
MOBF_WriteKey(MS_U32 u32WriteKey)622 void MOBF_WriteKey(MS_U32 u32WriteKey)
623 {
624 REG32_W((&_SHARNGCtrl[0].MOBF_KeyW) , u32WriteKey);
625 }
626
627 //-------------------------------------------------------------------------------------------------
628 /// Set MOBF decrypt key
629 /// @param u32ReadKey \b IN: Decrypt Key
630
631 /// @note
632 //-------------------------------------------------------------------------------------------------
MOBF_ReadKey(MS_U32 u32ReadKey)633 void MOBF_ReadKey(MS_U32 u32ReadKey)
634 {
635 REG32_W((&_SHARNGCtrl[0].MOBF_KeyR) , u32ReadKey);
636 }
637
638 //-------------------------------------------------------------------------------------------------
639 /// Enable MOBF in MIU write port
640 /// @param bEnable \b IN: Enable/Disable
641
642 /// @note : MOBF Encrypt
643 //-------------------------------------------------------------------------------------------------
MOBF_WriteEnable(MS_BOOL bEnable)644 void MOBF_WriteEnable(MS_BOOL bEnable)
645 {
646 if(bEnable)
647 {
648 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
649 }
650 else
651 {
652 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_WRITE_EN));
653 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_WRITE_EN));
654 }
655 }
656
657 //-------------------------------------------------------------------------------------------------
658 /// Enable MOBF in MIU read port
659 /// @param bEnable \b IN: Enable/Disable
660
661 /// @note : MOBF Decrypt
662 //-------------------------------------------------------------------------------------------------
MOBF_ReadEnable(MS_BOOL bEnable)663 void MOBF_ReadEnable(MS_BOOL bEnable)
664 {
665 if(bEnable)
666 {
667 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
668 }
669 else
670 {
671 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)&(~MOBF_IN_MIU_READ_EN));
672 REG32_W((&_SHARNGCtrl[0].Rng_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl)|(MOBF_IN_MIU_READ_EN));
673 }
674 }
675
676 //-------------------------------------------------------------------------------------------------
677 /// Disable TDES
678 ///
679
680 /// @note : MOBF Decrypt
681 //-------------------------------------------------------------------------------------------------
MOBF_DisableTDES(void)682 void MOBF_DisableTDES(void)
683 {
684 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2),_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2) & (~AESDMA_DMA_USE_TDES_EN));
685 }
686
AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)687 void AESDMA_Parser_Set_Mode(AESDMA_ParserMode eMode)
688 {
689 MS_U32 u32Cmd = 0;
690
691 switch (eMode)
692 {
693 case E_AESDMA_PARSER_TS_PKT192:
694 u32Cmd |= (TS_MODE | PKT192_MODE);
695 break;
696
697 case E_AESDMA_PARSER_TS_PKT192_CLEAR:
698 u32Cmd |= (TS_MODE | PKT192_MODE | CLEAR_MODE);
699 break;
700
701 case E_AESDMA_PARSER_TS_PKT188:
702 u32Cmd |= (TS_MODE);
703 u32Cmd &= (~PKT192_MODE);
704 break;
705
706 case E_AESDMA_PARSER_TS_PKT188_CLEAR:
707 u32Cmd |= (TS_MODE | CLEAR_MODE);
708 u32Cmd &= (~PKT192_MODE);
709 break;
710
711 case E_AESDMA_PARSER_HDCP20_PKT192:
712 u32Cmd |= (HDCP20_MODE | PKT192_MODE);
713 break;
714
715 case E_AESDMA_PARSER_HDCP20_PKT192_CLEAR:
716 u32Cmd |= (HDCP20_MODE | PKT192_MODE | CLEAR_MODE);
717 break;
718
719 case E_AESDMA_PARSER_HDCP20_PKT188:
720 u32Cmd |= (HDCP20_MODE);
721 u32Cmd &= (~PKT192_MODE);
722 break;
723
724 case E_AESDMA_PARSER_HDCP20_PKT188_CLEAR:
725 u32Cmd |= (HDCP20_MODE | CLEAR_MODE);
726 u32Cmd &= (~PKT192_MODE);
727 break;
728
729 default:
730 return;
731 }
732
733 u32Cmd |= (AUTO_MODE | INIT_TRUST);
734 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~ParserCtrlSet)) | u32Cmd ) );
735 }
736
737
AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)738 void AESDMA_Parser_Insert_Scrmb(MS_BOOL bEnable)
739 {
740 if(bEnable)
741 {
742 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
743 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (INSERT_SCRMB)) );
744 }
745 else
746 {
747 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~INSERT_SCRMB)) );
748 }
749 }
750
AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)751 void AESDMA_Parser_Remove_Scrmb(MS_BOOL bEnable)
752 {
753 if(bEnable)
754 {
755 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
756 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (REMOVE_SCRMB)) );
757 }
758 else
759 {
760 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~REMOVE_SCRMB)) );
761 }
762 }
763
AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)764 void AESDMA_Parser_Mask_Scrmb(MS_BOOL bEnable)
765 {
766 if(bEnable)
767 {
768 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
769 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (TS_SCRMB_MASK)) );
770 }
771 else
772 {
773 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~TS_SCRMB_MASK)) );
774 }
775 }
776
AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)777 void AESDMA_Parser_Bypass_Pid(MS_BOOL bEnable)
778 {
779 if(bEnable)
780 {
781 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
782 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (BYPASS_PID)) );
783 }
784 else
785 {
786 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~BYPASS_PID)) );
787 }
788 }
789
AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)790 void AESDMA_Parser_Set_ScrmbPattern(AESDMA_ScrmbPattern ePattern)
791 {
792 MS_U32 u32Cmd = 0;
793
794 switch (ePattern)
795 {
796 case E_AESDMA_PARSER_SCRMB_10:
797 u32Cmd |= (SCRMB_PATTERN10);
798 break;
799
800 case E_AESDMA_PARSER_SCRMB_11:
801 u32Cmd |= (SCRMB_PATTERN11);
802 break;
803
804 default:
805 u32Cmd &= ~(SCRMB_PATTERN11);
806 break;
807 }
808
809 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~SCRMB_INITVALUE)) | u32Cmd ) );
810
811 }
812
AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)813 void AESDMA_Parser_Set_AddedScrmbPattern(AESDMA_ScrmbPattern ePattern)
814 {
815 MS_U32 u32Cmd = 0;
816
817 switch (ePattern)
818 {
819 case E_AESDMA_PARSER_SCRMB_10:
820 u32Cmd |= (SCRMB_PATTERN10_ADD);
821 break;
822
823 case E_AESDMA_PARSER_SCRMB_11:
824 u32Cmd |= (SCRMB_PATTERN11_ADD);
825 break;
826
827 default:
828 return;
829 }
830
831 REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_INITVALUE_ADD)) | u32Cmd ) );
832
833 }
834
AESDMA_Parser_Set_Pid(MS_U8 u8Index,MS_U16 u16Pid)835 void AESDMA_Parser_Set_Pid(MS_U8 u8Index, MS_U16 u16Pid)
836 {
837 if(u8Index==0)
838 {
839 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~PARSER_PID0_MASK)) | (u16Pid<<16) ) );
840 }
841 else if(u8Index==1)
842 {
843 REG32_W((&_PARSERCtrl[0].Parser_Pid1),(( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~PARSER_PID1_MASK)) | u16Pid ) );
844 }
845 else
846 {
847 printf("Edison do not support other PID\n");
848 }
849 }
850
AESDMA_Parser_Query_PidCount(void)851 MS_U8 AESDMA_Parser_Query_PidCount(void)
852 {
853 return PARSER_PID_COUNT;
854 }
855
AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)856 void AESDMA_Parser_Enable_HWParser(MS_BOOL bEnable)
857 {
858 #if AESDMS_SECURED_BANK_EN
859 //
860 // Set HW Parser controlled by DSCRMB3
861 //
862 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)|AESDMA_DSCRMB3_HW_PASER_EN);
863 #else
864 //
865 // Set HW Parser controlled by DSCRMB5
866 //
867 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001)&~(AESDMA_DSCRMB3_HW_PASER_EN));
868 #endif //#if AESDMS_SECURED_BANK_EN
869
870 if(bEnable)
871 {
872 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE)) );
873 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) | (HW_PARSER_MODE)) );
874 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (ENABLE_LG_PATCH)) );
875 }
876 else
877 {
878 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Ctrl) & (~HW_PARSER_MODE)) );
879 REG32_W((&_PARSERCtrl[0].Parser_Pid1),( _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~ENABLE_LG_PATCH)) );
880 }
881
882 //make sure CC_CTRL_BY_ACPU is set 0
883 REG32_W((&_CIPHERCtrl[0].Cipher_Ctrl),( _AESDMA_REG32_R(&_CIPHERCtrl[0].Cipher_Ctrl) & (~CC_CTRL_BY_ACPU)) );
884 }
885
RSA_ClearInt(void)886 void RSA_ClearInt(void)
887 {
888 //RSA interrupt clear
889 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_INT_CLR));
890 }
891
RSA_Reset(void)892 void RSA_Reset(void)
893 {
894 //RSA Rst
895 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_RSA_RST));
896 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_RSA_RST));
897
898 //add polling RSA status before load data to SRAM
899 while (( RSA_GetStatus() & RSA_STATUS_RSA_BUSY ) != 0);
900 }
901
RSA_Ind32Ctrl(MS_U8 u8dirction)902 void RSA_Ind32Ctrl(MS_U8 u8dirction)
903 {
904 //[1] reg_ind32_direction 0: Read. 1: Write
905 if(u8dirction==1)
906 {
907 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_DIRECTION_WRITE));
908 }
909 else
910 {
911 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)&(~RSA_IND32_CTRL_DIRECTION_WRITE));
912 }
913
914 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_IND32_CTRL_ADDR_AUTO_INC|RSA_IND32_CTRL_ACCESS_AUTO_START));
915
916 }
917
RSA_LoadSram(MS_U32 * u32Buf,RSA_IND32Address eMode)918 void RSA_LoadSram(MS_U32 *u32Buf, RSA_IND32Address eMode)
919 {
920 MS_U32 u32Cmd = 0;
921 MS_U32 i = 0;
922 MS_U32 WData_H = 0;
923 MS_U32 WData_L = 0;
924
925 switch (eMode)
926 {
927 case E_RSA_ADDRESS_E:
928 u32Cmd |= (RSA_E_BASE_ADDR);
929 break;
930
931 case E_RSA_ADDRESS_N:
932 u32Cmd |= (RSA_N_BASE_ADDR);
933 break;
934
935 case E_RSA_ADDRESS_A:
936 u32Cmd |= (RSA_A_BASE_ADDR);
937 break;
938
939 default:
940 return;
941 }
942
943 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Cmd));
944 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
945
946 for( i = 0; i < 64; i++ )
947 {
948 if( eMode == E_RSA_ADDRESS_E )
949 {
950 WData_L = (((*(u32Buf+i))>>8)&0xFF00)|(((*(u32Buf+i))>>24)&0xFF);
951 WData_H = (((*(u32Buf+i))>>8)&0xFF)|(((*(u32Buf+i))<<8)&0xFF00);
952 }
953 else
954 {
955 WData_L = (((*(u32Buf-i))>>8)&0xFF00)|(((*(u32Buf-i))>>24)&0xFF);
956 WData_H = (((*(u32Buf-i))>>8)&0xFF)|(((*(u32Buf-i))<<8)&0xFF00);
957 }
958
959 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_WDATA_MASK_L))|(WData_L<<16)));
960 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_WData) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&(~RSA_WDATA_MASK_H))|WData_H));
961 }
962
963 }
964
RSA_SetKeyLength(MS_U32 u32keylen)965 void RSA_SetKeyLength(MS_U32 u32keylen)
966 {
967 //[13:8] n_len_e: key length
968 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_KEY_LENGTH_MASK))|(u32keylen<<8));
969 }
970
RSA_SetKeyType(MS_U8 u8hwkey,MS_U8 u8pubkey)971 void RSA_SetKeyType(MS_U8 u8hwkey, MS_U8 u8pubkey)
972 {
973 //[1] hw_key_e : 0 : software key, 1: hardware key
974 //[2] e_pub_e : 0: pvivate key, 1: public key
975 if(u8hwkey==1)
976 {
977 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_HW_KEY));
978 }
979 else
980 {
981 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_HW_KEY));
982 }
983
984 if(u8pubkey==1)
985 {
986 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)|(RSA_CTRL_SEL_PUBLIC_KEY));
987 }
988 else
989 {
990 REG32_W((&_SHARNGCtrl[0].Rsa_Ctrl) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl)&(~RSA_CTRL_SEL_PUBLIC_KEY));
991 }
992
993 }
994
RSA_ExponetialStart(void)995 void RSA_ExponetialStart(void)
996 {
997 //RSA exp start
998 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_RData) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)|(RSA_EXP_START));
999 }
1000
RSA_GetStatus(void)1001 MS_U32 RSA_GetStatus(void)
1002 {
1003 return _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ctrl) & RSA_STATUS_MASK;
1004 }
1005
RSA_FileOutStart(void)1006 void RSA_FileOutStart(void)
1007 {
1008 //RSA ind32_start
1009 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Start) , _AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Start)|(RSA_INDIRECT_START));
1010 }
1011
RSA_SetFileOutAddr(MS_U32 u32offset)1012 void RSA_SetFileOutAddr(MS_U32 u32offset)
1013 {
1014 MS_PHY u32Addr = 0;
1015 u32Addr = RSA_Z_BASE_ADDR + u32offset;
1016
1017 REG32_W((&_SHARNGCtrl[0].Rsa_Ind32_Addr) , ((_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_Addr)&(~RSA_ADDRESS_MASK))|u32Addr));
1018 }
1019
RSA_FileOut(void)1020 MS_U32 RSA_FileOut(void)
1021 {
1022 MS_U32 u32out_L = 0;
1023 MS_U32 u32out_H = 0;
1024
1025 u32out_L = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_WData)&RSA_RDATA_MASK_L)>>16;
1026 u32out_H = (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rsa_Ind32_RData)&RSA_RDATA_MASK_H)<<16;
1027
1028 return (u32out_H|u32out_L);
1029 }
1030
RSA_Get_RSA_IsFinished(void)1031 MS_U32 RSA_Get_RSA_IsFinished(void)
1032 {
1033 return (RSA_GetStatus()&RSA_STATUS_RSA_BUSY);
1034 }
1035
1036 //reserved for secure protect function
1037 /*
1038 void AESDMA_Secure_SetCipherKey(MS_U32 *cipherkey)
1039 {
1040 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_L.Key_L) , cipherkey[0]);
1041 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_L.Key_H) , cipherkey[1]);
1042 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_H.Key_L) , cipherkey[2]);
1043 REG32_W((&_DMASECURECtrl[0].Secure_CipherKey_H.Key_H) , cipherkey[3]);
1044 }
1045
1046 void AESDMA_Secure_SetInitVector(MS_U32 *pInitVector)
1047 {
1048 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_L.IV_L), pInitVector[0]);
1049 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_L.IV_H), pInitVector[1]);
1050 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_H.IV_L), pInitVector[2]);
1051 REG32_W((&_DMASECURECtrl[0].Secure_InitVector_H.IV_H), pInitVector[3]);
1052 }
1053
1054 void AESDMA_SecureProtect(MS_BOOL bEnable)
1055 {
1056 if(bEnable)
1057 {
1058 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl)|(AESDMA_SECURE_PROTECT_S));
1059 }
1060 else
1061 {
1062 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl)&(~AESDMA_SECURE_PROTECT_S));
1063 }
1064 }
1065
1066 void AESDMA_Set_FileOutEnable(MS_BOOL bEnable)
1067 {
1068 if (bEnable)
1069 {
1070 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) |AESDMA_CTRL_FILEIN_START));
1071 }
1072 else
1073 {
1074 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) &~AESDMA_CTRL_FILEIN_START));
1075 }
1076 }
1077
1078 void AESDMA_Secure_Start(MS_BOOL AESDMAStart)
1079 {
1080 if (AESDMAStart)
1081 {
1082 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) &~AESDMA_SECURE_FILEIN_START));
1083 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) | AESDMA_SECURE_FILEIN_START));
1084 }
1085 else
1086 {
1087 REG32_W((&_DMASECURECtrl[0].Secure_file_st), (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_file_st) &~AESDMA_SECURE_FILEIN_START));
1088 }
1089 }
1090
1091 MS_U32 AESDMA_Get_AESDMA_SecureIsFinished(void)
1092 {
1093 return (_AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_status) & AESDMA_DONE_S);
1094 }
1095
1096 */
1097
1098 //-------------------------------------------------------------------------------------------------
1099 /// Get status of Secret Key in Normal bank
1100 /// @param N/A
1101 /// @note : Get Status
1102 //-------------------------------------------------------------------------------------------------
AESDMA_IsSecretKeyInNormalBank(void)1103 MS_U32 AESDMA_IsSecretKeyInNormalBank(void)
1104 {
1105 return (_AESDMA_REG32_R(&_SHARNGCtrl[0].Rng_Ctrl) & (SECRET_KEY_IN_NORMAL_BANK));
1106 }
1107
1108 //-------------------------------------------------------------------------------------------------
1109 /// Enable Two keys (Odd/Even) in using HW auto select key.
1110 /// @param bEnable \b IN: Enable/Disable
1111
1112 /// @note : Hardware Parser Decrypt
1113 //-------------------------------------------------------------------------------------------------
AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)1114 void AESDMA_Parser_Enable_Two_Keys(MS_BOOL bEnable)
1115 {
1116 if(bEnable)
1117 {
1118 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) | (SCRMB_ENABLE_TWO_KEY) );
1119 }
1120 else
1121 {
1122 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _AESDMA_REG32_R(&_PARSERCtrl[0].Parser_Pid1) & (~SCRMB_ENABLE_TWO_KEY) );
1123 }
1124 }
1125
1126 //-------------------------------------------------------------------------------------------------
1127 /// Set Odd keys in using HW auto select key.
1128 /// @param cipherkey
1129 /// @note : Hardware Parser Decrypt
1130 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherOddKey(MS_U32 * cipherkey)1131 void AESDMA_Set_CipherOddKey(MS_U32 *cipherkey)
1132 {
1133 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_L) , cipherkey[0]);
1134 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_L.Key_H) , cipherkey[1]);
1135 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_L) , cipherkey[2]);
1136 REG32_W((&_AESDMACtrlEx[0].Dma_CipherKey_H.Key_H) , cipherkey[3]);
1137 }
1138
1139 //-------------------------------------------------------------------------------------------------
1140 /// Set Odd IVs in using HW auto select key.
1141 /// @param cipherkey
1142 /// @note : Hardware Parser Decrypt
1143 //-------------------------------------------------------------------------------------------------
AESDMA_Set_OddInitVector(MS_U32 * pInitVector)1144 void AESDMA_Set_OddInitVector(MS_U32 *pInitVector)
1145 {
1146 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_L), pInitVector[0]);
1147 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_L.IV_H), pInitVector[1]);
1148 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_L), pInitVector[2]);
1149 REG32_W((&_AESDMACtrlEx[0].Dma_InitVector_H.IV_H), pInitVector[3]);
1150 }
1151
1152 //-------------------------------------------------------------------------------------------------
1153 /// Set Even keys in using HW auto select key.
1154 /// @param cipherkey
1155 /// @note : Hardware Parser Decrypt
1156 //-------------------------------------------------------------------------------------------------
AESDMA_Set_CipherEvenKey(MS_U32 * cipherkey)1157 void AESDMA_Set_CipherEvenKey(MS_U32 *cipherkey)
1158 {
1159 AESDMA_Set_CipherKey(cipherkey);
1160 }
1161
1162 //-------------------------------------------------------------------------------------------------
1163 /// Set Even IVs in using HW auto select key.
1164 /// @param cipherkey
1165 /// @note : Hardware Parser Decrypt
1166 //-------------------------------------------------------------------------------------------------
AESDMA_Set_EvenInitVector(MS_U32 * pInitVector)1167 void AESDMA_Set_EvenInitVector(MS_U32 *pInitVector)
1168 {
1169 AESDMA_Set_InitVector(pInitVector);
1170 }
1171
1172 //-------------------------------------------------------------------------------------------------
1173 /// Set HDCP Data
1174 /// @param u8Idx \b IN: Index
1175 /// @param pu8Data \b IN: Content Keys
1176 /// @param pu8privData \b IN: RIV
1177 /// @note : Set HDCP2.2
1178 //-------------------------------------------------------------------------------------------------
HDCP_ProcessCipher(MS_U8 u8Idx,MS_U8 * pu8Data,MS_U8 * pu8privData)1179 void HDCP_ProcessCipher (MS_U8 u8Idx, MS_U8 *pu8Data, MS_U8* pu8privData)
1180 {
1181 REG_HDCP22Data *pData = NULL;
1182 REG_HDCP22SEKCtrl *pCtrl = NULL;
1183 MS_U16 offset = 0;
1184 MS_U16 BKOffset = 0;
1185
1186 MS_U32 *cipherkey = (MS_U32 *)((void *)pu8Data);
1187 MS_U32 *riv = (MS_U32 *)((void *)pu8privData);
1188
1189 offset = u8Idx * (sizeof(REG_HDCP22Data) >> 1);
1190 BKOffset = u8Idx * 0x300;
1191
1192 pData = (REG_HDCP22Data*)((MS_U16*)_HDCP22Data + offset);
1193 pCtrl = (REG_HDCP22SEKCtrl*)((MS_U16*)_HDCP22SekCtrl + BKOffset);
1194
1195 //Content Keys
1196 REG32_W((&pData[0].Hdcp22_ContentKey[0]) , cipherkey[0]);
1197 REG32_W((&pData[0].Hdcp22_ContentKey[1]) , cipherkey[1]);
1198 REG32_W((&pData[0].Hdcp22_ContentKey[2]) , cipherkey[2]);
1199 REG32_W((&pData[0].Hdcp22_ContentKey[3]) , cipherkey[3]);
1200
1201 //RIV
1202 REG32_W((&pData[0].Hdcp22_Riv[0]) , riv[0]);
1203 REG32_W((&pData[0].Hdcp22_Riv[1]) , riv[1]);
1204
1205 //Set SKE successful
1206 REG32_W((&pCtrl[0].SEK), (_AESDMA_REG32_R(&pCtrl[0].SEK) | HDCP_SEK_BIT0));
1207 }
1208
1209 //-------------------------------------------------------------------------------------------------
1210 /// Get the status of HW supports HDCP2.2
1211 /// @param N/A
1212 /// @note : Support HDCP2.2
1213 //-------------------------------------------------------------------------------------------------
HDCP_GetHdcpCipherState(MS_U8 u8Idx,MS_U8 * pu8State)1214 void HDCP_GetHdcpCipherState(MS_U8 u8Idx, MS_U8 *pu8State)
1215 {
1216 #define HDCP_SUPPORT_EN 0x00000001
1217 REG_HDCP22SEKCtrl *pCtrl = NULL;
1218 MS_U16 offset = 0;
1219 MS_U16 BKOffset = 0;
1220
1221 offset = u8Idx * (sizeof(REG_HDCP22Data) >> 1);
1222 BKOffset = u8Idx * 0x300;
1223
1224 pCtrl = (REG_HDCP22SEKCtrl*)((MS_U16*)_HDCP22SekCtrl + BKOffset);
1225
1226 *pu8State = (MS_U8)(_AESDMA_REG32_R(&pCtrl[0].SEK) & HDCP_SUPPORT_EN);
1227 }
1228
AESDMA_BackupRegisters(void)1229 static void AESDMA_BackupRegisters(void)
1230 {
1231 MS_VIRT Reg_AESDMA;
1232 MS_U32 i = 0;
1233 Reg_AESDMA = (MS_VIRT)(&_AESDMACtrl[0].Dma_Ctrl);
1234
1235 // reset all AESdma register
1236 for (i = 0 ; i < 19 ; i++)
1237 {
1238 _gAESDMARegisterBackup.Dma_Ctrl[i] = _AESDMA_REG32_R((REG32 *)(Reg_AESDMA+(i*8)));
1239 }
1240 // reset secure_dma3_ctrl register
1241 _gAESDMARegisterBackup.Secure_dma3_ctrl = _AESDMA_REG32_R((&_DMASECURECtrl[0].Secure_dma3_ctrl));
1242
1243 // reset hw_parser_ctrl register
1244 _gAESDMARegisterBackup.Parser_Pid1 = _AESDMA_REG32_R((&_PARSERCtrl[0].Parser_Pid1));
1245 _gAESDMARegisterBackup.Parser_Ctrl = _AESDMA_REG32_R((&_PARSERCtrl[0].Parser_Ctrl));
1246 _gAESDMARegisterBackup.Kslot_Index = _AESDMA_REG32_R((&_AESDSCMB6Ctrl[0].Reg0001));
1247 }
1248
AESDMA_RestoreRegisters(void)1249 static void AESDMA_RestoreRegisters(void)
1250 {
1251 MS_VIRT Reg_AESDMA;
1252 MS_U32 i = 0;
1253 Reg_AESDMA = (MS_VIRT)(&_AESDMACtrl[0].Dma_Ctrl);
1254
1255 // reset all AESdma register
1256 for (i = 0 ; i < 19 ; i++)
1257 {
1258 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), _gAESDMARegisterBackup.Dma_Ctrl[i]);
1259 }
1260 // reset secure_dma3_ctrl register
1261 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), _gAESDMARegisterBackup.Secure_dma3_ctrl);
1262
1263 // reset hw_parser_ctrl register
1264 REG32_W((&_PARSERCtrl[0].Parser_Pid1), _gAESDMARegisterBackup.Parser_Pid1);
1265 REG32_W((&_PARSERCtrl[0].Parser_Ctrl), _gAESDMARegisterBackup.Parser_Ctrl);
1266 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001), _gAESDMARegisterBackup.Kslot_Index);
1267 }
1268
1269 //-------------------------------------------------------------------------------------------------
1270 /// Reset AESDMA
1271 /// @param N/A
1272 /// @note : Clear Registers, not to do sw reset
1273 //-------------------------------------------------------------------------------------------------
AESDMA_NormalReset(void)1274 void AESDMA_NormalReset(void)
1275 {
1276 MS_VIRT Reg_AESDMA;
1277 MS_U32 i = 0;
1278 Reg_AESDMA = (MS_VIRT)(&_AESDMACtrl[0].Dma_Ctrl);
1279
1280 REG32_W((&_AESDMACtrl[0].Dma_Ctrl) , 0x00000000); // clear ctrl register
1281
1282 // reset all AESdma register
1283 for (i = 0 ; i < 19 ; i++)
1284 {
1285 REG32_W((REG32 *)(Reg_AESDMA+(i*8)), 0x00000000);
1286 }
1287 // reset secure_dma3_ctrl register
1288 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl), 0x00000000);
1289
1290 // reset hw_parser_ctrl register
1291 REG32_W((&_PARSERCtrl[0].Parser_Pid1),0x00000000);
1292 REG32_W((&_PARSERCtrl[0].Parser_Ctrl),0x00000000);
1293 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001), AESDMA_DSCRMB6_KSLOT_INDEX_DEFAULT);
1294 }
1295
AESDMA_Set_SecureBankEnable(MS_BOOL bEnable)1296 void AESDMA_Set_SecureBankEnable (MS_BOOL bEnable)
1297 {
1298 #if AESDMS_SECURED_BANK_EN
1299 if ( bEnable == TRUE)
1300 {
1301 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl) |(AESDMA_SECURE_PROTECT_S | AESDMA_SECURE_PROTECT_SHA_S | AESDMA_SECURE_PROTECT_RSA_S));
1302 }
1303 else
1304 {
1305 REG32_W((&_DMASECURECtrl[0].Secure_dma3_ctrl) , _AESDMA_REG32_R(&_DMASECURECtrl[0].Secure_dma3_ctrl) &~(AESDMA_SECURE_PROTECT_S | AESDMA_SECURE_PROTECT_SHA_S | AESDMA_SECURE_PROTECT_RSA_S));
1306 }
1307 #endif
1308 }
1309
HAL_AESDMA_HDMI_GetM0(AESDMA_HDMI_INPUT_PORT enInputPortType,MS_U8 * pu8Data)1310 void HAL_AESDMA_HDMI_GetM0(AESDMA_HDMI_INPUT_PORT enInputPortType, MS_U8 *pu8Data)
1311 {
1312 MS_U16 u16bank_offset;
1313 MS_U32 m0[2];
1314 MS_U8* buf = (MS_U8*)m0;
1315 int i;
1316
1317 switch(enInputPortType)
1318 {
1319 default:
1320 case E_AESDMA_HDMI_INPUT_PORT_DVI0: u16bank_offset = 0x0000; break; // BK 0x171200
1321 case E_AESDMA_HDMI_INPUT_PORT_DVI1: u16bank_offset = 0x0300; break; // BK 0x171500
1322 case E_AESDMA_HDMI_INPUT_PORT_DVI2: u16bank_offset = 0x0600; break; // BK 0x171800
1323 case E_AESDMA_HDMI_INPUT_PORT_DVI3: u16bank_offset = 0x0900; break; // BK 0x171B00
1324 }
1325
1326 // read 8 bytes
1327 for(i = 0; i < 2; ++i)
1328 {
1329 m0[i] = _AESDMA_REG32_R(&((REG_HDCP14SEKCtrl*)((MS_U16*)_HDCP14SekCtrl + u16bank_offset))[i].REG_0001);
1330 }
1331 for (i = 0; i < 8; ++i)
1332 {
1333 pu8Data[i] = buf[i];
1334 }
1335 }
1336
1337 //-------------------------------------------------------------------------------------------------
1338 /// Set Index of KSlot
1339 /// @param u32Index
1340 /// @param bEnable \b IN: TRUE: For Odd Key/FALSE: For Even Key
1341 /// @note : AESDMA AES CTR64
1342 //-------------------------------------------------------------------------------------------------
AESDMA_SetKeyIndex(MS_U32 u32Index,MS_BOOL bIsOddKey)1343 void AESDMA_SetKeyIndex (MS_U32 u32Index, MS_BOOL bIsOddKey)
1344 {
1345 if ( (u32Index < 0x10 || u32Index > 0x1F) && (u32Index != 0)) {
1346 return;
1347 }
1348 MS_U32 u32Value = 0;
1349 #if AESDMS_SECURED_BANK_EN
1350 //
1351 // For Secured Bank
1352 //
1353 if (bIsOddKey == FALSE) {
1354 //Even Key (default key), [7:0]
1355 u32Value = _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001) & 0xFFFFFF00;
1356 //Set Key Index, 0 = Default key
1357 u32Value = u32Index == 0 ? (u32Value | 0x1) : (u32Value | u32Index);
1358 }
1359 else {
1360 //Odd Key (HW Parser key)
1361 u32Value = _AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001) & 0xFFFF00FF;
1362 //Set Key Index, 0 = Default key
1363 u32Value = u32Index == 0 ? (u32Value | 0x2) : (u32Value | ((u32Index<<8) & 0xFF00));
1364 }
1365 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001) , u32Value);
1366 #else
1367 //
1368 // For Normal Bank
1369 //
1370 if (bIsOddKey == FALSE) {
1371 //Even Key (default key), [7:0]
1372 u32Value = _AESDMA_REG32_R(&_AESDSCMB7Ctrl[0].Reg0001) & 0xFFFFFF00;
1373 //Set Key Index, 0 = Default key
1374 u32Value = u32Index == 0 ? (u32Value | 0x0) : (u32Value | u32Index);
1375 }
1376 else {
1377 //Odd Key (HW Parser key)
1378 u32Value = _AESDMA_REG32_R(&_AESDSCMB7Ctrl[0].Reg0001) & 0xFFFF00FF;
1379 //Set Key Index, 0 = Default key
1380 u32Value = u32Index == 0 ? (u32Value | 0x2) : (u32Value | ((u32Index<<8) & 0xFF00));
1381 }
1382 REG32_W((&_AESDSCMB7Ctrl[0].Reg0001) , u32Value);
1383 #endif //#if AESDMS_SECURED_BANK_EN
1384 }
1385
1386 //-------------------------------------------------------------------------------------------------
1387 /// Enable AES CTR64
1388 /// @param bEnable \b IN: Enable/Disable
1389 /// @note : AESDMA AES CTR64
1390 //-------------------------------------------------------------------------------------------------
AESDMA_SET_CTR64(MS_BOOL bEnable)1391 void AESDMA_SET_CTR64(MS_BOOL bEnable)
1392 {
1393 if(bEnable)
1394 {
1395 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern_Mask), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PS_Pattern_Mask)|AESDMA_CTR_IV_LSB64);
1396 }
1397 else
1398 {
1399 REG32_W((&_AESDMACtrl[0].Dma_PS_Pattern_Mask), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_PS_Pattern_Mask) & ~AESDMA_CTR_IV_LSB64);
1400 }
1401 }
1402
1403 //-------------------------------------------------------------------------------------------------
1404 /// Select Efuse key
1405 /// @param u8KeyIdx \b IN: the index of efuse key
1406 /// @note : Select Efuse Key
1407 //-------------------------------------------------------------------------------------------------
AESDMA_SetSecureKeyIdx(MS_U8 u8KeyIdx)1408 void AESDMA_SetSecureKeyIdx (MS_U8 u8KeyIdx)
1409 {
1410 MS_U32 u32Ctrl;
1411
1412 #if AESDMS_SECURED_BANK_EN
1413 u32Ctrl = _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl3_Secure);
1414 #else
1415 u32Ctrl = _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl2);
1416 #endif
1417
1418 switch (u8KeyIdx)
1419 {
1420 case E_DRVAESDMA_SECRETKEY_1:
1421 u32Ctrl &= ~AESDMA_USE_SECRET_KEY2;
1422 u32Ctrl |= AESDMA_USE_SECRET_KEY;
1423 #if AESDMS_SECURED_BANK_EN
1424 REG32_W((&_AESDMACtrl[0].Dma_Ctrl3_Secure), u32Ctrl);
1425 #else
1426 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), u32Ctrl);
1427 #endif
1428 break;
1429 case E_DRVAESDMA_SECRETKEY_2:
1430 #if AESDMS_SECURED_BANK_EN
1431 u32Ctrl &= ~AESDMA_USE_SECRET_KEY1;
1432 u32Ctrl |= AESDMA_USE_SECRET_KEY2;
1433 REG32_W((&_AESDMACtrl[0].Dma_Ctrl3_Secure), u32Ctrl);
1434 #else
1435 u32Ctrl |= AESDMA_USE_SECRET_KEY1;
1436 u32Ctrl |= AESDMA_USE_SECRET_KEY2;
1437 REG32_W((&_AESDMACtrl[0].Dma_Ctrl2), u32Ctrl);
1438 #endif
1439 break;
1440 case E_DRVAESDMA_SECRETKEY_EAEK:
1441 {
1442 AESDMA_BackupRegisters();
1443
1444 AESDMA_Reset();
1445 REG32_W((&_AESDMACtrl[0].Dma_Filein_Num), 0x10); // size
1446 AESDMA_Set_CIPHER_ENG(E_AESDMA_CIPHER_ECB, TRUE); // AES ECB decrypt
1447 REG32_W((&_AESDMACtrl[0].Dma_Matched_Pat), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Pat) & 0xFFFF0000 );
1448 REG32_W((&_AESDMACtrl[0].Dma_Matched_Pat), _AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Matched_Pat) | AESDMA_GEN_INTERNALKEY2 | AESDMA_HWKEY_EN); // h72 = 0x0022
1449 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) | AESDMA_CTRL_FILEOUT_START)); // h50 = 0x0001
1450 while (!AESDMA_Get_AESDMA_IsFinished());
1451 REG32_W((&_AESDMACtrl[0].Dma_Ctrl), (_AESDMA_REG32_R(&_AESDMACtrl[0].Dma_Ctrl) & 0xFFFF0000 )); // h50 = 0x0000
1452
1453 AESDMA_RestoreRegisters();
1454
1455 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001), (_AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001) & 0xFFFF0000));
1456 REG32_W((&_AESDSCMB6Ctrl[0].Reg0001), (_AESDMA_REG32_R(&_AESDSCMB6Ctrl[0].Reg0001) | AESDMA_DSCRMB6_KSLOT_INDEX_USE_INTERNAL_KEY2)); // h00 = 0x0206 , // [7:0] 0x6 use_int_key_2, [15:7] 0x2 default value
1457 break;
1458 }
1459 default:
1460 break;
1461 }
1462 }
1463
AESDMA_POWER_SUSPEND(void)1464 MS_BOOL AESDMA_POWER_SUSPEND(void)
1465 {
1466 SECUREBASECtrl_Buffer = _AESDMA_REG32_R(&_SECUREBASECtrl[0].Reg0001);
1467 return TRUE;
1468 }
1469
AESDMA_POWER_RESUME(void)1470 MS_BOOL AESDMA_POWER_RESUME(void)
1471 {
1472 REG32_W((&_SECUREBASECtrl[0].Reg0001), SECUREBASECtrl_Buffer);
1473 return TRUE;
1474 }
1475