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Searched refs:VP9_REG_RESET_SWRST (Results 1 – 25 of 28) sorted by relevance

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/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maldives/hvd_v3/
H A DhalHVD_EX.c3381 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3555 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6065 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mustang/hvd_v3/
H A DhalHVD_EX.c3521 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3697 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6418 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DhalHVD_EX.c3493 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3676 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6692 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
H A DregHVD_EX.h434 #define VP9_REG_RESET_SWRST BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DhalHVD_EX.c3510 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3690 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6314 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
H A DregHVD_EX.h417 #define VP9_REG_RESET_SWRST BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DhalHVD_EX.c3515 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3695 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6314 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
H A DregHVD_EX.h417 #define VP9_REG_RESET_SWRST BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DhalHVD_EX.c3595 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3777 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6523 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
H A DregHVD_EX.h446 #define VP9_REG_RESET_SWRST BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DhalHVD_EX.c3568 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3734 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6292 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
H A DregHVD_EX.h418 #define VP9_REG_RESET_SWRST BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DhalHVD_EX.c3609 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3786 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6496 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
H A DregHVD_EX.h419 #define VP9_REG_RESET_SWRST BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DhalHVD_EX.c4548 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
4757 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
7793 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DhalHVD_EX.c3546 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3716 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6769 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
H A DregHVD_EX.h418 #define VP9_REG_RESET_SWRST BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DhalHVD_EX.c4411 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
4616 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
7580 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DhalHVD_EX.c3506 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3689 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6749 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
H A DregHVD_EX.h434 #define VP9_REG_RESET_SWRST BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DhalHVD_EX.c4426 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
4631 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
7638 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DhalHVD_EX.c3532 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3702 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6711 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
H A DregHVD_EX.h418 #define VP9_REG_RESET_SWRST BIT(0) macro
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DhalHVD_EX.c3819 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
3992 _HVD_WriteWordMask(VP9_REG_RESET, 0, VP9_REG_RESET_SWRST); in HAL_HVD_EX_InitHW()
6848 _HVD_WriteWordMask(VP9_REG_RESET, VP9_REG_RESET_SWRST, VP9_REG_RESET_SWRST); in HAL_VP9_EX_DeinitHW()
H A DregHVD_EX.h434 #define VP9_REG_RESET_SWRST BIT(0) macro

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