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Searched refs:TOP_CKG_HVD_IDB_480MHZ (Results 1 – 25 of 25) sorted by relevance

/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/messi/hvd_v3/
H A DregHVD_EX.h477 #define TOP_CKG_HVD_IDB_480MHZ BITS(10:8, 3) // for overclocking macro
H A DhalHVD_EX.c3902 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7821/hvd_v3/
H A DregHVD_EX.h478 #define TOP_CKG_HVD_IDB_480MHZ BITS(10:8, 3) // for overclocking macro
H A DhalHVD_EX.c4058 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/M7621/hvd_v3/
H A DregHVD_EX.h494 #define TOP_CKG_HVD_IDB_480MHZ BITS(10:8, 3) // for overclocking macro
H A DhalHVD_EX.c4032 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/manhattan/hvd_v3/
H A DregHVD_EX.h478 #define TOP_CKG_HVD_IDB_480MHZ BITS(10:8, 3) // for overclocking macro
H A DhalHVD_EX.c3943 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/macan/hvd_v3/
H A DregHVD_EX.h479 #define TOP_CKG_HVD_IDB_480MHZ BITS(10:8, 3) // for overclocking macro
H A DhalHVD_EX.c3993 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mainz/hvd_v3/
H A DregHVD_EX.h477 #define TOP_CKG_HVD_IDB_480MHZ BITS(10:8, 3) macro
H A DhalHVD_EX.c3897 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maxim/hvd_v3/
H A DregHVD_EX.h494 #define TOP_CKG_HVD_IDB_480MHZ BITS(10:8, 3) // for overclocking macro
H A DhalHVD_EX.c4053 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/maserati/hvd_v3/
H A DregHVD_EX.h478 #define TOP_CKG_HVD_IDB_480MHZ BITS(10:8, 3) // for overclocking macro
H A DhalHVD_EX.c4080 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_lite/hal/kano/hvd_lite/
H A DregHVD_EX.h613 #define TOP_CKG_HVD_IDB_480MHZ BITS(2:0, 3) // for overclocking macro
H A DhalHVD_EX.c4240 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/mooney/hvd_v3/
H A DregHVD_EX.h506 #define TOP_CKG_HVD_IDB_480MHZ BITS(10:8, 3) macro
H A DhalHVD_EX.c3996 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6/hvd_v3/
H A DregHVD_EX.h732 #define TOP_CKG_HVD_IDB_480MHZ BITS(2:0, 3) // for overclocking macro
H A DhalHVD_EX.c4943 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/curry/hvd_v3/
H A DregHVD_EX.h732 #define TOP_CKG_HVD_IDB_480MHZ BITS(2:0, 3) // for overclocking macro
H A DhalHVD_EX.c4928 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()
/utopia/UTPA2-700.0.x/modules/vdec_v3/hal/k6lite/hvd_v3/
H A DhalHVD_EX.c5059 _HVD_WriteWordMask(REG_TOP_HVD_IDB, TOP_CKG_HVD_IDB_480MHZ, TOP_CKG_HVD_IDB_CLK_MASK); in HAL_HVD_EX_PowerCtrl()