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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file regHVD.h 98 /// @brief HVD Module Register Definition 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_HVD_H_ 103 #define _REG_HVD_H_ 104 105 106 //------------------------------------------------------------------------------------------------- 107 // Hardware Capability 108 //------------------------------------------------------------------------------------------------- 109 110 111 //------------------------------------------------------------------------------------------------- 112 // Macro and Define 113 //------------------------------------------------------------------------------------------------- 114 115 //***************************************************************************** 116 // RIU macro 117 #define HVD_MACRO_START do { 118 #define HVD_MACRO_END } while (0) 119 #define HVD_RIU_BASE (u32HVDRegOSBase) 120 121 #define HVD_HIGHBYTE(u16) ((MS_U8)((u16) >> 8)) 122 #define HVD_LOWBYTE(u16) ((MS_U8)(u16)) 123 #define HVD_RIU_READ_BYTE(addr) ( READ_BYTE( HVD_RIU_BASE + (addr) ) ) 124 #define HVD_RIU_READ_WORD(addr) ( READ_WORD( HVD_RIU_BASE + (addr) ) ) 125 #define HVD_RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( HVD_RIU_BASE+(addr), val); } 126 #define HVD_RIU_WRITE_WORD(addr, val) { WRITE_WORD( HVD_RIU_BASE+(addr), val); } 127 128 129 #define _HVD_ReadByte( u32Reg ) HVD_RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1)) 130 131 #define _HVD_Read2Byte( u32Reg ) (HVD_RIU_READ_WORD((u32Reg)<<1)) 132 133 #define _HVD_Read4Byte( u32Reg ) ( (MS_U32)HVD_RIU_READ_WORD((u32Reg)<<1) | ((MS_U32)HVD_RIU_READ_WORD(((u32Reg)+2)<<1)<<16 ) ) 134 135 #define _HVD_ReadRegBit( u32Reg, u8Mask ) (HVD_RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask)) 136 137 #define _HVD_ReadWordBit( u32Reg, u16Mask ) (_HVD_Read2Byte( u32Reg ) & (u16Mask)) 138 139 #define _HVD_WriteRegBit( u32Reg, bEnable, u8Mask ) \ 140 HVD_MACRO_START \ 141 HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (HVD_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \ 142 (HVD_RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \ 143 HVD_MACRO_END 144 145 #define _HVD_WriteByte( u32Reg, u8Val ) \ 146 HVD_MACRO_START \ 147 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \ 148 HVD_MACRO_END 149 150 #define _HVD_Write2Byte( u32Reg, u16Val ) \ 151 HVD_MACRO_START \ 152 if ( ((u32Reg) & 0x01) ) \ 153 { \ 154 HVD_RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ 155 HVD_RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ 156 } \ 157 else \ 158 { \ 159 HVD_RIU_WRITE_WORD( ((u32Reg)<<1) , u16Val); \ 160 } \ 161 HVD_MACRO_END 162 163 #define _HVD_Write3Byte( u32Reg, u32Val ) \ 164 if ((u32Reg) & 0x01) \ 165 { \ 166 HVD_RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ 167 HVD_RIU_WRITE_WORD( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ 168 } \ 169 else \ 170 { \ 171 HVD_RIU_WRITE_WORD( (u32Reg) << 1, u32Val); \ 172 HVD_RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ 173 } 174 175 #define _HVD_Write4Byte( u32Reg, u32Val ) \ 176 HVD_MACRO_START \ 177 if ((u32Reg) & 0x01) \ 178 { \ 179 HVD_RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ 180 HVD_RIU_WRITE_WORD( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ 181 HVD_RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ 182 } \ 183 else \ 184 { \ 185 HVD_RIU_WRITE_WORD( (u32Reg) <<1 , u32Val); \ 186 HVD_RIU_WRITE_WORD( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ 187 } \ 188 HVD_MACRO_END 189 190 #define _HVD_WriteByteMask( u32Reg, u8Val, u8Msk ) \ 191 HVD_MACRO_START \ 192 HVD_RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (HVD_RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 193 HVD_MACRO_END 194 195 #define _HVD_WriteWordMask( u32Reg, u16Val , u16Msk) \ 196 HVD_MACRO_START \ 197 if ( ((u32Reg) & 0x01) ) \ 198 { \ 199 _HVD_WriteByteMask( ((u32Reg)+1) , (((u16Val) & 0xff00)>>8) , (((u16Msk)&0xff00)>>8) ); \ 200 _HVD_WriteByteMask( (u32Reg) , ((u16Val) & 0x00ff) , ((u16Msk)&0x00ff) ); \ 201 } \ 202 else \ 203 { \ 204 HVD_RIU_WRITE_WORD( ((u32Reg)<<1) , (((u16Val) & (u16Msk)) | (_HVD_Read2Byte( u32Reg ) & (~( u16Msk )))) ); \ 205 } \ 206 HVD_MACRO_END 207 208 //------------------------------------------------------------------------------ 209 // MVD Reg 210 //------------------------------------------------------------------------------ 211 #define REG_MVD_BASE (0x1100) 212 213 #define MVD_REG_STAT_CTRL (REG_MVD_BASE) 214 #define MVD_REG_CTRL_RST BIT(0) 215 #define MVD_REG_CTRL_INIT BIT(2) 216 #define MVD_REG_DISCONNECT_MIU BIT(6) 217 218 #if 1//Note: this setting should be set according client table of each chip 219 #define MIU0_REG_BASE 0x1200 220 #define MIU1_REG_BASE 0x0600 221 222 #define MIU_CLIENT_SELECT_GP2 (MIU0_REG_BASE + (0x007A<<1)) 223 #define MIU_CLIENT_SELECT_GP2_MVD BIT(4) 224 #endif 225 226 227 228 //------------------------------------------------------------------------------ 229 // HVD Reg 230 //------------------------------------------------------------------------------ 231 #define REG_HVD_BASE (0x1B00) 232 #define REG_EVD_BASE (0x1C00) 233 #define REG_MIU_SOURCE_BASE (0x0600) 234 #define REG_G2VP9_BASE (0x60E00) 235 #define REG_HVD_BBU5_BBU6_BASE (0x1700) 236 #define REG_EVD_BBU3_BBU4_BASE (0x2700) 237 238 239 #define HVD_REG_REV_ID (REG_HVD_BASE + ((0x0000) << 1)) 240 #define HVD_REG_RESET (REG_HVD_BASE + ((0x0001) << 1)) 241 #define HVD_REG_RESET_SWRST BIT(0) 242 #define HVD_REG_RESET_IDB_MIU_256 BIT(1) 243 #define HVD_REG_RESET_SWRST_FIN BIT(2) 244 #define HVD_REG_RESET_STOP_BBU BIT(3) 245 #define HVD_REG_RESET_MIU_RDY BIT(4) 246 #define HVD_REG_RESET_MIU1_128 BIT(5) 247 #define HVD_REG_RESET_MIU1_256 BIT(6) 248 #define HVD_REG_MC_MIU_256 BIT(7) 249 #define HVD_REG_RESET_HK_AVS_MODE BIT(8) 250 #define HVD_REG_RESET_HK_RM_MODE BIT(9) 251 #define HVD_REG_RESET_HK_RV9_DEC_MODE BIT(10) 252 #define HVD_REG_RESET_MIU_128 BIT(11) 253 #define HVD_REG_RESET_CPUIF_SEL BIT(12) 254 #define HVD_REG_RESET_ALL_SRAM_SD_EN BIT(13) 255 #define HVD_REG_RESET_MIU_256 BIT(14) 256 #define HVD_REG_RESET_BOND_HD BIT(15) 257 258 #define HVD_REG_ESB_ST_ADDR_L(reg_base) (reg_base + ((0x0002) << 1)) 259 #define HVD_REG_ESB_ST_ADDR_H(reg_base) (reg_base + ((0x0003) << 1)) 260 261 #define HVD_REG_ESB_LENGTH_L(reg_base) (reg_base + ((0x0004) << 1)) 262 #define HVD_REG_ESB_LENGTH_H(reg_base) (reg_base + ((0x0005) << 1)) 263 264 #define HVD_REG_ESB_RPTR(reg_base) (reg_base + ((0x0006) << 1)) 265 #define HVD_REG_ESB_RPTR_POLL BIT(0) 266 267 #define HVD_REG_ESB_RPTR_H(reg_base) (reg_base + ((0x0007) << 1)) 268 269 #define HVD_REG_MIF_BBU(reg_base) (reg_base + ((0x0008) << 1)) 270 #define HVD_REG_MIF_OFFSET_L_BITS 7 271 #define HVD_REG_MIF_OFFSET_H BIT(12) 272 #define HVD_REG_BBU_TSP_INPUT BIT(8) 273 #define HVD_REG_BBU_PASER_MASK (BIT(10) | BIT(9)) 274 #define HVD_REG_BBU_PASER_DISABLE 0 275 #define HVD_REG_BBU_PASER_ENABLE_ALL BIT(9) 276 #define HVD_REG_BBU_PASER_ENABLE_03 (BIT(9) | BIT(10)) 277 #define HVD_REG_BBU_AUTO_NAL_TAB BIT(11) 278 279 #define HVD_REG_NAL_TBL_ST_ADDR_L(reg_base) (reg_base + ((0x0009) << 1)) 280 #define HVD_REG_NAL_TBL_ST_ADDR_H(reg_base) (reg_base + ((0x000A) << 1)) 281 282 #define HVD_REG_HI_MBOX0_L(reg_base) (reg_base + ((0x000B) << 1)) 283 #define HVD_REG_HI_MBOX0_H(reg_base) (reg_base + ((0x000C) << 1)) 284 #define HVD_REG_HI_MBOX1_L(reg_base) (reg_base + ((0x000D) << 1)) 285 #define HVD_REG_HI_MBOX1_H(reg_base) (reg_base + ((0x000E) << 1)) 286 #define HVD_REG_HI_MBOX_SET(reg_base) (reg_base + ((0x000F) << 1)) 287 #define HVD_REG_HI_MBOX0_SET BIT(0) 288 #define HVD_REG_HI_MBOX1_SET BIT(8) 289 290 #define HVD_REG_RISC_MBOX_CLR(reg_base) (reg_base + ((0x0010) << 1)) 291 #define HVD_REG_RISC_MBOX0_CLR BIT(0) 292 #define HVD_REG_RISC_MBOX1_CLR BIT(1) 293 #define HVD_REG_RISC_ISR_CLR BIT(2) 294 #define HVD_REG_NAL_WPTR_SYNC BIT(3) 295 #define HVD_REG_RISC_ISR_MSK BIT(6) 296 #define HVD_REG_RISC_ISR_FORCE BIT(10) 297 298 #define HVD_REG_RISC_MBOX_RDY(reg_base) (reg_base + ((0x0011) << 1)) 299 #define HVD_REG_RISC_MBOX0_RDY BIT(0) 300 #define HVD_REG_RISC_MBOX1_RDY BIT(4) 301 #define HVD_REG_RISC_ISR_VALID BIT(8) 302 303 #define HVD_REG_HI_MBOX_RDY(reg_base) (reg_base + ((0x0012) << 1)) 304 #define HVD_REG_HI_MBOX0_RDY BIT(0) 305 #define HVD_REG_HI_MBOX1_RDY BIT(8) 306 307 #define HVD_REG_RISC_MBOX0_L(reg_base) (reg_base + ((0x0013) << 1)) 308 #define HVD_REG_RISC_MBOX0_H(reg_base) (reg_base + ((0x0014) << 1)) 309 #define HVD_REG_RISC_MBOX1_L(reg_base) (reg_base + ((0x0015) << 1)) 310 #define HVD_REG_RISC_MBOX1_H(reg_base) (reg_base + ((0x0016) << 1)) 311 312 #define HVD_REG_POLL_NAL_RPTR(reg_base) (reg_base + ((0x0017) << 1)) 313 #define HVD_REG_POLL_NAL_RPTR_BIT BIT(0) 314 #define HVD_REG_NAL_RPTR_HI(reg_base) (reg_base + ((0x0018) << 1)) 315 #define HVD_REG_NAL_WPTR_HI(reg_base) (reg_base + ((0x0019) << 1)) 316 #define HVD_REG_NAL_TAB_LEN(reg_base) (reg_base + ((0x0020) << 1)) 317 318 #define HVD_REG_DEBUG_DAT_L (REG_HVD_BASE + ((0x0023) << 1)) 319 #define HVD_REG_DEBUG_DAT_H (REG_HVD_BASE + ((0x0024) << 1)) 320 #define HVD_REG_DEBUG_SEL (REG_HVD_BASE + ((0x0025) << 1)) 321 322 #define HVD_REG_BWA_CLK (REG_HVD_BASE + ((0x002D) << 1)) 323 #define HVD_REG_CLK_HVD_SW_OV_EN BIT(0) 324 #define HVD_REG_CLK_HVD_SW_UPD BIT(1) 325 #define HVD_REG_CLK_HVD_IDB_SW_OV_EN BIT(2) 326 #define HVD_REG_CLK_HVD_IDB_SW_UPD BIT(3) 327 #define HVD_REG_CLK_HVD_SW_DIV_MASK BMASK(8:4) 328 #define HVD_REG_CLK_HVD_SW_DIV_10 BITS(8:4, 10) 329 #define HVD_REG_CLK_HVD_SW_DIV_30 BITS(8:4, 30) 330 #define HVD_REG_CLK_HVD_IDB_SW_DIV_MASK BMASK(13:9) 331 #define HVD_REG_CLK_HVD_IDB_SW_DIV_10 BITS(13:9, 10) 332 #define HVD_REG_CLK_HVD_IDB_SW_DIV_30 BITS(13:9, 30) 333 334 /* Second bitstream registers definition */ 335 #define HVD_REG_MODE_BS2 (REG_HVD_BASE + ((0x0030) << 1)) 336 #define HVD_REG_MODE_HK_AVS_MODE_BS2 BIT(8) 337 #define HVD_REG_MODE_HK_RM_MODE_BS2 BIT(9) 338 #define HVD_REG_MODE_HK_RV9_DEC_MODE_BS2 BIT(10) 339 340 #define HVD_REG_ESB_ST_ADDR_L_BS2(reg_base) (reg_base + ((0x0032) << 1)) 341 #define HVD_REG_ESB_ST_ADDR_H_BS2(reg_base) (reg_base + ((0x0033) << 1)) 342 343 #define HVD_REG_ESB_LENGTH_L_BS2(reg_base) (reg_base + ((0x0034) << 1)) 344 #define HVD_REG_ESB_LENGTH_H_BS2(reg_base) (reg_base + ((0x0035) << 1)) 345 346 #define HVD_REG_ESB_RPTR_L_BS2(reg_base) (reg_base + ((0x0036) << 1)) 347 #define HVD_REG_ESB_RPTR_H_BS2(reg_base) (reg_base + ((0x0037) << 1)) 348 349 #define HVD_REG_MIF_BBU_BS2(reg_base) (reg_base + ((0x0038) << 1)) 350 #define HVD_REG_MIF_OFFSET_L_BITS_BS2 7 351 #define HVD_REG_MIF_OFFSET_H_BS2 BIT(12) 352 #define HVD_REG_BBU_TSP_INPUT_BS2 BIT(8) 353 #define HVD_REG_BBU_PASER_MASK_BS2 (BIT(10) | BIT(9)) 354 #define HVD_REG_BBU_PASER_DISABLE_BS2 0 355 #define HVD_REG_BBU_PASER_ENABLE_ALL_BS2 BIT(9) 356 #define HVD_REG_BBU_PASER_ENABLE_03_BS2 (BIT(9) | BIT(10)) 357 #define HVD_REG_BBU_AUTO_NAL_TAB_BS2 BIT(11) 358 359 #define EVD_REG_ESB_ST_ADDR_L_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x0002) << 1)) 360 #define EVD_REG_ESB_ST_ADDR_H_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x0003) << 1)) 361 362 #define EVD_REG_ESB_LENGTH_L_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x0004) << 1)) 363 #define EVD_REG_ESB_LENGTH_H_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x0005) << 1)) 364 365 #define EVD_REG_ESB_RPTR_L_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x0036) << 1)) 366 #define EVD_REG_ESB_RPTR_H_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x0037) << 1)) 367 368 #define EVD_REG_MIF_BBU_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x0038) << 1)) 369 #define EVD_REG_MIF_OFFSET_L_BITS_BS3 7 370 #define EVD_REG_MIF_OFFSET_H_BS3 BIT(12) 371 #define EVD_REG_BBU_TSP_INPUT_BS3 BIT(8) 372 #define EVD_REG_BBU_PASER_MASK_BS3 (BIT(10) | BIT(9)) 373 #define EVD_REG_BBU_PASER_DISABLE_BS3 0 374 #define EVD_REG_BBU_PASER_ENABLE_ALL_BS3 BIT(9) 375 #define EVD_REG_BBU_PASER_ENABLE_03_BS3 (BIT(9) | BIT(10)) 376 #define EVD_REG_BBU_AUTO_NAL_TAB_BS3 BIT(11) 377 378 379 #define HVD_REG_ESB_ST_ADDR_L_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x0002) << 1)) 380 #define HVD_REG_ESB_ST_ADDR_H_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x0003) << 1)) 381 382 #define HVD_REG_ESB_LENGTH_L_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x0004) << 1)) 383 #define HVD_REG_ESB_LENGTH_H_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x0005) << 1)) 384 385 #define HVD_REG_ESB_RPTR_L_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x0036) << 1)) 386 #define HVD_REG_ESB_RPTR_H_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x0037) << 1)) 387 388 #define HVD_REG_MIF_BBU_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x0038) << 1)) 389 #define HVD_REG_MIF_OFFSET_L_BITS_BS5 7 390 #define HVD_REG_MIF_OFFSET_H_BS5 BIT(12) 391 #define HVD_REG_BBU_TSP_INPUT_BS5 BIT(8) 392 #define HVD_REG_BBU_PASER_MASK_BS5 (BIT(10) | BIT(9)) 393 #define HVD_REG_BBU_PASER_DISABLE_BS5 0 394 #define HVD_REG_BBU_PASER_ENABLE_ALL_BS5 BIT(9) 395 #define HVD_REG_BBU_PASER_ENABLE_03_BS5 (BIT(9) | BIT(10)) 396 #define HVD_REG_BBU_AUTO_NAL_TAB_BS5 BIT(11) 397 398 399 400 401 402 #define EVD_REG_ESB_ST_ADDR_L_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x0032) << 1)) 403 #define EVD_REG_ESB_ST_ADDR_H_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x0033) << 1)) 404 405 #define EVD_REG_ESB_LENGTH_L_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x0034) << 1)) 406 #define EVD_REG_ESB_LENGTH_H_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x0035) << 1)) 407 408 #define EVD_REG_ESB_RPTR_L_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x0076) << 1)) 409 #define EVD_REG_ESB_RPTR_H_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x0077) << 1)) 410 411 #define EVD_REG_MIF_BBU_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x0078) << 1)) 412 #define EVD_REG_MIF_OFFSET_L_BITS_BS4 7 413 #define EVD_REG_MIF_OFFSET_H_BS4 BIT(12) 414 #define EVD_REG_BBU_TSP_INPUT_BS4 BIT(8) 415 #define EVD_REG_BBU_PASER_MASK_BS4 (BIT(10) | BIT(9)) 416 #define EVD_REG_BBU_PASER_DISABLE_BS4 0 417 #define EVD_REG_BBU_PASER_ENABLE_ALL_BS4 BIT(9) 418 #define EVD_REG_BBU_PASER_ENABLE_03_BS4 (BIT(9) | BIT(10)) 419 #define EVD_REG_BBU_AUTO_NAL_TAB_BS4 BIT(11) 420 421 422 #define HVD_REG_ESB_ST_ADDR_L_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x0032) << 1)) 423 #define HVD_REG_ESB_ST_ADDR_H_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x0033) << 1)) 424 425 #define HVD_REG_ESB_LENGTH_L_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x0034) << 1)) 426 #define HVD_REG_ESB_LENGTH_H_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x0035) << 1)) 427 428 #define HVD_REG_ESB_RPTR_L_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x0076) << 1)) 429 #define HVD_REG_ESB_RPTR_H_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x0077) << 1)) 430 431 #define HVD_REG_MIF_BBU_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x0078) << 1)) 432 #define HVD_REG_MIF_OFFSET_L_BITS_BS6 7 433 #define HVD_REG_MIF_OFFSET_H_BS6 BIT(12) 434 #define HVD_REG_BBU_TSP_INPUT_BS6 BIT(8) 435 #define HVD_REG_BBU_PASER_MASK_BS6 (BIT(10) | BIT(9)) 436 #define HVD_REG_BBU_PASER_DISABLE_BS6 0 437 #define HVD_REG_BBU_PASER_ENABLE_ALL_BS6 BIT(9) 438 #define HVD_REG_BBU_PASER_ENABLE_03_BS6 (BIT(9) | BIT(10)) 439 #define HVD_REG_BBU_AUTO_NAL_TAB_BS6 BIT(11) 440 441 442 443 #define HVD_REG_NAL_TBL_ST_ADDR_L_BS2(reg_base) (reg_base + ((0x0039) << 1)) 444 #define HVD_REG_NAL_TBL_ST_ADDR_H_BS2(reg_base) (reg_base + ((0x003A) << 1)) 445 446 #define HVD_REG_NAL_RPTR_HI_BS2(reg_base) (reg_base + ((0x003B) << 1)) 447 #define HVD_REG_NAL_WPTR_HI_BS2(reg_base) (reg_base + ((0x003C) << 1)) 448 #define HVD_REG_NAL_TAB_LEN_BS2(reg_base) (reg_base + ((0x003D) << 1)) 449 450 #define EVD_REG_NAL_TBL_ST_ADDR_L_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x0039) << 1)) 451 #define EVD_REG_NAL_TBL_ST_ADDR_H_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x003A) << 1)) 452 453 #define EVD_REG_NAL_RPTR_HI_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x003B) << 1)) 454 #define EVD_REG_NAL_WPTR_HI_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x003C) << 1)) 455 #define EVD_REG_NAL_TAB_LEN_BS3 (REG_EVD_BBU3_BBU4_BASE + ((0x003D) << 1)) 456 457 #define EVD_REG_NAL_TBL_ST_ADDR_L_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x0079) << 1)) 458 #define EVD_REG_NAL_TBL_ST_ADDR_H_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x007A) << 1)) 459 460 #define EVD_REG_NAL_RPTR_HI_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x007B) << 1)) 461 #define EVD_REG_NAL_WPTR_HI_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x007C) << 1)) 462 #define EVD_REG_NAL_TAB_LEN_BS4 (REG_EVD_BBU3_BBU4_BASE + ((0x007D) << 1)) 463 464 465 #define HVD_REG_NAL_TBL_ST_ADDR_L_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x0039) << 1)) 466 #define HVD_REG_NAL_TBL_ST_ADDR_H_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x003A) << 1)) 467 468 #define HVD_REG_NAL_RPTR_HI_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x003B) << 1)) 469 #define HVD_REG_NAL_WPTR_HI_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x003C) << 1)) 470 #define HVD_REG_NAL_TAB_LEN_BS5 (REG_HVD_BBU5_BBU6_BASE + ((0x003D) << 1)) 471 472 #define HVD_REG_NAL_TBL_ST_ADDR_L_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x0079) << 1)) 473 #define HVD_REG_NAL_TBL_ST_ADDR_H_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x007A) << 1)) 474 475 #define HVD_REG_NAL_RPTR_HI_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x007B) << 1)) 476 #define HVD_REG_NAL_WPTR_HI_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x007C) << 1)) 477 #define HVD_REG_NAL_TAB_LEN_BS6 (REG_HVD_BBU5_BBU6_BASE + ((0x007D) << 1)) 478 479 480 #define HVD_REG_ESB_WPTR_L_BS2 (REG_HVD_BASE + ((0x003E) << 1)) 481 #define HVD_REG_ESB_WPTR_H_BS2 (REG_HVD_BASE + ((0x003F) << 1)) 482 483 /* VP8 Registers */ 484 #define HVD_REG_HK_VP8 (REG_HVD_BASE + ((0x0040) << 1)) 485 #define HVD_REG_HK_VP8_DEC_MODE BIT(0) 486 #define HVD_REG_HK_PLAYER_FM BIT(1) 487 488 #define HVD_REG_ESB_ST_ADR_L_BS34 (REG_HVD_BASE + ((0x0042) << 1)) 489 #define HVD_REG_ESB_ST_ADR_H_BS34 (REG_HVD_BASE + ((0x0043) << 1)) 490 #define HVD_REG_ESB_LENGTH_L_BS34 (REG_HVD_BASE + ((0x0044) << 1)) 491 #define HVD_REG_ESB_LENGTH_H_BS34 (REG_HVD_BASE + ((0x0045) << 1)) 492 493 494 #define EVD_REG_MIF_SOURCE_GROUP0 (REG_MIU_SOURCE_BASE + ((0x0078) << 1)) 495 #define EVD_REG_MIF_SOURCE_GROUP1 (REG_MIU_SOURCE_BASE + ((0x0079) << 1)) 496 #define EVD_REG_MIF_SOURCE_GROUP2 (REG_MIU_SOURCE_BASE + ((0x007A) << 1)) 497 #define EVD_REG_MIF_SOURCE_GROUP3 (REG_MIU_SOURCE_BASE + ((0x007B) << 1)) 498 #define EVD_REG_MIF_SOURCE_GROUP4 (REG_MIU_SOURCE_BASE + ((0x007C) << 1)) 499 #define EVD_REG_MIF_SOURCE_GROUP5 (REG_MIU_SOURCE_BASE + ((0x007B) << 1)) 500 501 502 503 #define HVD_REG_MIF_BS34 (REG_HVD_BASE + ((0x0048) << 1)) 504 #define HVD_REG_BS34_MIF_OFFSET_L_BITS 7 505 #define HVD_REG_BS34_MIF_OFFSET_H BIT(12) 506 #define HVD_REG_BS34_TSP_INPUT BIT(8) 507 #define HVD_REG_BS34_PASER_MASK (BIT(10) | BIT(9)) 508 #define HVD_REG_BS34_PASER_DISABLE 0 509 #define HVD_REG_BS34_PASER_ENABLE_ALL BIT(9) 510 #define HVD_REG_BS34_PASER_ENABLE_03 (BIT(9) | BIT(10)) 511 #define HVD_REG_BS34_AUTO_NAL_TAB BIT(11) 512 #define HVD_REG_BS34_NAL_BUF_SKIP BIT(13) 513 #define HVD_REG_BS34_NAL_BUF_SKIP_RDY BIT(14) 514 515 #define HVD_REG_NAL_TAB_ST_L_BS3 (REG_HVD_BASE + ((0x0049) << 1)) 516 #define HVD_REG_NAL_TAB_ST_H_BS3 (REG_HVD_BASE + ((0x004A) << 1)) 517 #define HVD_REG_NAL_RPTR_HI_BS3 (REG_HVD_BASE + ((0x004B) << 1)) 518 #define HVD_REG_NAL_WPTR_HI_BS3 (REG_HVD_BASE + ((0x004C) << 1)) 519 #define HVD_REG_NAL_TAB_LEN_BS3 (REG_HVD_BASE + ((0x004D) << 1)) 520 #define HVD_REG_NAL_TAB_ST_L_BS4 (REG_HVD_BASE + ((0x0059) << 1)) 521 #define HVD_REG_NAL_TAB_ST_H_BS4 (REG_HVD_BASE + ((0x005A) << 1)) 522 #define HVD_REG_NAL_RPTR_HI_BS4 (REG_HVD_BASE + ((0x005B) << 1)) 523 #define HVD_REG_NAL_WPTR_HI_BS4 (REG_HVD_BASE + ((0x005C) << 1)) 524 #define HVD_REG_NAL_TAB_LEN_BS4 (REG_HVD_BASE + ((0x005D) << 1)) 525 526 //------------------------------------------------------------------------------ 527 // EVD Reg 528 //------------------------------------------------------------------------------ 529 #define REG_EVDPLL_BASE (0x10900) 530 #define REG_EVDPLL_PD (REG_EVDPLL_BASE + ((0x0041) << 1)) 531 #define REG_EVDPLL_PD_DIS BIT(8) 532 533 #define REG_EVDPLL_LOOP_DIV_SECOND (REG_EVDPLL_BASE+(0x0043<<1)) 534 #define REG_EVDPLL_LOOP_DIV_SECOND_MASK BMASK(7:0) 535 #define REG_EVDPLL_LOOP_DIV_SECOND_456MHZ BITS(7:0, 19) 536 537 #define EVD_REG_RESET (REG_EVD_BASE + ((0x0001) << 1)) 538 #define EVD_REG_RESET_SWRST BIT(0) 539 #define EVD_REG_RESET_SWRST_FIN BIT(2) 540 #define EVD_REG_RESET_STOP_BBU BIT(3) 541 #define EVD_REG_RESET_MIU_RDY BIT(4) 542 #define EVD_REG_RESET_MIU1_128 BIT(5) 543 #define EVD_REG_RESET_MIU1_256 BIT(6) 544 #define EVD_REG_RESET_USE_HVD_MIU_EN BIT(7) 545 #define EVD_REG_RESET_HK_HEVC_MODE BIT(8) 546 #define EVD_REG_RESET_HK_TSP2EVD_EN BIT(9) 547 #define EVD_REG_RESET_MIU0_256 BIT(10) 548 #define EVD_REG_RESET_MIU0_128 BIT(11) 549 #define EVD_REG_RESET_CPUIF_SEL BIT(12) 550 #define EVD_REG_RESET_ALL_SRAM_SD_EN BIT(13) 551 #define EVD_REG_RESET_BOND_UHD BIT(14) 552 #define EVD_REG_RESET_BOND_HD BIT(15) 553 554 #define EVD_BBU23_SETTING (REG_EVD_BASE + ((0x0001B) << 1)) 555 #define REG_TSP2EVD_EN_BS3 BIT(9) 556 #define REG_TSP2EVD_EN_BS4 BIT(10) 557 558 559 #define REG_CLK_EVD (REG_EVD_BASE + ((0x002d) << 1)) 560 #define REG_CLK_EVD_SW_OV_EN BIT(0) 561 #define REG_CLK_EVD_SW_UPD BIT(1) 562 #define REG_CLK_EVD_PPU_SW_OV_EN BIT(2) 563 #define REG_CLK_EVD_PPU_SW_UPD BIT(3) 564 #define REG_CLK_EVD_SW_DIV_MASK BMASK(8:4) 565 #define REG_CLK_EVD_SW_DIV_10 BITS(8:4, 10) 566 #define REG_CLK_EVD_SW_DIV_30 BITS(8:4, 30) 567 #define REG_CLK_EVD_PPU_SW_DIV_MASK BMASK(13:9) 568 #define REG_CLK_EVD_PPU_SW_DIV_10 BITS(13:9, 10) 569 #define REG_CLK_EVD_PPU_SW_DIV_30 BITS(13:9, 30) 570 571 572 573 #define EVD_BBU_MIU_SETTING (REG_EVD_BASE + ((0x00040) << 1)) 574 #define REG_BBU_MIU_128 BIT(0) 575 #define REG_BBU_MIU_256 BIT(1) 576 577 //------------------------------------------------------------------------------ 578 // G2 VP9 Reg 579 //------------------------------------------------------------------------------ 580 #define VP9_REG_RESET (REG_G2VP9_BASE + ((0x0001) << 1)) 581 #define VP9_REG_RESET_SWRST BIT(0) 582 #define VP9_REG_RESET_SWRST_FIN BIT(2) 583 #define VP9_REG_RESET_MIU_RDY BIT(4) 584 #define VP9_REG_RESET_ALL_SRAM_SD_EN BIT(13) 585 #define VP9_REG_RESET_APB_SEL BIT(15) 586 587 #define EVD_REG_VP9_MODE (REG_EVD_BASE + ((0x001b) << 1)) 588 #define EVD_REG_SET_VP9_MODE BIT(0) 589 590 591 //------------------------------------------------------------------------------ 592 // ChipTop Reg 593 //------------------------------------------------------------------------------ 594 595 #define CHIPTOP_REG_BASE (0x1E00 ) 596 #define CLKGEN0_REG_BASE (0x0B00 ) 597 #define CLKGEN2_REG_BASE (0x0A00) 598 599 600 #define REG_TOP_PSRAM0_1_MIUMUX (CHIPTOP_REG_BASE+(0x002D<<1)) //TODO 601 #define TOP_CKG_PSRAM0_MASK BMASK(1:0) 602 #define TOP_CKG_PSRAM0_DIS BIT(0) 603 #define TOP_CKG_PSRAM0_INV BIT(1) 604 #define TOP_CKG_PSRAM1_MASK BMASK(3:2) 605 #define TOP_CKG_PSRAM1_DIS BIT(0) 606 #define TOP_CKG_PSRAM1_INV BIT(1) 607 #define TOP_MIU_MUX_G07_MASK BMASK(7:6) 608 #define TOP_MIU_MUX_G07_OD_LSB_R BITS(7:6,0) 609 #define TOP_MIU_MUX_G07_GOP2_R BITS(7:6,1) 610 #define TOP_MIU_MUX_G08_MASK BMASK(9:8) 611 #define TOP_MIU_MUX_G08_OD_LSB_W BITS(9:8,0) 612 #define TOP_MIU_MUX_G08_VE_W BITS(9:8,1) 613 #define TOP_MIU_MUX_G15_MASK BMASK(11:10) 614 #define TOP_MIU_MUX_G15_GOP2_R BITS(11:10,0) 615 #define TOP_MIU_MUX_G15_OD_LSB_R BITS(11:10,1) 616 #define TOP_MIU_MUX_G1A_MASK BMASK(13:12) 617 #define TOP_MIU_MUX_G1A_VE_W BITS(13:12,0) 618 #define TOP_MIU_MUX_G1A_OD_LSB_W BITS(13:12,1) 619 #define TOP_MIU_MUX_G26_MASK BMASK(15:14) 620 #define TOP_MIU_MUX_G26_RVD_RW BITS(15:14,0) 621 #define TOP_MIU_MUX_G26_SVD_INTP_R BITS(15:14,1) 622 #define TOP_MIU_MUX_G26_MVD_R BITS(15:14,2) 623 624 #define REG_TOP_VPU (CLKGEN0_REG_BASE+(0x0030<<1)) 625 #define TOP_CKG_VPU_MASK BMASK(6:0) 626 #define TOP_CKG_VPU_DIS BIT(0) 627 #define TOP_CKG_VPU_INV BIT(1) 628 #define TOP_CKG_VPU_CLK_MASK BMASK(6:2) 629 #define TOP_CKG_VPU_480MHZ BITS(6:2, 3) 630 #define TOP_CKG_VPU_432MHZ BITS(6:2, 6) 631 #define TOP_CKG_VPU_384MHZ BITS(6:2, 7) 632 #define TOP_CKG_VPU_ICG_EN BIT(8) 633 #define TOP_CKG_VPU_LITE_ICG_EN BIT(9) 634 635 #define REG_TOP_HVD (CLKGEN0_REG_BASE+(0x0034<<1)) 636 #define TOP_CKG_HVD_MASK BMASK(4:0) 637 #define TOP_CKG_HVD_DIS BIT(0) 638 #define TOP_CKG_HVD_INV BIT(1) 639 #define TOP_CKG_HVD_CLK_MASK BMASK(4:2) 640 #define TOP_CKG_HVD_384MHZ BITS(4:2, 0) // default use this 641 #define TOP_CKG_HVD_288MHZ BITS(4:2, 3) 642 #define TOP_CKG_HVD_432MHZ BITS(4:2, 7) // for overclocking 643 644 645 #define REG_TOP_VP9 (CLKGEN0_REG_BASE+(0x0032<<1)) 646 #define TOP_CKG_VP9_MASK BMASK(8:4) 647 #define TOP_CKG_VP9_DIS BIT(4) 648 #define TOP_CKG_VP9_INV BIT(5) 649 #define TOP_CKG_VP9_CLK_MASK BMASK(8:6) 650 #define TOP_CKG_VP9_432MHZ BITS(8:6,0) 651 #define TOP_CKG_VP9_384MHZ BITS(8:6,1) 652 #define TOP_CKG_VP9_345MHZ BITS(8:6,2) 653 #define TOP_CKG_VP9_320MHZ BITS(8:6,3) 654 #define TOP_CKG_VP9_288MHZ BITS(8:6,4) 655 #define TOP_CKG_VP9_240MHZ BITS(8:6,5) 656 #define TOP_CKG_VP9_216MHZ BITS(8:6,6) 657 #define TOP_CKG_VP9_172MHZ BITS(8:6,7) 658 659 #define REG_TOP_MVD (CLKGEN0_REG_BASE+(0x0039<<1)) 660 #define TOP_CKG_MVD_MASK BMASK(3:0) 661 #define TOP_CKG_MHVD_DIS BIT(0) 662 #define TOP_CKG_MVD_INV BIT(1) 663 #define TOP_CKG_MVD_CLK_MASK BMASK(3:2) 664 #define TOP_CKG_MVD_144MHZ BITS(3:2, 0) 665 #define TOP_CKG_MVD_123MHZ BITS(3:2, 1) 666 #define TOP_CKG_MVD_MIU BITS(3:2, 2) 667 #define TOP_CKG_MVD_XTAL BITS(3:2, 3) 668 669 #define REG_TOP_MVD2 (CLKGEN0_REG_BASE+(0x0039<<1)) 670 #define TOP_CKG_MVD2_MASK BMASK(11:8) 671 #define TOP_CKG_MHVD2_DIS BIT(8) 672 #define TOP_CKG_MVD2_INV BIT(9) 673 #define TOP_CKG_MVD2_CLK_MASK BMASK(11:10) 674 #define TOP_CKG_MVD2_170MHZ BITS(11:10, 0) 675 #define TOP_CKG_MVD2_144MHZ BITS(11:10, 1) 676 #define TOP_CKG_MVD2_160MHZ BITS(11:10, 1) 677 #define TOP_CKG_MVD2_CLK_MIU_P BITS(11:10, 1) 678 679 #define REG_TOP_CKG_EVD_PPU (CLKGEN2_REG_BASE+(0x001c<<1)) 680 #define TOP_CKG_EVD_PPU_MASK BMASK(4:2) 681 #define TOP_CKG_EVD_PPU_DIS BIT(0) 682 #define TOP_CKG_EVD_PPU_INV BIT(1) 683 #define TOP_CKG_EVD_PPU_PLL_BUF BITS(4:2, 0) 684 #define TOP_CKG_EVD_PPU_MIU128PLL BITS(4:2, 1) 685 #define TOP_CKG_EVD_PPU_MIU256PLL BITS(4:2, 2) 686 #define TOP_CKG_EVD_PPU_480MHZ BITS(4:2, 3) 687 #define TOP_CKG_EVD_PPU_384MHZ BITS(4:2, 4) 688 #define TOP_CKG_EVD_PPU_320MHZ BITS(4:2, 5) 689 #define TOP_CKG_EVD_PPU_240MHZ BITS(4:2, 6) 690 #define TOP_CKG_EVD_PPU_192MHZ BITS(4:2, 7) 691 692 #define REG_TOP_CKG_EVD (CLKGEN0_REG_BASE+(0x003d<<1)) 693 #define TOP_CKG_EVD_MASK BMASK(4:2) 694 #define TOP_CKG_EVD_DIS BIT(0) 695 #define TOP_CKG_EVD_INV BIT(1) 696 #define TOP_CKG_EVD_PLL_BUF BITS(4:2, 0) 697 #define TOP_CKG_EVD_MIU128PLL BITS(4:2, 1) 698 #define TOP_CKG_EVD_MIU256PLL BITS(4:2, 2) 699 #define TOP_CKG_EVD_480MHZ BITS(4:2, 3) 700 #define TOP_CKG_EVD_384MHZ BITS(4:2, 4) 701 #define TOP_CKG_EVD_320MHZ BITS(4:2, 5) 702 #define TOP_CKG_EVD_240MHZ BITS(4:2, 6) 703 #define TOP_CKG_EVD_192MHZ BITS(4:2, 7) 704 705 706 #define REG_TOP_UART_SEL0 (CHIPTOP_REG_BASE+(0x0053<<1)) 707 #define REG_TOP_UART_SEL_0_MASK BMASK(3:0) 708 #define REG_TOP_UART_SEL_MHEG5 BITS(3:0, 1) 709 #define REG_TOP_UART_SEL_VD_MHEG5 BITS(3:0, 2) 710 #define REG_TOP_UART_SEL_TSP BITS(3:0, 3) 711 #define REG_TOP_UART_SEL_PIU_0 BITS(3:0, 4) 712 #define REG_TOP_UART_SEL_PIU_1 BITS(3:0, 5) 713 #define REG_TOP_UART_SEL_PIU_FAST BITS(3:0, 7) 714 #define REG_TOP_UART_SEL_VD_R2_LITE BITS(3:0, 8) 715 #define REG_TOP_UART_SEL_VD_MCU_51_TXD0 BITS(3:0, 10) 716 #define REG_TOP_UART_SEL_VD_MCU_51_TXD1 BITS(3:0, 11) 717 718 #define REG_TOP_HVD_AEC_LITE (CLKGEN2_REG_BASE+(0x0018<<1)) 719 #define TOP_CKG_HVD_AEC_LITE_MASK BMASK(4:0) 720 #define TOP_CKG_HVD_AEC_LITE_DIS BIT(0) 721 #define TOP_CKG_HVD_AEC_LITE_INV BIT(1) 722 #define TOP_CKG_HVD_AEC_LITE_CLK_MASK BMASK(3:2) 723 #define TOP_CKG_HVD_AEC_LITE_288MHZ BITS(3:2, 0) //default use this 724 #define TOP_CKG_HVD_AEC_LITE_240MHZ BITS(3:2, 1) 725 #define TOP_CKG_HVD_AEC_LITE_216MHZ BITS(3:2, 2) 726 #define TOP_CKG_HVD_AEC_LITE_320MHZ BITS(3:2, 3) 727 728 #define REG_TOP_HVD_IDB (CLKGEN2_REG_BASE+(0x001a<<1)) 729 #define TOP_CKG_HVD_IDB_CLK_MASK BMASK(2:0) 730 #define TOP_CKG_HVD_IDB_432MHZ BITS(2:0, 0) // default use this 731 #define TOP_CKG_HVD_IDB_384MHZ BITS(2:0, 1) 732 #define TOP_CKG_HVD_IDB_480MHZ BITS(2:0, 3) // for overclocking 733 734 #define REG_TOP_HVD_AEC (CLKGEN2_REG_BASE+(0x001b<<1)) 735 #define TOP_CKG_HVD_AEC_MASK BMASK(4:0) 736 #define TOP_CKG_HVD_AEC_DIS BIT(0) 737 #define TOP_CKG_HVD_AEC_INV BIT(1) 738 #define TOP_CKG_HVD_AEC_CLK_MASK BMASK(3:2) 739 #define TOP_CKG_HVD_AEC_288MHZ BITS(3:2, 0) //default use this 740 #define TOP_CKG_HVD_AEC_240MHZ BITS(3:2, 1) 741 #define TOP_CKG_HVD_AEC_216MHZ BITS(3:2, 2) 742 #define TOP_CKG_HVD_AEC_320MHZ BITS(3:2, 3) // for overclocking 743 744 #define REG_TOP_VP8 (CLKGEN2_REG_BASE+(0x001d<<1)) 745 #define TOP_CKG_VP8_MASK BMASK(3:0) 746 #define TOP_CKG_VP8_DIS BIT(0) 747 #define TOP_CKG_VP8_INV BIT(1) 748 #define TOP_CKG_VP8_CLK_MASK BMASK(3:2) 749 #define TOP_CKG_VP8_216MHZ BITS(3:2, 0) // default use this 750 #define TOP_CKG_VP8_172MHZ BITS(3:2, 1) 751 #define TOP_CKG_VP8_144MHZ BITS(3:2, 2) 752 #define TOP_CKG_VP8_240MHZ BITS(3:2, 3) // for overclocking 753 754 755 756 //------------------------------------------------------------------------------ 757 // MIU Reg 758 //------------------------------------------------------------------------------ 759 #define MIU0_REG_HVD_BASE (0x1200) 760 #define MIU0_REG_HVD_BASE2 (0x61500) 761 762 #define MIU1_REG_HVD_BASE (0x0600) 763 #define MIU1_REG_HVD_BASE2 (0x62200) 764 765 //#define MIU2_REG_HVD_BASE (0x62000) 766 //#define MIU2_REG_HVD_BASE2 (0x62300) 767 768 769 #define MIU0_CLIENT_SELECT_GP4 (MIU0_REG_HVD_BASE + (0x007C<<1)) 770 #define MIU0_CLIENT_SELECT_GP4_HVD_MIF0 BIT(4) 771 #define MIU0_CLIENT_SELECT_GP4_HVD_MIF1 BIT(5) 772 /* 773 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1)) 774 #define MIU2_CLIENT_SELECT_GP4_HVD_MIF0 BIT(4) 775 #define MIU2_CLIENT_SELECT_GP4_HVD_MIF1 BIT(5) 776 */ 777 /* 778 #define MIU2_CLIENT_SELECT_GP4 (MIU2_REG_HVD_BASE + (0x007C<<1)) 779 #define MIU2_CLIENT_SELECT_GP4_HVD_MIF0 BIT(2) 780 #define MIU2_CLIENT_SELECT_GP4_HVD_MIF1 BIT(3) 781 #define MIU2_CLIENT_SELECT_GP4_HVD_MALI BIT(4) 782 */ 783 784 //#define MIU2_REG_HVD_BASE (0x62000) 785 //#define MIU2_REG_HVD_BASE2 (0x62300) 786 787 788 789 #define MIU0_REG_RQ0_MASK (MIU0_REG_HVD_BASE+(( 0x0023)<<1)) 790 #define MIU0_REG_RQ1_MASK (MIU0_REG_HVD_BASE+(( 0x0033)<<1)) 791 #define MIU0_REG_RQ2_MASK (MIU0_REG_HVD_BASE+(( 0x0043)<<1)) 792 #define MIU0_REG_RQ3_MASK (MIU0_REG_HVD_BASE+(( 0x0053)<<1)) 793 #define MIU0_REG_RQ4_MASK (MIU0_REG_HVD_BASE2+(( 0x0003)<<1)) 794 #define MIU0_REG_RQ5_MASK (MIU0_REG_HVD_BASE2+(( 0x0013)<<1)) 795 796 #define MIU1_REG_RQ0_MASK (MIU1_REG_HVD_BASE+(( 0x0023)<<1)) 797 #define MIU1_REG_RQ1_MASK (MIU1_REG_HVD_BASE+(( 0x0033)<<1)) 798 #define MIU1_REG_RQ2_MASK (MIU1_REG_HVD_BASE+(( 0x0043)<<1)) 799 #define MIU1_REG_RQ3_MASK (MIU1_REG_HVD_BASE+(( 0x0053)<<1)) 800 #define MIU1_REG_RQ4_MASK (MIU1_REG_HVD_BASE2+(( 0x0003)<<1)) 801 #define MIU1_REG_RQ5_MASK (MIU1_REG_HVD_BASE2+(( 0x0013)<<1)) 802 803 /* 804 #define MIU2_REG_RQ0_MASK (MIU2_REG_HVD_BASE+(( 0x0023)<<1)) 805 #define MIU2_REG_RQ1_MASK (MIU2_REG_HVD_BASE+(( 0x0033)<<1)) 806 #define MIU2_REG_RQ2_MASK (MIU2_REG_HVD_BASE+(( 0x0043)<<1)) 807 #define MIU2_REG_RQ3_MASK (MIU2_REG_HVD_BASE+(( 0x0053)<<1)) 808 #define MIU2_REG_RQ4_MASK (MIU2_REG_HVD_BASE2+(( 0x0003)<<1)) 809 #define MIU2_REG_RQ5_MASK (MIU2_REG_HVD_BASE2+(( 0x0013)<<1)) 810 */ 811 812 813 814 #define MIU0_REG_SEL0 (MIU0_REG_HVD_BASE+(( 0x0078)<<1)) 815 #define MIU0_REG_SEL1 (MIU0_REG_HVD_BASE+(( 0x0079)<<1)) 816 #define MIU0_REG_SEL2 (MIU0_REG_HVD_BASE+(( 0x007A)<<1)) 817 #define MIU0_REG_SEL3 (MIU0_REG_HVD_BASE+(( 0x007B)<<1)) 818 #define MIU0_REG_SEL4 (MIU0_REG_HVD_BASE+(( 0x007C)<<1)) 819 #define MIU0_REG_SEL5 (MIU0_REG_HVD_BASE+(( 0x007D)<<1)) 820 /* 821 #define MIU2_REG_SEL0 (MIU2_REG_HVD_BASE+(( 0x0078)<<1)) 822 #define MIU2_REG_SEL1 (MIU2_REG_HVD_BASE+(( 0x0079)<<1)) 823 #define MIU2_REG_SEL2 (MIU2_REG_HVD_BASE+(( 0x007A)<<1)) 824 #define MIU2_REG_SEL3 (MIU2_REG_HVD_BASE+(( 0x007B)<<1)) 825 #define MIU2_REG_SEL4 (MIU2_REG_HVD_BASE+(( 0x007C)<<1)) 826 #define MIU2_REG_SEL5 (MIU2_REG_HVD_BASE+(( 0x007D)<<1)) 827 */ 828 829 //#define MIU1_REG_SEL0 (MIU1_REG_HVD_BASE+(( 0x0078)<<1)) 830 831 832 #define MIU_HVD_RW (BIT(10)|BIT(11)) 833 #define MIU_MVD_RW (BIT(5)|BIT(6)) 834 835 //------------------------------------------------------------------------------ 836 // SRAM Reg 837 //------------------------------------------------------------------------------ 838 839 #ifdef CONFIG_MSTAR_SRAMPD 840 #define REG_PATGEN_HI_BASE 0x71300 841 #define REG_PATGEN_VP9_BASE 0x71800 842 843 #define REG_HICODEC_SRAM_SD_EN (REG_PATGEN_HI_BASE+(( 0x0010)<<1)) 844 #define HICODEC_SRAM_HICODEC0 BIT(0) 845 #define HICODEC_SRAM_HICODEC1 BIT(1) 846 847 #define REG_HICODEC_LITE_SRAM_SD_EN (REG_PATGEN_VP9_BASE+(( 0x0010)<<1)) 848 #define HICODEC_LITE_SRAM_HICODEC0 BIT(0) 849 #define HICODEC_LITE_SRAM_HICODEC1 BIT(1) 850 #endif 851 852 //------------------------------------------------------------------------------------------------- 853 // Type and Structure 854 //------------------------------------------------------------------------------------------------- 855 856 857 #endif // _REG_HVD_H_ 858