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Searched refs:pll (Results 1 – 25 of 144) sorted by relevance

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/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_pll.c272 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) in rockchip_get_pll_settings() argument
274 struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
282 if (pll->type == pll_rk3588) in rockchip_get_pll_settings()
291 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, in rk3036_pll_set_rate() argument
298 rate = rockchip_get_pll_settings(pll, drate); in rk3036_pll_set_rate()
313 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { in rk3036_pll_set_rate()
314 rk_clrsetreg(base + pll->mode_offset, in rk3036_pll_set_rate()
315 pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
316 RKCLK_PLL_MODE_SLOW << pll->mode_shift); in rk3036_pll_set_rate()
320 rk_setreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-keystone/
H A Dclock.c47 if (!(pllctl_reg_read(data->pll, stat) & PLLSTAT_GOSTAT_MASK)) in wait_for_completion()
54 pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLENSRC_MASK | in bypass_main_pll()
69 if (data->pll == MAIN_PLL) in configure_mult_div()
70 pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); in configure_mult_div()
72 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
78 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
83 clrsetbits_le32(keystone_pll_regs[data->pll].reg1, in configure_mult_div()
87 clrsetbits_le32(keystone_pll_regs[data->pll].reg0, in configure_mult_div()
101 tmp = pllctl_reg_read(data->pll, secctl); in configure_main_pll()
105 setbits_le32(keystone_pll_regs[data->pll].reg1, in configure_main_pll()
[all …]
H A Dcmd_clock.c17 .pll = MAIN_PLL,
29 cmd_pll_data.pll = PASS_PLL; in do_pll_cmd()
32 cmd_pll_data.pll = TETRIS_PLL; in do_pll_cmd()
36 cmd_pll_data.pll = DDR3A_PLL; in do_pll_cmd()
38 cmd_pll_data.pll = DDR3B_PLL; in do_pll_cmd()
41 cmd_pll_data.pll = DDR3_PLL; in do_pll_cmd()
51 cmd_pll_data.pll, cmd_pll_data.pll_m, in do_pll_cmd()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5445x/
H A Dspeed.c60 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
66 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
74 pll_t *pll = (pll_t *)MMAP_PLL; in setup_5441x_clocks() local
81 out_be32(&pll->pcr, 0x00000013); in setup_5441x_clocks()
82 out_be32(&pll->pdr, 0x00e70c61); in setup_5441x_clocks()
93 temp = in_be32(&pll->pcr); in setup_5441x_clocks()
96 out_be32(&pll->pcr, temp); in setup_5441x_clocks()
98 temp = in_be32(&pll->pdr); in setup_5441x_clocks()
101 out_be32(&pll->pdr, temp); in setup_5441x_clocks()
107 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) * in setup_5441x_clocks()
[all …]
/rk3399_rockchip-uboot/arch/arm/cpu/arm926ejs/mx27/
H A Dgeneric.c27 static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref) in imx_decode_pll() argument
29 unsigned int mfi = (pll >> 10) & 0xf; in imx_decode_pll()
30 unsigned int mfn = pll & 0x3ff; in imx_decode_pll()
31 unsigned int mfd = (pll >> 16) & 0x3ff; in imx_decode_pll()
32 unsigned int pd = (pll >> 26) & 0xf; in imx_decode_pll()
47 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in clk_in_26m() local
49 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { in clk_in_26m()
59 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_mpllclk() local
60 ulong cscr = readl(&pll->cscr); in imx_get_mpllclk()
68 return imx_decode_pll(readl(&pll->mpctl0), fref); in imx_get_mpllclk()
[all …]
H A Dtimer.c92 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in timer_init() local
97 writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0); in timer_init()
98 writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1); in timer_init()
/rk3399_rockchip-uboot/arch/arm/mach-keystone/include/mach/
H A Dclock_defs.h54 #define pllctl_reg(pll, reg) (&(pllctl_regs[pll]->reg)) argument
55 #define pllctl_reg_read(pll, reg) __raw_readl(pllctl_reg(pll, reg)) argument
56 #define pllctl_reg_write(pll, reg, val) __raw_writel(val, pllctl_reg(pll, reg)) argument
58 #define pllctl_reg_rmw(pll, reg, mask, val) \ argument
59 pllctl_reg_write(pll, reg, \
60 (pllctl_reg_read(pll, reg) & ~(mask)) | val)
62 #define pllctl_reg_setbits(pll, reg, mask) \ argument
63 pllctl_reg_rmw(pll, reg, 0, mask)
65 #define pllctl_reg_clrbits(pll, reg, mask) \ argument
66 pllctl_reg_rmw(pll, reg, mask, 0)
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf5227x/
H A Dspeed.c58 pll_t *pll = (pll_t *)MMAP_PLL; in clock_exit_limp() local
64 while (!(in_be32(&pll->psr) & PLL_PSR_LOCK)) in clock_exit_limp()
75 pll_t *pll = (pll_t *)MMAP_PLL; in get_clocks() local
79 pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF; in get_clocks()
91 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
94 pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF); in get_clocks()
96 out_be32(&pll->pcr, pcrvalue); in get_clocks()
98 ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * in get_clocks()
104 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
113 temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1; in get_clocks()
[all …]
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-s32v234/
H A Dmc_cgm_regs.h71 #define PLLDIG_PLLDV(pll) ((MC_CGM0_BASE_ADDR + 0x00000028) + ((pll) * 0x80)) argument
95 #define PLLDIG_PLLFD(pll) ((MC_CGM0_BASE_ADDR + 0x00000030) + ((pll) * 0x80)) argument
101 #define PLLDIG_PLLCAL1(pll) ((MC_CGM0_BASE_ADDR + 0x00000038) + ((pll) * 0x80)) argument
111 #define DFS_DLLPRG1(pll) (DFS0_BASE_ADDR + 0x00000000 + ((pll) * 0x80)) argument
138 #define DFS_CTRL(pll) (DFS0_BASE_ADDR + 0x00000018 + ((pll) * 0x80)) argument
143 #define DFS_PORTSR(pll) (DFS0_BASE_ADDR + 0x0000000C +((pll) * 0x80)) argument
145 #define DFS_PORTRESET(pll) (DFS0_BASE_ADDR + 0x00000014 + ((pll) * 0x80)) argument
152 #define DFS_DVPORTn(pll,n) (DFS0_BASE_ADDR + ((pll) * 0x80) + (0x0000001C + ((n) * 0x4))) argument
/rk3399_rockchip-uboot/board/freescale/s32v234evb/
H A Dclock.c18 static int select_pll_source_clk(enum pll_type pll, u32 refclk_freq) in select_pll_source_clk() argument
40 switch (pll) { in select_pll_source_clk()
51 pll_idx = pll; in select_pll_source_clk()
82 static int program_pll(enum pll_type pll, u32 refclk_freq, u32 freq0, u32 freq1, in program_pll() argument
104 if (select_pll_source_clk(pll, refclk_freq) < 0) { in program_pll()
115 PLLDIG_PLLDV_MFD(plldv_mfd), PLLDIG_PLLDV(pll)); in program_pll()
117 writel(readl(PLLDIG_PLLFD(pll)) | PLLDIG_PLLFD_MFN_SET(pllfd_mfn) | in program_pll()
118 PLLDIG_PLLFD_SMDEN, PLLDIG_PLLFD(pll)); in program_pll()
121 writel(readl(MC_ME_RUNn_MC(0)) | MC_ME_RUNMODE_MC_PLL(pll), in program_pll()
127 if ((pll == ARM_PLL) || (pll == ENET_PLL) || (pll == DDR_PLL)) { in program_pll()
[all …]
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf52x2/
H A Dspeed.c22 pll_t *pll = (pll_t *) MMAP_PLL; in get_clocks() local
24 out_8(&pll->odr, CONFIG_SYS_PLL_ODR); in get_clocks()
25 out_8(&pll->fdr, CONFIG_SYS_PLL_FDR); in get_clocks()
58 pll_t *pll = (pll_t *)(MMAP_PLL); in get_clocks() local
61 out_be32(&pll->syncr, 0x01080000); in get_clocks()
62 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) in get_clocks()
64 out_be32(&pll->syncr, 0x01000000); in get_clocks()
65 while (!(in_be32(&pll->synsr) & FMPLL_SYNSR_LOCK)) in get_clocks()
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf532x/
H A Dspeed.c54 pll_t *pll = (pll_t *)(MMAP_PLL); in get_sys_clock() local
68 u32 pfdr = (in_be32(&pll->pcr) & 0x3F) + 1; in get_sys_clock()
69 u32 refdiv = (1 << ((in_be32(&pll->pcr) & PLL_PCR_REFDIV(7)) >> 8)); in get_sys_clock()
70 u32 busdiv = ((in_be32(&pll->pdr) & 0x00F0) >> 4) + 1; in get_sys_clock()
75 return (FREF * in_8(&pll->pfdr)) / (BUSDIV * 4); in get_sys_clock()
145 pll_t *pll = (pll_t *)(MMAP_PLL); in clock_pll() local
154 u32 busdiv = ((in_be32(&pll->pdr) >> 4) & 0x0F) + 1; in clock_pll()
155 mfd = (in_be32(&pll->pcr) & 0x3F) + 1; in clock_pll()
160 mfd = in_8(&pll->pfdr); in clock_pll()
212 out_be32(&pll->pdr, in clock_pll()
[all …]
/rk3399_rockchip-uboot/arch/mips/mach-ath79/qca953x/
H A Dclk.c35 u32 val, ctrl, xtal, pll, div; in get_clocks() local
47 pll = xtal / div; in get_clocks()
52 pll *= div; in get_clocks()
57 pll >>= div; in get_clocks()
62 gd->cpu_clk = pll / div; in get_clocks()
69 pll = xtal / div; in get_clocks()
74 pll *= div; in get_clocks()
79 pll >>= div; in get_clocks()
84 gd->mem_clk = pll / div; in get_clocks()
/rk3399_rockchip-uboot/drivers/video/sunxi/
H A Dsunxi_dw_hdmi.c32 u32 pll; member
95 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_init()
99 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_init()
102 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_init()
103 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
149 writel(0x30dc5fc0, &phy->pll); in sunxi_dw_hdmi_phy_set()
153 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
156 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
158 setbits_le32(&phy->pll, tmp + 2); in sunxi_dw_hdmi_phy_set()
160 setbits_le32(&phy->pll, 0x3f); in sunxi_dw_hdmi_phy_set()
[all …]
/rk3399_rockchip-uboot/arch/mips/mach-ath79/ar933x/
H A Dclk.c35 u32 val, xtal, pll, div; in get_clocks() local
45 pll = xtal / div; in get_clocks()
50 pll *= div; in get_clocks()
55 pll >>= div; in get_clocks()
62 gd->cpu_clk = pll / div; in get_clocks()
67 gd->mem_clk = pll / div; in get_clocks()
72 gd->bus_clk = pll / div; in get_clocks()
/rk3399_rockchip-uboot/arch/arm/mach-uniphier/clk/
H A DMakefile16 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
17 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
18 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
22 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o pll-ld11.o
23 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o pll-ld20.o
24 obj-$(CONFIG_ARCH_UNIPHIER_PXS3) += clk-pxs3.o pll-pxs3.o
28 obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pll-base-ld20.o
29 obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pll-base-ld20.o
/rk3399_rockchip-uboot/arch/arm/cpu/armv7/iproc-common/
H A Darmpll.c42 uint32_t pll; in armpll_config() local
97 pll = readl(IHOST_PROC_CLK_PLLARMB); in armpll_config()
98 pll &= ~((1 << IHOST_PROC_CLK_PLLARMB__PLLARM_NDIV_FRAC_WIDTH) - 1); in armpll_config()
103 pll |= ndiv_frac; in armpll_config()
104 writel(pll, IHOST_PROC_CLK_PLLARMB); in armpll_config()
126 pll = readl(IHOST_PROC_CLK_PLLARMA); in armpll_config()
127 pll |= (1 << IHOST_PROC_CLK_PLLARMA__PLLARM_SOFT_POST_RESETB); in armpll_config()
128 writel(pll, IHOST_PROC_CLK_PLLARMA); in armpll_config()
/rk3399_rockchip-uboot/arch/arm/mach-tegra/
H A Dclock.c93 struct clk_pll *pll = get_pll(clkid); in clock_ll_read_pll() local
102 data = readl(&pll->pll_base); in clock_ll_read_pll()
106 data = readl(&pll->pll_misc); in clock_ll_read_pll()
117 struct clk_pll *pll = NULL; in clock_start_pll() local
123 pll = get_pll(clkid); in clock_start_pll()
139 if (pll) in clock_start_pll()
140 misc_data = readl(&pll->pll_misc); in clock_start_pll()
152 if (pll) { in clock_start_pll()
153 writel(misc_data, &pll->pll_misc); in clock_start_pll()
154 writel(data, &pll->pll_base); in clock_start_pll()
[all …]
H A Dcpu.c171 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate() argument
180 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { in pllx_set_rate()
190 writel(reg, &pll->pll_base); in pllx_set_rate()
205 writel(reg, &pll->pll_misc); in pllx_set_rate()
208 reg = readl(&pll->pll_base); in pllx_set_rate()
210 writel(reg, &pll->pll_base); in pllx_set_rate()
214 reg = readl(&pll->pll_misc); in pllx_set_rate()
217 writel(reg, &pll->pll_misc); in pllx_set_rate()
221 reg = readl(&pll->pll_base); in pllx_set_rate()
223 writel(reg, &pll->pll_base); in pllx_set_rate()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-imx/mx5/
H A Dclock.c161 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) in decode_pll() argument
167 ctrl = readl(&pll->ctrl); in decode_pll()
170 mfn = readl(&pll->hfs_mfn); in decode_pll()
171 mfd = readl(&pll->hfs_mfd); in decode_pll()
172 op = readl(&pll->hfs_op); in decode_pll()
174 mfn = readl(&pll->mfn); in decode_pll()
175 mfd = readl(&pll->mfd); in decode_pll()
176 op = readl(&pll->op); in decode_pll()
552 static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) in calc_pll_params() argument
608 pll->pd = (u32)pd; in calc_pll_params()
[all …]
/rk3399_rockchip-uboot/arch/m68k/cpu/mcf523x/
H A Dspeed.c24 pll_t *pll = (pll_t *)(MMAP_PLL); in get_clocks() local
26 out_be32(&pll->syncr, PLL_SYNCR_MFD(1)); in get_clocks()
28 while (!(in_be32(&pll->synsr) & PLL_SYNSR_LOCK)) in get_clocks()
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/s32v234/
H A Dgeneric.c28 static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv, in get_pllfreq() argument
56 if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) { in get_pllfreq()
58 readl(DFS_DVPORTn(pll, selected_output - 1)); in get_pllfreq()
83 static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq, in decode_pll() argument
88 plldv = readl(PLLDIG_PLLDV(pll)); in decode_pll()
89 pllfd = readl(PLLDIG_PLLFD(pll)); in decode_pll()
91 return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output); in decode_pll()
/rk3399_rockchip-uboot/drivers/video/
H A Di915_reg.h169 #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B) argument
176 #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0) argument
177 #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1) argument
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rv1108.c41 rk_clrsetreg(&priv->cru->pll[1].con3, WORK_MODE_MASK, in rkdclk_init()
43 rk_clrsetreg(&priv->cru->pll[1].con3, GLOBAL_POWER_DOWN_MASK, in rkdclk_init()
45 rk_clrsetreg(&priv->cru->pll[1].con3, DSMPD_MASK, in rkdclk_init()
47 rk_clrsetreg(&priv->cru->pll[1].con0, FBDIV_MASK, in rkdclk_init()
49 rk_clrsetreg(&priv->cru->pll[1].con1, in rkdclk_init()
54 rk_clrsetreg(&priv->cru->pll[1].con3, GLOBAL_POWER_DOWN_MASK, in rkdclk_init()
56 while (!(readl(&priv->cru->pll[1].con2) & (1u << LOCK_STA_SHIFT))) in rkdclk_init()
62 rk_clrsetreg(&priv->cru->pll[1].con3, WORK_MODE_MASK, in rkdclk_init()
/rk3399_rockchip-uboot/arch/arm/dts/
H A Dkeystone-k2e-clocks.dtsi14 compatible = "ti,keystone,main-pll-clock";
22 compatible = "ti,keystone,pll-clock";
31 compatible = "ti,keystone,pll-clock";
33 clock-output-names = "ddr-3a-pll-clk";

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