Lines Matching refs:pll
32 u32 pll; member
95 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_init()
99 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_init()
102 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_init()
103 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_init()
149 writel(0x30dc5fc0, &phy->pll); in sunxi_dw_hdmi_phy_set()
153 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
156 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
158 setbits_le32(&phy->pll, tmp + 2); in sunxi_dw_hdmi_phy_set()
160 setbits_le32(&phy->pll, 0x3f); in sunxi_dw_hdmi_phy_set()
167 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
171 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
174 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
175 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
181 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
185 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
188 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
189 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()
195 writel(0x39dc5040, &phy->pll); in sunxi_dw_hdmi_phy_set()
199 setbits_le32(&phy->pll, BIT(25)); in sunxi_dw_hdmi_phy_set()
202 setbits_le32(&phy->pll, BIT(31) | BIT(30)); in sunxi_dw_hdmi_phy_set()
203 setbits_le32(&phy->pll, tmp); in sunxi_dw_hdmi_phy_set()