Lines Matching refs:pll
272 rockchip_get_pll_settings(struct rockchip_pll_clock *pll, ulong rate) in rockchip_get_pll_settings() argument
274 struct rockchip_pll_rate_table *rate_table = pll->rate_table; in rockchip_get_pll_settings()
282 if (pll->type == pll_rk3588) in rockchip_get_pll_settings()
291 static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, in rk3036_pll_set_rate() argument
298 rate = rockchip_get_pll_settings(pll, drate); in rk3036_pll_set_rate()
313 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { in rk3036_pll_set_rate()
314 rk_clrsetreg(base + pll->mode_offset, in rk3036_pll_set_rate()
315 pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
316 RKCLK_PLL_MODE_SLOW << pll->mode_shift); in rk3036_pll_set_rate()
320 rk_setreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
323 rk_clrsetreg(base + pll->con_offset, in rk3036_pll_set_rate()
328 rk_clrsetreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
333 rk_clrsetreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
337 writel((readl(base + pll->con_offset + 0x8) & in rk3036_pll_set_rate()
340 base + pll->con_offset + 0x8); in rk3036_pll_set_rate()
344 rk_clrreg(base + pll->con_offset + 0x4, in rk3036_pll_set_rate()
348 while ((timeout > 0) && !(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) { in rk3036_pll_set_rate()
353 if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) in rk3036_pll_set_rate()
356 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) { in rk3036_pll_set_rate()
357 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, in rk3036_pll_set_rate()
358 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); in rk3036_pll_set_rate()
362 pll, readl(base + pll->con_offset), in rk3036_pll_set_rate()
363 readl(base + pll->con_offset + 0x4), in rk3036_pll_set_rate()
364 readl(base + pll->con_offset + 0x8), in rk3036_pll_set_rate()
365 readl(base + pll->mode_offset)); in rk3036_pll_set_rate()
370 static ulong rk3036_pll_get_rate(struct rockchip_pll_clock *pll, in rk3036_pll_get_rate() argument
378 con = readl(base + pll->mode_offset); in rk3036_pll_get_rate()
379 shift = pll->mode_shift; in rk3036_pll_get_rate()
380 mask = pll->mode_mask << shift; in rk3036_pll_get_rate()
382 if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) in rk3036_pll_get_rate()
392 con = readl(base + pll->con_offset); in rk3036_pll_get_rate()
397 con = readl(base + pll->con_offset + 0x4); in rk3036_pll_get_rate()
404 con = readl(base + pll->con_offset + 0x8); in rk3036_pll_get_rate()
444 static int rk3588_pll_set_rate(struct rockchip_pll_clock *pll, in rk3588_pll_set_rate() argument
450 rate = rockchip_get_pll_settings(pll, drate); in rk3588_pll_set_rate()
466 rk_clrsetreg(base + pll->mode_offset, in rk3588_pll_set_rate()
467 pll->mode_mask << pll->mode_shift, in rk3588_pll_set_rate()
468 RKCLK_PLL_MODE_SLOW << pll->mode_shift); in rk3588_pll_set_rate()
471 pll->mode_mask << 6, in rk3588_pll_set_rate()
475 pll->mode_mask << 6, in rk3588_pll_set_rate()
479 pll->mode_mask << 14, in rk3588_pll_set_rate()
483 rk_setreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
486 rk_clrsetreg(base + pll->con_offset, in rk3588_pll_set_rate()
489 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
495 rk_clrsetreg(base + pll->con_offset + RK3588_PLLCON(2), in rk3588_pll_set_rate()
499 rk_clrreg(base + pll->con_offset + RK3588_PLLCON(1), in rk3588_pll_set_rate()
503 while (!(readl(base + pll->con_offset + RK3588_PLLCON(6)) & in rk3588_pll_set_rate()
509 rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift, in rk3588_pll_set_rate()
510 RKCLK_PLL_MODE_NORMAL << pll->mode_shift); in rk3588_pll_set_rate()
513 pll->mode_mask << 6, in rk3588_pll_set_rate()
523 pll->mode_mask << 6, in rk3588_pll_set_rate()
533 pll->mode_mask << 14, in rk3588_pll_set_rate()
553 pll, readl(base + pll->con_offset), in rk3588_pll_set_rate()
554 readl(base + pll->con_offset + 0x4), in rk3588_pll_set_rate()
555 readl(base + pll->con_offset + 0x8), in rk3588_pll_set_rate()
556 readl(base + pll->mode_offset)); in rk3588_pll_set_rate()
561 static ulong rk3588_pll_get_rate(struct rockchip_pll_clock *pll, in rk3588_pll_get_rate() argument
568 con = readl(base + pll->mode_offset); in rk3588_pll_get_rate()
569 shift = pll->mode_shift; in rk3588_pll_get_rate()
573 mode = (con & (pll->mode_mask << shift)) >> shift; in rk3588_pll_get_rate()
579 con = readl(base + pll->con_offset); in rk3588_pll_get_rate()
582 con = readl(base + pll->con_offset + RK3588_PLLCON(1)); in rk3588_pll_get_rate()
587 con = readl(base + pll->con_offset + RK3588_PLLCON(2)); in rk3588_pll_get_rate()
620 ulong rockchip_pll_get_rate(struct rockchip_pll_clock *pll, in rockchip_pll_get_rate() argument
626 switch (pll->type) { in rockchip_pll_get_rate()
628 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_get_rate()
629 rate = rk3036_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
632 pll->mode_mask = PLL_RK3328_MODE_MASK; in rockchip_pll_get_rate()
633 rate = rk3036_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
636 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_get_rate()
637 rate = rk3588_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
646 int rockchip_pll_set_rate(struct rockchip_pll_clock *pll, in rockchip_pll_set_rate() argument
652 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) in rockchip_pll_set_rate()
655 switch (pll->type) { in rockchip_pll_set_rate()
657 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_set_rate()
658 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
661 pll->mode_mask = PLL_RK3328_MODE_MASK; in rockchip_pll_set_rate()
662 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
665 pll->mode_mask = PLL_MODE_MASK; in rockchip_pll_set_rate()
666 ret = rk3588_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()