171 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,  in pllx_set_rate()  argument
180 	if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {  in pllx_set_rate()
190 	writel(reg, &pll->pll_base);  in pllx_set_rate()
205 	writel(reg, &pll->pll_misc);  in pllx_set_rate()
208 	reg = readl(&pll->pll_base);  in pllx_set_rate()
210 	writel(reg, &pll->pll_base);  in pllx_set_rate()
214 	reg = readl(&pll->pll_misc);  in pllx_set_rate()
217 	writel(reg, &pll->pll_misc);  in pllx_set_rate()
221 	reg = readl(&pll->pll_base);  in pllx_set_rate()
223 	writel(reg, &pll->pll_base);  in pllx_set_rate()
232 	struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];  in init_pllx()  local
256 	pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);  in init_pllx()