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Searched refs:con1 (Results 1 – 25 of 42) sorted by relevance

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/rk3399_rockchip-uboot/drivers/adc/
H A Dexynos-adc.c50 cfg = readl(&regs->con1); in exynos_adc_start_channel()
51 writel(cfg | ADC_V2_CON1_STC_EN, &regs->con1); in exynos_adc_start_channel()
65 cfg = readl(&regs->con1); in exynos_adc_stop()
68 writel(cfg, &regs->con1); in exynos_adc_stop()
88 writel(ADC_V2_CON1_SOFT_RESET, &regs->con1); in exynos_adc_probe()
/rk3399_rockchip-uboot/drivers/net/
H A Dpic32_eth.c64 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_mii_init()
71 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_mii_init()
239 writel(ETHCON_ON | ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_ctrl_reset()
246 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_ctrl_reset()
270 writel(ETHCON_ON, &ectl_p->con1.set); in pic32_ctrl_reset()
297 writel(ETHCON_BUFCDEC, &ectl_p->con1.set); in pic32_rx_desc_init()
319 writel(ETHCON_RXEN, &ectl_p->con1.set); in pic32_rx_desc_init()
356 if (readl(&ectl_p->con1.raw) & ETHCON_ON) in pic32_eth_stop()
363 writel(ETHCON_TXRTS | ETHCON_RXEN, &ectl_p->con1.clr); in pic32_eth_stop()
374 writel(ETHCON_ON, &ectl_p->con1.clr); in pic32_eth_stop()
[all …]
H A Dpic32_eth.h15 struct pic32_reg_atomic con1; /* 0x00 */ member
H A Dgmac_rockchip.c1631 void *con1; in rk3568_set_to_rmii() local
1642 con1 = &grf->mac1_con1; in rk3568_set_to_rmii()
1644 con1 = &grf->mac0_con1; in rk3568_set_to_rmii()
1646 rk_clrsetreg(con1, in rk3568_set_to_rmii()
1654 void *con0, *con1; in rk3568_set_to_rgmii() local
1682 con1 = &grf->mac1_con1; in rk3568_set_to_rgmii()
1685 con1 = &grf->mac0_con1; in rk3568_set_to_rgmii()
1694 rk_clrsetreg(con1, in rk3568_set_to_rgmii()
/rk3399_rockchip-uboot/drivers/clk/exynos/
H A Dclk-pll.c20 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq) in pll145x_get_rate() argument
22 unsigned long pll_con1 = readl(con1); in pll145x_get_rate()
H A Dclk-pll.h9 unsigned long pll145x_get_rate(unsigned int *con1, unsigned long fin_freq);
/rk3399_rockchip-uboot/arch/arm/mach-exynos/include/mach/
H A Dadc.h59 unsigned int con1; member
/rk3399_rockchip-uboot/drivers/clk/rockchip/
H A Dclk_rk3036.c80 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkclk_set_pll()
83 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
88 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkclk_set_pll()
93 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT); in rkclk_set_pll()
96 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkclk_set_pll()
232 con = readl(&pll->con1); in rkclk_pll_get_rate()
H A Dclk_rv1108.c94 rk_clrsetreg(&pll->con1, POSTDIV1_MASK | POSTDIV2_MASK | REFDIV_MASK, in rkclk_set_pll()
121 uint32_t con0, con1, con3; in rkclk_pll_get_rate() local
130 con1 = readl(&pll->con1); in rkclk_pll_get_rate()
132 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; in rkclk_pll_get_rate()
133 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; in rkclk_pll_get_rate()
134 refdiv = (con1 >> REFDIV_SHIFT) & REFDIV_MASK; in rkclk_pll_get_rate()
/rk3399_rockchip-uboot/drivers/video/drm/rk628/
H A Drk628_cru.c63 u32 con0 = 0, con1 = 0, con2 = 0; in rk628_cru_clk_get_rate_pll() local
95 rk628_i2c_read(rk628, offset + CRU_CPLL_CON1, &con1); in rk628_cru_clk_get_rate_pll()
101 dsmpd = (con1 & PLL_DSMPD_MASK) >> PLL_DSMPD_SHIFT; in rk628_cru_clk_get_rate_pll()
102 postdiv2 = (con1 & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rk628_cru_clk_get_rate_pll()
103 refdiv = (con1 & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT; in rk628_cru_clk_get_rate_pll()
/rk3399_rockchip-uboot/arch/arm/include/asm/arch-rockchip/
H A Dcru_rk3188.h42 u32 con1; member
H A Dcru_rk3066.h42 u32 con1; member
H A Dsdram_rk3308.h22 u32 con1; member
H A Dcru_rk3128.h35 unsigned int con1; member
H A Dcru_rk3368.h32 unsigned int con1; member
H A Dgrf_rv1126b.h14 uint32_t con1; /* address offset: 0x0004 */ member
25 uint32_t con1; /* address offset: 0x0004 */ member
H A Dcru_rk322x.h34 unsigned int con1; member
H A Dcru_rk3036.h41 unsigned int con1; member
H A Dcru_rv1108.h29 unsigned int con1; member
H A Dcru_rk3288.h45 u32 con1; member
H A Dcru_rv1103b.h48 unsigned int con1; member
H A Dcru_rv1106.h57 unsigned int con1; member
H A Dgrf_rv1103b.h48 uint32_t con1; /* address offset: 0x0004 */ member
/rk3399_rockchip-uboot/drivers/ram/rockchip/
H A Dsdram_rk3308.c81 rk_clrsetreg(&priv->cru->pll[pll_type].con1, PLLPD0_MASK, in pll_set()
83 rk_clrsetreg(&priv->cru->pll[pll_type].con1, in pll_set()
91 rk_clrsetreg(&priv->cru->pll[pll_type].con1, in pll_set()
98 rk_clrsetreg(&priv->cru->pll[pll_type].con1, PLLPD0_MASK, in pll_set()
102 while (!(readl(&priv->cru->pll[pll_type].con1) & in pll_set()
588 writel(CG_EXIT_TH << CG_EXIT_TH_SHIFT, &priv->standby->con1); in enable_ddr_standby()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c336 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT); in rkdclk_init()
342 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK, in rkdclk_init()
347 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT)) in rkdclk_init()

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